1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // CS42L43 CODEC driver
4 //
5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/bitops.h>
9 #include <linux/bits.h>
10 #include <linux/build_bug.h>
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/bitmap.h>
17 #include <linux/gcd.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/jiffies.h>
21 #include <linux/mfd/cs42l43.h>
22 #include <linux/mfd/cs42l43-regs.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/regmap.h>
27 #include <linux/string.h>
28 #include <linux/workqueue.h>
29 #include <sound/control.h>
30 #include <sound/cs42l43.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc-component.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/soc-dai.h>
36 #include <sound/soc.h>
37 #include <sound/tlv.h>
38
39 #include "cs42l43.h"
40
41 #define CS42L43_DECL_MUX(name, reg) \
42 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
43 0, CS42L43_MIXER_SRC_MASK, \
44 cs42l43_mixer_texts, cs42l43_mixer_values); \
45 static const struct snd_kcontrol_new cs42l43_##name##_mux = \
46 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
47
48 #define CS42L43B_DECL_MUX(name, reg) \
49 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
50 0, CS42L43_MIXER_SRC_MASK, \
51 cs42l43b_mixer_texts, cs42l43b_mixer_values); \
52 static const struct snd_kcontrol_new cs42l43_##name##_mux = \
53 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
54
55 #define CS42L43_DECL_MIXER(name, reg) \
56 CS42L43_DECL_MUX(name##_in1, reg); \
57 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \
58 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \
59 CS42L43_DECL_MUX(name##_in4, reg + 0xC)
60
61 #define CS42L43B_DECL_MIXER(name, reg) \
62 CS42L43B_DECL_MUX(name##_in1, reg); \
63 CS42L43B_DECL_MUX(name##_in2, reg + 0x4); \
64 CS42L43B_DECL_MUX(name##_in3, reg + 0x8); \
65 CS42L43B_DECL_MUX(name##_in4, reg + 0xC)
66
67 #define CS42L43_DAPM_MUX(name_str, name) \
68 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux)
69
70 #define CS42L43_DAPM_MIXER(name_str, name) \
71 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \
72 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \
73 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \
74 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \
75 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
76
77 #define CS42L43_BASE_ROUTES(name_str) \
78 { name_str, "Tone Generator 1", "Tone 1" }, \
79 { name_str, "Tone Generator 2", "Tone 2" }, \
80 { name_str, "Decimator 1", "Decimator 1" }, \
81 { name_str, "Decimator 2", "Decimator 2" }, \
82 { name_str, "Decimator 3", "Decimator 3" }, \
83 { name_str, "Decimator 4", "Decimator 4" }, \
84 { name_str, "ASPRX1", "ASPRX1" }, \
85 { name_str, "ASPRX2", "ASPRX2" }, \
86 { name_str, "ASPRX3", "ASPRX3" }, \
87 { name_str, "ASPRX4", "ASPRX4" }, \
88 { name_str, "ASPRX5", "ASPRX5" }, \
89 { name_str, "ASPRX6", "ASPRX6" }, \
90 { name_str, "DP5RX1", "DP5RX1" }, \
91 { name_str, "DP5RX2", "DP5RX2" }, \
92 { name_str, "DP6RX1", "DP6RX1" }, \
93 { name_str, "DP6RX2", "DP6RX2" }, \
94 { name_str, "DP7RX1", "DP7RX1" }, \
95 { name_str, "DP7RX2", "DP7RX2" }, \
96 { name_str, "ASRC INT1", "ASRC_INT1" }, \
97 { name_str, "ASRC INT2", "ASRC_INT2" }, \
98 { name_str, "ASRC INT3", "ASRC_INT3" }, \
99 { name_str, "ASRC INT4", "ASRC_INT4" }, \
100 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \
101 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \
102 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \
103 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \
104 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \
105 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \
106 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \
107 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \
108 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \
109 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \
110 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \
111 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \
112 { name_str, "EQ1", "EQ" }, \
113 { name_str, "EQ2", "EQ" }
114
115 #define CS42L43B_BASE_ROUTES(name_str) \
116 { name_str, "Decimator 5", "Decimator 5" }, \
117 { name_str, "Decimator 6", "Decimator 6" }, \
118 { name_str, "ISRC1 DEC3", "ISRC1DEC3" }, \
119 { name_str, "ISRC1 DEC4", "ISRC1DEC4" }, \
120 { name_str, "ISRC2 DEC3", "ISRC2DEC3" }, \
121 { name_str, "ISRC2 DEC4", "ISRC2DEC4" }
122
123 #define CS42L43_MUX_ROUTES(name_str, widget) \
124 { widget, NULL, name_str " Input" }, \
125 { name_str " Input", NULL, "Mixer Core" }, \
126 CS42L43_BASE_ROUTES(name_str " Input")
127
128 #define CS42L43B_MUX_ROUTES(name_str, widget) \
129 CS42L43_MUX_ROUTES(name_str, widget), \
130 CS42L43B_BASE_ROUTES(name_str " Input")
131
132 #define CS42L43_MIXER_ROUTES(name_str, widget) \
133 { name_str " Mixer", NULL, name_str " Input 1" }, \
134 { name_str " Mixer", NULL, name_str " Input 2" }, \
135 { name_str " Mixer", NULL, name_str " Input 3" }, \
136 { name_str " Mixer", NULL, name_str " Input 4" }, \
137 { widget, NULL, name_str " Mixer" }, \
138 { name_str " Mixer", NULL, "Mixer Core" }, \
139 CS42L43_BASE_ROUTES(name_str " Input 1"), \
140 CS42L43_BASE_ROUTES(name_str " Input 2"), \
141 CS42L43_BASE_ROUTES(name_str " Input 3"), \
142 CS42L43_BASE_ROUTES(name_str " Input 4")
143
144 #define CS42L43B_MIXER_ROUTES(name_str, widget) \
145 CS42L43_MIXER_ROUTES(name_str, widget), \
146 CS42L43B_BASE_ROUTES(name_str " Input 1"), \
147 CS42L43B_BASE_ROUTES(name_str " Input 2"), \
148 CS42L43B_BASE_ROUTES(name_str " Input 3"), \
149 CS42L43B_BASE_ROUTES(name_str " Input 4")
150
151 #define CS42L43_MIXER_VOLUMES(name_str, base) \
152 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \
153 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
154 cs42l43_mixer_tlv), \
155 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \
156 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
157 cs42l43_mixer_tlv), \
158 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \
159 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
160 cs42l43_mixer_tlv), \
161 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \
162 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
163 cs42l43_mixer_tlv)
164
165 #define CS42L43_IRQ_ERROR(name) \
166 static irqreturn_t cs42l43_##name(int irq, void *data) \
167 { \
168 struct cs42l43_codec *priv = data; \
169 dev_err(priv->dev, "Error " #name " IRQ\n"); \
170 return IRQ_HANDLED; \
171 }
172
173 CS42L43_IRQ_ERROR(pll_lost_lock)
CS42L43_IRQ_ERROR(spkr_clock_stop)174 CS42L43_IRQ_ERROR(spkr_clock_stop)
175 CS42L43_IRQ_ERROR(spkl_clock_stop)
176 CS42L43_IRQ_ERROR(spkr_brown_out)
177 CS42L43_IRQ_ERROR(spkl_brown_out)
178 CS42L43_IRQ_ERROR(spkr_therm_shutdown)
179 CS42L43_IRQ_ERROR(spkl_therm_shutdown)
180 CS42L43_IRQ_ERROR(spkr_therm_warm)
181 CS42L43_IRQ_ERROR(spkl_therm_warm)
182 CS42L43_IRQ_ERROR(spkr_sc_detect)
183 CS42L43_IRQ_ERROR(spkl_sc_detect)
184
185 static void cs42l43_hp_ilimit_clear_work(struct work_struct *work)
186 {
187 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
188 hp_ilimit_clear_work.work);
189 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(priv->component);
190
191 snd_soc_dapm_mutex_lock(dapm);
192
193 priv->hp_ilimit_count--;
194
195 if (priv->hp_ilimit_count)
196 queue_delayed_work(system_dfl_wq, &priv->hp_ilimit_clear_work,
197 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
198
199 snd_soc_dapm_mutex_unlock(dapm);
200 }
201
cs42l43_hp_ilimit(int irq,void * data)202 static irqreturn_t cs42l43_hp_ilimit(int irq, void *data)
203 {
204 struct cs42l43_codec *priv = data;
205 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(priv->component);
206 struct cs42l43 *cs42l43 = priv->core;
207
208 dev_dbg(priv->dev, "headphone ilimit IRQ\n");
209
210 snd_soc_dapm_mutex_lock(dapm);
211
212 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) {
213 if (!priv->hp_ilimit_count)
214 queue_delayed_work(system_dfl_wq, &priv->hp_ilimit_clear_work,
215 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
216
217 priv->hp_ilimit_count++;
218 snd_soc_dapm_mutex_unlock(dapm);
219 return IRQ_HANDLED;
220 }
221
222 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n",
223 CS42L43_HP_ILIMIT_BACKOFF_MS);
224
225 priv->hp_ilimited = true;
226
227 // No need to wait for disable, as just disabling for a period of time
228 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
229 CS42L43_HP_EN_MASK, 0);
230
231 snd_soc_dapm_mutex_unlock(dapm);
232
233 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS);
234
235 snd_soc_dapm_mutex_lock(dapm);
236
237 if (priv->hp_ena && !priv->load_detect_running) {
238 unsigned long time_left;
239
240 reinit_completion(&priv->hp_startup);
241
242 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
243 CS42L43_HP_EN_MASK, priv->hp_ena);
244
245 time_left = wait_for_completion_timeout(&priv->hp_startup,
246 msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS));
247 if (!time_left)
248 dev_err(priv->dev, "ilimit HP restore timed out\n");
249 }
250
251 priv->hp_ilimited = false;
252
253 snd_soc_dapm_mutex_unlock(dapm);
254
255 return IRQ_HANDLED;
256 }
257
258 #define CS42L43_IRQ_COMPLETE(name) \
259 static irqreturn_t cs42l43_##name(int irq, void *data) \
260 { \
261 struct cs42l43_codec *priv = data; \
262 dev_dbg(priv->dev, #name " completed\n"); \
263 complete(&priv->name); \
264 return IRQ_HANDLED; \
265 }
266
267 CS42L43_IRQ_COMPLETE(pll_ready)
CS42L43_IRQ_COMPLETE(hp_startup)268 CS42L43_IRQ_COMPLETE(hp_startup)
269 CS42L43_IRQ_COMPLETE(hp_shutdown)
270 CS42L43_IRQ_COMPLETE(type_detect)
271 CS42L43_IRQ_COMPLETE(spkr_shutdown)
272 CS42L43_IRQ_COMPLETE(spkl_shutdown)
273 CS42L43_IRQ_COMPLETE(spkr_startup)
274 CS42L43_IRQ_COMPLETE(spkl_startup)
275 CS42L43_IRQ_COMPLETE(load_detect)
276
277 static irqreturn_t cs42l43_mic_shutter(int irq, void *data)
278 {
279 struct cs42l43_codec *priv = data;
280 struct snd_soc_component *component = priv->component;
281 int i;
282
283 dev_dbg(priv->dev, "Microphone shutter changed\n");
284
285 if (!component)
286 return IRQ_NONE;
287
288 for (i = 1; i < ARRAY_SIZE(priv->kctl); i++) {
289 if (!priv->kctl[i])
290 return IRQ_NONE;
291
292 snd_ctl_notify(component->card->snd_card,
293 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[i]->id);
294 }
295
296 return IRQ_HANDLED;
297 }
298
cs42l43_spk_shutter(int irq,void * data)299 static irqreturn_t cs42l43_spk_shutter(int irq, void *data)
300 {
301 struct cs42l43_codec *priv = data;
302 struct snd_soc_component *component = priv->component;
303
304 dev_dbg(priv->dev, "Speaker shutter changed\n");
305
306 if (!component)
307 return IRQ_NONE;
308
309 if (!priv->kctl[0])
310 return IRQ_NONE;
311
312 snd_ctl_notify(component->card->snd_card,
313 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[0]->id);
314
315 return IRQ_HANDLED;
316 }
317
318 static const unsigned int cs42l43_sample_rates[] = {
319 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000,
320 };
321
322 #define CS42L43_CONSUMER_RATE_MASK 0xFF
323 #define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer
324
325 static const struct snd_pcm_hw_constraint_list cs42l43_constraint = {
326 .count = ARRAY_SIZE(cs42l43_sample_rates),
327 .list = cs42l43_sample_rates,
328 };
329
cs42l43_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)330 static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
331 {
332 struct snd_soc_component *component = dai->component;
333 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
334 struct cs42l43 *cs42l43 = priv->core;
335 int ret;
336 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap,
337 CS42L43_ASP_CLK_CONFIG2,
338 CS42L43_ASP_MASTER_MODE_MASK);
339
340 if (provider)
341 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
342 else
343 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
344
345 if (cs42l43->variant_id == CS42L43_DEVID_VAL && (dai->id == 3 || dai->id == 4)) {
346 ret = snd_pcm_hw_constraint_minmax(substream->runtime,
347 SNDRV_PCM_HW_PARAM_CHANNELS,
348 1, 2);
349 if (ret < 0)
350 return ret;
351 }
352
353 return snd_pcm_hw_constraint_list(substream->runtime, 0,
354 SNDRV_PCM_HW_PARAM_RATE,
355 &priv->constraint);
356 }
357
cs42l43_convert_sample_rate(unsigned int rate)358 static int cs42l43_convert_sample_rate(unsigned int rate)
359 {
360 switch (rate) {
361 case 8000:
362 return 0x11;
363 case 16000:
364 return 0x12;
365 case 24000:
366 return 0x02;
367 case 32000:
368 return 0x13;
369 case 44100:
370 return 0x0B;
371 case 48000:
372 return 0x03;
373 case 96000:
374 return 0x04;
375 case 192000:
376 return 0x05;
377 default:
378 return -EINVAL;
379 }
380 }
381
cs42l43_set_sample_rate(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)382 static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream,
383 struct snd_pcm_hw_params *params,
384 struct snd_soc_dai *dai)
385 {
386 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
387 struct cs42l43 *cs42l43 = priv->core;
388 int ret;
389
390 ret = cs42l43_convert_sample_rate(params_rate(params));
391 if (ret < 0) {
392 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
393 return ret;
394 }
395
396 //FIXME: For now lets just set sample rate 1, this needs expanded in the future
397 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
398 CS42L43_SAMPLE_RATE_MASK, ret);
399
400 return 0;
401 }
402
cs42l43_asp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)403 static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream,
404 struct snd_pcm_hw_params *params,
405 struct snd_soc_dai *dai)
406 {
407 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
408 struct cs42l43 *cs42l43 = priv->core;
409 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
410 CS42L43_ASP_FSYNC_MODE_MASK);
411 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
412 CS42L43_ASP_MASTER_MODE_MASK);
413 int n_chans = params_channels(params);
414 int data_width = params_width(params);
415 int n_slots = n_chans;
416 int slot_width = data_width;
417 int frame, bclk_target, i;
418 unsigned int reg;
419 int *slots;
420
421 if (priv->n_slots) {
422 n_slots = priv->n_slots;
423 slot_width = priv->slot_width;
424 }
425
426 if (!dsp_mode && (n_slots & 0x1)) {
427 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
428 n_slots++;
429 }
430
431 frame = n_slots * slot_width;
432 bclk_target = params_rate(params) * frame;
433
434 if (provider) {
435 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK);
436 int n = bclk_target / gcd_nm;
437 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm;
438
439 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) ||
440 m > CS42L43_ASP_BCLK_M_MASK) {
441 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
442 return -EINVAL;
443 }
444
445 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
446 n, m, bclk_target, n_slots, slot_width);
447
448 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
449 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK,
450 n << CS42L43_ASP_BCLK_N_SHIFT |
451 m << CS42L43_ASP_BCLK_M_SHIFT);
452 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
453 CS42L43_ASP_FSYNC_M_MASK, frame);
454 }
455
456 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
457 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK,
458 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT);
459
460 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
461 reg = CS42L43_ASP_TX_CH1_CTRL;
462 slots = priv->tx_slots;
463 } else {
464 reg = CS42L43_ASP_RX_CH1_CTRL;
465 slots = priv->rx_slots;
466 }
467
468 for (i = 0; i < n_chans; i++, reg += 4) {
469 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK);
470 int slot_pos;
471
472 if (dsp_mode)
473 slot_pos = slots[i] * slot_width;
474 else
475 slot_pos = (slots[i] / 2) * slot_width;
476
477 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
478 i, slots[i], slot_pos, slot_phase);
479
480 regmap_update_bits(cs42l43->regmap, reg,
481 CS42L43_ASP_CH_WIDTH_MASK |
482 CS42L43_ASP_CH_SLOT_MASK |
483 CS42L43_ASP_CH_SLOT_PHASE_MASK,
484 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
485 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) |
486 slot_phase);
487 }
488
489 return cs42l43_set_sample_rate(substream, params, dai);
490 }
491
cs42l43_asp_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)492 static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
493 {
494 struct snd_soc_component *component = dai->component;
495 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
496 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
497 struct cs42l43 *cs42l43 = priv->core;
498 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
499 CS42L43_ASP_MASTER_MODE_MASK);
500 struct snd_soc_dapm_route routes[] = {
501 { "BCLK", NULL, "FSYNC" },
502 };
503 unsigned int asp_ctrl = 0;
504 unsigned int data_ctrl = 0;
505 unsigned int fsync_ctrl = 0;
506 unsigned int clk_config = 0;
507
508 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
509 case SND_SOC_DAIFMT_DSP_A:
510 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
511 fallthrough;
512 case SND_SOC_DAIFMT_DSP_B:
513 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK;
514 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
515 break;
516 case SND_SOC_DAIFMT_I2S:
517 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
518 break;
519 case SND_SOC_DAIFMT_LEFT_J:
520 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
521 break;
522 default:
523 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
524 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
525 return -EINVAL;
526 }
527
528 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
529 case SND_SOC_DAIFMT_CBC_CFC:
530 if (provider)
531 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
532 break;
533 case SND_SOC_DAIFMT_CBP_CFP:
534 if (!provider)
535 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
536 clk_config |= CS42L43_ASP_MASTER_MODE_MASK;
537 break;
538 default:
539 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
540 fmt & SND_SOC_DAIFMT_MASTER_MASK);
541 return -EINVAL;
542 }
543
544 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
545 case SND_SOC_DAIFMT_NB_NF:
546 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */
547 break;
548 case SND_SOC_DAIFMT_IB_NF:
549 break;
550 case SND_SOC_DAIFMT_NB_IF:
551 clk_config |= CS42L43_ASP_BCLK_INV_MASK;
552 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
553 CS42L43_ASP_FSYNC_OUT_INV_MASK;
554 break;
555 case SND_SOC_DAIFMT_IB_IF:
556 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
557 CS42L43_ASP_FSYNC_OUT_INV_MASK;
558 break;
559 default:
560 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
561 fmt & SND_SOC_DAIFMT_INV_MASK);
562 return -EINVAL;
563 }
564
565 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
566 CS42L43_ASP_FSYNC_MODE_MASK,
567 asp_ctrl);
568 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
569 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK |
570 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK,
571 data_ctrl);
572 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
573 CS42L43_ASP_MASTER_MODE_MASK |
574 CS42L43_ASP_BCLK_INV_MASK,
575 clk_config);
576 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
577 CS42L43_ASP_FSYNC_IN_INV_MASK |
578 CS42L43_ASP_FSYNC_OUT_INV_MASK,
579 fsync_ctrl);
580
581 return 0;
582 }
583
cs42l43_mask_to_slots(struct cs42l43_codec * priv,unsigned long mask,int * slots,unsigned int nslots)584 static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned long mask,
585 int *slots, unsigned int nslots)
586 {
587 int i = 0;
588 int slot;
589
590 for_each_set_bit(slot, &mask, BITS_PER_TYPE(mask)) {
591 if (i == nslots) {
592 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n",
593 mask);
594 return;
595 }
596
597 slots[i++] = slot;
598 }
599
600 }
601
cs42l43_asp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)602 static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
603 unsigned int rx_mask, int slots, int slot_width)
604 {
605 struct snd_soc_component *component = dai->component;
606 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
607
608 priv->n_slots = slots;
609 priv->slot_width = slot_width;
610
611 if (!slots) {
612 tx_mask = CS42L43_DEFAULT_SLOTS;
613 rx_mask = CS42L43_DEFAULT_SLOTS;
614 }
615
616 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots,
617 ARRAY_SIZE(priv->tx_slots));
618 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots,
619 ARRAY_SIZE(priv->rx_slots));
620
621 return 0;
622 }
623
cs42l43_dai_probe(struct snd_soc_dai * dai)624 static int cs42l43_dai_probe(struct snd_soc_dai *dai)
625 {
626 struct snd_soc_component *component = dai->component;
627 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
628 static const char * const controls[] = {
629 "Speaker Digital Switch",
630 "Decimator 1 Switch",
631 "Decimator 2 Switch",
632 "Decimator 3 Switch",
633 "Decimator 4 Switch",
634 "Decimator 5 Switch",
635 "Decimator 6 Switch",
636 };
637 int control_size, i;
638
639 static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl));
640
641 switch (priv->core->variant_id) {
642 case CS42L43_DEVID_VAL:
643 control_size = ARRAY_SIZE(controls) - 2; // ignore Decimator 5 and 6
644 break;
645 case CS42L43B_DEVID_VAL:
646 control_size = ARRAY_SIZE(controls);
647 break;
648 default:
649 return -EINVAL;
650 }
651
652 for (i = 0; i < control_size; i++) {
653 if (priv->kctl[i])
654 continue;
655
656 priv->kctl[i] = snd_soc_component_get_kcontrol(component, controls[i]);
657 }
658
659 return 0;
660 }
661
cs42l43_dai_remove(struct snd_soc_dai * dai)662 static int cs42l43_dai_remove(struct snd_soc_dai *dai)
663 {
664 struct snd_soc_component *component = dai->component;
665 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
666 int i;
667
668 for (i = 0; i < ARRAY_SIZE(priv->kctl); i++)
669 priv->kctl[i] = NULL;
670
671 return 0;
672 }
673
674 static const struct snd_soc_dai_ops cs42l43_asp_ops = {
675 .probe = cs42l43_dai_probe,
676 .remove = cs42l43_dai_remove,
677 .startup = cs42l43_startup,
678 .hw_params = cs42l43_asp_hw_params,
679 .set_fmt = cs42l43_asp_set_fmt,
680 .set_tdm_slot = cs42l43_asp_set_tdm_slot,
681 };
682
cs42l43_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)683 static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream,
684 struct snd_pcm_hw_params *params,
685 struct snd_soc_dai *dai)
686 {
687 int ret;
688
689 ret = cs42l43_sdw_add_peripheral(substream, params, dai);
690 if (ret)
691 return ret;
692
693 return cs42l43_set_sample_rate(substream, params, dai);
694 }
695
696 static const struct snd_soc_dai_ops cs42l43_sdw_ops = {
697 .probe = cs42l43_dai_probe,
698 .remove = cs42l43_dai_remove,
699 .startup = cs42l43_startup,
700 .set_stream = cs42l43_sdw_set_stream,
701 .hw_params = cs42l43_sdw_hw_params,
702 .hw_free = cs42l43_sdw_remove_peripheral,
703 };
704
705 #define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
706 SNDRV_PCM_FMTBIT_S32_LE)
707 #define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
708
709 static struct snd_soc_dai_driver cs42l43_dais[] = {
710 {
711 .name = "cs42l43-asp",
712 .ops = &cs42l43_asp_ops,
713 .symmetric_rate = 1,
714 .capture = {
715 .stream_name = "ASP Capture",
716 .channels_min = 1,
717 .channels_max = CS42L43_ASP_MAX_CHANNELS,
718 .rates = SNDRV_PCM_RATE_KNOT,
719 .formats = CS42L43_ASP_FORMATS,
720 },
721 .playback = {
722 .stream_name = "ASP Playback",
723 .channels_min = 1,
724 .channels_max = CS42L43_ASP_MAX_CHANNELS,
725 .rates = SNDRV_PCM_RATE_KNOT,
726 .formats = CS42L43_ASP_FORMATS,
727 },
728 },
729 {
730 .name = "cs42l43-dp1",
731 .id = 1,
732 .ops = &cs42l43_sdw_ops,
733 .capture = {
734 .stream_name = "DP1 Capture",
735 .channels_min = 1,
736 .channels_max = 4,
737 .rates = SNDRV_PCM_RATE_KNOT,
738 .formats = CS42L43_SDW_FORMATS,
739 },
740 },
741 {
742 .name = "cs42l43-dp2",
743 .id = 2,
744 .ops = &cs42l43_sdw_ops,
745 .capture = {
746 .stream_name = "DP2 Capture",
747 .channels_min = 1,
748 .channels_max = 2,
749 .rates = SNDRV_PCM_RATE_KNOT,
750 .formats = CS42L43_SDW_FORMATS,
751 },
752 },
753 {
754 .name = "cs42l43-dp3",
755 .id = 3,
756 .ops = &cs42l43_sdw_ops,
757 .capture = {
758 .stream_name = "DP3 Capture",
759 .channels_min = 1,
760 .channels_max = 4,
761 .rates = SNDRV_PCM_RATE_KNOT,
762 .formats = CS42L43_SDW_FORMATS,
763 },
764 },
765 {
766 .name = "cs42l43-dp4",
767 .id = 4,
768 .ops = &cs42l43_sdw_ops,
769 .capture = {
770 .stream_name = "DP4 Capture",
771 .channels_min = 1,
772 .channels_max = 4,
773 .rates = SNDRV_PCM_RATE_KNOT,
774 .formats = CS42L43_SDW_FORMATS,
775 },
776 },
777 {
778 .name = "cs42l43-dp5",
779 .id = 5,
780 .ops = &cs42l43_sdw_ops,
781 .playback = {
782 .stream_name = "DP5 Playback",
783 .channels_min = 1,
784 .channels_max = 2,
785 .rates = SNDRV_PCM_RATE_KNOT,
786 .formats = CS42L43_SDW_FORMATS,
787 },
788 },
789 {
790 .name = "cs42l43-dp6",
791 .id = 6,
792 .ops = &cs42l43_sdw_ops,
793 .playback = {
794 .stream_name = "DP6 Playback",
795 .channels_min = 1,
796 .channels_max = 2,
797 .rates = SNDRV_PCM_RATE_KNOT,
798 .formats = CS42L43_SDW_FORMATS,
799 },
800 },
801 {
802 .name = "cs42l43-dp7",
803 .id = 7,
804 .ops = &cs42l43_sdw_ops,
805 .playback = {
806 .stream_name = "DP7 Playback",
807 .channels_min = 1,
808 .channels_max = 2,
809 .rates = SNDRV_PCM_RATE_KNOT,
810 .formats = CS42L43_SDW_FORMATS,
811 },
812 },
813 };
814
815 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
816
817 static const char * const cs42l43_ramp_text[] = {
818 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
819 "15ms/6dB", "30ms/6dB",
820 };
821
822 static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" };
823
824 static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1,
825 CS42L43_ADC_AIN_SEL_SHIFT,
826 cs42l43_adc1_input_text);
827
828 static const struct snd_kcontrol_new cs42l43_adc1_input_ctl =
829 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input);
830
831 static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
832
833 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text);
834 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text);
835
836 static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = {
837 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode),
838 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode),
839 };
840
841 static const char * const cs42l43_pdm_clk_text[] = {
842 "3.072MHz", "1.536MHz", "768kHz",
843 };
844
845 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL,
846 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
847 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL,
848 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
849
850 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
851 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
852
853 static const char * const cs42l43_wnf_corner_text[] = {
854 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz",
855 };
856
857 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
858 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
859 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
860 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
861 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
862 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
863 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
864 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
865 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5,
866 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
867 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_wnf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6,
868 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
869
870 static const char * const cs42l43_hpf_corner_text[] = {
871 "3Hz", "12Hz", "48Hz", "96Hz",
872 };
873
874 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
875 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
876 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
877 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
878 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
879 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
880 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
881 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
882 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL5,
883 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
884 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_hpf_corner, CS42L43B_DECIM_HPF_WNF_CTRL6,
885 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
886
887 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
888 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
889 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
890 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
891 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
892 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
893 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
894 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
895 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
896 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
897 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
898 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
899 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
900 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
901 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
902 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
903
904 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
905 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
906 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec1_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
907 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
908 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
909 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
910 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec2_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
911 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
912 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
913 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
914 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec3_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
915 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
916 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
917 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
918 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec4_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
919 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
920 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
921 CS42L43B_DECIM5_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text);
922 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec5_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
923 CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text);
924 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_up, CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
925 CS42L43B_DECIM6_PATH1_VOL_RISE_RATE_SHIFT, cs42l43_ramp_text);
926 static SOC_ENUM_SINGLE_DECL(cs42l43b_dec6_ramp_down, CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
927 CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_SHIFT, cs42l43_ramp_text);
928
929 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
930
931 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP,
932 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text);
933
934 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP,
935 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text);
936
937 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
938
939 static const char * const cs42l43_headphone_ramp_text[] = {
940 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44",
941 "48", "66", "72",
942 };
943
944 static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL,
945 CS42L43_HP_PATH_VOL_RAMP_SHIFT,
946 cs42l43_headphone_ramp_text);
947
948 static const char * const cs42l43_tone_freq_text[] = {
949 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz",
950 };
951
952 static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL,
953 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
954
955 static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL,
956 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
957
958 static const char * const cs42l43_mixer_texts[] = {
959 "None",
960 "Tone Generator 1", "Tone Generator 2",
961 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4",
962 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
963 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
964 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
965 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
966 "ISRC1 INT1", "ISRC1 INT2",
967 "ISRC1 DEC1", "ISRC1 DEC2",
968 "ISRC2 INT1", "ISRC2 INT2",
969 "ISRC2 DEC1", "ISRC2 DEC2",
970 "EQ1", "EQ2",
971 };
972
973 static const unsigned int cs42l43_mixer_values[] = {
974 0x00, // None
975 0x04, 0x05, // Tone Generator 1, 2
976 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4
977 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
978 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
979 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
980 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
981 0x50, 0x51, // ISRC1 INT1, 2
982 0x52, 0x53, // ISRC1 DEC1, 2
983 0x54, 0x55, // ISRC2 INT1, 2
984 0x56, 0x57, // ISRC2 DEC1, 2
985 0x58, 0x59, // EQ1, 2
986 };
987
988 static const char * const cs42l43b_mixer_texts[] = {
989 "None",
990 "Tone Generator 1", "Tone Generator 2",
991 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", "Decimator 5", "Decimator 6",
992 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
993 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
994 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
995 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
996 "ISRC1 INT1", "ISRC1 INT2",
997 "ISRC1 DEC1", "ISRC1 DEC2", "ISRC1 DEC3", "ISRC1 DEC4",
998 "ISRC2 INT1", "ISRC2 INT2",
999 "ISRC2 DEC1", "ISRC2 DEC2", "ISRC2 DEC3", "ISRC2 DEC4",
1000 "EQ1", "EQ2",
1001 };
1002
1003 static const unsigned int cs42l43b_mixer_values[] = {
1004 0x00, // None
1005 0x04, 0x05, // Tone Generator 1, 2
1006 0x10, 0x11, 0x80, 0x81, 0x12, 0x13, // Decimator 1, 2, 3, 4, 5, 6
1007 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
1008 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
1009 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
1010 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
1011 0x50, 0x51, // ISRC1 INT1, 2
1012 0x52, 0x53, 0x78, 0x79, // ISRC1 DEC1, 2, 3, 4
1013 0x54, 0x55, // ISRC2 INT1, 2
1014 0x56, 0x57, 0x7A, 0x7B, // ISRC2 DEC1, 2, 3, 4
1015 0x58, 0x59, // EQ1, 2
1016 };
1017
1018 /* A variant */
1019 CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT);
1020 CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT);
1021 CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT);
1022 CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT);
1023 CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT);
1024 CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT);
1025
1026 CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
1027 CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
1028 CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
1029 CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
1030 CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
1031 CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
1032 CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
1033 CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
1034 CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
1035 CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
1036
1037 CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1);
1038 CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1);
1039 CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1);
1040 CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1);
1041 CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
1042 CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
1043 CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
1044 CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
1045
1046 CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1);
1047 CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1);
1048 CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
1049 CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
1050 CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1);
1051 CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1);
1052 CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
1053 CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
1054
1055 CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1);
1056 CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1);
1057
1058 CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1);
1059 CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1);
1060
1061 CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1);
1062 CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1);
1063
1064 CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1);
1065 CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1);
1066
1067 /* B variant */
1068 CS42L43B_DECL_MUX(b_asptx1, CS42L43_ASPTX1_INPUT);
1069 CS42L43B_DECL_MUX(b_asptx2, CS42L43_ASPTX2_INPUT);
1070 CS42L43B_DECL_MUX(b_asptx3, CS42L43_ASPTX3_INPUT);
1071 CS42L43B_DECL_MUX(b_asptx4, CS42L43_ASPTX4_INPUT);
1072 CS42L43B_DECL_MUX(b_asptx5, CS42L43_ASPTX5_INPUT);
1073 CS42L43B_DECL_MUX(b_asptx6, CS42L43_ASPTX6_INPUT);
1074
1075 CS42L43B_DECL_MUX(b_dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
1076 CS42L43B_DECL_MUX(b_dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
1077 CS42L43B_DECL_MUX(b_dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
1078 CS42L43B_DECL_MUX(b_dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
1079 CS42L43B_DECL_MUX(b_dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
1080 CS42L43B_DECL_MUX(b_dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
1081 CS42L43B_DECL_MUX(b_dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
1082 CS42L43B_DECL_MUX(b_dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
1083 CS42L43B_DECL_MUX(b_dp3tx3, CS42L43B_SWIRE_DP3_CH3_INPUT);
1084 CS42L43B_DECL_MUX(b_dp3tx4, CS42L43B_SWIRE_DP3_CH4_INPUT);
1085 CS42L43B_DECL_MUX(b_dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
1086 CS42L43B_DECL_MUX(b_dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
1087 CS42L43B_DECL_MUX(b_dp4tx3, CS42L43B_SWIRE_DP4_CH3_INPUT);
1088 CS42L43B_DECL_MUX(b_dp4tx4, CS42L43B_SWIRE_DP4_CH4_INPUT);
1089
1090 CS42L43B_DECL_MUX(b_asrcint1, CS42L43_ASRC_INT1_INPUT1);
1091 CS42L43B_DECL_MUX(b_asrcint2, CS42L43_ASRC_INT2_INPUT1);
1092 CS42L43B_DECL_MUX(b_asrcint3, CS42L43_ASRC_INT3_INPUT1);
1093 CS42L43B_DECL_MUX(b_asrcint4, CS42L43_ASRC_INT4_INPUT1);
1094 CS42L43B_DECL_MUX(b_asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
1095 CS42L43B_DECL_MUX(b_asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
1096 CS42L43B_DECL_MUX(b_asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
1097 CS42L43B_DECL_MUX(b_asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
1098
1099 CS42L43B_DECL_MUX(b_isrc1int1, CS42L43_ISRC1INT1_INPUT1);
1100 CS42L43B_DECL_MUX(b_isrc1int2, CS42L43_ISRC1INT2_INPUT1);
1101 CS42L43B_DECL_MUX(b_isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
1102 CS42L43B_DECL_MUX(b_isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
1103 CS42L43B_DECL_MUX(b_isrc1dec3, CS42L43B_ISRC1DEC3_INPUT1);
1104 CS42L43B_DECL_MUX(b_isrc1dec4, CS42L43B_ISRC1DEC4_INPUT1);
1105 CS42L43B_DECL_MUX(b_isrc2int1, CS42L43_ISRC2INT1_INPUT1);
1106 CS42L43B_DECL_MUX(b_isrc2int2, CS42L43_ISRC2INT2_INPUT1);
1107 CS42L43B_DECL_MUX(b_isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
1108 CS42L43B_DECL_MUX(b_isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
1109 CS42L43B_DECL_MUX(b_isrc2dec3, CS42L43B_ISRC2DEC3_INPUT1);
1110 CS42L43B_DECL_MUX(b_isrc2dec4, CS42L43B_ISRC2DEC4_INPUT1);
1111
1112 CS42L43B_DECL_MUX(b_spdif1, CS42L43_SPDIF1_INPUT1);
1113 CS42L43B_DECL_MUX(b_spdif2, CS42L43_SPDIF2_INPUT1);
1114
1115 CS42L43B_DECL_MIXER(b_eq1, CS42L43_EQ1MIX_INPUT1);
1116 CS42L43B_DECL_MIXER(b_eq2, CS42L43_EQ2MIX_INPUT1);
1117
1118 CS42L43B_DECL_MIXER(b_amp1, CS42L43_AMP1MIX_INPUT1);
1119 CS42L43B_DECL_MIXER(b_amp2, CS42L43_AMP2MIX_INPUT1);
1120
1121 CS42L43B_DECL_MIXER(b_amp3, CS42L43_AMP3MIX_INPUT1);
1122 CS42L43B_DECL_MIXER(b_amp4, CS42L43_AMP4MIX_INPUT1);
1123
cs42l43_dapm_get_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1124 static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol,
1125 struct snd_ctl_elem_value *ucontrol)
1126 {
1127 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1128 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1129 int ret;
1130
1131 snd_soc_dapm_mutex_lock(dapm);
1132 ret = snd_soc_get_volsw(kcontrol, ucontrol);
1133 snd_soc_dapm_mutex_unlock(dapm);
1134
1135 return ret;
1136 }
1137
cs42l43_dapm_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1138 static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol,
1139 struct snd_ctl_elem_value *ucontrol)
1140 {
1141 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1142 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1143 int ret;
1144
1145 snd_soc_dapm_mutex_lock(dapm);
1146 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1147 snd_soc_dapm_mutex_unlock(dapm);
1148
1149 return ret;
1150 }
1151
cs42l43_dapm_get_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1152 static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol,
1153 struct snd_ctl_elem_value *ucontrol)
1154 {
1155 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1156 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1157 int ret;
1158
1159 snd_soc_dapm_mutex_lock(dapm);
1160 ret = snd_soc_get_enum_double(kcontrol, ucontrol);
1161 snd_soc_dapm_mutex_unlock(dapm);
1162
1163 return ret;
1164 }
1165
cs42l43_dapm_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1166 static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol,
1167 struct snd_ctl_elem_value *ucontrol)
1168 {
1169 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1170 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1171 int ret;
1172
1173 snd_soc_dapm_mutex_lock(dapm);
1174 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1175 snd_soc_dapm_mutex_unlock(dapm);
1176
1177 return ret;
1178 }
1179
cs42l43_eq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1180 static int cs42l43_eq_get(struct snd_kcontrol *kcontrol,
1181 struct snd_ctl_elem_value *ucontrol)
1182 {
1183 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1184 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1185
1186 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
1187
1188 return 0;
1189 }
1190
cs42l43_eq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1191 static int cs42l43_eq_put(struct snd_kcontrol *kcontrol,
1192 struct snd_ctl_elem_value *ucontrol)
1193 {
1194 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1195 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1196 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1197
1198 snd_soc_dapm_mutex_lock(dapm);
1199
1200 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
1201
1202 snd_soc_dapm_mutex_unlock(dapm);
1203
1204 return 0;
1205 }
1206
cs42l43_spk_vu_sync(struct cs42l43_codec * priv)1207 static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv)
1208 {
1209 struct cs42l43 *cs42l43 = priv->core;
1210
1211 guard(mutex)(&priv->spk_vu_lock);
1212
1213 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1214 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK);
1215 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1216 CS42L43_AMP1_2_VU_MASK, 0);
1217 }
1218
cs42l43_shutter_get(struct cs42l43_codec * priv,unsigned int shift)1219 static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift)
1220 {
1221 struct cs42l43 *cs42l43 = priv->core;
1222 unsigned int val;
1223 int ret;
1224
1225 ret = pm_runtime_resume_and_get(priv->dev);
1226 if (ret) {
1227 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
1228 return ret;
1229 }
1230
1231 /*
1232 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
1233 * be cached for the non-volatiles, so drop it from the cache here so
1234 * we force a read.
1235 */
1236 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
1237 CS42L43_SHUTTER_CONTROL);
1238 if (ret) {
1239 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
1240 goto error;
1241 }
1242
1243 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
1244 if (ret) {
1245 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
1246 goto error;
1247 }
1248
1249 ret = !(val & BIT(shift));
1250
1251 dev_dbg(priv->dev, "%s shutter is %s\n",
1252 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker",
1253 ret ? "open" : "closed");
1254
1255 error:
1256 pm_runtime_put_autosuspend(priv->dev);
1257
1258 return ret;
1259 }
1260
cs42l43_decim_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1261 static int cs42l43_decim_get(struct snd_kcontrol *kcontrol,
1262 struct snd_ctl_elem_value *ucontrol)
1263 {
1264 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1265 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1266 int ret;
1267
1268 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT);
1269 if (ret > 0)
1270 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol);
1271 else if (!ret)
1272 ucontrol->value.integer.value[0] = ret;
1273
1274 return ret;
1275 }
1276
cs42l43_spk_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1277 static int cs42l43_spk_get(struct snd_kcontrol *kcontrol,
1278 struct snd_ctl_elem_value *ucontrol)
1279 {
1280 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1281 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1282 int ret;
1283
1284 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT);
1285 if (ret > 0)
1286 ret = snd_soc_get_volsw(kcontrol, ucontrol);
1287 else if (!ret)
1288 ucontrol->value.integer.value[0] = ret;
1289
1290 return ret;
1291 }
1292
cs42l43_spk_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1293 static int cs42l43_spk_put(struct snd_kcontrol *kcontrol,
1294 struct snd_ctl_elem_value *ucontrol)
1295 {
1296 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1297 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1298 int ret;
1299
1300 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1301 if (ret > 0)
1302 cs42l43_spk_vu_sync(priv);
1303
1304 return ret;
1305 }
1306
1307 static const struct snd_kcontrol_new cs42l43_controls[] = {
1308 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum,
1309 cs42l43_jack_get, cs42l43_jack_put),
1310
1311 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2,
1312 CS42L43_ADC_PGA_GAIN_SHIFT,
1313 0xF, 4, cs42l43_adc_tlv),
1314
1315 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1316 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0),
1317 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1318 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0),
1319 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk),
1320 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk),
1321
1322 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1323 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1324 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1325 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1326 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1327 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1328 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1329 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1330
1331 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner),
1332 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner),
1333 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner),
1334 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner),
1335
1336 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1337 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1338 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1339 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1340 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1341 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1342 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1343 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1344
1345 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner),
1346 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner),
1347 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner),
1348 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner),
1349
1350 SOC_DOUBLE_R_EXT("Speaker Digital Switch",
1351 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1352 CS42L43_AMP_MUTE_SHIFT, 1, 1,
1353 cs42l43_spk_get, cs42l43_spk_put),
1354
1355 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume",
1356 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1357 CS42L43_AMP_VOL_SHIFT,
1358 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put,
1359 cs42l43_speaker_tlv),
1360
1361 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up),
1362 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down),
1363
1364 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1),
1365 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1),
1366
1367 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL,
1368 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT,
1369 0x11B, 229, cs42l43_headphone_tlv),
1370
1371 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1,
1372 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0),
1373
1374 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL,
1375 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0),
1376 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL,
1377 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0),
1378 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp),
1379
1380 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1),
1381 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1),
1382
1383 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq),
1384 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq),
1385
1386 SOC_DOUBLE_EXT("EQ Switch",
1387 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT,
1388 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1,
1389 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw),
1390
1391 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS,
1392 cs42l43_eq_get, cs42l43_eq_put),
1393
1394 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1),
1395 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1),
1396 };
1397
cs42l43_eq_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1398 static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w,
1399 struct snd_kcontrol *kcontrol, int event)
1400 {
1401 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1402 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1403 struct cs42l43 *cs42l43 = priv->core;
1404 unsigned int val;
1405 int i, ret;
1406
1407 switch (event) {
1408 case SND_SOC_DAPM_PRE_PMU:
1409 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1410 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK,
1411 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK);
1412
1413 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1414 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK);
1415
1416 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++)
1417 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1418 priv->eq_coeffs[i]);
1419
1420 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1421 CS42L43_WRITE_MODE_MASK, 0);
1422
1423 return 0;
1424 case SND_SOC_DAPM_POST_PMU:
1425 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1426 val, (val & CS42L43_INITIALIZE_DONE_MASK),
1427 2000, 10000);
1428 if (ret)
1429 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1430
1431 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1432 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0);
1433 return ret;
1434 default:
1435 return 0;
1436 }
1437 }
1438
1439 struct cs42l43_pll_config {
1440 unsigned int freq;
1441
1442 unsigned int div;
1443 unsigned int mode;
1444 unsigned int cal;
1445 };
1446
1447 static const struct cs42l43_pll_config cs42l43_pll_configs[] = {
1448 { 2400000, 0x50000000, 0x1, 0xA4 },
1449 { 3000000, 0x40000000, 0x1, 0x83 },
1450 { 3072000, 0x40000000, 0x3, 0x80 },
1451 };
1452
cs42l43_set_pll(struct cs42l43_codec * priv,unsigned int src,unsigned int freq)1453 static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src,
1454 unsigned int freq)
1455 {
1456 struct cs42l43 *cs42l43 = priv->core;
1457
1458 lockdep_assert_held(&cs42l43->pll_lock);
1459
1460 if (priv->refclk_src == src && priv->refclk_freq == freq)
1461 return 0;
1462
1463 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1464 dev_err(priv->dev, "PLL active, can't change configuration\n");
1465 return -EBUSY;
1466 }
1467
1468 switch (src) {
1469 case CS42L43_SYSCLK_MCLK:
1470 case CS42L43_SYSCLK_SDW:
1471 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1472 src ? "SoundWire" : "MCLK", freq);
1473
1474 priv->refclk_src = src;
1475 priv->refclk_freq = freq;
1476
1477 return 0;
1478 default:
1479 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1480 return -EINVAL;
1481 }
1482 }
1483
cs42l43_enable_pll(struct cs42l43_codec * priv)1484 static int cs42l43_enable_pll(struct cs42l43_codec *priv)
1485 {
1486 static const struct reg_sequence enable_seq[] = {
1487 { CS42L43_OSC_DIV_SEL, 0x0, },
1488 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, },
1489 };
1490 struct cs42l43 *cs42l43 = priv->core;
1491 const struct cs42l43_pll_config *config = NULL;
1492 unsigned int div = 0;
1493 unsigned int freq = priv->refclk_freq;
1494 unsigned long time_left;
1495
1496 lockdep_assert_held(&cs42l43->pll_lock);
1497
1498 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1499 if (!freq)
1500 freq = cs42l43->sdw_freq;
1501 else if (!cs42l43->sdw_freq)
1502 cs42l43->sdw_freq = freq;
1503 }
1504
1505 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1506
1507 div = fls(freq) -
1508 fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
1509 freq >>= div;
1510
1511 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
1512 int i;
1513
1514 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) {
1515 if (freq == cs42l43_pll_configs[i].freq) {
1516 config = &cs42l43_pll_configs[i];
1517 break;
1518 }
1519 }
1520 }
1521
1522 if (!config) {
1523 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1524 return -EINVAL;
1525 }
1526
1527 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1528 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK,
1529 div << CS42L43_PLL_REFCLK_DIV_SHIFT |
1530 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1531 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
1532 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1533 CS42L43_PLL_MODE_BYPASS_500_MASK |
1534 CS42L43_PLL_MODE_BYPASS_1029_MASK,
1535 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1536 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
1537 CS42L43_PLL_CAL_RATIO_MASK, config->cal);
1538 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1539 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK);
1540
1541 reinit_completion(&priv->pll_ready);
1542
1543 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1544 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK);
1545
1546 time_left = wait_for_completion_timeout(&priv->pll_ready,
1547 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS));
1548 if (!time_left) {
1549 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1550 CS42L43_PLL_EN_MASK, 0);
1551 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1552 CS42L43_PLL_REFCLK_EN_MASK, 0);
1553
1554 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1555 return -ETIMEDOUT;
1556 }
1557
1558 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1559 cs42l43->sdw_pll_active = true;
1560
1561 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1562
1563 /*
1564 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL,
1565 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole
1566 * change over happens under the regmap lock to prevent any reads.
1567 */
1568 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
1569
1570 return 0;
1571 }
1572
cs42l43_disable_pll(struct cs42l43_codec * priv)1573 static int cs42l43_disable_pll(struct cs42l43_codec *priv)
1574 {
1575 static const struct reg_sequence disable_seq[] = {
1576 { CS42L43_MCLK_SRC_SEL, 0x0, 5, },
1577 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, },
1578 };
1579 struct cs42l43 *cs42l43 = priv->core;
1580
1581 dev_dbg(priv->dev, "Disabling PLL\n");
1582
1583 lockdep_assert_held(&cs42l43->pll_lock);
1584
1585 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
1586 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
1587 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1588 CS42L43_PLL_REFCLK_EN_MASK, 0);
1589
1590 cs42l43->sdw_pll_active = false;
1591
1592 return 0;
1593 }
1594
cs42l43_pll_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1595 static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w,
1596 struct snd_kcontrol *kcontrol, int event)
1597 {
1598 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1599 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1600 struct cs42l43 *cs42l43 = priv->core;
1601 int ret;
1602
1603 guard(mutex)(&cs42l43->pll_lock);
1604
1605 switch (event) {
1606 case SND_SOC_DAPM_PRE_PMU:
1607 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1608 ret = clk_prepare_enable(priv->mclk);
1609 if (ret) {
1610 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1611 break;
1612 }
1613 }
1614
1615 ret = cs42l43_enable_pll(priv);
1616 break;
1617 case SND_SOC_DAPM_POST_PMD:
1618 ret = cs42l43_disable_pll(priv);
1619
1620 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1621 clk_disable_unprepare(priv->mclk);
1622 break;
1623 default:
1624 ret = 0;
1625 break;
1626 }
1627
1628 return ret;
1629 }
1630
cs42l43_dapm_wait_completion(struct completion * pmu,struct completion * pmd,int event,int timeout_ms)1631 static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd,
1632 int event, int timeout_ms)
1633 {
1634 unsigned long time_left;
1635
1636 switch (event) {
1637 case SND_SOC_DAPM_PRE_PMU:
1638 reinit_completion(pmu);
1639 return 0;
1640 case SND_SOC_DAPM_PRE_PMD:
1641 reinit_completion(pmd);
1642 return 0;
1643 case SND_SOC_DAPM_POST_PMU:
1644 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms));
1645 break;
1646 case SND_SOC_DAPM_POST_PMD:
1647 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms));
1648 break;
1649 default:
1650 return 0;
1651 }
1652
1653 if (!time_left)
1654 return -ETIMEDOUT;
1655 else
1656 return 0;
1657 }
1658
cs42l43_spkr_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1659 static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w,
1660 struct snd_kcontrol *kcontrol, int event)
1661 {
1662 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1663 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1664
1665 return cs42l43_dapm_wait_completion(&priv->spkr_startup,
1666 &priv->spkr_shutdown, event,
1667 CS42L43_SPK_TIMEOUT_MS);
1668 }
1669
cs42l43_spkl_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1670 static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w,
1671 struct snd_kcontrol *kcontrol, int event)
1672 {
1673 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1674 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1675
1676 return cs42l43_dapm_wait_completion(&priv->spkl_startup,
1677 &priv->spkl_shutdown, event,
1678 CS42L43_SPK_TIMEOUT_MS);
1679 }
1680
cs42l43_hp_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1681 static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w,
1682 struct snd_kcontrol *kcontrol, int event)
1683 {
1684 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1685 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1686 struct cs42l43 *cs42l43 = priv->core;
1687 unsigned int mask = 1 << w->shift;
1688 unsigned int val = 0;
1689 int ret;
1690
1691 switch (event) {
1692 case SND_SOC_DAPM_PRE_PMU:
1693 val = mask;
1694 fallthrough;
1695 case SND_SOC_DAPM_PRE_PMD:
1696 priv->hp_ena &= ~mask;
1697 priv->hp_ena |= val;
1698
1699 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1700 &priv->hp_shutdown, event,
1701 CS42L43_HP_TIMEOUT_MS);
1702 if (ret)
1703 return ret;
1704
1705 if (!priv->load_detect_running && !priv->hp_ilimited)
1706 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
1707 mask, val);
1708 break;
1709 case SND_SOC_DAPM_POST_PMU:
1710 case SND_SOC_DAPM_POST_PMD:
1711 if (priv->load_detect_running || priv->hp_ilimited)
1712 break;
1713
1714 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1715 &priv->hp_shutdown, event,
1716 CS42L43_HP_TIMEOUT_MS);
1717 if (ret)
1718 return ret;
1719 break;
1720 default:
1721 break;
1722 }
1723
1724 return 0;
1725 }
1726
cs42l43_mic_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1727 static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w,
1728 struct snd_kcontrol *kcontrol, int event)
1729 {
1730 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1731 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1732 struct cs42l43 *cs42l43 = priv->core;
1733 unsigned int reg, ramp, mute;
1734 unsigned int *val;
1735 int ret;
1736
1737 if (cs42l43->variant_id == CS42L43_DEVID_VAL) {
1738 switch (w->shift) {
1739 case CS42L43_ADC1_EN_SHIFT:
1740 case CS42L43_PDM1_DIN_L_EN_SHIFT:
1741 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1742 ramp = CS42L43_DECIM1_VD_RAMP_MASK;
1743 mute = CS42L43_DECIM1_MUTE_MASK;
1744 val = &priv->decim_cache[0];
1745 break;
1746 case CS42L43_ADC2_EN_SHIFT:
1747 case CS42L43_PDM1_DIN_R_EN_SHIFT:
1748 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1749 ramp = CS42L43_DECIM2_VD_RAMP_MASK;
1750 mute = CS42L43_DECIM2_MUTE_MASK;
1751 val = &priv->decim_cache[1];
1752 break;
1753 case CS42L43_PDM2_DIN_L_EN_SHIFT:
1754 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1755 ramp = CS42L43_DECIM3_VD_RAMP_MASK;
1756 mute = CS42L43_DECIM3_MUTE_MASK;
1757 val = &priv->decim_cache[2];
1758 break;
1759 case CS42L43_PDM2_DIN_R_EN_SHIFT:
1760 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1761 ramp = CS42L43_DECIM4_VD_RAMP_MASK;
1762 mute = CS42L43_DECIM4_MUTE_MASK;
1763 val = &priv->decim_cache[3];
1764 break;
1765 default:
1766 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1767 return -EINVAL;
1768 }
1769 } else if (cs42l43->variant_id == CS42L43B_DEVID_VAL) {
1770 switch (w->shift) {
1771 case CS42L43_ADC1_EN_SHIFT:
1772 reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2;
1773 ramp = CS42L43_DECIM1_VD_RAMP_MASK;
1774 mute = CS42L43_DECIM1_MUTE_MASK;
1775 val = &priv->decim_cache[0];
1776 break;
1777 case CS42L43_ADC2_EN_SHIFT:
1778 reg = CS42L43B_DECIM_VOL_CTRL_CH1_CH2;
1779 ramp = CS42L43_DECIM2_VD_RAMP_MASK;
1780 mute = CS42L43_DECIM2_MUTE_MASK;
1781 val = &priv->decim_cache[1];
1782 break;
1783 case CS42L43_PDM1_DIN_L_EN_SHIFT:
1784 reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4;
1785 ramp = CS42L43_DECIM3_VD_RAMP_MASK;
1786 mute = CS42L43_DECIM3_MUTE_MASK;
1787 val = &priv->decim_cache[2];
1788 break;
1789 case CS42L43_PDM1_DIN_R_EN_SHIFT:
1790 reg = CS42L43B_DECIM_VOL_CTRL_CH3_CH4;
1791 ramp = CS42L43_DECIM4_VD_RAMP_MASK;
1792 mute = CS42L43_DECIM4_MUTE_MASK;
1793 val = &priv->decim_cache[3];
1794 break;
1795 case CS42L43_PDM2_DIN_L_EN_SHIFT:
1796 reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6;
1797 ramp = CS42L43B_DECIM5_PATH1_VOL_FALL_RATE_MASK;
1798 mute = CS42L43B_DECIM5_MUTE_MASK;
1799 val = &priv->decim_cache[4];
1800 break;
1801 case CS42L43_PDM2_DIN_R_EN_SHIFT:
1802 reg = CS42L43B_DECIM_VOL_CTRL_CH5_CH6;
1803 ramp = CS42L43B_DECIM6_PATH1_VOL_FALL_RATE_MASK;
1804 mute = CS42L43B_DECIM6_MUTE_MASK;
1805 val = &priv->decim_cache[5];
1806 break;
1807 default:
1808 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1809 return -EINVAL;
1810 }
1811 } else {
1812 return -EINVAL;
1813 }
1814
1815 switch (event) {
1816 case SND_SOC_DAPM_PRE_PMU:
1817 ret = regmap_read(cs42l43->regmap, reg, val);
1818 if (ret) {
1819 dev_err(priv->dev,
1820 "Failed to cache decimator settings: %d\n",
1821 ret);
1822 return ret;
1823 }
1824
1825 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
1826 break;
1827 case SND_SOC_DAPM_POST_PMU:
1828 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
1829 break;
1830 default:
1831 break;
1832 }
1833
1834 return 0;
1835 }
1836
cs42l43_adc_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1837 static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w,
1838 struct snd_kcontrol *kcontrol, int event)
1839 {
1840 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1841 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1842 struct cs42l43 *cs42l43 = priv->core;
1843 unsigned int mask = 1 << w->shift;
1844 unsigned int val = 0;
1845 int ret;
1846
1847 ret = cs42l43_mic_ev(w, kcontrol, event);
1848 if (ret)
1849 return ret;
1850
1851 switch (event) {
1852 case SND_SOC_DAPM_PRE_PMU:
1853 val = mask;
1854 fallthrough;
1855 case SND_SOC_DAPM_PRE_PMD:
1856 priv->adc_ena &= ~mask;
1857 priv->adc_ena |= val;
1858
1859 if (!priv->load_detect_running)
1860 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
1861 mask, val);
1862 fallthrough;
1863 default:
1864 return 0;
1865 }
1866 }
1867
1868 static const struct snd_soc_dapm_widget cs42l43_widgets[] = {
1869 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev,
1870 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1871
1872 SND_SOC_DAPM_INPUT("ADC1_IN1_P"),
1873 SND_SOC_DAPM_INPUT("ADC1_IN1_N"),
1874 SND_SOC_DAPM_INPUT("ADC1_IN2_P"),
1875 SND_SOC_DAPM_INPUT("ADC1_IN2_N"),
1876 SND_SOC_DAPM_INPUT("ADC2_IN_P"),
1877 SND_SOC_DAPM_INPUT("ADC2_IN_N"),
1878
1879 SND_SOC_DAPM_INPUT("PDM1_DIN"),
1880 SND_SOC_DAPM_INPUT("PDM2_DIN"),
1881
1882 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl),
1883
1884 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0,
1885 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1886 SND_SOC_DAPM_PRE_PMD),
1887 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0,
1888 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1889 SND_SOC_DAPM_PRE_PMD),
1890
1891 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT,
1892 0, NULL, 0, cs42l43_mic_ev,
1893 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1894 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT,
1895 0, NULL, 0, cs42l43_mic_ev,
1896 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1897 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT,
1898 0, NULL, 0, cs42l43_mic_ev,
1899 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1900 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT,
1901 0, NULL, 0, cs42l43_mic_ev,
1902 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1903
1904 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0),
1908
1909 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT,
1910 0, NULL, 0),
1911 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT,
1912 0, NULL, 0),
1913
1914 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0,
1915 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0),
1916 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1,
1917 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0),
1918 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2,
1919 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0),
1920 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3,
1921 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0),
1922 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4,
1923 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0),
1924 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5,
1925 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0),
1926
1927 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0,
1928 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0),
1929 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1,
1930 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0),
1931 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2,
1932 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0),
1933 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3,
1934 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0),
1935 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4,
1936 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0),
1937 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5,
1938 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0),
1939
1940 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1941 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1942 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
1943 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
1944
1945 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1946 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1947
1948 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1949 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1950
1951 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1952 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1953
1954 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1955 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1956
1957 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1958 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1959
1960 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1961 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1962
1963 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1964
1965 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0,
1966 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1967 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1968 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0,
1969 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1970 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1971
1972 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"),
1973 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"),
1974 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"),
1975 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"),
1976
1977 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
1978 0, NULL, 0),
1979 SND_SOC_DAPM_OUTPUT("SPDIF_TX"),
1980
1981 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0,
1982 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1983 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1984 SND_SOC_DAPM_OUTPUT("AMP3_OUT"),
1985 SND_SOC_DAPM_OUTPUT("AMP4_OUT"),
1986
1987 SND_SOC_DAPM_SIGGEN("Tone"),
1988 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT,
1989 0, NULL, 0),
1990 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL,
1991 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1992 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL,
1993 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1994
1995 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT,
1996 0, NULL, 0),
1997 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT,
1998 0, NULL, 0),
1999
2000 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL,
2001 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
2002 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL,
2003 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
2004 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL,
2005 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
2006 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL,
2007 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
2008
2009 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL,
2010 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
2011 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL,
2012 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
2013 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL,
2014 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
2015 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL,
2016 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
2017
2018 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4,
2019 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0),
2020 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4,
2021 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0),
2022
2023 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES,
2024 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0),
2025 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES,
2026 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0),
2027 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES,
2028 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0),
2029 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES,
2030 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0),
2031 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES,
2032 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0),
2033 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES,
2034 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0),
2035 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES,
2036 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0),
2037 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES,
2038 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0),
2039
2040 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT,
2041 0, NULL, 0),
2042 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT,
2043 0, NULL, 0, cs42l43_eq_ev,
2044 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2045
2046 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT,
2047 0, NULL, 0),
2048 };
2049
2050 static const struct snd_soc_dapm_route cs42l43_routes[] = {
2051 { "ADC1_IN1_P", NULL, "PLL" },
2052 { "ADC1_IN1_N", NULL, "PLL" },
2053 { "ADC1_IN2_P", NULL, "PLL" },
2054 { "ADC1_IN2_N", NULL, "PLL" },
2055 { "ADC2_IN_P", NULL, "PLL" },
2056 { "ADC2_IN_N", NULL, "PLL" },
2057 { "PDM1_DIN", NULL, "PLL" },
2058 { "PDM2_DIN", NULL, "PLL" },
2059 { "AMP1_OUT_P", NULL, "PLL" },
2060 { "AMP1_OUT_N", NULL, "PLL" },
2061 { "AMP2_OUT_P", NULL, "PLL" },
2062 { "AMP2_OUT_N", NULL, "PLL" },
2063 { "SPDIF_TX", NULL, "PLL" },
2064 { "HP", NULL, "PLL" },
2065 { "AMP3_OUT", NULL, "PLL" },
2066 { "AMP4_OUT", NULL, "PLL" },
2067 { "Tone 1", NULL, "PLL" },
2068 { "Tone 2", NULL, "PLL" },
2069 { "ASP Playback", NULL, "PLL" },
2070 { "ASP Capture", NULL, "PLL" },
2071 { "DP1 Capture", NULL, "PLL" },
2072 { "DP2 Capture", NULL, "PLL" },
2073 { "DP3 Capture", NULL, "PLL" },
2074 { "DP4 Capture", NULL, "PLL" },
2075 { "DP5 Playback", NULL, "PLL" },
2076 { "DP6 Playback", NULL, "PLL" },
2077 { "DP7 Playback", NULL, "PLL" },
2078
2079 { "ADC1 Input", "IN1", "ADC1_IN1_P" },
2080 { "ADC1 Input", "IN1", "ADC1_IN1_N" },
2081 { "ADC1 Input", "IN2", "ADC1_IN2_P" },
2082 { "ADC1 Input", "IN2", "ADC1_IN2_N" },
2083
2084 { "ADC1", NULL, "ADC1 Input" },
2085 { "ADC2", NULL, "ADC2_IN_P" },
2086 { "ADC2", NULL, "ADC2_IN_N" },
2087
2088 { "PDM1L", NULL, "PDM1_DIN" },
2089 { "PDM1R", NULL, "PDM1_DIN" },
2090 { "PDM2L", NULL, "PDM2_DIN" },
2091 { "PDM2R", NULL, "PDM2_DIN" },
2092
2093 { "ASP Capture", NULL, "ASPTX1" },
2094 { "ASP Capture", NULL, "ASPTX2" },
2095 { "ASP Capture", NULL, "ASPTX3" },
2096 { "ASP Capture", NULL, "ASPTX4" },
2097 { "ASP Capture", NULL, "ASPTX5" },
2098 { "ASP Capture", NULL, "ASPTX6" },
2099 { "ASPTX1", NULL, "BCLK" },
2100 { "ASPTX2", NULL, "BCLK" },
2101 { "ASPTX3", NULL, "BCLK" },
2102 { "ASPTX4", NULL, "BCLK" },
2103 { "ASPTX5", NULL, "BCLK" },
2104 { "ASPTX6", NULL, "BCLK" },
2105
2106 { "ASPRX1", NULL, "ASP Playback" },
2107 { "ASPRX2", NULL, "ASP Playback" },
2108 { "ASPRX3", NULL, "ASP Playback" },
2109 { "ASPRX4", NULL, "ASP Playback" },
2110 { "ASPRX5", NULL, "ASP Playback" },
2111 { "ASPRX6", NULL, "ASP Playback" },
2112 { "ASPRX1", NULL, "BCLK" },
2113 { "ASPRX2", NULL, "BCLK" },
2114 { "ASPRX3", NULL, "BCLK" },
2115 { "ASPRX4", NULL, "BCLK" },
2116 { "ASPRX5", NULL, "BCLK" },
2117 { "ASPRX6", NULL, "BCLK" },
2118
2119 { "DP1 Capture", NULL, "DP1TX1" },
2120 { "DP1 Capture", NULL, "DP1TX2" },
2121 { "DP1 Capture", NULL, "DP1TX3" },
2122 { "DP1 Capture", NULL, "DP1TX4" },
2123
2124 { "DP2 Capture", NULL, "DP2TX1" },
2125 { "DP2 Capture", NULL, "DP2TX2" },
2126
2127 { "DP3 Capture", NULL, "DP3TX1" },
2128 { "DP3 Capture", NULL, "DP3TX2" },
2129
2130 { "DP4 Capture", NULL, "DP4TX1" },
2131 { "DP4 Capture", NULL, "DP4TX2" },
2132
2133 { "DP5RX1", NULL, "DP5 Playback" },
2134 { "DP5RX2", NULL, "DP5 Playback" },
2135
2136 { "DP6RX1", NULL, "DP6 Playback" },
2137 { "DP6RX2", NULL, "DP6 Playback" },
2138
2139 { "DP7RX1", NULL, "DP7 Playback" },
2140 { "DP7RX2", NULL, "DP7 Playback" },
2141
2142 { "AMP1", NULL, "vdd-amp" },
2143 { "AMP2", NULL, "vdd-amp" },
2144
2145 { "AMP1_OUT_P", NULL, "AMP1" },
2146 { "AMP1_OUT_N", NULL, "AMP1" },
2147 { "AMP2_OUT_P", NULL, "AMP2" },
2148 { "AMP2_OUT_N", NULL, "AMP2" },
2149
2150 { "SPDIF_TX", NULL, "SPDIF" },
2151
2152 { "AMP3_OUT", NULL, "HP" },
2153 { "AMP4_OUT", NULL, "HP" },
2154
2155 { "Tone 1", NULL, "Tone" },
2156 { "Tone 1", NULL, "Tone Generator" },
2157 { "Tone 2", NULL, "Tone" },
2158 { "Tone 2", NULL, "Tone Generator" },
2159
2160 { "ISRC1INT2", NULL, "ISRC1" },
2161 { "ISRC1INT1", NULL, "ISRC1" },
2162 { "ISRC1DEC2", NULL, "ISRC1" },
2163 { "ISRC1DEC1", NULL, "ISRC1" },
2164
2165 { "ISRC2INT2", NULL, "ISRC2" },
2166 { "ISRC2INT1", NULL, "ISRC2" },
2167 { "ISRC2DEC2", NULL, "ISRC2" },
2168 { "ISRC2DEC1", NULL, "ISRC2" },
2169
2170 { "ASRC_INT1", NULL, "ASRC_INT" },
2171 { "ASRC_INT2", NULL, "ASRC_INT" },
2172 { "ASRC_INT3", NULL, "ASRC_INT" },
2173 { "ASRC_INT4", NULL, "ASRC_INT" },
2174 { "ASRC_DEC1", NULL, "ASRC_DEC" },
2175 { "ASRC_DEC2", NULL, "ASRC_DEC" },
2176 { "ASRC_DEC3", NULL, "ASRC_DEC" },
2177 { "ASRC_DEC4", NULL, "ASRC_DEC" },
2178
2179 { "EQ", NULL, "EQ Clock" },
2180 };
2181
2182 static const struct snd_kcontrol_new cs42l43_a_controls[] = {
2183 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up,
2184 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2185 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down,
2186 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2187 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up,
2188 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2189 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down,
2190 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2191 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up,
2192 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2193 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down,
2194 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2195 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up,
2196 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2197 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down,
2198 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2199
2200 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
2201 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2202 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
2203 CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
2204 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2205 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
2206 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2207 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
2208 CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
2209 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2210 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
2211 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2212 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
2213 CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
2214 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2215 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
2216 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2217 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
2218 CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
2219 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2220 };
2221
2222 static const struct snd_kcontrol_new cs42l43_b_controls[] = {
2223 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
2224 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2225 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
2226 CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
2227 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2228 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
2229 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2230 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43B_DECIM_VOL_CTRL_CH1_CH2,
2231 CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
2232 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2233 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
2234 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2235 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
2236 CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
2237 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2238 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
2239 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2240 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43B_DECIM_VOL_CTRL_CH3_CH4,
2241 CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
2242 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2243 SOC_SINGLE_TLV("Decimator 5 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
2244 CS42L43B_DECIM5_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2245 SOC_SINGLE_EXT("Decimator 5 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
2246 CS42L43B_DECIM5_MUTE_SHIFT, 1, 1,
2247 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2248 SOC_SINGLE_TLV("Decimator 6 Volume", CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
2249 CS42L43B_DECIM6_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
2250 SOC_SINGLE_EXT("Decimator 6 Switch", CS42L43B_DECIM_VOL_CTRL_CH5_CH6,
2251 CS42L43B_DECIM6_MUTE_SHIFT, 1, 1,
2252 cs42l43_decim_get, cs42l43_dapm_put_volsw),
2253
2254 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43b_dec1_ramp_up,
2255 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2256 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43b_dec1_ramp_down,
2257 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2258 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43b_dec2_ramp_up,
2259 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2260 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43b_dec2_ramp_down,
2261 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2262 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43b_dec3_ramp_up,
2263 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2264 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43b_dec3_ramp_down,
2265 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2266 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43b_dec4_ramp_up,
2267 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2268 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43b_dec4_ramp_down,
2269 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2270 SOC_ENUM_EXT("Decimator 5 Ramp Up", cs42l43b_dec5_ramp_up,
2271 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2272 SOC_ENUM_EXT("Decimator 5 Ramp Down", cs42l43b_dec5_ramp_down,
2273 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2274 SOC_ENUM_EXT("Decimator 6 Ramp Up", cs42l43b_dec6_ramp_up,
2275 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2276 SOC_ENUM_EXT("Decimator 6 Ramp Down", cs42l43b_dec6_ramp_down,
2277 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
2278
2279 SOC_SINGLE("Decimator 5 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5,
2280 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
2281 SOC_SINGLE("Decimator 6 WNF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6,
2282 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
2283
2284 SOC_ENUM("Decimator 5 WNF Corner Frequency", cs42l43b_dec5_wnf_corner),
2285 SOC_ENUM("Decimator 6 WNF Corner Frequency", cs42l43b_dec6_wnf_corner),
2286
2287 SOC_SINGLE("Decimator 5 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL5,
2288 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
2289 SOC_SINGLE("Decimator 6 HPF Switch", CS42L43B_DECIM_HPF_WNF_CTRL6,
2290 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
2291
2292 SOC_ENUM("Decimator 5 HPF Corner Frequency", cs42l43b_dec5_hpf_corner),
2293 SOC_ENUM("Decimator 6 HPF Corner Frequency", cs42l43b_dec6_hpf_corner),
2294 };
2295
2296 static const struct snd_soc_dapm_widget cs42l43_a_widgets[] = {
2297 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0,
2298 &cs42l43_dec_mode_ctl[0]),
2299 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0,
2300 &cs42l43_dec_mode_ctl[1]),
2301 CS42L43_DAPM_MUX("ASPTX1", asptx1),
2302 CS42L43_DAPM_MUX("ASPTX2", asptx2),
2303 CS42L43_DAPM_MUX("ASPTX3", asptx3),
2304 CS42L43_DAPM_MUX("ASPTX4", asptx4),
2305 CS42L43_DAPM_MUX("ASPTX5", asptx5),
2306 CS42L43_DAPM_MUX("ASPTX6", asptx6),
2307
2308 CS42L43_DAPM_MUX("DP1TX1", dp1tx1),
2309 CS42L43_DAPM_MUX("DP1TX2", dp1tx2),
2310 CS42L43_DAPM_MUX("DP1TX3", dp1tx3),
2311 CS42L43_DAPM_MUX("DP1TX4", dp1tx4),
2312 CS42L43_DAPM_MUX("DP2TX1", dp2tx1),
2313 CS42L43_DAPM_MUX("DP2TX2", dp2tx2),
2314 CS42L43_DAPM_MUX("DP3TX1", dp3tx1),
2315 CS42L43_DAPM_MUX("DP3TX2", dp3tx2),
2316 CS42L43_DAPM_MUX("DP4TX1", dp4tx1),
2317 CS42L43_DAPM_MUX("DP4TX2", dp4tx2),
2318
2319 CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
2320 CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
2321 CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
2322 CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
2323 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
2324 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
2325 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
2326 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
2327
2328 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1),
2329 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2),
2330 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1),
2331 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2),
2332 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1),
2333 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2),
2334 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1),
2335 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2),
2336
2337 CS42L43_DAPM_MUX("SPDIF1", spdif1),
2338 CS42L43_DAPM_MUX("SPDIF2", spdif2),
2339
2340 CS42L43_DAPM_MIXER("EQ1", eq1),
2341 CS42L43_DAPM_MIXER("EQ2", eq2),
2342
2343 CS42L43_DAPM_MIXER("Speaker L", amp1),
2344 CS42L43_DAPM_MIXER("Speaker R", amp2),
2345
2346 CS42L43_DAPM_MIXER("Headphone L", amp3),
2347 CS42L43_DAPM_MIXER("Headphone R", amp4),
2348 };
2349
2350 static const struct snd_soc_dapm_widget cs42l43_b_widgets[] = {
2351 SND_SOC_DAPM_AIF_OUT("DP3TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
2352 SND_SOC_DAPM_AIF_OUT("DP3TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
2353 SND_SOC_DAPM_AIF_OUT("DP4TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
2354 SND_SOC_DAPM_AIF_OUT("DP4TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
2355
2356 SND_SOC_DAPM_PGA("Decimator 5", SND_SOC_NOPM, 0, 0, NULL, 0),
2357 SND_SOC_DAPM_PGA("Decimator 6", SND_SOC_NOPM, 0, 0, NULL, 0),
2358
2359 SND_SOC_DAPM_PGA("ISRC1DEC3", CS42L43_ISRC1_CTRL,
2360 CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0),
2361 SND_SOC_DAPM_PGA("ISRC1DEC4", CS42L43_ISRC1_CTRL,
2362 CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0),
2363 SND_SOC_DAPM_PGA("ISRC2DEC3", CS42L43_ISRC2_CTRL,
2364 CS42L43B_ISRC_DEC3_EN_SHIFT, 0, NULL, 0),
2365 SND_SOC_DAPM_PGA("ISRC2DEC4", CS42L43_ISRC2_CTRL,
2366 CS42L43B_ISRC_DEC4_EN_SHIFT, 0, NULL, 0),
2367
2368 CS42L43_DAPM_MUX("ASPTX1", b_asptx1),
2369 CS42L43_DAPM_MUX("ASPTX2", b_asptx2),
2370 CS42L43_DAPM_MUX("ASPTX3", b_asptx3),
2371 CS42L43_DAPM_MUX("ASPTX4", b_asptx4),
2372 CS42L43_DAPM_MUX("ASPTX5", b_asptx5),
2373 CS42L43_DAPM_MUX("ASPTX6", b_asptx6),
2374
2375 CS42L43_DAPM_MUX("DP1TX1", b_dp1tx1),
2376 CS42L43_DAPM_MUX("DP1TX2", b_dp1tx2),
2377 CS42L43_DAPM_MUX("DP1TX3", b_dp1tx3),
2378 CS42L43_DAPM_MUX("DP1TX4", b_dp1tx4),
2379 CS42L43_DAPM_MUX("DP2TX1", b_dp2tx1),
2380 CS42L43_DAPM_MUX("DP2TX2", b_dp2tx2),
2381 CS42L43_DAPM_MUX("DP3TX1", b_dp3tx1),
2382 CS42L43_DAPM_MUX("DP3TX2", b_dp3tx2),
2383 CS42L43_DAPM_MUX("DP3TX3", b_dp3tx3),
2384 CS42L43_DAPM_MUX("DP3TX4", b_dp3tx4),
2385 CS42L43_DAPM_MUX("DP4TX1", b_dp4tx1),
2386 CS42L43_DAPM_MUX("DP4TX2", b_dp4tx2),
2387 CS42L43_DAPM_MUX("DP4TX3", b_dp4tx3),
2388 CS42L43_DAPM_MUX("DP4TX4", b_dp4tx4),
2389
2390 CS42L43_DAPM_MUX("ASRC INT1", b_asrcint1),
2391 CS42L43_DAPM_MUX("ASRC INT2", b_asrcint2),
2392 CS42L43_DAPM_MUX("ASRC INT3", b_asrcint3),
2393 CS42L43_DAPM_MUX("ASRC INT4", b_asrcint4),
2394 CS42L43_DAPM_MUX("ASRC DEC1", b_asrcdec1),
2395 CS42L43_DAPM_MUX("ASRC DEC2", b_asrcdec2),
2396 CS42L43_DAPM_MUX("ASRC DEC3", b_asrcdec3),
2397 CS42L43_DAPM_MUX("ASRC DEC4", b_asrcdec4),
2398
2399 CS42L43_DAPM_MUX("ISRC1INT1", b_isrc1int1),
2400 CS42L43_DAPM_MUX("ISRC1INT2", b_isrc1int2),
2401 CS42L43_DAPM_MUX("ISRC1DEC1", b_isrc1dec1),
2402 CS42L43_DAPM_MUX("ISRC1DEC2", b_isrc1dec2),
2403 CS42L43_DAPM_MUX("ISRC1DEC3", b_isrc1dec3),
2404 CS42L43_DAPM_MUX("ISRC1DEC4", b_isrc1dec4),
2405 CS42L43_DAPM_MUX("ISRC2INT1", b_isrc2int1),
2406 CS42L43_DAPM_MUX("ISRC2INT2", b_isrc2int2),
2407 CS42L43_DAPM_MUX("ISRC2DEC1", b_isrc2dec1),
2408 CS42L43_DAPM_MUX("ISRC2DEC2", b_isrc2dec2),
2409 CS42L43_DAPM_MUX("ISRC2DEC3", b_isrc2dec3),
2410 CS42L43_DAPM_MUX("ISRC2DEC4", b_isrc2dec4),
2411
2412 CS42L43_DAPM_MUX("SPDIF1", b_spdif1),
2413 CS42L43_DAPM_MUX("SPDIF2", b_spdif2),
2414
2415 CS42L43_DAPM_MIXER("EQ1", b_eq1),
2416 CS42L43_DAPM_MIXER("EQ2", b_eq2),
2417
2418 CS42L43_DAPM_MIXER("Speaker L", b_amp1),
2419 CS42L43_DAPM_MIXER("Speaker R", b_amp2),
2420
2421 CS42L43_DAPM_MIXER("Headphone L", b_amp3),
2422 CS42L43_DAPM_MIXER("Headphone R", b_amp4),
2423 };
2424
2425 static const struct snd_soc_dapm_route cs42l43_a_routes[] = {
2426 { "Decimator 1 Mode", "PDM", "PDM1L" },
2427 { "Decimator 1 Mode", "ADC", "ADC1" },
2428 { "Decimator 2 Mode", "PDM", "PDM1R" },
2429 { "Decimator 2 Mode", "ADC", "ADC2" },
2430
2431 { "Decimator 1", NULL, "Decimator 1 Mode" },
2432 { "Decimator 2", NULL, "Decimator 2 Mode" },
2433 { "Decimator 3", NULL, "PDM2L" },
2434 { "Decimator 4", NULL, "PDM2R" },
2435
2436 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"),
2437 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"),
2438 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"),
2439 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"),
2440 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"),
2441 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"),
2442
2443 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"),
2444 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"),
2445 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"),
2446 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"),
2447 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"),
2448 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"),
2449 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"),
2450 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"),
2451 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"),
2452 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"),
2453
2454 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
2455 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
2456 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
2457 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
2458 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
2459 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
2460 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
2461 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
2462
2463 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2464 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2465 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2466 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2467 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2468 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2469 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2470 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2471
2472 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
2473 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
2474
2475 CS42L43_MIXER_ROUTES("EQ1", "EQ"),
2476 CS42L43_MIXER_ROUTES("EQ2", "EQ"),
2477
2478 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"),
2479 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"),
2480
2481 CS42L43_MIXER_ROUTES("Headphone L", "HP"),
2482 CS42L43_MIXER_ROUTES("Headphone R", "HP"),
2483 };
2484
2485 static const struct snd_soc_dapm_route cs42l43_b_routes[] = {
2486 { "Decimator 1", NULL, "ADC1" },
2487 { "Decimator 2", NULL, "ADC2" },
2488 { "Decimator 3", NULL, "PDM1L" },
2489 { "Decimator 4", NULL, "PDM1R" },
2490 { "Decimator 5", NULL, "PDM2L" },
2491 { "Decimator 6", NULL, "PDM2R" },
2492
2493 { "DP3 Capture", NULL, "DP3TX3" },
2494 { "DP3 Capture", NULL, "DP3TX4" },
2495 { "DP4 Capture", NULL, "DP4TX3" },
2496 { "DP4 Capture", NULL, "DP4TX4" },
2497
2498 { "ISRC1DEC3", NULL, "ISRC1" },
2499 { "ISRC1DEC4", NULL, "ISRC1" },
2500 { "ISRC2DEC3", NULL, "ISRC2" },
2501 { "ISRC2DEC4", NULL, "ISRC2" },
2502
2503 CS42L43B_MUX_ROUTES("ASPTX1", "ASPTX1"),
2504 CS42L43B_MUX_ROUTES("ASPTX2", "ASPTX2"),
2505 CS42L43B_MUX_ROUTES("ASPTX3", "ASPTX3"),
2506 CS42L43B_MUX_ROUTES("ASPTX4", "ASPTX4"),
2507 CS42L43B_MUX_ROUTES("ASPTX5", "ASPTX5"),
2508 CS42L43B_MUX_ROUTES("ASPTX6", "ASPTX6"),
2509
2510 CS42L43B_MUX_ROUTES("DP1TX1", "DP1TX1"),
2511 CS42L43B_MUX_ROUTES("DP1TX2", "DP1TX2"),
2512 CS42L43B_MUX_ROUTES("DP1TX3", "DP1TX3"),
2513 CS42L43B_MUX_ROUTES("DP1TX4", "DP1TX4"),
2514 CS42L43B_MUX_ROUTES("DP2TX1", "DP2TX1"),
2515 CS42L43B_MUX_ROUTES("DP2TX2", "DP2TX2"),
2516 CS42L43B_MUX_ROUTES("DP3TX1", "DP3TX1"),
2517 CS42L43B_MUX_ROUTES("DP3TX2", "DP3TX2"),
2518 CS42L43B_MUX_ROUTES("DP3TX3", "DP3TX3"),
2519 CS42L43B_MUX_ROUTES("DP3TX4", "DP3TX4"),
2520 CS42L43B_MUX_ROUTES("DP4TX1", "DP4TX1"),
2521 CS42L43B_MUX_ROUTES("DP4TX2", "DP4TX2"),
2522 CS42L43B_MUX_ROUTES("DP4TX3", "DP4TX3"),
2523 CS42L43B_MUX_ROUTES("DP4TX4", "DP4TX4"),
2524
2525 CS42L43B_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
2526 CS42L43B_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
2527 CS42L43B_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
2528 CS42L43B_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
2529 CS42L43B_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
2530 CS42L43B_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
2531 CS42L43B_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
2532 CS42L43B_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
2533
2534 CS42L43B_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2535 CS42L43B_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2536 CS42L43B_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2537 CS42L43B_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2538 CS42L43B_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"),
2539 CS42L43B_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"),
2540 CS42L43B_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2541 CS42L43B_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2542 CS42L43B_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2543 CS42L43B_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2544 CS42L43B_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"),
2545 CS42L43B_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"),
2546
2547 CS42L43B_MUX_ROUTES("SPDIF1", "SPDIF"),
2548 CS42L43B_MUX_ROUTES("SPDIF2", "SPDIF"),
2549
2550 CS42L43B_MIXER_ROUTES("EQ1", "EQ"),
2551 CS42L43B_MIXER_ROUTES("EQ2", "EQ"),
2552
2553 CS42L43B_MIXER_ROUTES("Speaker L", "AMP1"),
2554 CS42L43B_MIXER_ROUTES("Speaker R", "AMP2"),
2555
2556 CS42L43B_MIXER_ROUTES("Headphone L", "HP"),
2557 CS42L43B_MIXER_ROUTES("Headphone R", "HP"),
2558 };
2559
cs42l43_set_sysclk(struct snd_soc_component * component,int clk_id,int src,unsigned int freq,int dir)2560 static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id,
2561 int src, unsigned int freq, int dir)
2562 {
2563 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2564 struct cs42l43 *cs42l43 = priv->core;
2565
2566 guard(mutex)(&cs42l43->pll_lock);
2567
2568 return cs42l43_set_pll(priv, src, freq);
2569 }
2570
cs42l43_component_probe(struct snd_soc_component * component)2571 static int cs42l43_component_probe(struct snd_soc_component *component)
2572 {
2573 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
2574 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2575 unsigned int num_controls, num_widgets, num_routes;
2576 const struct snd_soc_dapm_widget *widgets;
2577 const struct snd_kcontrol_new *controls;
2578 const struct snd_soc_dapm_route *routes;
2579 struct cs42l43 *cs42l43 = priv->core;
2580 int ret;
2581
2582 snd_soc_component_init_regmap(component, cs42l43->regmap);
2583
2584 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots,
2585 ARRAY_SIZE(priv->tx_slots));
2586 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots,
2587 ARRAY_SIZE(priv->rx_slots));
2588
2589 priv->component = component;
2590 priv->constraint = cs42l43_constraint;
2591
2592 switch (cs42l43->variant_id) {
2593 case CS42L43_DEVID_VAL:
2594 controls = cs42l43_a_controls;
2595 num_controls = ARRAY_SIZE(cs42l43_a_controls);
2596 widgets = cs42l43_a_widgets;
2597 num_widgets = ARRAY_SIZE(cs42l43_a_widgets);
2598 routes = cs42l43_a_routes;
2599 num_routes = ARRAY_SIZE(cs42l43_a_routes);
2600 break;
2601 case CS42L43B_DEVID_VAL:
2602 controls = cs42l43_b_controls;
2603 num_controls = ARRAY_SIZE(cs42l43_b_controls);
2604 widgets = cs42l43_b_widgets;
2605 num_widgets = ARRAY_SIZE(cs42l43_b_widgets);
2606 routes = cs42l43_b_routes;
2607 num_routes = ARRAY_SIZE(cs42l43_b_routes);
2608 break;
2609 default:
2610 return -EINVAL;
2611 }
2612
2613 ret = snd_soc_add_component_controls(component, controls, num_controls);
2614 if (ret)
2615 return ret;
2616
2617 ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
2618 if (ret)
2619 return ret;
2620
2621 ret = snd_soc_dapm_add_routes(dapm, routes, num_routes);
2622 if (ret)
2623 return ret;
2624
2625 return 0;
2626 }
2627
cs42l43_component_remove(struct snd_soc_component * component)2628 static void cs42l43_component_remove(struct snd_soc_component *component)
2629 {
2630 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2631
2632 cs42l43_set_jack(priv->component, NULL, NULL);
2633
2634 cancel_delayed_work_sync(&priv->bias_sense_timeout);
2635 cancel_delayed_work_sync(&priv->tip_sense_work);
2636
2637 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work);
2638
2639 priv->component = NULL;
2640 }
2641
2642 static const struct snd_soc_component_driver cs42l43_component_drv = {
2643 .name = "cs42l43-codec",
2644
2645 .probe = cs42l43_component_probe,
2646 .remove = cs42l43_component_remove,
2647 .set_sysclk = cs42l43_set_sysclk,
2648 .set_jack = cs42l43_set_jack,
2649
2650 .endianness = 1,
2651
2652 .controls = cs42l43_controls,
2653 .num_controls = ARRAY_SIZE(cs42l43_controls),
2654 .dapm_widgets = cs42l43_widgets,
2655 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets),
2656 .dapm_routes = cs42l43_routes,
2657 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes),
2658 };
2659
2660 struct cs42l43_irq {
2661 unsigned int irq;
2662 const char *name;
2663 irq_handler_t handler;
2664 };
2665
2666 static const struct cs42l43_irq cs42l43_irqs[] = {
2667 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock },
2668 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready },
2669 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup },
2670 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown },
2671 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect },
2672 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense },
2673 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense },
2674 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press },
2675 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release },
2676 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp },
2677 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop },
2678 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop },
2679 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out },
2680 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out },
2681 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown },
2682 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown },
2683 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup },
2684 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup },
2685 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown },
2686 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown },
2687 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm },
2688 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm },
2689 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect },
2690 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect },
2691 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit },
2692 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect },
2693 };
2694
cs42l43_request_irq(struct cs42l43_codec * priv,const char * const name,unsigned int irq,irq_handler_t handler,unsigned long flags)2695 static int cs42l43_request_irq(struct cs42l43_codec *priv,
2696 const char * const name, unsigned int irq,
2697 irq_handler_t handler, unsigned long flags)
2698 {
2699 int ret;
2700
2701 ret = irq_create_mapping(priv->dom, irq);
2702 if (ret < 0)
2703 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
2704
2705 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2706
2707 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
2708 IRQF_ONESHOT | flags, name, priv);
2709 if (ret)
2710 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
2711
2712 return 0;
2713 }
2714
cs42l43_disable_irq(struct cs42l43_codec * priv,unsigned int irq)2715 static void cs42l43_disable_irq(struct cs42l43_codec *priv, unsigned int irq)
2716 {
2717 int ret;
2718
2719 ret = irq_find_mapping(priv->dom, irq);
2720 if (ret > 0)
2721 disable_irq(ret);
2722 }
2723
cs42l43_enable_irq(struct cs42l43_codec * priv,unsigned int irq)2724 static void cs42l43_enable_irq(struct cs42l43_codec *priv, unsigned int irq)
2725 {
2726 int ret;
2727
2728 ret = irq_find_mapping(priv->dom, irq);
2729 if (ret > 0)
2730 enable_irq(ret);
2731 }
2732
cs42l43_shutter_irq(struct cs42l43_codec * priv,unsigned int shutter,const char * const open_name,unsigned int * open_irq,const char * const close_name,unsigned int * close_irq,irq_handler_t handler)2733 static int cs42l43_shutter_irq(struct cs42l43_codec *priv, unsigned int shutter,
2734 const char * const open_name, unsigned int *open_irq,
2735 const char * const close_name, unsigned int *close_irq,
2736 irq_handler_t handler)
2737 {
2738 int ret;
2739
2740 switch (shutter) {
2741 case 0x1:
2742 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2743 return 0;
2744 case 0x2:
2745 *open_irq = CS42L43_GPIO1_RISE;
2746 *close_irq = CS42L43_GPIO1_FALL;
2747 break;
2748 case 0x4:
2749 *open_irq = CS42L43_GPIO2_RISE;
2750 *close_irq = CS42L43_GPIO2_FALL;
2751 break;
2752 case 0x8:
2753 *open_irq = CS42L43_GPIO3_RISE;
2754 *close_irq = CS42L43_GPIO3_FALL;
2755 break;
2756 default:
2757 return 0;
2758 }
2759
2760 ret = cs42l43_request_irq(priv, close_name, *close_irq, handler, IRQF_SHARED);
2761 if (ret)
2762 return ret;
2763
2764 return cs42l43_request_irq(priv, open_name, *open_irq, handler, IRQF_SHARED);
2765 }
2766
cs42l43_codec_probe(struct platform_device * pdev)2767 static int cs42l43_codec_probe(struct platform_device *pdev)
2768 {
2769 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
2770 struct cs42l43_codec *priv;
2771 unsigned int val;
2772 int i, ret;
2773
2774 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2775 if (!priv)
2776 return -ENOMEM;
2777
2778 priv->dev = &pdev->dev;
2779 priv->core = cs42l43;
2780
2781 priv->dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
2782 if (!priv->dom)
2783 return -EPROBE_DEFER;
2784
2785 platform_set_drvdata(pdev, priv);
2786
2787 mutex_init(&priv->jack_lock);
2788 mutex_init(&priv->spk_vu_lock);
2789
2790 init_completion(&priv->hp_startup);
2791 init_completion(&priv->hp_shutdown);
2792 init_completion(&priv->spkr_shutdown);
2793 init_completion(&priv->spkl_shutdown);
2794 init_completion(&priv->spkr_startup);
2795 init_completion(&priv->spkl_startup);
2796 init_completion(&priv->pll_ready);
2797 init_completion(&priv->type_detect);
2798 init_completion(&priv->load_detect);
2799
2800 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2801 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2802 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work);
2803
2804 pm_runtime_set_autosuspend_delay(priv->dev, 100);
2805 pm_runtime_use_autosuspend(priv->dev);
2806 pm_runtime_set_active(priv->dev);
2807 pm_runtime_get_noresume(priv->dev);
2808
2809 ret = devm_pm_runtime_enable(priv->dev);
2810 if (ret)
2811 goto err_pm;
2812
2813 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) {
2814 ret = cs42l43_request_irq(priv, cs42l43_irqs[i].name,
2815 cs42l43_irqs[i].irq,
2816 cs42l43_irqs[i].handler, 0);
2817 if (ret)
2818 goto err_pm;
2819 }
2820
2821 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
2822 if (ret) {
2823 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2824 goto err_pm;
2825 }
2826
2827 ret = cs42l43_shutter_irq(priv, val & CS42L43_MIC_SHUTTER_CFG_MASK,
2828 "mic shutter open", &priv->shutter_irqs[0],
2829 "mic shutter close", &priv->shutter_irqs[1],
2830 cs42l43_mic_shutter);
2831 if (ret)
2832 goto err_pm;
2833
2834 ret = cs42l43_shutter_irq(priv, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >>
2835 CS42L43_SPK_SHUTTER_CFG_SHIFT,
2836 "spk shutter open", &priv->shutter_irqs[2],
2837 "spk shutter close", &priv->shutter_irqs[3],
2838 cs42l43_spk_shutter);
2839 if (ret)
2840 goto err_pm;
2841
2842 // Don't use devm as we need to get against the MFD device
2843 priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
2844 if (IS_ERR(priv->mclk)) {
2845 ret = PTR_ERR(priv->mclk);
2846 dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
2847 goto err_pm;
2848 }
2849
2850 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
2851 cs42l43_dais, ARRAY_SIZE(cs42l43_dais));
2852 if (ret) {
2853 dev_err_probe(priv->dev, ret, "Failed to register component\n");
2854 goto err_clk;
2855 }
2856
2857 pm_runtime_put_autosuspend(priv->dev);
2858
2859 return 0;
2860
2861 err_clk:
2862 clk_put(priv->mclk);
2863 err_pm:
2864 pm_runtime_put_sync(priv->dev);
2865
2866 return ret;
2867 }
2868
cs42l43_codec_remove(struct platform_device * pdev)2869 static void cs42l43_codec_remove(struct platform_device *pdev)
2870 {
2871 struct cs42l43_codec *priv = platform_get_drvdata(pdev);
2872
2873 clk_put(priv->mclk);
2874 }
2875
cs42l43_codec_runtime_resume(struct device * dev)2876 static int cs42l43_codec_runtime_resume(struct device *dev)
2877 {
2878 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2879
2880 dev_dbg(priv->dev, "Runtime resume\n");
2881
2882 // Toggle the speaker volume update incase the speaker volume was synced
2883 cs42l43_spk_vu_sync(priv);
2884
2885 return 0;
2886 }
2887
cs42l43_codec_suspend(struct device * dev)2888 static int cs42l43_codec_suspend(struct device *dev)
2889 {
2890 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2891 int i;
2892
2893 dev_dbg(priv->dev, "System suspend\n");
2894
2895 priv->suspend_jack_debounce = true;
2896
2897 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++)
2898 cs42l43_disable_irq(priv, cs42l43_irqs[i].irq);
2899
2900 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++)
2901 if (priv->shutter_irqs[i])
2902 cs42l43_disable_irq(priv, priv->shutter_irqs[i]);
2903
2904 cancel_delayed_work_sync(&priv->bias_sense_timeout);
2905 cancel_delayed_work_sync(&priv->tip_sense_work);
2906 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work);
2907
2908 cs42l43_clear_jack(priv);
2909
2910 return pm_runtime_force_suspend(dev);
2911 }
2912
cs42l43_codec_resume(struct device * dev)2913 static int cs42l43_codec_resume(struct device *dev)
2914 {
2915 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2916 int ret, i;
2917
2918 ret = pm_runtime_force_resume(dev);
2919 if (ret)
2920 return ret;
2921
2922 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++)
2923 cs42l43_enable_irq(priv, cs42l43_irqs[i].irq);
2924
2925 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++)
2926 if (priv->shutter_irqs[i])
2927 cs42l43_enable_irq(priv, priv->shutter_irqs[i]);
2928
2929 return 0;
2930 }
2931
2932 static const struct dev_pm_ops cs42l43_codec_pm_ops = {
2933 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)
2934 SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume)
2935 };
2936
2937 static const struct platform_device_id cs42l43_codec_id_table[] = {
2938 { .name = "cs42l43-codec" },
2939 { }
2940 };
2941 MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table);
2942
2943 static struct platform_driver cs42l43_codec_driver = {
2944 .driver = {
2945 .name = "cs42l43-codec",
2946 .pm = pm_ptr(&cs42l43_codec_pm_ops),
2947 },
2948
2949 .probe = cs42l43_codec_probe,
2950 .remove = cs42l43_codec_remove,
2951 .id_table = cs42l43_codec_id_table,
2952 };
2953 module_platform_driver(cs42l43_codec_driver);
2954
2955 MODULE_IMPORT_NS("SND_SOC_CS42L43");
2956
2957 MODULE_DESCRIPTION("CS42L43 CODEC Driver");
2958 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
2959 MODULE_LICENSE("GPL");
2960