1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/socket.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/module.h> 34 #include <sys/rman.h> 35 #include <sys/endian.h> 36 #include <sys/sockio.h> 37 #include <sys/priv.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 42 #include <dev/pci/pcireg.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_var.h> 48 #include <net/ethernet.h> 49 #include <net/iflib.h> 50 51 #define WANT_NATIVE_PCI_GET_SLOT 52 #include <linux/pci.h> 53 #include <linux/kmod.h> 54 #include <linux/module.h> 55 #include <linux/delay.h> 56 #include <linux/idr.h> 57 #include <linux/netdevice.h> 58 #include <linux/etherdevice.h> 59 #include <linux/rcupdate.h> 60 #include "opt_inet.h" 61 #include "opt_inet6.h" 62 #include "opt_rss.h" 63 64 #include "ifdi_if.h" 65 66 #include "bnxt.h" 67 #include "bnxt_hwrm.h" 68 #include "bnxt_ioctl.h" 69 #include "bnxt_sysctl.h" 70 #include "hsi_struct_def.h" 71 #include "bnxt_mgmt.h" 72 #include "bnxt_ulp.h" 73 #include "bnxt_auxbus_compat.h" 74 #include "bnxt_log.h" 75 #include "bnxt_log_data.h" 76 #include "bnxt_coredump.h" 77 78 /* 79 * PCI Device ID Table 80 */ 81 82 static const pci_vendor_info_t bnxt_vendor_info_array[] = 83 { 84 PVID(BROADCOM_VENDOR_ID, BCM57301, 85 "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet Controller"), 86 PVID(BROADCOM_VENDOR_ID, BCM57302, 87 "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet Controller"), 88 PVID(BROADCOM_VENDOR_ID, BCM57304, 89 "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet Controller"), 90 PVID(BROADCOM_VENDOR_ID, BCM57311, 91 "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet"), 92 PVID(BROADCOM_VENDOR_ID, BCM57312, 93 "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet"), 94 PVID(BROADCOM_VENDOR_ID, BCM57314, 95 "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet"), 96 PVID(BROADCOM_VENDOR_ID, BCM57402, 97 "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet Controller"), 98 PVID(BROADCOM_VENDOR_ID, BCM57402_NPAR, 99 "Broadcom BCM57402 NetXtreme-E Partition"), 100 PVID(BROADCOM_VENDOR_ID, BCM57404, 101 "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet Controller"), 102 PVID(BROADCOM_VENDOR_ID, BCM57404_NPAR, 103 "Broadcom BCM57404 NetXtreme-E Partition"), 104 PVID(BROADCOM_VENDOR_ID, BCM57406, 105 "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet Controller"), 106 PVID(BROADCOM_VENDOR_ID, BCM57406_NPAR, 107 "Broadcom BCM57406 NetXtreme-E Partition"), 108 PVID(BROADCOM_VENDOR_ID, BCM57407, 109 "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet Controller"), 110 PVID(BROADCOM_VENDOR_ID, BCM57407_NPAR, 111 "Broadcom BCM57407 NetXtreme-E Ethernet Partition"), 112 PVID(BROADCOM_VENDOR_ID, BCM57407_SFP, 113 "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet Controller"), 114 PVID(BROADCOM_VENDOR_ID, BCM57412, 115 "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet"), 116 PVID(BROADCOM_VENDOR_ID, BCM57412_NPAR1, 117 "Broadcom BCM57412 NetXtreme-E Ethernet Partition"), 118 PVID(BROADCOM_VENDOR_ID, BCM57412_NPAR2, 119 "Broadcom BCM57412 NetXtreme-E Ethernet Partition"), 120 PVID(BROADCOM_VENDOR_ID, BCM57414, 121 "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet"), 122 PVID(BROADCOM_VENDOR_ID, BCM57414_NPAR1, 123 "Broadcom BCM57414 NetXtreme-E Ethernet Partition"), 124 PVID(BROADCOM_VENDOR_ID, BCM57414_NPAR2, 125 "Broadcom BCM57414 NetXtreme-E Ethernet Partition"), 126 PVID(BROADCOM_VENDOR_ID, BCM57416, 127 "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet"), 128 PVID(BROADCOM_VENDOR_ID, BCM57416_NPAR1, 129 "Broadcom BCM57416 NetXtreme-E Ethernet Partition"), 130 PVID(BROADCOM_VENDOR_ID, BCM57416_NPAR2, 131 "Broadcom BCM57416 NetXtreme-E Ethernet Partition"), 132 PVID(BROADCOM_VENDOR_ID, BCM57416_SFP, 133 "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet"), 134 PVID(BROADCOM_VENDOR_ID, BCM57417, 135 "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet"), 136 PVID(BROADCOM_VENDOR_ID, BCM57417_NPAR1, 137 "Broadcom BCM57417 NetXtreme-E Ethernet Partition"), 138 PVID(BROADCOM_VENDOR_ID, BCM57417_NPAR2, 139 "Broadcom BCM57417 NetXtreme-E Ethernet Partition"), 140 PVID(BROADCOM_VENDOR_ID, BCM57417_SFP, 141 "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet"), 142 PVID(BROADCOM_VENDOR_ID, BCM57454, 143 "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet"), 144 PVID(BROADCOM_VENDOR_ID, BCM58700, 145 "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet"), 146 PVID(BROADCOM_VENDOR_ID, BCM57508, 147 "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet"), 148 PVID(BROADCOM_VENDOR_ID, BCM57504, 149 "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet"), 150 PVID(BROADCOM_VENDOR_ID, BCM57504_NPAR, 151 "Broadcom BCM57504 NetXtreme-E Ethernet Partition"), 152 PVID(BROADCOM_VENDOR_ID, BCM57502, 153 "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet"), 154 PVID(BROADCOM_VENDOR_ID, BCM57608, 155 "Broadcom BCM57608 NetXtreme-E 25Gb/50Gb/100Gb/200Gb/400Gb Ethernet"), 156 PVID(BROADCOM_VENDOR_ID, BCM57604, 157 "Broadcom BCM57604 NetXtreme-E 25Gb/50Gb/100Gb/200Gb Ethernet"), 158 PVID(BROADCOM_VENDOR_ID, BCM57602, 159 "Broadcom BCM57602 NetXtreme-E 25Gb/50Gb Ethernet"), 160 PVID(BROADCOM_VENDOR_ID, BCM57601, 161 "Broadcom BCM57601 NetXtreme-E 25Gb/50Gb Ethernet"), 162 PVID(BROADCOM_VENDOR_ID, NETXTREME_C_VF1, 163 "Broadcom NetXtreme-C Ethernet Virtual Function"), 164 PVID(BROADCOM_VENDOR_ID, NETXTREME_C_VF2, 165 "Broadcom NetXtreme-C Ethernet Virtual Function"), 166 PVID(BROADCOM_VENDOR_ID, NETXTREME_C_VF3, 167 "Broadcom NetXtreme-C Ethernet Virtual Function"), 168 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF1, 169 "Broadcom NetXtreme-E Ethernet Virtual Function"), 170 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF2, 171 "Broadcom NetXtreme-E Ethernet Virtual Function"), 172 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF3, 173 "Broadcom NetXtreme-E Ethernet Virtual Function"), 174 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF4, 175 "Broadcom NetXtreme-E Ethernet Virtual Function"), 176 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_VF5, 177 "Broadcom NetXtreme-E Ethernet Virtual Function"), 178 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_P5_VF1, 179 "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function"), 180 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_P5_VF2, 181 "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function"), 182 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_P5_VF_HV1, 183 "Broadcom NetXtreme-C Virtual Function for Hyper-V"), 184 PVID(BROADCOM_VENDOR_ID, NETXTREME_E_P5_VF_HV2, 185 "Broadcom NetXtreme-C Virtual Function for Hyper-V"), 186 PVID(BROADCOM_VENDOR_ID, E_P7_VF, 187 "Broadcom BCM5760X Virtual Function"), 188 /* required last entry */ 189 190 PVID_END 191 }; 192 193 /* 194 * Function prototypes 195 */ 196 197 SLIST_HEAD(softc_list, bnxt_softc_list) pf_list; 198 int bnxt_num_pfs = 0; 199 200 void 201 process_nq(struct bnxt_softc *softc, uint16_t nqid); 202 static void *bnxt_register(device_t dev); 203 204 /* Soft queue setup and teardown */ 205 static int bnxt_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, 206 uint64_t *paddrs, int ntxqs, int ntxqsets); 207 static int bnxt_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, 208 uint64_t *paddrs, int nrxqs, int nrxqsets); 209 static void bnxt_queues_free(if_ctx_t ctx); 210 211 /* Device setup and teardown */ 212 static int bnxt_attach_pre(if_ctx_t ctx); 213 static int bnxt_attach_post(if_ctx_t ctx); 214 static int bnxt_detach(if_ctx_t ctx); 215 216 /* Device configuration */ 217 static void bnxt_init(if_ctx_t ctx); 218 static void bnxt_stop(if_ctx_t ctx); 219 static void bnxt_multi_set(if_ctx_t ctx); 220 static int bnxt_mtu_set(if_ctx_t ctx, uint32_t mtu); 221 static void bnxt_media_status(if_ctx_t ctx, struct ifmediareq * ifmr); 222 static int bnxt_media_change(if_ctx_t ctx); 223 static int bnxt_promisc_set(if_ctx_t ctx, int flags); 224 static uint64_t bnxt_get_counter(if_ctx_t, ift_counter); 225 static void bnxt_update_admin_status(if_ctx_t ctx); 226 static void bnxt_if_timer(if_ctx_t ctx, uint16_t qid); 227 228 /* Interrupt enable / disable */ 229 static void bnxt_intr_enable(if_ctx_t ctx); 230 static int bnxt_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid); 231 static int bnxt_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid); 232 static void bnxt_disable_intr(if_ctx_t ctx); 233 static int bnxt_msix_intr_assign(if_ctx_t ctx, int msix); 234 235 /* vlan support */ 236 static void bnxt_vlan_register(if_ctx_t ctx, uint16_t vtag); 237 static void bnxt_vlan_unregister(if_ctx_t ctx, uint16_t vtag); 238 239 /* ioctl */ 240 static int bnxt_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data); 241 242 static int bnxt_shutdown(if_ctx_t ctx); 243 static int bnxt_suspend(if_ctx_t ctx); 244 static int bnxt_resume(if_ctx_t ctx); 245 246 /* Internal support functions */ 247 static int bnxt_probe_phy(struct bnxt_softc *softc); 248 static void bnxt_add_media_types(struct bnxt_softc *softc); 249 static int bnxt_pci_mapping(struct bnxt_softc *softc); 250 static void bnxt_pci_mapping_free(struct bnxt_softc *softc); 251 static int bnxt_update_link(struct bnxt_softc *softc, bool chng_link_state); 252 static int bnxt_handle_def_cp(void *arg); 253 static int bnxt_handle_isr(void *arg); 254 static void bnxt_clear_ids(struct bnxt_softc *softc); 255 static void inline bnxt_do_enable_intr(struct bnxt_cp_ring *cpr); 256 static void inline bnxt_do_disable_intr(struct bnxt_cp_ring *cpr); 257 static void bnxt_mark_cpr_invalid(struct bnxt_cp_ring *cpr); 258 static void bnxt_def_cp_task(void *context, int pending); 259 static void bnxt_handle_async_event(struct bnxt_softc *softc, 260 struct cmpl_base *cmpl); 261 static uint64_t bnxt_get_baudrate(struct bnxt_link_info *link); 262 static void bnxt_get_wol_settings(struct bnxt_softc *softc); 263 static int bnxt_wol_config(if_ctx_t ctx); 264 static bool bnxt_if_needs_restart(if_ctx_t, enum iflib_restart_event); 265 static int bnxt_i2c_req(if_ctx_t ctx, struct ifi2creq *i2c); 266 static void bnxt_get_port_module_status(struct bnxt_softc *softc); 267 static void bnxt_rdma_aux_device_init(struct bnxt_softc *softc); 268 static void bnxt_rdma_aux_device_uninit(struct bnxt_softc *softc); 269 static void bnxt_queue_fw_reset_work(struct bnxt_softc *bp, unsigned long delay); 270 void bnxt_queue_sp_work(struct bnxt_softc *bp); 271 272 void bnxt_fw_reset(struct bnxt_softc *bp); 273 static int bnxt_crash_dump_init(struct bnxt_softc *softc); 274 /* 275 * Device Interface Declaration 276 */ 277 278 static device_method_t bnxt_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_register, bnxt_register), 281 DEVMETHOD(device_probe, iflib_device_probe), 282 DEVMETHOD(device_attach, iflib_device_attach), 283 DEVMETHOD(device_detach, iflib_device_detach), 284 DEVMETHOD(device_shutdown, iflib_device_shutdown), 285 DEVMETHOD(device_suspend, iflib_device_suspend), 286 DEVMETHOD(device_resume, iflib_device_resume), 287 #ifdef PCI_IOV 288 DEVMETHOD(pci_iov_init, iflib_device_iov_init), 289 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit), 290 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf), 291 #endif 292 DEVMETHOD_END 293 }; 294 295 static driver_t bnxt_driver = { 296 "bnxt", bnxt_methods, sizeof(struct bnxt_softc), 297 }; 298 299 DRIVER_MODULE(bnxt, pci, bnxt_driver, 0, 0); 300 301 MODULE_LICENSE("Dual BSD/GPL"); 302 MODULE_DEPEND(if_bnxt, pci, 1, 1, 1); 303 MODULE_DEPEND(if_bnxt, ether, 1, 1, 1); 304 MODULE_DEPEND(if_bnxt, iflib, 1, 1, 1); 305 MODULE_DEPEND(if_bnxt, linuxkpi, 1, 1, 1); 306 MODULE_VERSION(if_bnxt, 1); 307 308 IFLIB_PNP_INFO(pci, bnxt, bnxt_vendor_info_array); 309 310 void writel_fbsd(struct bnxt_softc *bp, u32, u8, u32); 311 u32 readl_fbsd(struct bnxt_softc *bp, u32, u8); 312 313 u32 readl_fbsd(struct bnxt_softc *bp, u32 reg_off, u8 bar_idx) 314 { 315 316 if (!bar_idx) 317 return bus_space_read_4(bp->doorbell_bar.tag, bp->doorbell_bar.handle, reg_off); 318 else 319 return bus_space_read_4(bp->hwrm_bar.tag, bp->hwrm_bar.handle, reg_off); 320 } 321 322 void writel_fbsd(struct bnxt_softc *bp, u32 reg_off, u8 bar_idx, u32 val) 323 { 324 325 if (!bar_idx) 326 bus_space_write_4(bp->doorbell_bar.tag, bp->doorbell_bar.handle, reg_off, htole32(val)); 327 else 328 bus_space_write_4(bp->hwrm_bar.tag, bp->hwrm_bar.handle, reg_off, htole32(val)); 329 } 330 331 static DEFINE_IDA(bnxt_aux_dev_ids); 332 333 static device_method_t bnxt_iflib_methods[] = { 334 DEVMETHOD(ifdi_tx_queues_alloc, bnxt_tx_queues_alloc), 335 DEVMETHOD(ifdi_rx_queues_alloc, bnxt_rx_queues_alloc), 336 DEVMETHOD(ifdi_queues_free, bnxt_queues_free), 337 338 DEVMETHOD(ifdi_attach_pre, bnxt_attach_pre), 339 DEVMETHOD(ifdi_attach_post, bnxt_attach_post), 340 DEVMETHOD(ifdi_detach, bnxt_detach), 341 342 DEVMETHOD(ifdi_init, bnxt_init), 343 DEVMETHOD(ifdi_stop, bnxt_stop), 344 DEVMETHOD(ifdi_multi_set, bnxt_multi_set), 345 DEVMETHOD(ifdi_mtu_set, bnxt_mtu_set), 346 DEVMETHOD(ifdi_media_status, bnxt_media_status), 347 DEVMETHOD(ifdi_media_change, bnxt_media_change), 348 DEVMETHOD(ifdi_promisc_set, bnxt_promisc_set), 349 DEVMETHOD(ifdi_get_counter, bnxt_get_counter), 350 DEVMETHOD(ifdi_update_admin_status, bnxt_update_admin_status), 351 DEVMETHOD(ifdi_timer, bnxt_if_timer), 352 353 DEVMETHOD(ifdi_intr_enable, bnxt_intr_enable), 354 DEVMETHOD(ifdi_tx_queue_intr_enable, bnxt_tx_queue_intr_enable), 355 DEVMETHOD(ifdi_rx_queue_intr_enable, bnxt_rx_queue_intr_enable), 356 DEVMETHOD(ifdi_intr_disable, bnxt_disable_intr), 357 DEVMETHOD(ifdi_msix_intr_assign, bnxt_msix_intr_assign), 358 359 DEVMETHOD(ifdi_vlan_register, bnxt_vlan_register), 360 DEVMETHOD(ifdi_vlan_unregister, bnxt_vlan_unregister), 361 362 DEVMETHOD(ifdi_priv_ioctl, bnxt_priv_ioctl), 363 364 DEVMETHOD(ifdi_suspend, bnxt_suspend), 365 DEVMETHOD(ifdi_shutdown, bnxt_shutdown), 366 DEVMETHOD(ifdi_resume, bnxt_resume), 367 DEVMETHOD(ifdi_i2c_req, bnxt_i2c_req), 368 369 DEVMETHOD(ifdi_needs_restart, bnxt_if_needs_restart), 370 #ifdef PCI_IOV 371 DEVMETHOD(ifdi_iov_init, bnxt_iov_init), 372 DEVMETHOD(ifdi_iov_uninit, bnxt_iov_uninit), 373 DEVMETHOD(ifdi_iov_vf_add, bnxt_iov_vf_add), 374 #endif 375 DEVMETHOD_END 376 }; 377 378 static driver_t bnxt_iflib_driver = { 379 "bnxt", bnxt_iflib_methods, sizeof(struct bnxt_softc) 380 }; 381 382 /* 383 * iflib shared context 384 */ 385 #define BNXT_DRIVER_VERSION "230.0.133.0" 386 const char bnxt_driver_version[] = BNXT_DRIVER_VERSION; 387 388 static char drv_version_msg[] = 389 "Broadcom NetXtreme-C/E Ethernet Driver if_bnxt" \ 390 " v" BNXT_DRIVER_VERSION; 391 392 extern struct if_txrx bnxt_txrx; 393 394 static struct if_shared_ctx bnxt_sctx_template = { 395 .isc_magic = IFLIB_MAGIC, 396 .isc_driver = &bnxt_iflib_driver, 397 .isc_nfl = 2, 398 .isc_flags = IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ | IFLIB_NEED_ETHER_PAD, 399 .isc_q_align = PAGE_SIZE, 400 .isc_tx_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 401 .isc_tx_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 402 .isc_tso_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 403 .isc_tso_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 404 .isc_rx_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 405 .isc_rx_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 406 .isc_rx_nsegments = 1, 407 .isc_ntxqs = 3, 408 .isc_nrxqs = 3, 409 .isc_nrxd_min = {16, 16, 16}, 410 .isc_nrxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 8, 411 PAGE_SIZE / sizeof(struct rx_prod_pkt_bd), 412 PAGE_SIZE / sizeof(struct rx_prod_pkt_bd)}, 413 .isc_nrxd_max = {BNXT_MAX_RXD, BNXT_MAX_RXD, BNXT_MAX_RXD}, 414 .isc_ntxd_min = {16, 16, 16}, 415 .isc_ntxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 2, 416 PAGE_SIZE / sizeof(struct tx_bd_short), 417 PAGE_SIZE / sizeof(struct cmpl_base) * 16}, 418 .isc_ntxd_max = {BNXT_MAX_TXD, BNXT_MAX_TXD, BNXT_MAX_TXD}, 419 .isc_vendor_info = bnxt_vendor_info_array, 420 .isc_driver_version = bnxt_driver_version, 421 }; 422 423 static struct if_shared_ctx bnxt_sctx_template_p7 = { 424 .isc_magic = IFLIB_MAGIC, 425 .isc_driver = &bnxt_iflib_driver, 426 .isc_nfl = 2, 427 .isc_flags = IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ | IFLIB_NEED_ETHER_PAD, 428 .isc_q_align = PAGE_SIZE, 429 .isc_tx_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 430 .isc_tx_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 431 .isc_tso_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 432 .isc_tso_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 433 .isc_rx_maxsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 434 .isc_rx_maxsegsize = BNXT_TSO_SIZE + sizeof(struct ether_vlan_header), 435 .isc_rx_nsegments = 1, 436 .isc_ntxqs = 3, 437 .isc_nrxqs = 3, 438 .isc_nrxd_min = {16, 16, 16}, 439 .isc_nrxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 8, 440 PAGE_SIZE / sizeof(struct rx_prod_pkt_bd), 441 PAGE_SIZE / sizeof(struct rx_prod_pkt_bd)}, 442 .isc_nrxd_max = {BNXT_MAX_RXD, BNXT_MAX_RXD, BNXT_MAX_RXD}, 443 .isc_ntxd_min = {128, 128, 128}, 444 .isc_ntxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 2, 445 PAGE_SIZE / sizeof(struct tx_bd_short), 446 PAGE_SIZE / sizeof(struct cmpl_base) * 16}, 447 .isc_ntxd_max = {BNXT_MAX_TXD, BNXT_MAX_TXD, BNXT_MAX_TXD}, 448 .isc_vendor_info = bnxt_vendor_info_array, 449 .isc_driver_version = bnxt_driver_version, 450 }; 451 452 static struct if_shared_ctx bnxt_sctx_pf_init; 453 static struct if_shared_ctx bnxt_sctx_vf_init; 454 static bool sctx_initialized = false; 455 456 static inline void 457 bnxt_init_sctx_variants(uint16_t device_id) 458 { 459 if (device_id == BCM57608) 460 bnxt_sctx_pf_init = bnxt_sctx_template_p7; 461 else 462 bnxt_sctx_pf_init = bnxt_sctx_template; 463 464 bnxt_sctx_pf_init.isc_admin_intrcnt = BNXT_ROCE_IRQ_COUNT; 465 466 bnxt_sctx_vf_init = bnxt_sctx_template; 467 bnxt_sctx_vf_init.isc_flags |= IFLIB_IS_VF; 468 } 469 470 static inline bool 471 bnxt_is_vf_device(uint16_t device_id) 472 { 473 switch (device_id) { 474 case NETXTREME_C_VF1: 475 case NETXTREME_C_VF2: 476 case NETXTREME_C_VF3: 477 case NETXTREME_E_VF1: 478 case NETXTREME_E_VF2: 479 case NETXTREME_E_VF3: 480 case NETXTREME_E_VF4: 481 case NETXTREME_E_VF5: 482 case NETXTREME_E_P5_VF1: 483 case NETXTREME_E_P5_VF2: 484 case NETXTREME_E_P5_VF_HV1: 485 case NETXTREME_E_P5_VF_HV2: 486 case E_P7_VF: 487 return true; 488 default: 489 return false; 490 } 491 } 492 493 void 494 bnxt_set_flags_by_devid(struct bnxt_softc *softc) 495 { 496 uint16_t device_id = pci_get_device(softc->dev); 497 498 if (bnxt_is_vf_device(device_id)) 499 softc->flags |= BNXT_FLAG_VF; 500 501 switch (device_id) { 502 case BCM57402_NPAR: 503 case BCM57404_NPAR: 504 case BCM57406_NPAR: 505 case BCM57407_NPAR: 506 case BCM57412_NPAR1: 507 case BCM57412_NPAR2: 508 case BCM57414_NPAR1: 509 case BCM57414_NPAR2: 510 case BCM57416_NPAR1: 511 case BCM57416_NPAR2: 512 softc->flags |= BNXT_FLAG_NPAR; 513 break; 514 } 515 } 516 517 #define PCI_SUBSYSTEM_ID 0x2e 518 static struct workqueue_struct *bnxt_pf_wq; 519 520 extern void bnxt_destroy_irq(struct bnxt_softc *softc); 521 522 /* 523 * Device Methods 524 */ 525 526 static void * 527 bnxt_register(device_t dev) 528 { 529 uint16_t vendor_id = pci_get_vendor(dev); 530 uint16_t device_id = pci_get_device(dev); 531 532 if (vendor_id != BROADCOM_VENDOR_ID) 533 return NULL; 534 535 if (!sctx_initialized) { 536 printf("if_bnxt: %s\n", drv_version_msg); 537 sctx_initialized = true; 538 } 539 540 bnxt_init_sctx_variants(device_id); 541 542 if (bnxt_is_vf_device(device_id)) 543 return &bnxt_sctx_vf_init; 544 545 return &bnxt_sctx_pf_init; 546 } 547 548 static void 549 bnxt_nq_alloc(struct bnxt_softc *softc, int nqsets) 550 { 551 552 if (softc->nq_rings) 553 return; 554 555 softc->nq_rings = malloc(sizeof(struct bnxt_cp_ring) * nqsets, 556 M_DEVBUF, M_NOWAIT | M_ZERO); 557 } 558 559 static void 560 bnxt_nq_free(struct bnxt_softc *softc) 561 { 562 563 if (softc->nq_rings) 564 free(softc->nq_rings, M_DEVBUF); 565 softc->nq_rings = NULL; 566 } 567 568 569 static void 570 bnxt_set_db_mask(struct bnxt_softc *bp, struct bnxt_ring *db, 571 u32 ring_type) 572 { 573 if (BNXT_CHIP_P7(bp)) { 574 db->db_epoch_mask = db->db_ring_mask + 1; 575 db->db_epoch_shift = DBR_EPOCH_SFT - ilog2(db->db_epoch_mask); 576 577 } 578 } 579 580 /* 581 * Device Dependent Configuration Functions 582 */ 583 584 /* Soft queue setup and teardown */ 585 static int 586 bnxt_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, 587 uint64_t *paddrs, int ntxqs, int ntxqsets) 588 { 589 struct bnxt_softc *softc; 590 int i; 591 int rc; 592 593 softc = iflib_get_softc(ctx); 594 595 if (BNXT_CHIP_P5_PLUS(softc)) { 596 bnxt_nq_alloc(softc, ntxqsets); 597 if (!softc->nq_rings) { 598 device_printf(iflib_get_dev(ctx), 599 "unable to allocate NQ rings\n"); 600 rc = ENOMEM; 601 goto nq_alloc_fail; 602 } 603 } 604 605 softc->tx_cp_rings = malloc(sizeof(struct bnxt_cp_ring) * ntxqsets, 606 M_DEVBUF, M_NOWAIT | M_ZERO); 607 if (!softc->tx_cp_rings) { 608 device_printf(iflib_get_dev(ctx), 609 "unable to allocate TX completion rings\n"); 610 rc = ENOMEM; 611 goto cp_alloc_fail; 612 } 613 softc->tx_rings = malloc(sizeof(struct bnxt_ring) * ntxqsets, 614 M_DEVBUF, M_NOWAIT | M_ZERO); 615 if (!softc->tx_rings) { 616 device_printf(iflib_get_dev(ctx), 617 "unable to allocate TX rings\n"); 618 rc = ENOMEM; 619 goto ring_alloc_fail; 620 } 621 622 for (i=0; i < ntxqsets; i++) { 623 rc = iflib_dma_alloc(ctx, sizeof(struct ctx_hw_stats), 624 &softc->tx_stats[i], 0); 625 if (rc) 626 goto dma_alloc_fail; 627 bus_dmamap_sync(softc->tx_stats[i].idi_tag, softc->tx_stats[i].idi_map, 628 BUS_DMASYNC_PREREAD); 629 } 630 631 for (i = 0; i < ntxqsets; i++) { 632 /* Set up the completion ring */ 633 softc->tx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; 634 softc->tx_cp_rings[i].ring.phys_id = 635 (uint16_t)HWRM_NA_SIGNATURE; 636 softc->tx_cp_rings[i].ring.softc = softc; 637 softc->tx_cp_rings[i].ring.idx = i; 638 softc->tx_cp_rings[i].ring.id = 639 (softc->scctx->isc_nrxqsets * 2) + 1 + i; 640 softc->tx_cp_rings[i].ring.doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 641 softc->legacy_db_size: softc->tx_cp_rings[i].ring.id * 0x80; 642 softc->tx_cp_rings[i].ring.ring_size = 643 softc->scctx->isc_ntxd[0]; 644 softc->tx_cp_rings[i].ring.db_ring_mask = 645 softc->tx_cp_rings[i].ring.ring_size - 1; 646 softc->tx_cp_rings[i].ring.vaddr = vaddrs[i * ntxqs]; 647 softc->tx_cp_rings[i].ring.paddr = paddrs[i * ntxqs]; 648 649 650 /* Set up the TX ring */ 651 softc->tx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; 652 softc->tx_rings[i].softc = softc; 653 softc->tx_rings[i].idx = i; 654 softc->tx_rings[i].id = 655 (softc->scctx->isc_nrxqsets * 2) + 1 + i; 656 softc->tx_rings[i].doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 657 softc->legacy_db_size : softc->tx_rings[i].id * 0x80; 658 softc->tx_rings[i].ring_size = softc->scctx->isc_ntxd[1]; 659 softc->tx_rings[i].db_ring_mask = softc->tx_rings[i].ring_size - 1; 660 softc->tx_rings[i].vaddr = vaddrs[i * ntxqs + 1]; 661 softc->tx_rings[i].paddr = paddrs[i * ntxqs + 1]; 662 663 bnxt_create_tx_sysctls(softc, i); 664 665 if (BNXT_CHIP_P5_PLUS(softc)) { 666 /* Set up the Notification ring (NQ) */ 667 softc->nq_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; 668 softc->nq_rings[i].ring.phys_id = 669 (uint16_t)HWRM_NA_SIGNATURE; 670 softc->nq_rings[i].ring.softc = softc; 671 softc->nq_rings[i].ring.idx = i; 672 softc->nq_rings[i].ring.id = i; 673 softc->nq_rings[i].ring.doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 674 softc->legacy_db_size : softc->nq_rings[i].ring.id * 0x80; 675 softc->nq_rings[i].ring.ring_size = softc->scctx->isc_ntxd[2]; 676 softc->nq_rings[i].ring.db_ring_mask = softc->nq_rings[i].ring.ring_size - 1; 677 softc->nq_rings[i].ring.vaddr = vaddrs[i * ntxqs + 2]; 678 softc->nq_rings[i].ring.paddr = paddrs[i * ntxqs + 2]; 679 softc->nq_rings[i].type = Q_TYPE_TX; 680 } 681 } 682 683 softc->ntxqsets = ntxqsets; 684 return rc; 685 686 dma_alloc_fail: 687 for (i = i - 1; i >= 0; i--) 688 iflib_dma_free(&softc->tx_stats[i]); 689 free(softc->tx_rings, M_DEVBUF); 690 ring_alloc_fail: 691 free(softc->tx_cp_rings, M_DEVBUF); 692 cp_alloc_fail: 693 bnxt_nq_free(softc); 694 nq_alloc_fail: 695 return rc; 696 } 697 698 static void 699 bnxt_queues_free(if_ctx_t ctx) 700 { 701 struct bnxt_softc *softc = iflib_get_softc(ctx); 702 int i; 703 704 // Free TX queues 705 for (i=0; i<softc->ntxqsets; i++) 706 iflib_dma_free(&softc->tx_stats[i]); 707 free(softc->tx_rings, M_DEVBUF); 708 softc->tx_rings = NULL; 709 free(softc->tx_cp_rings, M_DEVBUF); 710 softc->tx_cp_rings = NULL; 711 softc->ntxqsets = 0; 712 713 // Free RX queues 714 for (i=0; i<softc->nrxqsets; i++) 715 iflib_dma_free(&softc->rx_stats[i]); 716 iflib_dma_free(&softc->hw_tx_port_stats); 717 iflib_dma_free(&softc->hw_rx_port_stats); 718 iflib_dma_free(&softc->hw_tx_port_stats_ext); 719 iflib_dma_free(&softc->hw_rx_port_stats_ext); 720 free(softc->grp_info, M_DEVBUF); 721 free(softc->ag_rings, M_DEVBUF); 722 free(softc->rx_rings, M_DEVBUF); 723 free(softc->rx_cp_rings, M_DEVBUF); 724 bnxt_nq_free(softc); 725 } 726 727 static int 728 bnxt_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, 729 uint64_t *paddrs, int nrxqs, int nrxqsets) 730 { 731 struct bnxt_softc *softc; 732 int i; 733 int rc; 734 735 softc = iflib_get_softc(ctx); 736 737 softc->rx_cp_rings = malloc(sizeof(struct bnxt_cp_ring) * nrxqsets, 738 M_DEVBUF, M_NOWAIT | M_ZERO); 739 if (!softc->rx_cp_rings) { 740 device_printf(iflib_get_dev(ctx), 741 "unable to allocate RX completion rings\n"); 742 rc = ENOMEM; 743 goto cp_alloc_fail; 744 } 745 softc->rx_rings = malloc(sizeof(struct bnxt_ring) * nrxqsets, 746 M_DEVBUF, M_NOWAIT | M_ZERO); 747 if (!softc->rx_rings) { 748 device_printf(iflib_get_dev(ctx), 749 "unable to allocate RX rings\n"); 750 rc = ENOMEM; 751 goto ring_alloc_fail; 752 } 753 softc->ag_rings = malloc(sizeof(struct bnxt_ring) * nrxqsets, 754 M_DEVBUF, M_NOWAIT | M_ZERO); 755 if (!softc->ag_rings) { 756 device_printf(iflib_get_dev(ctx), 757 "unable to allocate aggregation rings\n"); 758 rc = ENOMEM; 759 goto ag_alloc_fail; 760 } 761 softc->grp_info = malloc(sizeof(struct bnxt_grp_info) * nrxqsets, 762 M_DEVBUF, M_NOWAIT | M_ZERO); 763 if (!softc->grp_info) { 764 device_printf(iflib_get_dev(ctx), 765 "unable to allocate ring groups\n"); 766 rc = ENOMEM; 767 goto grp_alloc_fail; 768 } 769 770 for (i=0; i < nrxqsets; i++) { 771 rc = iflib_dma_alloc(ctx, sizeof(struct ctx_hw_stats), 772 &softc->rx_stats[i], 0); 773 if (rc) 774 goto hw_stats_alloc_fail; 775 bus_dmamap_sync(softc->rx_stats[i].idi_tag, softc->rx_stats[i].idi_map, 776 BUS_DMASYNC_PREREAD); 777 } 778 779 /* 780 * Additional 512 bytes for future expansion. 781 * To prevent corruption when loaded with newer firmwares with added counters. 782 * This can be deleted when there will be no further additions of counters. 783 */ 784 #define BNXT_PORT_STAT_PADDING 512 785 786 rc = iflib_dma_alloc(ctx, sizeof(struct rx_port_stats) + BNXT_PORT_STAT_PADDING, 787 &softc->hw_rx_port_stats, 0); 788 if (rc) 789 goto hw_port_rx_stats_alloc_fail; 790 791 bus_dmamap_sync(softc->hw_rx_port_stats.idi_tag, 792 softc->hw_rx_port_stats.idi_map, BUS_DMASYNC_PREREAD); 793 794 795 rc = iflib_dma_alloc(ctx, sizeof(struct tx_port_stats) + BNXT_PORT_STAT_PADDING, 796 &softc->hw_tx_port_stats, 0); 797 if (rc) 798 goto hw_port_tx_stats_alloc_fail; 799 800 bus_dmamap_sync(softc->hw_tx_port_stats.idi_tag, 801 softc->hw_tx_port_stats.idi_map, BUS_DMASYNC_PREREAD); 802 803 softc->rx_port_stats = (void *) softc->hw_rx_port_stats.idi_vaddr; 804 softc->tx_port_stats = (void *) softc->hw_tx_port_stats.idi_vaddr; 805 806 807 rc = iflib_dma_alloc(ctx, sizeof(struct rx_port_stats_ext), 808 &softc->hw_rx_port_stats_ext, 0); 809 if (rc) 810 goto hw_port_rx_stats_ext_alloc_fail; 811 812 bus_dmamap_sync(softc->hw_rx_port_stats_ext.idi_tag, 813 softc->hw_rx_port_stats_ext.idi_map, BUS_DMASYNC_PREREAD); 814 815 rc = iflib_dma_alloc(ctx, sizeof(struct tx_port_stats_ext), 816 &softc->hw_tx_port_stats_ext, 0); 817 if (rc) 818 goto hw_port_tx_stats_ext_alloc_fail; 819 820 bus_dmamap_sync(softc->hw_tx_port_stats_ext.idi_tag, 821 softc->hw_tx_port_stats_ext.idi_map, BUS_DMASYNC_PREREAD); 822 823 softc->rx_port_stats_ext = (void *) softc->hw_rx_port_stats_ext.idi_vaddr; 824 softc->tx_port_stats_ext = (void *) softc->hw_tx_port_stats_ext.idi_vaddr; 825 826 for (i = 0; i < nrxqsets; i++) { 827 /* Allocation the completion ring */ 828 softc->rx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; 829 softc->rx_cp_rings[i].ring.phys_id = 830 (uint16_t)HWRM_NA_SIGNATURE; 831 softc->rx_cp_rings[i].ring.softc = softc; 832 softc->rx_cp_rings[i].ring.idx = i; 833 softc->rx_cp_rings[i].ring.id = i + 1; 834 softc->rx_cp_rings[i].ring.doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 835 softc->legacy_db_size : softc->rx_cp_rings[i].ring.id * 0x80; 836 /* 837 * If this ring overflows, RX stops working. 838 */ 839 softc->rx_cp_rings[i].ring.ring_size = 840 softc->scctx->isc_nrxd[0]; 841 softc->rx_cp_rings[i].ring.db_ring_mask = 842 softc->rx_cp_rings[i].ring.ring_size - 1; 843 844 softc->rx_cp_rings[i].ring.vaddr = vaddrs[i * nrxqs]; 845 softc->rx_cp_rings[i].ring.paddr = paddrs[i * nrxqs]; 846 847 /* Allocate the RX ring */ 848 softc->rx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; 849 softc->rx_rings[i].softc = softc; 850 softc->rx_rings[i].idx = i; 851 softc->rx_rings[i].id = i + 1; 852 softc->rx_rings[i].doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 853 softc->legacy_db_size : softc->rx_rings[i].id * 0x80; 854 softc->rx_rings[i].ring_size = softc->scctx->isc_nrxd[1]; 855 softc->rx_rings[i].db_ring_mask = 856 softc->rx_rings[i].ring_size -1; 857 softc->rx_rings[i].vaddr = vaddrs[i * nrxqs + 1]; 858 softc->rx_rings[i].paddr = paddrs[i * nrxqs + 1]; 859 860 /* Allocate the TPA start buffer */ 861 softc->rx_rings[i].tpa_start = malloc(sizeof(struct bnxt_full_tpa_start) * 862 (RX_TPA_START_CMPL_AGG_ID_MASK >> RX_TPA_START_CMPL_AGG_ID_SFT), 863 M_DEVBUF, M_NOWAIT | M_ZERO); 864 if (softc->rx_rings[i].tpa_start == NULL) { 865 rc = -ENOMEM; 866 device_printf(softc->dev, 867 "Unable to allocate space for TPA\n"); 868 goto tpa_alloc_fail; 869 } 870 /* Allocate the AG ring */ 871 softc->ag_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; 872 softc->ag_rings[i].softc = softc; 873 softc->ag_rings[i].idx = i; 874 softc->ag_rings[i].id = nrxqsets + i + 1; 875 softc->ag_rings[i].doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 876 softc->legacy_db_size : softc->ag_rings[i].id * 0x80; 877 softc->ag_rings[i].ring_size = softc->scctx->isc_nrxd[2]; 878 softc->ag_rings[i].db_ring_mask = softc->ag_rings[i].ring_size - 1; 879 softc->ag_rings[i].vaddr = vaddrs[i * nrxqs + 2]; 880 softc->ag_rings[i].paddr = paddrs[i * nrxqs + 2]; 881 882 /* Allocate the ring group */ 883 softc->grp_info[i].grp_id = (uint16_t)HWRM_NA_SIGNATURE; 884 softc->grp_info[i].stats_ctx = 885 softc->rx_cp_rings[i].stats_ctx_id; 886 softc->grp_info[i].rx_ring_id = softc->rx_rings[i].phys_id; 887 softc->grp_info[i].ag_ring_id = softc->ag_rings[i].phys_id; 888 softc->grp_info[i].cp_ring_id = 889 softc->rx_cp_rings[i].ring.phys_id; 890 891 bnxt_create_rx_sysctls(softc, i); 892 } 893 894 /* 895 * When SR-IOV is enabled, avoid each VF sending PORT_QSTATS 896 * HWRM every sec with which firmware timeouts can happen 897 */ 898 if (BNXT_PF(softc)) 899 bnxt_create_port_stats_sysctls(softc); 900 901 /* And finally, the VNIC */ 902 softc->vnic_info.id = (uint16_t)HWRM_NA_SIGNATURE; 903 softc->vnic_info.filter_id = -1; 904 softc->vnic_info.def_ring_grp = (uint16_t)HWRM_NA_SIGNATURE; 905 softc->vnic_info.cos_rule = (uint16_t)HWRM_NA_SIGNATURE; 906 softc->vnic_info.lb_rule = (uint16_t)HWRM_NA_SIGNATURE; 907 softc->vnic_info.rx_mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST | 908 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN; 909 softc->vnic_info.mc_list_count = 0; 910 softc->vnic_info.flags = BNXT_VNIC_FLAG_DEFAULT; 911 rc = iflib_dma_alloc(ctx, BNXT_MAX_MC_ADDRS * ETHER_ADDR_LEN, 912 &softc->vnic_info.mc_list, 0); 913 if (rc) 914 goto mc_list_alloc_fail; 915 916 /* The VNIC RSS Hash Key */ 917 rc = iflib_dma_alloc(ctx, HW_HASH_KEY_SIZE, 918 &softc->vnic_info.rss_hash_key_tbl, 0); 919 if (rc) 920 goto rss_hash_alloc_fail; 921 bus_dmamap_sync(softc->vnic_info.rss_hash_key_tbl.idi_tag, 922 softc->vnic_info.rss_hash_key_tbl.idi_map, 923 BUS_DMASYNC_PREWRITE); 924 memcpy(softc->vnic_info.rss_hash_key_tbl.idi_vaddr, 925 softc->vnic_info.rss_hash_key, HW_HASH_KEY_SIZE); 926 927 /* Allocate the RSS tables */ 928 rc = iflib_dma_alloc(ctx, HW_HASH_INDEX_SIZE * sizeof(uint16_t), 929 &softc->vnic_info.rss_grp_tbl, 0); 930 if (rc) 931 goto rss_grp_alloc_fail; 932 bus_dmamap_sync(softc->vnic_info.rss_grp_tbl.idi_tag, 933 softc->vnic_info.rss_grp_tbl.idi_map, 934 BUS_DMASYNC_PREWRITE); 935 memset(softc->vnic_info.rss_grp_tbl.idi_vaddr, 0xff, 936 softc->vnic_info.rss_grp_tbl.idi_size); 937 938 softc->nrxqsets = nrxqsets; 939 return rc; 940 941 rss_grp_alloc_fail: 942 iflib_dma_free(&softc->vnic_info.rss_hash_key_tbl); 943 rss_hash_alloc_fail: 944 iflib_dma_free(&softc->vnic_info.mc_list); 945 mc_list_alloc_fail: 946 for (i = i - 1; i >= 0; i--) { 947 if (softc->rx_rings[i].tpa_start) 948 free(softc->rx_rings[i].tpa_start, M_DEVBUF); 949 } 950 tpa_alloc_fail: 951 iflib_dma_free(&softc->hw_tx_port_stats_ext); 952 hw_port_tx_stats_ext_alloc_fail: 953 iflib_dma_free(&softc->hw_rx_port_stats_ext); 954 hw_port_rx_stats_ext_alloc_fail: 955 iflib_dma_free(&softc->hw_tx_port_stats); 956 hw_port_tx_stats_alloc_fail: 957 iflib_dma_free(&softc->hw_rx_port_stats); 958 hw_port_rx_stats_alloc_fail: 959 for (i=0; i < nrxqsets; i++) { 960 if (softc->rx_stats[i].idi_vaddr) 961 iflib_dma_free(&softc->rx_stats[i]); 962 } 963 hw_stats_alloc_fail: 964 free(softc->grp_info, M_DEVBUF); 965 grp_alloc_fail: 966 free(softc->ag_rings, M_DEVBUF); 967 ag_alloc_fail: 968 free(softc->rx_rings, M_DEVBUF); 969 ring_alloc_fail: 970 free(softc->rx_cp_rings, M_DEVBUF); 971 cp_alloc_fail: 972 return rc; 973 } 974 975 static void bnxt_free_hwrm_short_cmd_req(struct bnxt_softc *softc) 976 { 977 if (softc->hwrm_short_cmd_req_addr.idi_vaddr) 978 iflib_dma_free(&softc->hwrm_short_cmd_req_addr); 979 softc->hwrm_short_cmd_req_addr.idi_vaddr = NULL; 980 } 981 982 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt_softc *softc) 983 { 984 int rc; 985 986 rc = iflib_dma_alloc(softc->ctx, softc->hwrm_max_req_len, 987 &softc->hwrm_short_cmd_req_addr, BUS_DMA_NOWAIT); 988 989 return rc; 990 } 991 992 static void bnxt_free_ring(struct bnxt_softc *softc, struct bnxt_ring_mem_info *rmem) 993 { 994 int i; 995 996 for (i = 0; i < rmem->nr_pages; i++) { 997 if (!rmem->pg_arr[i].idi_vaddr) 998 continue; 999 1000 iflib_dma_free(&rmem->pg_arr[i]); 1001 rmem->pg_arr[i].idi_vaddr = NULL; 1002 } 1003 if (rmem->pg_tbl.idi_vaddr) { 1004 iflib_dma_free(&rmem->pg_tbl); 1005 rmem->pg_tbl.idi_vaddr = NULL; 1006 1007 } 1008 if (rmem->vmem_size && *rmem->vmem) { 1009 free(*rmem->vmem, M_DEVBUF); 1010 *rmem->vmem = NULL; 1011 } 1012 } 1013 1014 static void bnxt_init_ctx_mem(struct bnxt_ctx_mem_type *ctxm, void *p, int len) 1015 { 1016 u8 init_val = ctxm->init_value; 1017 u16 offset = ctxm->init_offset; 1018 u8 *p2 = p; 1019 int i; 1020 1021 if (!init_val) 1022 return; 1023 if (offset == BNXT_CTX_INIT_INVALID_OFFSET) { 1024 memset(p, init_val, len); 1025 return; 1026 } 1027 for (i = 0; i < len; i += ctxm->entry_size) 1028 *(p2 + i + offset) = init_val; 1029 } 1030 1031 static int bnxt_alloc_ring(struct bnxt_softc *softc, struct bnxt_ring_mem_info *rmem) 1032 { 1033 uint64_t valid_bit = 0; 1034 int i; 1035 int rc; 1036 1037 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG)) 1038 valid_bit = PTU_PTE_VALID; 1039 1040 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl.idi_vaddr) { 1041 size_t pg_tbl_size = rmem->nr_pages * 8; 1042 1043 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG) 1044 pg_tbl_size = rmem->page_size; 1045 1046 rc = iflib_dma_alloc(softc->ctx, pg_tbl_size, &rmem->pg_tbl, 0); 1047 if (rc) 1048 return -ENOMEM; 1049 } 1050 1051 for (i = 0; i < rmem->nr_pages; i++) { 1052 uint64_t extra_bits = valid_bit; 1053 uint64_t *ptr; 1054 1055 rc = iflib_dma_alloc(softc->ctx, rmem->page_size, &rmem->pg_arr[i], 0); 1056 if (rc) 1057 return -ENOMEM; 1058 1059 if (rmem->ctx_mem) 1060 bnxt_init_ctx_mem(rmem->ctx_mem, rmem->pg_arr[i].idi_vaddr, 1061 rmem->page_size); 1062 1063 if (rmem->nr_pages > 1 || rmem->depth > 0) { 1064 if (i == rmem->nr_pages - 2 && 1065 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 1066 extra_bits |= PTU_PTE_NEXT_TO_LAST; 1067 else if (i == rmem->nr_pages - 1 && 1068 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 1069 extra_bits |= PTU_PTE_LAST; 1070 1071 ptr = (void *) rmem->pg_tbl.idi_vaddr; 1072 ptr[i] = htole64(rmem->pg_arr[i].idi_paddr | extra_bits); 1073 } 1074 } 1075 1076 if (rmem->vmem_size) { 1077 *rmem->vmem = malloc(rmem->vmem_size, M_DEVBUF, M_NOWAIT | M_ZERO); 1078 if (!(*rmem->vmem)) 1079 return -ENOMEM; 1080 } 1081 return 0; 1082 } 1083 1084 1085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES \ 1086 (HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP | \ 1087 HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ | \ 1088 HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ | \ 1089 HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC | \ 1090 HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) 1091 1092 static int bnxt_alloc_ctx_mem_blk(struct bnxt_softc *softc, 1093 struct bnxt_ctx_pg_info *ctx_pg) 1094 { 1095 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 1096 1097 rmem->page_size = BNXT_PAGE_SIZE; 1098 rmem->pg_arr = ctx_pg->ctx_arr; 1099 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 1100 if (rmem->depth >= 1) 1101 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG; 1102 1103 return bnxt_alloc_ring(softc, rmem); 1104 } 1105 1106 int 1107 bnxt_alloc_ctx_pg_tbls(struct bnxt_softc *softc, 1108 struct bnxt_ctx_pg_info *ctx_pg, uint32_t mem_size, uint8_t depth, 1109 struct bnxt_ctx_mem_type *ctxm) 1110 { 1111 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 1112 int rc; 1113 1114 if (!mem_size) 1115 return -EINVAL; 1116 1117 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 1118 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) { 1119 ctx_pg->nr_pages = 0; 1120 return -EINVAL; 1121 } 1122 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) { 1123 int nr_tbls, i; 1124 1125 rmem->depth = 2; 1126 ctx_pg->ctx_pg_tbl = kzalloc(MAX_CTX_PAGES * sizeof(ctx_pg), 1127 GFP_KERNEL); 1128 if (!ctx_pg->ctx_pg_tbl) 1129 return -ENOMEM; 1130 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES); 1131 rmem->nr_pages = nr_tbls; 1132 rc = bnxt_alloc_ctx_mem_blk(softc, ctx_pg); 1133 if (rc) 1134 return rc; 1135 for (i = 0; i < nr_tbls; i++) { 1136 struct bnxt_ctx_pg_info *pg_tbl; 1137 1138 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL); 1139 if (!pg_tbl) 1140 return -ENOMEM; 1141 ctx_pg->ctx_pg_tbl[i] = pg_tbl; 1142 rmem = &pg_tbl->ring_mem; 1143 memcpy(&rmem->pg_tbl, &ctx_pg->ctx_arr[i], sizeof(struct iflib_dma_info)); 1144 rmem->depth = 1; 1145 rmem->nr_pages = MAX_CTX_PAGES; 1146 rmem->ctx_mem = ctxm; 1147 if (i == (nr_tbls - 1)) { 1148 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES; 1149 1150 if (rem) 1151 rmem->nr_pages = rem; 1152 } 1153 rc = bnxt_alloc_ctx_mem_blk(softc, pg_tbl); 1154 if (rc) 1155 break; 1156 } 1157 } else { 1158 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 1159 if (rmem->nr_pages > 1 || depth) 1160 rmem->depth = 1; 1161 rmem->ctx_mem = ctxm; 1162 rc = bnxt_alloc_ctx_mem_blk(softc, ctx_pg); 1163 } 1164 return rc; 1165 } 1166 1167 void bnxt_free_ctx_pg_tbls(struct bnxt_softc *softc, 1168 struct bnxt_ctx_pg_info *ctx_pg) 1169 { 1170 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 1171 1172 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES || 1173 ctx_pg->ctx_pg_tbl) { 1174 int i, nr_tbls = rmem->nr_pages; 1175 1176 for (i = 0; i < nr_tbls; i++) { 1177 struct bnxt_ctx_pg_info *pg_tbl; 1178 struct bnxt_ring_mem_info *rmem2; 1179 1180 pg_tbl = ctx_pg->ctx_pg_tbl[i]; 1181 if (!pg_tbl) 1182 continue; 1183 rmem2 = &pg_tbl->ring_mem; 1184 bnxt_free_ring(softc, rmem2); 1185 ctx_pg->ctx_arr[i].idi_vaddr = NULL; 1186 free(pg_tbl , M_DEVBUF); 1187 ctx_pg->ctx_pg_tbl[i] = NULL; 1188 } 1189 kfree(ctx_pg->ctx_pg_tbl); 1190 ctx_pg->ctx_pg_tbl = NULL; 1191 } 1192 bnxt_free_ring(softc, rmem); 1193 ctx_pg->nr_pages = 0; 1194 } 1195 1196 static int bnxt_setup_ctxm_pg_tbls(struct bnxt_softc *softc, 1197 struct bnxt_ctx_mem_type *ctxm, u32 entries, 1198 u8 pg_lvl) 1199 { 1200 struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info; 1201 int i, rc = 0, n = 1; 1202 u32 mem_size; 1203 1204 if (!ctxm->entry_size || !ctx_pg) 1205 return -EINVAL; 1206 if (ctxm->instance_bmap) 1207 n = hweight32(ctxm->instance_bmap); 1208 if (ctxm->entry_multiple) 1209 entries = roundup(entries, ctxm->entry_multiple); 1210 entries = clamp_t(u32, entries, ctxm->min_entries, ctxm->max_entries); 1211 mem_size = entries * ctxm->entry_size; 1212 for (i = 0; i < n && !rc; i++) { 1213 ctx_pg[i].entries = entries; 1214 rc = bnxt_alloc_ctx_pg_tbls(softc, &ctx_pg[i], mem_size, pg_lvl, 1215 ctxm->init_value ? ctxm : NULL); 1216 } 1217 if (!rc) 1218 ctxm->mem_valid = 1; 1219 return rc; 1220 } 1221 1222 static void bnxt_free_ctx_mem(struct bnxt_softc *softc) 1223 { 1224 struct bnxt_ctx_mem_info *ctx = softc->ctx_mem; 1225 u16 type; 1226 1227 if (!ctx) 1228 return; 1229 1230 for (type = 0; type < BNXT_CTX_MAX; type++) { 1231 struct bnxt_ctx_mem_type *ctxm = &ctx->ctx_arr[type]; 1232 struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info; 1233 int i, n = 1; 1234 1235 if (!ctx_pg) 1236 continue; 1237 if (ctxm->instance_bmap) 1238 n = hweight32(ctxm->instance_bmap); 1239 for (i = 0; i < n; i++) 1240 bnxt_free_ctx_pg_tbls(softc, &ctx_pg[i]); 1241 1242 kfree(ctx_pg); 1243 ctxm->pg_info = NULL; 1244 } 1245 1246 ctx->flags &= ~BNXT_CTX_FLAG_INITED; 1247 kfree(ctx); 1248 softc->ctx_mem = NULL; 1249 } 1250 1251 const u16 bnxt_bstore_to_trace[] = { 1252 [BNXT_CTX_SRT_TRACE] = 1253 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT_TRACE, 1254 [BNXT_CTX_SRT2_TRACE] = 1255 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT2_TRACE, 1256 [BNXT_CTX_CRT_TRACE] = 1257 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT_TRACE, 1258 [BNXT_CTX_CRT2_TRACE] = 1259 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT2_TRACE, 1260 [BNXT_CTX_RIGP0_TRACE] = 1261 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP0_TRACE, 1262 [BNXT_CTX_L2_HWRM_TRACE] = 1263 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_L2_HWRM_TRACE, 1264 [BNXT_CTX_ROCE_HWRM_TRACE] = 1265 HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE, 1266 }; 1267 1268 static void 1269 bnxt_bs_trace_init(struct bnxt_softc *bp, struct bnxt_ctx_mem_type *ctxm) 1270 { 1271 uint32_t mem_size, pages, rem_bytes, magic_byte_offset; 1272 struct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info; 1273 struct bnxt_ring_mem_info *rmem, *rmem_pg_tbl; 1274 uint32_t last_pg, n = 1, size = sizeof(uint8_t); 1275 struct bnxt_bs_trace_info *bs_trace; 1276 uint16_t trace_type; 1277 1278 mem_size = ctxm->max_entries * ctxm->entry_size; 1279 rem_bytes = mem_size % BNXT_PAGE_SIZE; 1280 pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE); 1281 1282 last_pg = (pages - 1) & (MAX_CTX_PAGES - 1); 1283 magic_byte_offset = ((rem_bytes ? rem_bytes : BNXT_PAGE_SIZE) - size); 1284 1285 if (ctxm->instance_bmap) { 1286 if (ctxm->instance_bmap > 1) 1287 return; 1288 n = bitcount32(ctxm->instance_bmap); 1289 } 1290 1291 rmem = &ctx_pg[n - 1].ring_mem; 1292 trace_type = bnxt_bstore_to_trace[ctxm->type]; 1293 bs_trace = &bp->bs_trace[trace_type]; 1294 bs_trace->ctx_type = ctxm->type; 1295 bs_trace->trace_type = trace_type; 1296 if (pages > MAX_CTX_PAGES) { 1297 int last_pg_directory = rmem->nr_pages - 1; 1298 1299 rmem_pg_tbl = 1300 &ctx_pg[n - 1].ctx_pg_tbl[last_pg_directory]->ring_mem; 1301 bs_trace->magic_byte = rmem_pg_tbl->pg_arr[last_pg].idi_vaddr; 1302 } else { 1303 bs_trace->magic_byte = rmem->pg_arr[last_pg].idi_vaddr; 1304 } 1305 bs_trace->magic_byte += magic_byte_offset; 1306 *bs_trace->magic_byte = BNXT_TRACE_BUF_MAGIC_BYTE; 1307 } 1308 1309 static int 1310 bnxt_backing_store_cfg_v2(struct bnxt_softc *softc, u32 ena) 1311 { 1312 struct bnxt_ctx_mem_info *ctx = softc->ctx_mem; 1313 struct bnxt_ctx_mem_type *ctxm; 1314 u16 last_type = BNXT_CTX_INV; 1315 int rc = 0; 1316 u16 type; 1317 1318 if (BNXT_PF(softc)) { 1319 for (type = BNXT_CTX_SRT_TRACE; type <= BNXT_CTX_ROCE_HWRM_TRACE; type++) { 1320 ctxm = &ctx->ctx_arr[type]; 1321 if (!(ctxm->flags & BNXT_CTX_MEM_TYPE_VALID)) 1322 continue; 1323 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->max_entries, 1); 1324 if (rc) { 1325 device_printf(softc->dev, "Unable to setup ctx page for type:0x%x.\n", type); 1326 rc = 0; 1327 continue; 1328 } 1329 /* ckp TODO: this is trace buffer related stuff, so keeping it diabled now. needs revisit */ 1330 bnxt_bs_trace_init(softc, ctxm); 1331 last_type = type; 1332 } 1333 } 1334 1335 if (last_type == BNXT_CTX_INV) { 1336 if (!ena) 1337 return 0; 1338 else if (ena & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM) 1339 last_type = BNXT_CTX_MAX - 1; 1340 else 1341 last_type = BNXT_CTX_L2_MAX - 1; 1342 } 1343 ctx->ctx_arr[last_type].last = 1; 1344 1345 for (type = 0 ; type < BNXT_CTX_V2_MAX; type++) { 1346 ctxm = &ctx->ctx_arr[type]; 1347 1348 if (!ctxm->mem_valid) 1349 continue; 1350 rc = bnxt_hwrm_func_backing_store_cfg_v2(softc, ctxm, ctxm->last); 1351 if (rc) 1352 return rc; 1353 } 1354 return 0; 1355 } 1356 1357 static int bnxt_alloc_ctx_mem(struct bnxt_softc *softc) 1358 { 1359 struct bnxt_ctx_pg_info *ctx_pg; 1360 struct bnxt_ctx_mem_type *ctxm; 1361 struct bnxt_ctx_mem_info *ctx; 1362 u32 l2_qps, qp1_qps, max_qps; 1363 u32 ena, entries_sp, entries; 1364 u32 srqs, max_srqs, min; 1365 u32 num_mr, num_ah; 1366 u32 extra_srqs = 0; 1367 u32 extra_qps = 0; 1368 u8 pg_lvl = 1; 1369 int i, rc; 1370 1371 if (!BNXT_CHIP_P5_PLUS(softc)) 1372 return 0; 1373 1374 rc = bnxt_hwrm_func_backing_store_qcaps(softc); 1375 if (rc) { 1376 device_printf(softc->dev, "Failed querying context mem capability, rc = %d.\n", 1377 rc); 1378 return rc; 1379 } 1380 ctx = softc->ctx_mem; 1381 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 1382 return 0; 1383 1384 ena = 0; 1385 if (BNXT_VF(softc)) 1386 goto skip_legacy; 1387 1388 ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; 1389 l2_qps = ctxm->qp_l2_entries; 1390 qp1_qps = ctxm->qp_qp1_entries; 1391 max_qps = ctxm->max_entries; 1392 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; 1393 srqs = ctxm->srq_l2_entries; 1394 max_srqs = ctxm->max_entries; 1395 if (softc->flags & BNXT_FLAG_ROCE_CAP) { 1396 pg_lvl = 2; 1397 if (BNXT_SW_RES_LMT(softc)) { 1398 extra_qps = max_qps - l2_qps - qp1_qps; 1399 extra_srqs = max_srqs - srqs; 1400 } else { 1401 extra_qps = min_t(uint32_t, 65536, max_qps - l2_qps - qp1_qps); 1402 extra_srqs = min_t(uint32_t, 8192, max_srqs - srqs); 1403 } 1404 } 1405 1406 ctxm = &ctx->ctx_arr[BNXT_CTX_QP]; 1407 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, l2_qps + qp1_qps + extra_qps, 1408 pg_lvl); 1409 if (rc) 1410 return rc; 1411 1412 ctxm = &ctx->ctx_arr[BNXT_CTX_SRQ]; 1413 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, srqs + extra_srqs, pg_lvl); 1414 if (rc) 1415 return rc; 1416 1417 ctxm = &ctx->ctx_arr[BNXT_CTX_CQ]; 1418 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->cq_l2_entries + 1419 extra_qps * 2, pg_lvl); 1420 if (rc) 1421 return rc; 1422 1423 ctxm = &ctx->ctx_arr[BNXT_CTX_VNIC]; 1424 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->max_entries, 1); 1425 if (rc) 1426 return rc; 1427 1428 ctxm = &ctx->ctx_arr[BNXT_CTX_STAT]; 1429 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, ctxm->max_entries, 1); 1430 if (rc) 1431 return rc; 1432 1433 if (!(softc->flags & BNXT_FLAG_ROCE_CAP)) 1434 goto skip_rdma; 1435 1436 ctxm = &ctx->ctx_arr[BNXT_CTX_MRAV]; 1437 ctx_pg = ctxm->pg_info; 1438 /* 128K extra is needed to accomodate static AH context 1439 * allocation by f/w. 1440 */ 1441 num_mr = min_t(u32, ctxm->max_entries / 2, 1024 * 256); 1442 num_ah = min_t(u32, num_mr, 1024 * 128); 1443 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, num_mr + num_ah, 2); 1444 if (rc) 1445 return rc; 1446 ctx_pg->entries = num_mr + num_ah; 1447 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV; 1448 if (ctxm->mrav_num_entries_units) 1449 ctx_pg->entries = 1450 ((num_mr / ctxm->mrav_num_entries_units) << 16) | 1451 (num_ah / ctxm->mrav_num_entries_units); 1452 1453 ctxm = &ctx->ctx_arr[BNXT_CTX_TIM]; 1454 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, l2_qps + qp1_qps + extra_qps, 1); 1455 if (rc) 1456 return rc; 1457 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM; 1458 1459 skip_rdma: 1460 ctxm = &ctx->ctx_arr[BNXT_CTX_STQM]; 1461 min = ctxm->min_entries; 1462 entries_sp = ctx->ctx_arr[BNXT_CTX_VNIC].vnic_entries + l2_qps + 1463 2 * (extra_qps + qp1_qps) + min; 1464 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, entries_sp, 2); 1465 if (rc) 1466 return rc; 1467 1468 ctxm = &ctx->ctx_arr[BNXT_CTX_FTQM]; 1469 entries = l2_qps + 2 * (extra_qps + qp1_qps); 1470 rc = bnxt_setup_ctxm_pg_tbls(softc, ctxm, entries, 2); 1471 if (rc) 1472 return rc; 1473 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 1474 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 1475 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 1476 else 1477 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 1478 } 1479 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 1480 1481 skip_legacy: 1482 if (BNXT_CHIP_P7(softc)) { 1483 if (softc->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2) 1484 rc = bnxt_backing_store_cfg_v2(softc, ena); 1485 } else { 1486 rc = bnxt_hwrm_func_backing_store_cfg(softc, ena); 1487 } 1488 if (rc) { 1489 device_printf(softc->dev, "Failed configuring context mem, rc = %d.\n", 1490 rc); 1491 return rc; 1492 } 1493 ctx->flags |= BNXT_CTX_FLAG_INITED; 1494 1495 return 0; 1496 } 1497 1498 /* 1499 * If we update the index, a write barrier is needed after the write to ensure 1500 * the completion ring has space before the RX/TX ring does. Since we can't 1501 * make the RX and AG doorbells covered by the same barrier without remapping 1502 * MSI-X vectors, we create the barrier over the enture doorbell bar. 1503 * TODO: Remap the MSI-X vectors to allow a barrier to only cover the doorbells 1504 * for a single ring group. 1505 * 1506 * A barrier of just the size of the write is used to ensure the ordering 1507 * remains correct and no writes are lost. 1508 */ 1509 1510 static void bnxt_cuw_db_rx(void *db_ptr, uint16_t idx) 1511 { 1512 struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; 1513 struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; 1514 1515 bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 4, 1516 BUS_SPACE_BARRIER_WRITE); 1517 bus_space_write_4(db_bar->tag, db_bar->handle, ring->doorbell, 1518 htole32(RX_DOORBELL_KEY_RX | idx)); 1519 } 1520 1521 static void bnxt_cuw_db_tx(void *db_ptr, uint16_t idx) 1522 { 1523 struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; 1524 struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; 1525 1526 bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 4, 1527 BUS_SPACE_BARRIER_WRITE); 1528 bus_space_write_4(db_bar->tag, db_bar->handle, ring->doorbell, 1529 htole32(TX_DOORBELL_KEY_TX | idx)); 1530 } 1531 1532 static void bnxt_cuw_db_cq(void *db_ptr, bool enable_irq) 1533 { 1534 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1535 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1536 1537 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 4, 1538 BUS_SPACE_BARRIER_WRITE); 1539 bus_space_write_4(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1540 htole32(CMPL_DOORBELL_KEY_CMPL | 1541 ((cpr->cons == UINT32_MAX) ? 0 : 1542 (cpr->cons | CMPL_DOORBELL_IDX_VALID)) | 1543 ((enable_irq) ? 0 : CMPL_DOORBELL_MASK))); 1544 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1545 BUS_SPACE_BARRIER_WRITE); 1546 } 1547 1548 static void bnxt_thor_db_rx(void *db_ptr, uint16_t idx) 1549 { 1550 struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; 1551 struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; 1552 1553 bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 8, 1554 BUS_SPACE_BARRIER_WRITE); 1555 bus_space_write_8(db_bar->tag, db_bar->handle, ring->doorbell, 1556 htole64((DBR_PATH_L2 | DBR_TYPE_SRQ | idx) | 1557 ((uint64_t)ring->phys_id << DBR_XID_SFT))); 1558 } 1559 1560 static void bnxt_thor_db_tx(void *db_ptr, uint16_t idx) 1561 { 1562 struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; 1563 struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; 1564 1565 bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 8, 1566 BUS_SPACE_BARRIER_WRITE); 1567 bus_space_write_8(db_bar->tag, db_bar->handle, ring->doorbell, 1568 htole64((DBR_PATH_L2 | DBR_TYPE_SQ | idx) | 1569 ((uint64_t)ring->phys_id << DBR_XID_SFT))); 1570 } 1571 1572 static void bnxt_thor_db_rx_cq(void *db_ptr, bool enable_irq) 1573 { 1574 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1575 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1576 dbc_dbc_t db_msg = { 0 }; 1577 uint32_t cons = cpr->cons; 1578 1579 if (cons == UINT32_MAX) 1580 cons = 0; 1581 else 1582 cons = RING_NEXT(&cpr->ring, cons); 1583 1584 db_msg.index = ((cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK); 1585 1586 db_msg.type_path_xid = ((cpr->ring.phys_id << DBC_DBC_XID_SFT) & 1587 DBC_DBC_XID_MASK) | DBC_DBC_PATH_L2 | 1588 ((enable_irq) ? DBC_DBC_TYPE_CQ_ARMALL: DBC_DBC_TYPE_CQ); 1589 1590 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, 1591 BUS_SPACE_BARRIER_WRITE); 1592 bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1593 htole64(*(uint64_t *)&db_msg)); 1594 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1595 BUS_SPACE_BARRIER_WRITE); 1596 } 1597 1598 static void bnxt_thor_db_tx_cq(void *db_ptr, bool enable_irq) 1599 { 1600 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1601 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1602 dbc_dbc_t db_msg = { 0 }; 1603 uint32_t cons = cpr->cons; 1604 1605 db_msg.index = ((cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK); 1606 1607 db_msg.type_path_xid = ((cpr->ring.phys_id << DBC_DBC_XID_SFT) & 1608 DBC_DBC_XID_MASK) | DBC_DBC_PATH_L2 | 1609 ((enable_irq) ? DBC_DBC_TYPE_CQ_ARMALL: DBC_DBC_TYPE_CQ); 1610 1611 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, 1612 BUS_SPACE_BARRIER_WRITE); 1613 bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1614 htole64(*(uint64_t *)&db_msg)); 1615 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1616 BUS_SPACE_BARRIER_WRITE); 1617 } 1618 1619 static void bnxt_thor_db_nq(void *db_ptr, bool enable_irq) 1620 { 1621 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1622 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1623 dbc_dbc_t db_msg = { 0 }; 1624 uint32_t cons = cpr->cons; 1625 1626 db_msg.index = ((cons << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK); 1627 1628 db_msg.type_path_xid = ((cpr->ring.phys_id << DBC_DBC_XID_SFT) & 1629 DBC_DBC_XID_MASK) | DBC_DBC_PATH_L2 | 1630 ((enable_irq) ? DBC_DBC_TYPE_NQ_ARM: DBC_DBC_TYPE_NQ); 1631 1632 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, 1633 BUS_SPACE_BARRIER_WRITE); 1634 bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1635 htole64(*(uint64_t *)&db_msg)); 1636 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1637 BUS_SPACE_BARRIER_WRITE); 1638 } 1639 1640 static void 1641 bnxt_thor2_db_rx(void *db_ptr, uint16_t idx) 1642 { 1643 struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; 1644 struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; 1645 uint64_t db_val; 1646 1647 if (idx >= ring->ring_size) { 1648 device_printf(ring->softc->dev, "%s: BRCM DBG: idx: %d crossed boundary\n", __func__, idx); 1649 return; 1650 } 1651 1652 db_val = ((DBR_PATH_L2 | DBR_TYPE_SRQ | DBR_VALID | idx) | 1653 ((uint64_t)ring->phys_id << DBR_XID_SFT)); 1654 1655 /* Add the PI index */ 1656 db_val |= DB_RING_IDX(ring, idx, ring->epoch_arr[idx]); 1657 1658 bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 8, 1659 BUS_SPACE_BARRIER_WRITE); 1660 bus_space_write_8(db_bar->tag, db_bar->handle, ring->doorbell, 1661 htole64(db_val)); 1662 } 1663 1664 static void 1665 bnxt_thor2_db_tx(void *db_ptr, uint16_t idx) 1666 { 1667 struct bnxt_ring *ring = (struct bnxt_ring *) db_ptr; 1668 struct bnxt_bar_info *db_bar = &ring->softc->doorbell_bar; 1669 uint64_t db_val; 1670 1671 if (idx >= ring->ring_size) { 1672 device_printf(ring->softc->dev, "%s: BRCM DBG: idx: %d crossed boundary\n", __func__, idx); 1673 return; 1674 } 1675 1676 db_val = ((DBR_PATH_L2 | DBR_TYPE_SQ | DBR_VALID | idx) | 1677 ((uint64_t)ring->phys_id << DBR_XID_SFT)); 1678 1679 /* Add the PI index */ 1680 db_val |= DB_RING_IDX(ring, idx, ring->epoch_arr[idx]); 1681 1682 bus_space_barrier(db_bar->tag, db_bar->handle, ring->doorbell, 8, 1683 BUS_SPACE_BARRIER_WRITE); 1684 bus_space_write_8(db_bar->tag, db_bar->handle, ring->doorbell, 1685 htole64(db_val)); 1686 } 1687 1688 static void 1689 bnxt_thor2_db_rx_cq(void *db_ptr, bool enable_irq) 1690 { 1691 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1692 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1693 u64 db_msg = { 0 }; 1694 uint32_t cons = cpr->raw_cons; 1695 uint32_t toggle = 0; 1696 1697 if (cons == UINT32_MAX) 1698 cons = 0; 1699 1700 if (enable_irq == true) 1701 toggle = cpr->toggle; 1702 1703 db_msg = DBR_PATH_L2 | ((u64)cpr->ring.phys_id << DBR_XID_SFT) | DBR_VALID | 1704 DB_RING_IDX_CMP(&cpr->ring, cons) | DB_TOGGLE(toggle); 1705 1706 if (enable_irq) 1707 db_msg |= DBR_TYPE_CQ_ARMALL; 1708 else 1709 db_msg |= DBR_TYPE_CQ; 1710 1711 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, 1712 BUS_SPACE_BARRIER_WRITE); 1713 bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1714 htole64(*(uint64_t *)&db_msg)); 1715 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1716 BUS_SPACE_BARRIER_WRITE); 1717 } 1718 1719 static void 1720 bnxt_thor2_db_tx_cq(void *db_ptr, bool enable_irq) 1721 { 1722 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1723 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1724 u64 db_msg = { 0 }; 1725 uint32_t cons = cpr->raw_cons; 1726 uint32_t toggle = 0; 1727 1728 if (enable_irq == true) 1729 toggle = cpr->toggle; 1730 1731 db_msg = DBR_PATH_L2 | ((u64)cpr->ring.phys_id << DBR_XID_SFT) | DBR_VALID | 1732 DB_RING_IDX_CMP(&cpr->ring, cons) | DB_TOGGLE(toggle); 1733 1734 if (enable_irq) 1735 db_msg |= DBR_TYPE_CQ_ARMALL; 1736 else 1737 db_msg |= DBR_TYPE_CQ; 1738 1739 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, 1740 BUS_SPACE_BARRIER_WRITE); 1741 bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1742 htole64(*(uint64_t *)&db_msg)); 1743 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1744 BUS_SPACE_BARRIER_WRITE); 1745 } 1746 1747 static void 1748 bnxt_thor2_db_nq(void *db_ptr, bool enable_irq) 1749 { 1750 struct bnxt_cp_ring *cpr = (struct bnxt_cp_ring *) db_ptr; 1751 struct bnxt_bar_info *db_bar = &cpr->ring.softc->doorbell_bar; 1752 u64 db_msg = { 0 }; 1753 uint32_t cons = cpr->raw_cons; 1754 uint32_t toggle = 0; 1755 1756 if (enable_irq == true) 1757 toggle = cpr->toggle; 1758 1759 db_msg = DBR_PATH_L2 | ((u64)cpr->ring.phys_id << DBR_XID_SFT) | DBR_VALID | 1760 DB_RING_IDX_CMP(&cpr->ring, cons) | DB_TOGGLE(toggle); 1761 1762 if (enable_irq) 1763 db_msg |= DBR_TYPE_NQ_ARM; 1764 else 1765 db_msg |= DBR_TYPE_NQ_MASK; 1766 1767 bus_space_barrier(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 8, 1768 BUS_SPACE_BARRIER_WRITE); 1769 bus_space_write_8(db_bar->tag, db_bar->handle, cpr->ring.doorbell, 1770 htole64(*(uint64_t *)&db_msg)); 1771 bus_space_barrier(db_bar->tag, db_bar->handle, 0, db_bar->size, 1772 BUS_SPACE_BARRIER_WRITE); 1773 } 1774 1775 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *dev_name) 1776 { 1777 struct bnxt_softc_list *sc = NULL; 1778 1779 SLIST_FOREACH(sc, &pf_list, next) { 1780 /* get the softc reference based on device name */ 1781 if (dev_name && !strncmp(dev_name, if_name(iflib_get_ifp(sc->softc->ctx)), BNXT_MAX_STR)) { 1782 return sc->softc; 1783 } 1784 /* get the softc reference based on domain,bus,device,function */ 1785 if (!dev_name && 1786 (domain == sc->softc->domain) && 1787 (bus == sc->softc->bus) && 1788 (dev_fn == sc->softc->dev_fn)) { 1789 return sc->softc; 1790 1791 } 1792 } 1793 1794 return NULL; 1795 } 1796 1797 1798 static void bnxt_verify_asym_queues(struct bnxt_softc *softc) 1799 { 1800 uint8_t i, lltc = 0; 1801 1802 if (!softc->max_lltc) 1803 return; 1804 1805 /* Verify that lossless TX and RX queues are in the same index */ 1806 for (i = 0; i < softc->max_tc; i++) { 1807 if (BNXT_LLQ(softc->tx_q_info[i].queue_profile) && 1808 BNXT_LLQ(softc->rx_q_info[i].queue_profile)) 1809 lltc++; 1810 } 1811 softc->max_lltc = min(softc->max_lltc, lltc); 1812 } 1813 1814 static int bnxt_hwrm_poll(struct bnxt_softc *bp) 1815 { 1816 struct hwrm_ver_get_output *resp = 1817 (void *)bp->hwrm_cmd_resp.idi_vaddr; 1818 struct hwrm_ver_get_input req = {0}; 1819 int rc; 1820 1821 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET); 1822 1823 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1824 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1825 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1826 1827 rc = _hwrm_send_message(bp, &req, sizeof(req)); 1828 if (rc) 1829 return rc; 1830 1831 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) 1832 rc = -EAGAIN; 1833 1834 return rc; 1835 } 1836 1837 static void bnxt_rtnl_lock_sp(struct bnxt_softc *bp) 1838 { 1839 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK 1840 * set. If the device is being closed, bnxt_close() may be holding 1841 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we 1842 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl(). 1843 */ 1844 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 1845 rtnl_lock(); 1846 } 1847 1848 static void bnxt_rtnl_unlock_sp(struct bnxt_softc *bp) 1849 { 1850 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 1851 rtnl_unlock(); 1852 } 1853 1854 static void bnxt_fw_fatal_close(struct bnxt_softc *softc) 1855 { 1856 bnxt_disable_intr(softc->ctx); 1857 if (pci_is_enabled(softc->pdev)) 1858 pci_disable_device(softc->pdev); 1859 } 1860 1861 static u32 bnxt_fw_health_readl(struct bnxt_softc *bp, int reg_idx) 1862 { 1863 struct bnxt_fw_health *fw_health = bp->fw_health; 1864 u32 reg = fw_health->regs[reg_idx]; 1865 u32 reg_type, reg_off, val = 0; 1866 1867 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1868 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1869 switch (reg_type) { 1870 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1871 pci_read_config_dword(bp->pdev, reg_off, &val); 1872 break; 1873 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1874 reg_off = fw_health->mapped_regs[reg_idx]; 1875 fallthrough; 1876 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 1877 val = readl_fbsd(bp, reg_off, 0); 1878 break; 1879 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 1880 val = readl_fbsd(bp, reg_off, 2); 1881 break; 1882 } 1883 if (reg_idx == BNXT_FW_RESET_INPROG_REG) 1884 val &= fw_health->fw_reset_inprog_reg_mask; 1885 return val; 1886 } 1887 1888 static void bnxt_fw_reset_close(struct bnxt_softc *bp) 1889 { 1890 int i; 1891 bnxt_ulp_stop(bp); 1892 /* When firmware is in fatal state, quiesce device and disable 1893 * bus master to prevent any potential bad DMAs before freeing 1894 * kernel memory. 1895 */ 1896 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 1897 u16 val = 0; 1898 1899 val = pci_read_config(bp->dev, PCI_SUBSYSTEM_ID, 2); 1900 if (val == 0xffff) { 1901 bp->fw_reset_min_dsecs = 0; 1902 } 1903 bnxt_fw_fatal_close(bp); 1904 } 1905 1906 iflib_request_reset(bp->ctx); 1907 bnxt_stop(bp->ctx); 1908 bnxt_hwrm_func_drv_unrgtr(bp, false); 1909 1910 for (i = bp->nrxqsets-1; i>=0; i--) { 1911 if (BNXT_CHIP_P5_PLUS(bp)) 1912 iflib_irq_free(bp->ctx, &bp->nq_rings[i].irq); 1913 else 1914 iflib_irq_free(bp->ctx, &bp->rx_cp_rings[i].irq); 1915 1916 } 1917 if (pci_is_enabled(bp->pdev)) 1918 pci_disable_device(bp->pdev); 1919 pci_disable_busmaster(bp->dev); 1920 bnxt_free_ctx_mem(bp); 1921 } 1922 1923 static bool is_bnxt_fw_ok(struct bnxt_softc *bp) 1924 { 1925 struct bnxt_fw_health *fw_health = bp->fw_health; 1926 bool no_heartbeat = false, has_reset = false; 1927 u32 val; 1928 1929 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG); 1930 if (val == fw_health->last_fw_heartbeat) 1931 no_heartbeat = true; 1932 1933 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 1934 if (val != fw_health->last_fw_reset_cnt) 1935 has_reset = true; 1936 1937 if (!no_heartbeat && has_reset) 1938 return true; 1939 1940 return false; 1941 } 1942 1943 void bnxt_fw_reset(struct bnxt_softc *bp) 1944 { 1945 bnxt_rtnl_lock_sp(bp); 1946 if (test_bit(BNXT_STATE_OPEN, &bp->state) && 1947 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 1948 int tmo; 1949 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 1950 bnxt_fw_reset_close(bp); 1951 1952 if ((bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD)) { 1953 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN; 1954 tmo = HZ / 10; 1955 } else { 1956 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 1957 tmo = bp->fw_reset_min_dsecs * HZ /10; 1958 } 1959 bnxt_queue_fw_reset_work(bp, tmo); 1960 } 1961 bnxt_rtnl_unlock_sp(bp); 1962 } 1963 1964 static void bnxt_queue_fw_reset_work(struct bnxt_softc *bp, unsigned long delay) 1965 { 1966 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))) 1967 return; 1968 1969 if (BNXT_PF(bp)) 1970 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay); 1971 else 1972 schedule_delayed_work(&bp->fw_reset_task, delay); 1973 } 1974 1975 void bnxt_queue_sp_work(struct bnxt_softc *bp) 1976 { 1977 if (BNXT_PF(bp)) 1978 queue_work(bnxt_pf_wq, &bp->sp_task); 1979 else 1980 schedule_work(&bp->sp_task); 1981 } 1982 1983 static void bnxt_fw_reset_writel(struct bnxt_softc *bp, int reg_idx) 1984 { 1985 struct bnxt_fw_health *fw_health = bp->fw_health; 1986 u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; 1987 u32 val = fw_health->fw_reset_seq_vals[reg_idx]; 1988 u32 reg_type, reg_off, delay_msecs; 1989 1990 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx]; 1991 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); 1992 reg_off = BNXT_FW_HEALTH_REG_OFF(reg); 1993 switch (reg_type) { 1994 case BNXT_FW_HEALTH_REG_TYPE_CFG: 1995 pci_write_config_dword(bp->pdev, reg_off, val); 1996 break; 1997 case BNXT_FW_HEALTH_REG_TYPE_GRC: 1998 writel_fbsd(bp, BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4, 0, reg_off & BNXT_GRC_BASE_MASK); 1999 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000; 2000 fallthrough; 2001 case BNXT_FW_HEALTH_REG_TYPE_BAR0: 2002 writel_fbsd(bp, reg_off, 0, val); 2003 break; 2004 case BNXT_FW_HEALTH_REG_TYPE_BAR1: 2005 writel_fbsd(bp, reg_off, 2, val); 2006 break; 2007 } 2008 if (delay_msecs) { 2009 pci_read_config_dword(bp->pdev, 0, &val); 2010 msleep(delay_msecs); 2011 } 2012 } 2013 2014 static void bnxt_reset_all(struct bnxt_softc *bp) 2015 { 2016 struct bnxt_fw_health *fw_health = bp->fw_health; 2017 int i, rc; 2018 2019 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) { 2020 bp->fw_reset_timestamp = jiffies; 2021 return; 2022 } 2023 2024 if (fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST) { 2025 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) 2026 bnxt_fw_reset_writel(bp, i); 2027 } else if (fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU) { 2028 struct hwrm_fw_reset_input req = {0}; 2029 2030 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET); 2031 req.target_id = htole16(HWRM_TARGET_ID_KONG); 2032 req.embedded_proc_type = HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP; 2033 req.selfrst_status = HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP; 2034 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL; 2035 rc = hwrm_send_message(bp, &req, sizeof(req)); 2036 2037 if (rc != -ENODEV) 2038 device_printf(bp->dev, "Unable to reset FW rc=%d\n", rc); 2039 } 2040 bp->fw_reset_timestamp = jiffies; 2041 } 2042 2043 static int __bnxt_alloc_fw_health(struct bnxt_softc *bp) 2044 { 2045 if (bp->fw_health) 2046 return 0; 2047 2048 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL); 2049 if (!bp->fw_health) 2050 return -ENOMEM; 2051 2052 mutex_init(&bp->fw_health->lock); 2053 return 0; 2054 } 2055 2056 static int bnxt_alloc_fw_health(struct bnxt_softc *bp) 2057 { 2058 int rc; 2059 2060 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) && 2061 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 2062 return 0; 2063 2064 rc = __bnxt_alloc_fw_health(bp); 2065 if (rc) { 2066 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET; 2067 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 2068 return rc; 2069 } 2070 2071 return 0; 2072 } 2073 2074 static inline void __bnxt_map_fw_health_reg(struct bnxt_softc *bp, u32 reg) 2075 { 2076 writel_fbsd(bp, BNXT_GRCPF_REG_WINDOW_BASE_OUT + BNXT_FW_HEALTH_WIN_MAP_OFF, 0, reg & BNXT_GRC_BASE_MASK); 2077 } 2078 2079 static int bnxt_map_fw_health_regs(struct bnxt_softc *bp) 2080 { 2081 struct bnxt_fw_health *fw_health = bp->fw_health; 2082 u32 reg_base = 0xffffffff; 2083 int i; 2084 2085 bp->fw_health->status_reliable = false; 2086 bp->fw_health->resets_reliable = false; 2087 /* Only pre-map the monitoring GRC registers using window 3 */ 2088 for (i = 0; i < 4; i++) { 2089 u32 reg = fw_health->regs[i]; 2090 2091 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) 2092 continue; 2093 if (reg_base == 0xffffffff) 2094 reg_base = reg & BNXT_GRC_BASE_MASK; 2095 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) 2096 return -ERANGE; 2097 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg); 2098 } 2099 bp->fw_health->status_reliable = true; 2100 bp->fw_health->resets_reliable = true; 2101 if (reg_base == 0xffffffff) 2102 return 0; 2103 2104 __bnxt_map_fw_health_reg(bp, reg_base); 2105 return 0; 2106 } 2107 2108 static void bnxt_inv_fw_health_reg(struct bnxt_softc *bp) 2109 { 2110 struct bnxt_fw_health *fw_health = bp->fw_health; 2111 u32 reg_type; 2112 2113 if (!fw_health) 2114 return; 2115 2116 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]); 2117 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) 2118 fw_health->status_reliable = false; 2119 2120 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]); 2121 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) 2122 fw_health->resets_reliable = false; 2123 } 2124 2125 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt_softc *bp) 2126 { 2127 struct bnxt_fw_health *fw_health = bp->fw_health; 2128 struct hwrm_error_recovery_qcfg_output *resp = 2129 (void *)bp->hwrm_cmd_resp.idi_vaddr; 2130 struct hwrm_error_recovery_qcfg_input req = {0}; 2131 int rc, i; 2132 2133 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 2134 return 0; 2135 2136 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG); 2137 rc = _hwrm_send_message(bp, &req, sizeof(req)); 2138 2139 if (rc) 2140 goto err_recovery_out; 2141 fw_health->flags = le32toh(resp->flags); 2142 if ((fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU) && 2143 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) { 2144 rc = -EINVAL; 2145 goto err_recovery_out; 2146 } 2147 fw_health->polling_dsecs = le32toh(resp->driver_polling_freq); 2148 fw_health->master_func_wait_dsecs = 2149 le32toh(resp->master_func_wait_period); 2150 fw_health->normal_func_wait_dsecs = 2151 le32toh(resp->normal_func_wait_period); 2152 fw_health->post_reset_wait_dsecs = 2153 le32toh(resp->master_func_wait_period_after_reset); 2154 fw_health->post_reset_max_wait_dsecs = 2155 le32toh(resp->max_bailout_time_after_reset); 2156 fw_health->regs[BNXT_FW_HEALTH_REG] = 2157 le32toh(resp->fw_health_status_reg); 2158 fw_health->regs[BNXT_FW_HEARTBEAT_REG] = 2159 le32toh(resp->fw_heartbeat_reg); 2160 fw_health->regs[BNXT_FW_RESET_CNT_REG] = 2161 le32toh(resp->fw_reset_cnt_reg); 2162 fw_health->regs[BNXT_FW_RESET_INPROG_REG] = 2163 le32toh(resp->reset_inprogress_reg); 2164 fw_health->fw_reset_inprog_reg_mask = 2165 le32toh(resp->reset_inprogress_reg_mask); 2166 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt; 2167 if (fw_health->fw_reset_seq_cnt >= 16) { 2168 rc = -EINVAL; 2169 goto err_recovery_out; 2170 } 2171 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) { 2172 fw_health->fw_reset_seq_regs[i] = 2173 le32toh(resp->reset_reg[i]); 2174 fw_health->fw_reset_seq_vals[i] = 2175 le32toh(resp->reset_reg_val[i]); 2176 fw_health->fw_reset_seq_delay_msec[i] = 2177 le32toh(resp->delay_after_reset[i]); 2178 } 2179 err_recovery_out: 2180 if (!rc) 2181 rc = bnxt_map_fw_health_regs(bp); 2182 if (rc) 2183 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 2184 return rc; 2185 } 2186 2187 static int bnxt_drv_rgtr(struct bnxt_softc *bp) 2188 { 2189 int rc; 2190 2191 /* determine whether we can support error recovery before 2192 * registering with FW 2193 */ 2194 if (bnxt_alloc_fw_health(bp)) { 2195 device_printf(bp->dev, "no memory for firmware error recovery\n"); 2196 } else { 2197 rc = bnxt_hwrm_error_recovery_qcfg(bp); 2198 if (rc) 2199 device_printf(bp->dev, "hwrm query error recovery failure rc: %d\n", 2200 rc); 2201 } 2202 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false); //sumit dbg: revisit the params 2203 if (rc) 2204 return -ENODEV; 2205 return 0; 2206 } 2207 2208 static bool bnxt_fw_reset_timeout(struct bnxt_softc *bp) 2209 { 2210 return time_after(jiffies, bp->fw_reset_timestamp + 2211 (bp->fw_reset_max_dsecs * HZ / 10)); 2212 } 2213 2214 static int bnxt_open(struct bnxt_softc *bp) 2215 { 2216 int rc = 0; 2217 if (BNXT_PF(bp)) 2218 rc = bnxt_hwrm_nvm_get_dev_info(bp, &bp->nvm_info->mfg_id, 2219 &bp->nvm_info->device_id, &bp->nvm_info->sector_size, 2220 &bp->nvm_info->size, &bp->nvm_info->reserved_size, 2221 &bp->nvm_info->available_size); 2222 2223 /* Get the queue config */ 2224 rc = bnxt_hwrm_queue_qportcfg(bp, HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX); 2225 if (rc) { 2226 device_printf(bp->dev, "reinit: hwrm qportcfg (tx) failed\n"); 2227 return rc; 2228 } 2229 if (bp->is_asym_q) { 2230 rc = bnxt_hwrm_queue_qportcfg(bp, 2231 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX); 2232 if (rc) { 2233 device_printf(bp->dev, "re-init: hwrm qportcfg (rx) failed\n"); 2234 return rc; 2235 } 2236 bnxt_verify_asym_queues(bp); 2237 } else { 2238 bp->rx_max_q = bp->tx_max_q; 2239 memcpy(bp->rx_q_info, bp->tx_q_info, sizeof(bp->rx_q_info)); 2240 memcpy(bp->rx_q_ids, bp->tx_q_ids, sizeof(bp->rx_q_ids)); 2241 } 2242 /* Get the HW capabilities */ 2243 rc = bnxt_hwrm_func_qcaps(bp); 2244 if (rc) 2245 return rc; 2246 2247 bnxt_hwrm_dbg_qcaps(bp); 2248 2249 /* Register the driver with the FW */ 2250 rc = bnxt_drv_rgtr(bp); 2251 if (rc) 2252 return rc; 2253 if (bp->hwrm_spec_code >= 0x10803) { 2254 rc = bnxt_alloc_ctx_mem(bp); 2255 if (rc) { 2256 device_printf(bp->dev, "attach: alloc_ctx_mem failed\n"); 2257 return rc; 2258 } 2259 rc = bnxt_hwrm_func_resc_qcaps(bp, true); 2260 if (!rc) 2261 bp->flags |= BNXT_FLAG_FW_CAP_NEW_RM; 2262 } 2263 2264 if (BNXT_CHIP_P5_PLUS(bp)) 2265 bnxt_hwrm_reserve_rings(bp); 2266 2267 /* Get the current configuration of this function */ 2268 rc = bnxt_hwrm_func_qcfg(bp); 2269 if (rc) { 2270 device_printf(bp->dev, "re-init: hwrm func qcfg failed\n"); 2271 return rc; 2272 } 2273 2274 bnxt_msix_intr_assign(bp->ctx, 0); 2275 bnxt_init(bp->ctx); 2276 bnxt_intr_enable(bp->ctx); 2277 2278 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) { 2279 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 2280 bnxt_ulp_start(bp, 0); 2281 } 2282 } 2283 2284 device_printf(bp->dev, "Network interface is UP and operational\n"); 2285 2286 return rc; 2287 } 2288 static void bnxt_fw_reset_abort(struct bnxt_softc *bp, int rc) 2289 { 2290 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 2291 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) { 2292 bnxt_ulp_start(bp, rc); 2293 } 2294 bp->fw_reset_state = 0; 2295 } 2296 2297 static void bnxt_fw_reset_task(struct work_struct *work) 2298 { 2299 struct bnxt_softc *bp = container_of(work, struct bnxt_softc, fw_reset_task.work); 2300 int rc = 0; 2301 2302 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) { 2303 device_printf(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n"); 2304 return; 2305 } 2306 2307 switch (bp->fw_reset_state) { 2308 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: { 2309 u32 val; 2310 2311 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 2312 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 2313 !bnxt_fw_reset_timeout(bp)) { 2314 bnxt_queue_fw_reset_work(bp, HZ / 5); 2315 return; 2316 } 2317 2318 if (!bp->fw_health->primary) { 2319 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs; 2320 2321 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 2322 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 2323 return; 2324 } 2325 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 2326 } 2327 fallthrough; 2328 case BNXT_FW_RESET_STATE_RESET_FW: 2329 bnxt_reset_all(bp); 2330 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 2331 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10); 2332 return; 2333 case BNXT_FW_RESET_STATE_ENABLE_DEV: 2334 bnxt_inv_fw_health_reg(bp); 2335 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) && 2336 !bp->fw_reset_min_dsecs) { 2337 u16 val; 2338 2339 val = pci_read_config(bp->dev, PCI_SUBSYSTEM_ID, 2); 2340 if (val == 0xffff) { 2341 if (bnxt_fw_reset_timeout(bp)) { 2342 device_printf(bp->dev, "Firmware reset aborted, PCI config space invalid\n"); 2343 rc = -ETIMEDOUT; 2344 goto fw_reset_abort; 2345 } 2346 bnxt_queue_fw_reset_work(bp, HZ / 1000); 2347 return; 2348 } 2349 } 2350 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2351 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state); 2352 if (!pci_is_enabled(bp->pdev)) { 2353 if (pci_enable_device(bp->pdev)) { 2354 device_printf(bp->dev, "Cannot re-enable PCI device\n"); 2355 rc = -ENODEV; 2356 goto fw_reset_abort; 2357 } 2358 } 2359 pci_set_master(bp->pdev); 2360 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW; 2361 fallthrough; 2362 case BNXT_FW_RESET_STATE_POLL_FW: 2363 bp->hwrm_cmd_timeo = SHORT_HWRM_CMD_TIMEOUT; 2364 rc = bnxt_hwrm_poll(bp); 2365 if (rc) { 2366 if (bnxt_fw_reset_timeout(bp)) { 2367 device_printf(bp->dev, "Firmware reset aborted\n"); 2368 goto fw_reset_abort_status; 2369 } 2370 bnxt_queue_fw_reset_work(bp, HZ / 5); 2371 return; 2372 } 2373 bp->hwrm_cmd_timeo = DFLT_HWRM_CMD_TIMEOUT; 2374 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING; 2375 fallthrough; 2376 case BNXT_FW_RESET_STATE_OPENING: 2377 rc = bnxt_open(bp); 2378 if (rc) { 2379 device_printf(bp->dev, "bnxt_open() failed during FW reset\n"); 2380 bnxt_fw_reset_abort(bp, rc); 2381 rtnl_unlock(); 2382 return; 2383 } 2384 2385 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) && 2386 bp->fw_health->enabled) { 2387 bp->fw_health->last_fw_reset_cnt = 2388 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2389 } 2390 bp->fw_reset_state = 0; 2391 smp_mb__before_atomic(); 2392 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 2393 bnxt_ulp_start(bp, 0); 2394 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state); 2395 set_bit(BNXT_STATE_OPEN, &bp->state); 2396 bnxt_crash_dump_init(bp); 2397 #ifdef PCI_IOV 2398 bnxt_reenable_sriov(bp); 2399 #endif 2400 rtnl_unlock(); 2401 } 2402 return; 2403 2404 fw_reset_abort_status: 2405 if (bp->fw_health->status_reliable || 2406 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) { 2407 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 2408 2409 device_printf(bp->dev, "fw_health_status 0x%x\n", sts); 2410 } 2411 fw_reset_abort: 2412 rtnl_lock(); 2413 bnxt_fw_reset_abort(bp, rc); 2414 rtnl_unlock(); 2415 } 2416 2417 static void bnxt_force_fw_reset(struct bnxt_softc *bp) 2418 { 2419 struct bnxt_fw_health *fw_health = bp->fw_health; 2420 u32 wait_dsecs; 2421 2422 if (!test_bit(BNXT_STATE_OPEN, &bp->state) || 2423 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 2424 return; 2425 bnxt_fw_reset_close(bp); 2426 wait_dsecs = fw_health->master_func_wait_dsecs; 2427 if (fw_health->primary) { 2428 if (fw_health->flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU) 2429 wait_dsecs = 0; 2430 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW; 2431 } else { 2432 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10; 2433 wait_dsecs = fw_health->normal_func_wait_dsecs; 2434 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV; 2435 } 2436 2437 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs; 2438 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs; 2439 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10); 2440 } 2441 2442 static void bnxt_fw_exception(struct bnxt_softc *bp) 2443 { 2444 device_printf(bp->dev, "Detected firmware fatal condition, initiating reset\n"); 2445 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2446 bnxt_rtnl_lock_sp(bp); 2447 bnxt_force_fw_reset(bp); 2448 bnxt_rtnl_unlock_sp(bp); 2449 } 2450 2451 static void __bnxt_fw_recover(struct bnxt_softc *bp) 2452 { 2453 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) || 2454 test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state)) 2455 bnxt_fw_reset(bp); 2456 else 2457 bnxt_fw_exception(bp); 2458 } 2459 2460 static void bnxt_devlink_health_fw_report(struct bnxt_softc *bp) 2461 { 2462 struct bnxt_fw_health *fw_health = bp->fw_health; 2463 2464 if (!fw_health) 2465 return; 2466 2467 if (!fw_health->fw_reporter) { 2468 __bnxt_fw_recover(bp); 2469 return; 2470 } 2471 } 2472 2473 static void bnxt_sp_task(struct work_struct *work) 2474 { 2475 struct bnxt_softc *bp = container_of(work, struct bnxt_softc, sp_task); 2476 2477 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 2478 smp_mb__after_atomic(); 2479 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { 2480 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 2481 return; 2482 } 2483 2484 #ifdef PCI_IOV 2485 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) 2486 bnxt_hwrm_exec_fwd_req(bp); 2487 #endif 2488 2489 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) { 2490 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) || 2491 test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state)) 2492 bnxt_devlink_health_fw_report(bp); 2493 else 2494 bnxt_fw_reset(bp); 2495 } 2496 2497 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) { 2498 if (!is_bnxt_fw_ok(bp)) 2499 bnxt_devlink_health_fw_report(bp); 2500 } 2501 smp_mb__before_atomic(); 2502 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); 2503 } 2504 2505 int 2506 bnxt_hwrm_reserve_rings(struct bnxt_softc *softc) 2507 { 2508 if (BNXT_PF(softc)) 2509 return bnxt_hwrm_reserve_pf_rings(softc); 2510 2511 else 2512 return bnxt_hwrm_reserve_vf_rings(softc); 2513 } 2514 2515 static void 2516 bnxt_log_live_data(void *d) 2517 { 2518 struct bnxt_softc *bp = d; 2519 2520 bnxt_log_ring_states(bp); 2521 } 2522 2523 /* DDR Crash Dump Setup */ 2524 static int 2525 bnxt_crash_dump_init(struct bnxt_softc *softc) 2526 { 2527 int rc; 2528 2529 rc = bnxt_alloc_crash_dump_mem(softc); 2530 if (rc) { 2531 device_printf(softc->dev, 2532 "crash dump mem alloc failure rc: %d\n", rc); 2533 return (rc); 2534 } 2535 2536 rc = bnxt_hwrm_crash_dump_mem_cfg(softc); 2537 if (rc) { 2538 bnxt_free_crash_dump_mem(softc); 2539 device_printf(softc->dev, 2540 "hwrm crash dump mem failure rc: %d\n", rc); 2541 } 2542 2543 return (rc); 2544 } 2545 2546 /* Device setup and teardown */ 2547 static int 2548 bnxt_attach_pre(if_ctx_t ctx) 2549 { 2550 struct bnxt_softc *softc = iflib_get_softc(ctx); 2551 if_softc_ctx_t scctx; 2552 int rc = 0; 2553 2554 softc->ctx = ctx; 2555 softc->dev = iflib_get_dev(ctx); 2556 softc->media = iflib_get_media(ctx); 2557 softc->scctx = iflib_get_softc_ctx(ctx); 2558 softc->sctx = iflib_get_sctx(ctx); 2559 scctx = softc->scctx; 2560 softc->domain = pci_get_domain(softc->dev); 2561 softc->bus = pci_get_bus(softc->dev); 2562 softc->slot = pci_get_slot(softc->dev); 2563 softc->function = pci_get_function(softc->dev); 2564 softc->dev_fn = PCI_DEVFN(softc->slot, softc->function); 2565 2566 bnxt_set_flags_by_devid(softc); 2567 2568 if (bnxt_num_pfs == 0) 2569 SLIST_INIT(&pf_list); 2570 bnxt_num_pfs++; 2571 softc->list.softc = softc; 2572 SLIST_INSERT_HEAD(&pf_list, &softc->list, next); 2573 2574 pci_enable_busmaster(softc->dev); 2575 2576 if (bnxt_pci_mapping(softc)) { 2577 device_printf(softc->dev, "PCI mapping failed\n"); 2578 rc = ENXIO; 2579 goto pci_map_fail; 2580 } 2581 2582 softc->pdev = kzalloc(sizeof(*softc->pdev), GFP_KERNEL); 2583 if (!softc->pdev) { 2584 device_printf(softc->dev, "pdev alloc failed\n"); 2585 rc = -ENOMEM; 2586 goto free_pci_map; 2587 } 2588 2589 rc = linux_pci_attach_device(softc->dev, NULL, NULL, softc->pdev); 2590 if (rc) { 2591 device_printf(softc->dev, "Failed to attach Linux PCI device 0x%x\n", rc); 2592 goto pci_attach_fail; 2593 } 2594 2595 mtx_init(&softc->log_lock, "BNXT LOG Lock", NULL, MTX_DEF); 2596 TAILQ_INIT(&softc->loggers_list); 2597 bnxt_register_logger(softc, BNXT_LOGGER_L2, BNXT_L2_MAX_LOG_BUFFERS, 2598 bnxt_log_live_data, BNXT_L2_MAX_LIVE_LOG_SIZE); 2599 2600 /* HWRM setup/init */ 2601 BNXT_HWRM_LOCK_INIT(softc, device_get_nameunit(softc->dev)); 2602 rc = bnxt_alloc_hwrm_dma_mem(softc); 2603 if (rc) 2604 goto dma_fail; 2605 2606 /* Get firmware version and compare with driver */ 2607 softc->ver_info = malloc(sizeof(struct bnxt_ver_info), 2608 M_DEVBUF, M_NOWAIT | M_ZERO); 2609 if (softc->ver_info == NULL) { 2610 rc = ENOMEM; 2611 device_printf(softc->dev, 2612 "Unable to allocate space for version info\n"); 2613 goto ver_alloc_fail; 2614 } 2615 /* Default minimum required HWRM version */ 2616 softc->ver_info->hwrm_min_major = HWRM_VERSION_MAJOR; 2617 softc->ver_info->hwrm_min_minor = HWRM_VERSION_MINOR; 2618 softc->ver_info->hwrm_min_update = HWRM_VERSION_UPDATE; 2619 2620 rc = bnxt_hwrm_ver_get(softc); 2621 if (rc) { 2622 device_printf(softc->dev, "attach: hwrm ver get failed\n"); 2623 goto ver_fail; 2624 } 2625 2626 if ((softc->flags & BNXT_FLAG_SHORT_CMD) || 2627 softc->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) { 2628 rc = bnxt_alloc_hwrm_short_cmd_req(softc); 2629 if (rc) 2630 goto hwrm_short_cmd_alloc_fail; 2631 } 2632 2633 /* Now perform a function reset */ 2634 rc = bnxt_hwrm_func_reset(softc); 2635 2636 if ((softc->ver_info->chip_num == BCM57508) || 2637 (softc->ver_info->chip_num == BCM57504) || 2638 (softc->ver_info->chip_num == BCM57504_NPAR) || 2639 (softc->ver_info->chip_num == BCM57502) || 2640 (softc->ver_info->chip_num == BCM57601) || 2641 (softc->ver_info->chip_num == BCM57602) || 2642 (softc->ver_info->chip_num == BCM57604)) 2643 softc->flags |= BNXT_FLAG_CHIP_P5; 2644 2645 if (softc->ver_info->chip_num == BCM57608) 2646 softc->flags |= BNXT_FLAG_CHIP_P7; 2647 2648 softc->flags |= BNXT_FLAG_TPA; 2649 2650 if (BNXT_CHIP_P5_PLUS(softc) && (!softc->ver_info->chip_rev) && 2651 (!softc->ver_info->chip_metal)) 2652 softc->flags &= ~BNXT_FLAG_TPA; 2653 2654 if (BNXT_CHIP_P5_PLUS(softc)) 2655 softc->flags &= ~BNXT_FLAG_TPA; 2656 2657 /* Get NVRAM info */ 2658 if (BNXT_PF(softc)) { 2659 if (!bnxt_pf_wq) { 2660 bnxt_pf_wq = 2661 create_singlethread_workqueue("bnxt_pf_wq"); 2662 if (!bnxt_pf_wq) { 2663 device_printf(softc->dev, "Unable to create workqueue.\n"); 2664 rc = -ENOMEM; 2665 goto nvm_alloc_fail; 2666 } 2667 } 2668 2669 softc->nvm_info = malloc(sizeof(struct bnxt_nvram_info), 2670 M_DEVBUF, M_NOWAIT | M_ZERO); 2671 if (softc->nvm_info == NULL) { 2672 rc = ENOMEM; 2673 device_printf(softc->dev, 2674 "Unable to allocate space for NVRAM info\n"); 2675 goto nvm_alloc_fail; 2676 } 2677 2678 rc = bnxt_hwrm_nvm_get_dev_info(softc, &softc->nvm_info->mfg_id, 2679 &softc->nvm_info->device_id, &softc->nvm_info->sector_size, 2680 &softc->nvm_info->size, &softc->nvm_info->reserved_size, 2681 &softc->nvm_info->available_size); 2682 } 2683 2684 if (BNXT_CHIP_P5(softc)) { 2685 softc->db_ops.bnxt_db_tx = bnxt_thor_db_tx; 2686 softc->db_ops.bnxt_db_rx = bnxt_thor_db_rx; 2687 softc->db_ops.bnxt_db_rx_cq = bnxt_thor_db_rx_cq; 2688 softc->db_ops.bnxt_db_tx_cq = bnxt_thor_db_tx_cq; 2689 softc->db_ops.bnxt_db_nq = bnxt_thor_db_nq; 2690 } else if (BNXT_CHIP_P7(softc)) { 2691 softc->db_ops.bnxt_db_tx = bnxt_thor2_db_tx; 2692 softc->db_ops.bnxt_db_rx = bnxt_thor2_db_rx; 2693 softc->db_ops.bnxt_db_rx_cq = bnxt_thor2_db_rx_cq; 2694 softc->db_ops.bnxt_db_tx_cq = bnxt_thor2_db_tx_cq; 2695 softc->db_ops.bnxt_db_nq = bnxt_thor2_db_nq; 2696 } else { 2697 softc->db_ops.bnxt_db_tx = bnxt_cuw_db_tx; 2698 softc->db_ops.bnxt_db_rx = bnxt_cuw_db_rx; 2699 softc->db_ops.bnxt_db_rx_cq = bnxt_cuw_db_cq; 2700 softc->db_ops.bnxt_db_tx_cq = bnxt_cuw_db_cq; 2701 } 2702 2703 2704 /* Get the queue config */ 2705 rc = bnxt_hwrm_queue_qportcfg(softc, HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX); 2706 if (rc) { 2707 device_printf(softc->dev, "attach: hwrm qportcfg (tx) failed\n"); 2708 goto failed; 2709 } 2710 if (softc->is_asym_q) { 2711 rc = bnxt_hwrm_queue_qportcfg(softc, 2712 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX); 2713 if (rc) { 2714 device_printf(softc->dev, "attach: hwrm qportcfg (rx) failed\n"); 2715 return rc; 2716 } 2717 bnxt_verify_asym_queues(softc); 2718 } else { 2719 softc->rx_max_q = softc->tx_max_q; 2720 memcpy(softc->rx_q_info, softc->tx_q_info, sizeof(softc->rx_q_info)); 2721 memcpy(softc->rx_q_ids, softc->tx_q_ids, sizeof(softc->rx_q_ids)); 2722 } 2723 2724 /* Get the HW capabilities */ 2725 rc = bnxt_hwrm_func_qcaps(softc); 2726 if (rc) 2727 goto failed; 2728 2729 /* Inform PF to approve MAC as default VF MAC. */ 2730 if (BNXT_VF(softc)) { 2731 rc = bnxt_approve_mac(softc); 2732 if (rc) { 2733 device_printf(softc->dev, "attach: bnxt_approve_mac failed\n"); 2734 goto failed; 2735 } 2736 } 2737 2738 bnxt_hwrm_dbg_qcaps(softc); 2739 2740 /* 2741 * Register the driver with the FW 2742 * Register the async events with the FW 2743 */ 2744 rc = bnxt_drv_rgtr(softc); 2745 if (rc) 2746 goto failed; 2747 2748 if (softc->hwrm_spec_code >= 0x10803) { 2749 rc = bnxt_alloc_ctx_mem(softc); 2750 if (rc) { 2751 device_printf(softc->dev, "attach: alloc_ctx_mem failed\n"); 2752 return rc; 2753 } 2754 rc = bnxt_hwrm_func_resc_qcaps(softc, true); 2755 if (!rc) 2756 softc->flags |= BNXT_FLAG_FW_CAP_NEW_RM; 2757 } 2758 2759 /* Get the current configuration of this function */ 2760 rc = bnxt_hwrm_func_qcfg(softc); 2761 if (rc) { 2762 device_printf(softc->dev, "attach: hwrm func qcfg failed\n"); 2763 goto failed; 2764 } 2765 2766 scctx->isc_txrx = &bnxt_txrx; 2767 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | 2768 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_TSO); 2769 scctx->isc_capabilities = scctx->isc_capenable = 2770 /* These are translated to hwassit bits */ 2771 IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | IFCAP_TSO4 | IFCAP_TSO6 | 2772 /* These are checked by iflib */ 2773 IFCAP_LRO | IFCAP_VLAN_HWFILTER | 2774 /* These are part of the iflib mask */ 2775 IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | IFCAP_VLAN_MTU | 2776 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | 2777 /* These likely get lost... */ 2778 IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU; 2779 2780 if (bnxt_wol_supported(softc)) 2781 scctx->isc_capabilities |= IFCAP_WOL_MAGIC; 2782 bnxt_get_wol_settings(softc); 2783 if (softc->wol) 2784 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 2785 2786 /* Get the queue config */ 2787 bnxt_get_wol_settings(softc); 2788 2789 if (BNXT_CHIP_P5_PLUS(softc)) 2790 bnxt_hwrm_reserve_rings(softc); 2791 2792 rc = bnxt_hwrm_func_qcfg(softc); 2793 if (rc) { 2794 device_printf(softc->dev, "attach: hwrm func qcfg failed\n"); 2795 goto failed; 2796 } 2797 2798 bnxt_clear_ids(softc); 2799 if (rc) 2800 goto failed; 2801 2802 /* Now set up iflib sc */ 2803 scctx->isc_tx_nsegments = 31, 2804 scctx->isc_tx_tso_segments_max = 31; 2805 scctx->isc_tx_tso_size_max = BNXT_TSO_SIZE; 2806 scctx->isc_tx_tso_segsize_max = BNXT_TSO_SIZE; 2807 scctx->isc_vectors = softc->func.max_cp_rings; 2808 scctx->isc_min_frame_size = BNXT_MIN_FRAME_SIZE; 2809 scctx->isc_txrx = &bnxt_txrx; 2810 2811 if (scctx->isc_nrxd[0] < 2812 ((scctx->isc_nrxd[1] * 4) + scctx->isc_nrxd[2])) 2813 device_printf(softc->dev, 2814 "WARNING: nrxd0 (%d) should be at least 4 * nrxd1 (%d) + nrxd2 (%d). Driver may be unstable\n", 2815 scctx->isc_nrxd[0], scctx->isc_nrxd[1], scctx->isc_nrxd[2]); 2816 if (scctx->isc_ntxd[0] < scctx->isc_ntxd[1] * 2) 2817 device_printf(softc->dev, 2818 "WARNING: ntxd0 (%d) should be at least 2 * ntxd1 (%d). Driver may be unstable\n", 2819 scctx->isc_ntxd[0], scctx->isc_ntxd[1]); 2820 scctx->isc_txqsizes[0] = sizeof(struct cmpl_base) * scctx->isc_ntxd[0]; 2821 scctx->isc_txqsizes[1] = sizeof(struct tx_bd_short) * 2822 scctx->isc_ntxd[1]; 2823 scctx->isc_txqsizes[2] = sizeof(struct cmpl_base) * scctx->isc_ntxd[2]; 2824 scctx->isc_rxqsizes[0] = sizeof(struct cmpl_base) * scctx->isc_nrxd[0]; 2825 scctx->isc_rxqsizes[1] = sizeof(struct rx_prod_pkt_bd) * 2826 scctx->isc_nrxd[1]; 2827 scctx->isc_rxqsizes[2] = sizeof(struct rx_prod_pkt_bd) * 2828 scctx->isc_nrxd[2]; 2829 2830 scctx->isc_nrxqsets_max = min(pci_msix_count(softc->dev)-1, 2831 softc->fn_qcfg.alloc_completion_rings - 1); 2832 scctx->isc_nrxqsets_max = min(scctx->isc_nrxqsets_max, 2833 softc->fn_qcfg.alloc_rx_rings); 2834 scctx->isc_nrxqsets_max = min(scctx->isc_nrxqsets_max, 2835 softc->fn_qcfg.alloc_vnics); 2836 scctx->isc_ntxqsets_max = min(softc->fn_qcfg.alloc_tx_rings, 2837 softc->fn_qcfg.alloc_completion_rings - scctx->isc_nrxqsets_max - 1); 2838 2839 scctx->isc_rss_table_size = HW_HASH_INDEX_SIZE; 2840 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 2841 2842 /* iflib will map and release this bar */ 2843 scctx->isc_msix_bar = pci_msix_table_bar(softc->dev); 2844 2845 /* 2846 * Default settings for HW LRO (TPA): 2847 * Disable HW LRO by default 2848 * Can be enabled after taking care of 'packet forwarding' 2849 */ 2850 if (softc->flags & BNXT_FLAG_TPA) { 2851 softc->hw_lro.enable = 0; 2852 softc->hw_lro.is_mode_gro = 0; 2853 softc->hw_lro.max_agg_segs = 5; /* 2^5 = 32 segs */ 2854 softc->hw_lro.max_aggs = HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX; 2855 softc->hw_lro.min_agg_len = 512; 2856 } 2857 2858 /* Allocate the default completion ring */ 2859 softc->def_cp_ring.stats_ctx_id = HWRM_NA_SIGNATURE; 2860 softc->def_cp_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; 2861 softc->def_cp_ring.ring.softc = softc; 2862 softc->def_cp_ring.ring.id = 0; 2863 softc->def_cp_ring.ring.doorbell = (BNXT_CHIP_P5_PLUS(softc)) ? 2864 softc->legacy_db_size : softc->def_cp_ring.ring.id * 0x80; 2865 softc->def_cp_ring.ring.ring_size = PAGE_SIZE / 2866 sizeof(struct cmpl_base); 2867 softc->def_cp_ring.ring.db_ring_mask = softc->def_cp_ring.ring.ring_size -1 ; 2868 rc = iflib_dma_alloc(ctx, 2869 sizeof(struct cmpl_base) * softc->def_cp_ring.ring.ring_size, 2870 &softc->def_cp_ring_mem, 0); 2871 softc->def_cp_ring.ring.vaddr = softc->def_cp_ring_mem.idi_vaddr; 2872 softc->def_cp_ring.ring.paddr = softc->def_cp_ring_mem.idi_paddr; 2873 iflib_config_task_init(ctx, &softc->def_cp_task, bnxt_def_cp_task); 2874 2875 rc = bnxt_init_sysctl_ctx(softc); 2876 if (rc) 2877 goto init_sysctl_failed; 2878 if (BNXT_PF(softc)) { 2879 rc = bnxt_create_nvram_sysctls(softc->nvm_info); 2880 if (rc) 2881 goto failed; 2882 } 2883 2884 arc4rand(softc->vnic_info.rss_hash_key, HW_HASH_KEY_SIZE, 0); 2885 softc->vnic_info.rss_hash_type = 2886 HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 | 2887 HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 | 2888 HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 | 2889 HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 | 2890 HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 | 2891 HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2892 rc = bnxt_create_config_sysctls_pre(softc); 2893 if (rc) 2894 goto failed; 2895 2896 rc = bnxt_create_hw_lro_sysctls(softc); 2897 if (rc) 2898 goto failed; 2899 2900 rc = bnxt_create_pause_fc_sysctls(softc); 2901 if (rc) 2902 goto failed; 2903 2904 rc = bnxt_create_dcb_sysctls(softc); 2905 if (rc) 2906 goto failed; 2907 2908 set_bit(BNXT_STATE_OPEN, &softc->state); 2909 INIT_WORK(&softc->sp_task, bnxt_sp_task); 2910 INIT_DELAYED_WORK(&softc->fw_reset_task, bnxt_fw_reset_task); 2911 2912 /* Initialize the vlan list */ 2913 SLIST_INIT(&softc->vnic_info.vlan_tags); 2914 softc->vnic_info.vlan_tag_list.idi_vaddr = NULL; 2915 softc->state_bv = bit_alloc(BNXT_STATE_MAX, M_DEVBUF, 2916 M_WAITOK|M_ZERO); 2917 2918 if (BNXT_PF(softc)) { 2919 const char *part_num; 2920 2921 if (pci_get_vpd_readonly(softc->dev, "PN", &part_num) == 0) 2922 snprintf(softc->board_partno, sizeof(softc->board_partno), "%s", part_num); 2923 } 2924 2925 return (rc); 2926 2927 2928 failed: 2929 bnxt_free_sysctl_ctx(softc); 2930 init_sysctl_failed: 2931 bnxt_hwrm_func_drv_unrgtr(softc, false); 2932 if (BNXT_PF(softc)) 2933 free(softc->nvm_info, M_DEVBUF); 2934 nvm_alloc_fail: 2935 bnxt_free_hwrm_short_cmd_req(softc); 2936 hwrm_short_cmd_alloc_fail: 2937 ver_fail: 2938 free(softc->ver_info, M_DEVBUF); 2939 ver_alloc_fail: 2940 bnxt_free_hwrm_dma_mem(softc); 2941 dma_fail: 2942 BNXT_HWRM_LOCK_DESTROY(softc); 2943 if (softc->pdev) 2944 linux_pci_detach_device(softc->pdev); 2945 pci_attach_fail: 2946 kfree(softc->pdev); 2947 softc->pdev = NULL; 2948 free_pci_map: 2949 bnxt_pci_mapping_free(softc); 2950 pci_map_fail: 2951 pci_disable_busmaster(softc->dev); 2952 return (rc); 2953 } 2954 2955 static int 2956 bnxt_attach_post(if_ctx_t ctx) 2957 { 2958 struct bnxt_softc *softc = iflib_get_softc(ctx); 2959 if_t ifp = iflib_get_ifp(ctx); 2960 int rc; 2961 2962 softc->ifp = ifp; 2963 bnxt_create_config_sysctls_post(softc); 2964 2965 /* Update link state etc... */ 2966 rc = bnxt_probe_phy(softc); 2967 if (rc) 2968 goto failed; 2969 2970 /* Needs to be done after probing the phy */ 2971 bnxt_create_ver_sysctls(softc); 2972 ifmedia_removeall(softc->media); 2973 bnxt_add_media_types(softc); 2974 ifmedia_set(softc->media, IFM_ETHER | IFM_AUTO); 2975 2976 softc->scctx->isc_max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + 2977 ETHER_CRC_LEN; 2978 2979 softc->rx_buf_size = min(softc->scctx->isc_max_frame_size, BNXT_PAGE_SIZE); 2980 bnxt_dcb_init(softc); 2981 bnxt_rdma_aux_device_init(softc); 2982 2983 /* SR-IOV attach */ 2984 if (BNXT_PF(softc) && BNXT_CHIP_P5_PLUS(softc)) 2985 bnxt_sriov_attach(softc); 2986 2987 rc = bnxt_crash_dump_init(softc); 2988 if (rc) 2989 device_printf(softc->dev, 2990 "crash dump init failure rc: %d\n", rc); 2991 2992 failed: 2993 return rc; 2994 } 2995 2996 static int 2997 bnxt_detach(if_ctx_t ctx) 2998 { 2999 struct bnxt_softc *softc = iflib_get_softc(ctx); 3000 struct bnxt_vlan_tag *tag; 3001 struct bnxt_vlan_tag *tmp; 3002 int i; 3003 3004 bnxt_rdma_aux_device_uninit(softc); 3005 cancel_delayed_work_sync(&softc->fw_reset_task); 3006 cancel_work_sync(&softc->sp_task); 3007 bnxt_dcb_free(softc); 3008 SLIST_REMOVE(&pf_list, &softc->list, bnxt_softc_list, next); 3009 bnxt_num_pfs--; 3010 bnxt_wol_config(ctx); 3011 bnxt_do_disable_intr(&softc->def_cp_ring); 3012 bnxt_free_sysctl_ctx(softc); 3013 bnxt_free_crash_dump_mem(softc); 3014 bnxt_hwrm_func_reset(softc); 3015 bnxt_free_ctx_mem(softc); 3016 bnxt_clear_ids(softc); 3017 iflib_irq_free(ctx, &softc->def_cp_ring.irq); 3018 /* We need to free() these here... */ 3019 for (i = softc->nrxqsets-1; i>=0; i--) { 3020 if (BNXT_CHIP_P5_PLUS(softc)) 3021 iflib_irq_free(ctx, &softc->nq_rings[i].irq); 3022 else 3023 iflib_irq_free(ctx, &softc->rx_cp_rings[i].irq); 3024 3025 } 3026 iflib_dma_free(&softc->vnic_info.mc_list); 3027 iflib_dma_free(&softc->vnic_info.rss_hash_key_tbl); 3028 iflib_dma_free(&softc->vnic_info.rss_grp_tbl); 3029 if (softc->vnic_info.vlan_tag_list.idi_vaddr) 3030 iflib_dma_free(&softc->vnic_info.vlan_tag_list); 3031 SLIST_FOREACH_SAFE(tag, &softc->vnic_info.vlan_tags, next, tmp) 3032 free(tag, M_DEVBUF); 3033 iflib_dma_free(&softc->def_cp_ring_mem); 3034 for (i = 0; i < softc->nrxqsets; i++) 3035 free(softc->rx_rings[i].tpa_start, M_DEVBUF); 3036 free(softc->ver_info, M_DEVBUF); 3037 if (BNXT_PF(softc)) 3038 free(softc->nvm_info, M_DEVBUF); 3039 3040 bnxt_hwrm_func_drv_unrgtr(softc, false); 3041 bnxt_free_hwrm_dma_mem(softc); 3042 bnxt_free_hwrm_short_cmd_req(softc); 3043 BNXT_HWRM_LOCK_DESTROY(softc); 3044 3045 bnxt_unregister_logger(softc, BNXT_LOGGER_L2); 3046 mtx_destroy(&softc->log_lock); 3047 3048 if (!bnxt_num_pfs && bnxt_pf_wq) 3049 destroy_workqueue(bnxt_pf_wq); 3050 3051 if (softc->pdev) 3052 linux_pci_detach_device(softc->pdev); 3053 free(softc->state_bv, M_DEVBUF); 3054 pci_disable_busmaster(softc->dev); 3055 bnxt_pci_mapping_free(softc); 3056 3057 return 0; 3058 } 3059 3060 static void 3061 bnxt_hwrm_resource_free(struct bnxt_softc *softc) 3062 { 3063 int i, rc = 0; 3064 3065 rc = bnxt_hwrm_ring_free(softc, 3066 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, 3067 &softc->def_cp_ring.ring, 3068 (uint16_t)HWRM_NA_SIGNATURE); 3069 if (rc) 3070 goto fail; 3071 3072 for (i = 0; i < softc->ntxqsets; i++) { 3073 rc = bnxt_hwrm_ring_free(softc, 3074 HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, 3075 &softc->tx_rings[i], 3076 softc->tx_cp_rings[i].ring.phys_id); 3077 if (rc) 3078 goto fail; 3079 3080 rc = bnxt_hwrm_ring_free(softc, 3081 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, 3082 &softc->tx_cp_rings[i].ring, 3083 (uint16_t)HWRM_NA_SIGNATURE); 3084 if (rc) 3085 goto fail; 3086 3087 rc = bnxt_hwrm_stat_ctx_free(softc, &softc->tx_cp_rings[i]); 3088 if (rc) 3089 goto fail; 3090 } 3091 rc = bnxt_hwrm_free_filter(softc); 3092 if (rc) 3093 goto fail; 3094 3095 rc = bnxt_hwrm_vnic_free(softc, &softc->vnic_info); 3096 if (rc) 3097 goto fail; 3098 3099 rc = bnxt_hwrm_vnic_ctx_free(softc, softc->vnic_info.rss_id); 3100 if (rc) 3101 goto fail; 3102 3103 for (i = 0; i < softc->nrxqsets; i++) { 3104 rc = bnxt_hwrm_ring_grp_free(softc, &softc->grp_info[i]); 3105 if (rc) 3106 goto fail; 3107 3108 rc = bnxt_hwrm_ring_free(softc, 3109 HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG, 3110 &softc->ag_rings[i], 3111 (uint16_t)HWRM_NA_SIGNATURE); 3112 if (rc) 3113 goto fail; 3114 3115 rc = bnxt_hwrm_ring_free(softc, 3116 HWRM_RING_ALLOC_INPUT_RING_TYPE_RX, 3117 &softc->rx_rings[i], 3118 softc->rx_cp_rings[i].ring.phys_id); 3119 if (rc) 3120 goto fail; 3121 3122 rc = bnxt_hwrm_ring_free(softc, 3123 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, 3124 &softc->rx_cp_rings[i].ring, 3125 (uint16_t)HWRM_NA_SIGNATURE); 3126 if (rc) 3127 goto fail; 3128 3129 if (BNXT_CHIP_P5_PLUS(softc)) { 3130 rc = bnxt_hwrm_ring_free(softc, 3131 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ, 3132 &softc->nq_rings[i].ring, 3133 (uint16_t)HWRM_NA_SIGNATURE); 3134 if (rc) 3135 goto fail; 3136 } 3137 3138 rc = bnxt_hwrm_stat_ctx_free(softc, &softc->rx_cp_rings[i]); 3139 if (rc) 3140 goto fail; 3141 } 3142 3143 fail: 3144 return; 3145 } 3146 3147 3148 static void 3149 bnxt_func_reset(struct bnxt_softc *softc) 3150 { 3151 3152 if (!BNXT_CHIP_P5_PLUS(softc)) { 3153 bnxt_hwrm_func_reset(softc); 3154 return; 3155 } 3156 3157 bnxt_hwrm_resource_free(softc); 3158 return; 3159 } 3160 3161 static void 3162 bnxt_rss_grp_tbl_init(struct bnxt_softc *softc) 3163 { 3164 uint16_t *rgt = (uint16_t *) softc->vnic_info.rss_grp_tbl.idi_vaddr; 3165 int i, j; 3166 3167 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { 3168 if (BNXT_CHIP_P5_PLUS(softc)) { 3169 rgt[i++] = htole16(softc->rx_rings[j].phys_id); 3170 rgt[i] = htole16(softc->rx_cp_rings[j].ring.phys_id); 3171 } else { 3172 rgt[i] = htole16(softc->grp_info[j].grp_id); 3173 } 3174 if (++j == softc->nrxqsets) 3175 j = 0; 3176 } 3177 } 3178 3179 static void bnxt_get_port_module_status(struct bnxt_softc *softc) 3180 { 3181 struct bnxt_link_info *link_info = &softc->link_info; 3182 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp; 3183 uint8_t module_status; 3184 3185 if (bnxt_update_link(softc, false)) 3186 return; 3187 3188 module_status = link_info->module_status; 3189 switch (module_status) { 3190 case HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX: 3191 case HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN: 3192 case HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG: 3193 device_printf(softc->dev, "Unqualified SFP+ module detected on port %d\n", 3194 softc->pf.port_id); 3195 if (softc->hwrm_spec_code >= 0x10201) { 3196 device_printf(softc->dev, "Module part number %s\n", 3197 resp->phy_vendor_partnumber); 3198 } 3199 if (module_status == HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX) 3200 device_printf(softc->dev, "TX is disabled\n"); 3201 if (module_status == HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN) 3202 device_printf(softc->dev, "SFP+ module is shutdown\n"); 3203 } 3204 } 3205 3206 static void bnxt_aux_dev_free(struct bnxt_softc *softc) 3207 { 3208 kfree(softc->aux_dev); 3209 softc->aux_dev = NULL; 3210 } 3211 3212 static struct bnxt_aux_dev *bnxt_aux_dev_init(struct bnxt_softc *softc) 3213 { 3214 struct bnxt_aux_dev *bnxt_adev; 3215 3216 msleep(1000 * 2); 3217 bnxt_adev = kzalloc(sizeof(*bnxt_adev), GFP_KERNEL); 3218 if (!bnxt_adev) 3219 return ERR_PTR(-ENOMEM); 3220 3221 return bnxt_adev; 3222 } 3223 3224 static void bnxt_rdma_aux_device_uninit(struct bnxt_softc *softc) 3225 { 3226 struct bnxt_aux_dev *bnxt_adev = softc->aux_dev; 3227 3228 /* Skip if no auxiliary device init was done. */ 3229 if (!(softc->flags & BNXT_FLAG_ROCE_CAP)) 3230 return; 3231 3232 if (IS_ERR_OR_NULL(bnxt_adev)) 3233 return; 3234 3235 bnxt_rdma_aux_device_del(softc); 3236 3237 if (bnxt_adev->id >= 0) 3238 ida_free(&bnxt_aux_dev_ids, bnxt_adev->id); 3239 3240 bnxt_aux_dev_free(softc); 3241 } 3242 3243 static void bnxt_rdma_aux_device_init(struct bnxt_softc *softc) 3244 { 3245 int rc; 3246 3247 if (!(softc->flags & BNXT_FLAG_ROCE_CAP)) 3248 return; 3249 3250 softc->aux_dev = bnxt_aux_dev_init(softc); 3251 if (IS_ERR_OR_NULL(softc->aux_dev)) { 3252 device_printf(softc->dev, "Failed to init auxiliary device for ROCE\n"); 3253 goto skip_aux_init; 3254 } 3255 3256 softc->aux_dev->id = ida_alloc(&bnxt_aux_dev_ids, GFP_KERNEL); 3257 if (softc->aux_dev->id < 0) { 3258 device_printf(softc->dev, "ida alloc failed for ROCE auxiliary device\n"); 3259 bnxt_aux_dev_free(softc); 3260 goto skip_aux_init; 3261 } 3262 3263 msleep(1000 * 2); 3264 /* If aux bus init fails, continue with netdev init. */ 3265 rc = bnxt_rdma_aux_device_add(softc); 3266 if (rc) { 3267 device_printf(softc->dev, "Failed to add auxiliary device for ROCE\n"); 3268 msleep(1000 * 2); 3269 ida_free(&bnxt_aux_dev_ids, softc->aux_dev->id); 3270 } 3271 device_printf(softc->dev, "%s:%d Added auxiliary device (id %d) for ROCE \n", 3272 __func__, __LINE__, softc->aux_dev->id); 3273 skip_aux_init: 3274 return; 3275 } 3276 3277 /* Device configuration */ 3278 static void 3279 bnxt_init(if_ctx_t ctx) 3280 { 3281 struct bnxt_softc *softc = iflib_get_softc(ctx); 3282 struct ifmediareq ifmr; 3283 int i; 3284 int rc; 3285 3286 if (!BNXT_CHIP_P5_PLUS(softc)) { 3287 rc = bnxt_hwrm_func_reset(softc); 3288 if (rc) 3289 return; 3290 } else if (softc->is_dev_init) { 3291 bnxt_stop(ctx); 3292 } 3293 3294 softc->is_dev_init = true; 3295 bnxt_clear_ids(softc); 3296 3297 if (BNXT_CHIP_P5_PLUS(softc)) 3298 goto skip_def_cp_ring; 3299 /* Allocate the default completion ring */ 3300 softc->def_cp_ring.cons = UINT32_MAX; 3301 softc->def_cp_ring.v_bit = 1; 3302 bnxt_mark_cpr_invalid(&softc->def_cp_ring); 3303 rc = bnxt_hwrm_ring_alloc(softc, 3304 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, 3305 &softc->def_cp_ring.ring); 3306 bnxt_set_db_mask(softc, &softc->def_cp_ring.ring, 3307 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL); 3308 if (rc) 3309 goto fail; 3310 skip_def_cp_ring: 3311 for (i = 0; i < softc->nrxqsets; i++) { 3312 /* Allocate the statistics context */ 3313 rc = bnxt_hwrm_stat_ctx_alloc(softc, &softc->rx_cp_rings[i], 3314 softc->rx_stats[i].idi_paddr); 3315 if (rc) 3316 goto fail; 3317 3318 if (BNXT_CHIP_P5_PLUS(softc)) { 3319 /* Allocate the NQ */ 3320 softc->nq_rings[i].cons = 0; 3321 softc->nq_rings[i].raw_cons = 0; 3322 softc->nq_rings[i].v_bit = 1; 3323 softc->nq_rings[i].last_idx = UINT32_MAX; 3324 bnxt_mark_cpr_invalid(&softc->nq_rings[i]); 3325 rc = bnxt_hwrm_ring_alloc(softc, 3326 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ, 3327 &softc->nq_rings[i].ring); 3328 bnxt_set_db_mask(softc, &softc->nq_rings[i].ring, 3329 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ); 3330 if (rc) 3331 goto fail; 3332 3333 softc->db_ops.bnxt_db_nq(&softc->nq_rings[i], 1); 3334 } 3335 /* Allocate the completion ring */ 3336 softc->rx_cp_rings[i].cons = UINT32_MAX; 3337 softc->rx_cp_rings[i].raw_cons = UINT32_MAX; 3338 softc->rx_cp_rings[i].v_bit = 1; 3339 softc->rx_cp_rings[i].last_idx = UINT32_MAX; 3340 softc->rx_cp_rings[i].toggle = 0; 3341 bnxt_mark_cpr_invalid(&softc->rx_cp_rings[i]); 3342 rc = bnxt_hwrm_ring_alloc(softc, 3343 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, 3344 &softc->rx_cp_rings[i].ring); 3345 bnxt_set_db_mask(softc, &softc->rx_cp_rings[i].ring, 3346 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL); 3347 if (rc) 3348 goto fail; 3349 3350 if (BNXT_CHIP_P5_PLUS(softc)) 3351 softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[i], 1); 3352 3353 /* Allocate the RX ring */ 3354 rc = bnxt_hwrm_ring_alloc(softc, 3355 HWRM_RING_ALLOC_INPUT_RING_TYPE_RX, &softc->rx_rings[i]); 3356 bnxt_set_db_mask(softc, &softc->rx_rings[i], 3357 HWRM_RING_ALLOC_INPUT_RING_TYPE_RX); 3358 if (rc) 3359 goto fail; 3360 softc->db_ops.bnxt_db_rx(&softc->rx_rings[i], 0); 3361 3362 /* Allocate the AG ring */ 3363 rc = bnxt_hwrm_ring_alloc(softc, 3364 HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG, 3365 &softc->ag_rings[i]); 3366 bnxt_set_db_mask(softc, &softc->ag_rings[i], 3367 HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG); 3368 if (rc) 3369 goto fail; 3370 softc->db_ops.bnxt_db_rx(&softc->ag_rings[i], 0); 3371 3372 /* Allocate the ring group */ 3373 softc->grp_info[i].stats_ctx = 3374 softc->rx_cp_rings[i].stats_ctx_id; 3375 softc->grp_info[i].rx_ring_id = softc->rx_rings[i].phys_id; 3376 softc->grp_info[i].ag_ring_id = softc->ag_rings[i].phys_id; 3377 softc->grp_info[i].cp_ring_id = 3378 softc->rx_cp_rings[i].ring.phys_id; 3379 rc = bnxt_hwrm_ring_grp_alloc(softc, &softc->grp_info[i]); 3380 if (rc) 3381 goto fail; 3382 } 3383 3384 /* Inform PF to approve MAC as default VF MAC. */ 3385 if (BNXT_VF(softc)) 3386 bnxt_update_vf_mac(softc); 3387 3388 /* And now set the default CP / NQ ring for the async */ 3389 rc = bnxt_cfg_async_cr(softc); 3390 if (rc) 3391 goto fail; 3392 3393 /* Allocate the VNIC RSS context */ 3394 rc = bnxt_hwrm_vnic_ctx_alloc(softc, &softc->vnic_info.rss_id); 3395 if (rc) 3396 goto fail; 3397 3398 /* Allocate the vnic */ 3399 softc->vnic_info.def_ring_grp = softc->grp_info[0].grp_id; 3400 softc->vnic_info.mru = softc->scctx->isc_max_frame_size; 3401 rc = bnxt_hwrm_vnic_alloc(softc, &softc->vnic_info); 3402 if (rc) 3403 goto fail; 3404 rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); 3405 if (rc) 3406 goto fail; 3407 rc = bnxt_hwrm_vnic_set_hds(softc, &softc->vnic_info); 3408 if (rc) 3409 goto fail; 3410 rc = bnxt_hwrm_set_filter(softc); 3411 if (rc) 3412 goto fail; 3413 3414 bnxt_rss_grp_tbl_init(softc); 3415 3416 rc = bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, 3417 softc->vnic_info.rss_hash_type); 3418 if (rc) 3419 goto fail; 3420 3421 rc = bnxt_hwrm_vnic_tpa_cfg(softc); 3422 if (rc) 3423 goto fail; 3424 3425 for (i = 0; i < softc->ntxqsets; i++) { 3426 /* Allocate the statistics context */ 3427 rc = bnxt_hwrm_stat_ctx_alloc(softc, &softc->tx_cp_rings[i], 3428 softc->tx_stats[i].idi_paddr); 3429 if (rc) 3430 goto fail; 3431 3432 /* Allocate the completion ring */ 3433 softc->tx_cp_rings[i].cons = UINT32_MAX; 3434 softc->tx_cp_rings[i].raw_cons = UINT32_MAX; 3435 softc->tx_cp_rings[i].v_bit = 1; 3436 softc->tx_cp_rings[i].toggle = 0; 3437 bnxt_mark_cpr_invalid(&softc->tx_cp_rings[i]); 3438 rc = bnxt_hwrm_ring_alloc(softc, 3439 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL, 3440 &softc->tx_cp_rings[i].ring); 3441 bnxt_set_db_mask(softc, &softc->tx_cp_rings[i].ring, 3442 HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL); 3443 if (rc) 3444 goto fail; 3445 3446 if (BNXT_CHIP_P5_PLUS(softc)) 3447 softc->db_ops.bnxt_db_tx_cq(&softc->tx_cp_rings[i], 1); 3448 3449 /* Allocate the TX ring */ 3450 rc = bnxt_hwrm_ring_alloc(softc, 3451 HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, 3452 &softc->tx_rings[i]); 3453 bnxt_set_db_mask(softc, &softc->tx_rings[i], 3454 HWRM_RING_ALLOC_INPUT_RING_TYPE_TX); 3455 if (rc) 3456 goto fail; 3457 softc->db_ops.bnxt_db_tx(&softc->tx_rings[i], 0); 3458 } 3459 3460 bnxt_do_enable_intr(&softc->def_cp_ring); 3461 bnxt_get_port_module_status(softc); 3462 bnxt_media_status(softc->ctx, &ifmr); 3463 bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); 3464 return; 3465 3466 fail: 3467 bnxt_func_reset(softc); 3468 bnxt_clear_ids(softc); 3469 return; 3470 } 3471 3472 static void 3473 bnxt_stop(if_ctx_t ctx) 3474 { 3475 struct bnxt_softc *softc = iflib_get_softc(ctx); 3476 3477 softc->is_dev_init = false; 3478 bnxt_do_disable_intr(&softc->def_cp_ring); 3479 bnxt_func_reset(softc); 3480 bnxt_clear_ids(softc); 3481 return; 3482 } 3483 3484 static u_int 3485 bnxt_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3486 { 3487 uint8_t *mta = arg; 3488 3489 if (cnt == BNXT_MAX_MC_ADDRS) 3490 return (1); 3491 3492 bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 3493 3494 return (1); 3495 } 3496 3497 static void 3498 bnxt_multi_set(if_ctx_t ctx) 3499 { 3500 struct bnxt_softc *softc = iflib_get_softc(ctx); 3501 if_t ifp = iflib_get_ifp(ctx); 3502 uint8_t *mta; 3503 int mcnt; 3504 3505 mta = softc->vnic_info.mc_list.idi_vaddr; 3506 bzero(mta, softc->vnic_info.mc_list.idi_size); 3507 mcnt = if_foreach_llmaddr(ifp, bnxt_copy_maddr, mta); 3508 3509 if (mcnt > BNXT_MAX_MC_ADDRS) { 3510 softc->vnic_info.rx_mask |= 3511 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; 3512 bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); 3513 } else { 3514 softc->vnic_info.rx_mask &= 3515 ~HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; 3516 bus_dmamap_sync(softc->vnic_info.mc_list.idi_tag, 3517 softc->vnic_info.mc_list.idi_map, BUS_DMASYNC_PREWRITE); 3518 softc->vnic_info.mc_list_count = mcnt; 3519 softc->vnic_info.rx_mask |= 3520 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST; 3521 if (bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info)) 3522 device_printf(softc->dev, 3523 "set_multi: rx_mask set failed\n"); 3524 } 3525 } 3526 3527 static int 3528 bnxt_mtu_set(if_ctx_t ctx, uint32_t mtu) 3529 { 3530 struct bnxt_softc *softc = iflib_get_softc(ctx); 3531 3532 if (mtu > BNXT_MAX_MTU) 3533 return EINVAL; 3534 3535 softc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 3536 softc->rx_buf_size = min(softc->scctx->isc_max_frame_size, BNXT_PAGE_SIZE); 3537 return 0; 3538 } 3539 3540 static void 3541 bnxt_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) 3542 { 3543 struct bnxt_softc *softc = iflib_get_softc(ctx); 3544 struct bnxt_link_info *link_info = &softc->link_info; 3545 struct ifmedia_entry *next; 3546 uint64_t target_baudrate = bnxt_get_baudrate(link_info); 3547 int active_media = IFM_UNKNOWN; 3548 3549 bnxt_update_link(softc, true); 3550 3551 ifmr->ifm_status = IFM_AVALID; 3552 ifmr->ifm_active = IFM_ETHER; 3553 3554 if (!link_info->link_up) 3555 return; 3556 3557 ifmr->ifm_status |= IFM_ACTIVE; 3558 if (link_info->duplex == HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL) 3559 ifmr->ifm_active |= IFM_FDX; 3560 else 3561 ifmr->ifm_active |= IFM_HDX; 3562 3563 /* 3564 * Go through the list of supported media which got prepared 3565 * as part of bnxt_add_media_types() using api ifmedia_add(). 3566 */ 3567 LIST_FOREACH(next, &(iflib_get_media(ctx)->ifm_list), ifm_list) { 3568 if (ifmedia_baudrate(next->ifm_media) == target_baudrate) { 3569 active_media = next->ifm_media; 3570 break; 3571 } 3572 } 3573 ifmr->ifm_active |= active_media; 3574 3575 if (link_info->flow_ctrl.rx) 3576 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3577 if (link_info->flow_ctrl.tx) 3578 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3579 3580 bnxt_report_link(softc); 3581 return; 3582 } 3583 3584 static int 3585 bnxt_media_change(if_ctx_t ctx) 3586 { 3587 struct bnxt_softc *softc = iflib_get_softc(ctx); 3588 struct ifmedia *ifm = iflib_get_media(ctx); 3589 struct ifmediareq ifmr; 3590 int rc; 3591 struct bnxt_link_info *link_info = &softc->link_info; 3592 3593 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3594 return EINVAL; 3595 3596 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3597 case IFM_100_T: 3598 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3599 link_info->req_link_speed = 3600 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB; 3601 break; 3602 case IFM_1000_KX: 3603 case IFM_1000_SGMII: 3604 case IFM_1000_CX: 3605 case IFM_1000_SX: 3606 case IFM_1000_LX: 3607 3608 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3609 3610 if (link_info->support_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) { 3611 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB; 3612 3613 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB) { 3614 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB; 3615 link_info->force_speed2_nrz = true; 3616 } 3617 3618 break; 3619 3620 case IFM_2500_KX: 3621 case IFM_2500_T: 3622 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3623 link_info->req_link_speed = 3624 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB; 3625 break; 3626 case IFM_10G_CR1: 3627 case IFM_10G_KR: 3628 case IFM_10G_LR: 3629 case IFM_10G_SR: 3630 3631 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3632 3633 if (link_info->support_speeds & HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB) { 3634 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB; 3635 3636 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB) { 3637 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB; 3638 link_info->force_speed2_nrz = true; 3639 } 3640 3641 break; 3642 case IFM_20G_KR2: 3643 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3644 link_info->req_link_speed = 3645 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB; 3646 break; 3647 case IFM_25G_CR: 3648 case IFM_25G_KR: 3649 case IFM_25G_SR: 3650 case IFM_25G_LR: 3651 3652 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3653 3654 if (link_info->support_speeds & HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB) { 3655 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB; 3656 3657 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB) { 3658 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB; 3659 link_info->force_speed2_nrz = true; 3660 } 3661 3662 break; 3663 3664 case IFM_40G_CR4: 3665 case IFM_40G_KR4: 3666 case IFM_40G_LR4: 3667 case IFM_40G_SR4: 3668 case IFM_40G_XLAUI: 3669 case IFM_40G_XLAUI_AC: 3670 3671 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3672 3673 if (link_info->support_speeds & HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB) { 3674 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB; 3675 3676 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB) { 3677 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB; 3678 link_info->force_speed2_nrz = true; 3679 } 3680 3681 break; 3682 3683 case IFM_50G_CR2: 3684 case IFM_50G_KR2: 3685 case IFM_50G_KR4: 3686 case IFM_50G_SR2: 3687 case IFM_50G_LR2: 3688 3689 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3690 3691 if (link_info->support_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) { 3692 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB; 3693 3694 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB) { 3695 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB; 3696 link_info->force_speed2_nrz = true; 3697 } 3698 3699 break; 3700 3701 case IFM_50G_CP: 3702 case IFM_50G_LR: 3703 case IFM_50G_SR: 3704 case IFM_50G_KR_PAM4: 3705 3706 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3707 3708 if (link_info->support_pam4_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) { 3709 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB; 3710 link_info->force_pam4_speed = true; 3711 3712 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56) { 3713 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56; 3714 link_info->force_pam4_56_speed2 = true; 3715 } 3716 3717 break; 3718 3719 case IFM_100G_CR4: 3720 case IFM_100G_KR4: 3721 case IFM_100G_LR4: 3722 case IFM_100G_SR4: 3723 case IFM_100G_AUI4: 3724 3725 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3726 3727 if (link_info->support_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) { 3728 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB; 3729 3730 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB) { 3731 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB; 3732 link_info->force_speed2_nrz = true; 3733 } 3734 3735 break; 3736 3737 case IFM_100G_CP2: 3738 case IFM_100G_SR2: 3739 case IFM_100G_KR2_PAM4: 3740 case IFM_100G_AUI2: 3741 3742 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3743 3744 if (link_info->support_pam4_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) { 3745 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB; 3746 link_info->force_pam4_speed = true; 3747 3748 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56) { 3749 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56; 3750 link_info->force_pam4_56_speed2 = true; 3751 } 3752 3753 break; 3754 3755 case IFM_100G_KR_PAM4: 3756 case IFM_100G_CR_PAM4: 3757 case IFM_100G_DR: 3758 case IFM_100G_AUI2_AC: 3759 3760 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3761 3762 if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112) { 3763 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112; 3764 link_info->force_pam4_112_speed2 = true; 3765 } 3766 3767 break; 3768 3769 case IFM_200G_SR4: 3770 case IFM_200G_FR4: 3771 case IFM_200G_LR4: 3772 case IFM_200G_DR4: 3773 case IFM_200G_CR4_PAM4: 3774 case IFM_200G_KR4_PAM4: 3775 3776 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3777 3778 if (link_info->support_pam4_speeds & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) { 3779 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB; 3780 link_info->force_pam4_speed = true; 3781 3782 } else if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56) { 3783 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56; 3784 link_info->force_pam4_56_speed2 = true; 3785 } 3786 3787 break; 3788 3789 case IFM_200G_AUI4: 3790 3791 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3792 3793 if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112) { 3794 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112; 3795 link_info->force_pam4_112_speed2 = true; 3796 } 3797 3798 break; 3799 3800 case IFM_400G_FR8: 3801 case IFM_400G_LR8: 3802 case IFM_400G_AUI8: 3803 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3804 3805 if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56) { 3806 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56; 3807 link_info->force_pam4_56_speed2 = true; 3808 } 3809 3810 break; 3811 3812 case IFM_400G_AUI8_AC: 3813 case IFM_400G_DR4: 3814 link_info->autoneg &= ~BNXT_AUTONEG_SPEED; 3815 3816 if (link_info->support_speeds2 & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112) { 3817 link_info->req_link_speed = HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112; 3818 link_info->force_pam4_112_speed2 = true; 3819 } 3820 3821 break; 3822 3823 case IFM_1000_T: 3824 link_info->advertising = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB; 3825 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3826 break; 3827 case IFM_10G_T: 3828 link_info->advertising = HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB; 3829 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3830 break; 3831 default: 3832 device_printf(softc->dev, 3833 "Unsupported media type! Using auto\n"); 3834 /* Fall-through */ 3835 case IFM_AUTO: 3836 // Auto 3837 link_info->autoneg |= BNXT_AUTONEG_SPEED; 3838 break; 3839 } 3840 3841 rc = bnxt_hwrm_set_link_setting(softc, true, true, true); 3842 bnxt_media_status(softc->ctx, &ifmr); 3843 return rc; 3844 } 3845 3846 static int 3847 bnxt_promisc_set(if_ctx_t ctx, int flags) 3848 { 3849 struct bnxt_softc *softc = iflib_get_softc(ctx); 3850 if_t ifp = iflib_get_ifp(ctx); 3851 int rc; 3852 3853 if (if_getflags(ifp) & IFF_ALLMULTI || 3854 if_llmaddr_count(ifp) > BNXT_MAX_MC_ADDRS) 3855 softc->vnic_info.rx_mask |= 3856 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; 3857 else 3858 softc->vnic_info.rx_mask &= 3859 ~HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; 3860 3861 if ((if_getflags(ifp) & IFF_PROMISC) && 3862 bnxt_promisc_ok(softc)) 3863 softc->vnic_info.rx_mask |= 3864 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS | 3865 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN; 3866 else 3867 softc->vnic_info.rx_mask &= 3868 ~(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS | 3869 HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN); 3870 3871 rc = bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); 3872 3873 return rc; 3874 } 3875 3876 static uint64_t 3877 bnxt_get_counter(if_ctx_t ctx, ift_counter cnt) 3878 { 3879 if_t ifp = iflib_get_ifp(ctx); 3880 3881 if (cnt < IFCOUNTERS) 3882 return if_get_counter_default(ifp, cnt); 3883 3884 return 0; 3885 } 3886 3887 static void 3888 bnxt_update_admin_status(if_ctx_t ctx) 3889 { 3890 struct bnxt_softc *softc = iflib_get_softc(ctx); 3891 3892 /* 3893 * When SR-IOV is enabled, avoid each VF sending this HWRM 3894 * request every sec with which firmware timeouts can happen 3895 */ 3896 if (!BNXT_PF(softc)) 3897 return; 3898 3899 bnxt_hwrm_port_qstats(softc); 3900 3901 if (BNXT_CHIP_P5_PLUS(softc) && 3902 (softc->flags & BNXT_FLAG_FW_CAP_EXT_STATS)) 3903 bnxt_hwrm_port_qstats_ext(softc); 3904 3905 if (BNXT_CHIP_P5_PLUS(softc)) { 3906 struct ifmediareq ifmr; 3907 3908 if (bit_test(softc->state_bv, BNXT_STATE_LINK_CHANGE)) { 3909 bit_clear(softc->state_bv, BNXT_STATE_LINK_CHANGE); 3910 bnxt_media_status(softc->ctx, &ifmr); 3911 } 3912 } 3913 3914 return; 3915 } 3916 3917 static void 3918 bnxt_if_timer(if_ctx_t ctx, uint16_t qid) 3919 { 3920 3921 struct bnxt_softc *softc = iflib_get_softc(ctx); 3922 uint64_t ticks_now = ticks; 3923 3924 /* Schedule bnxt_update_admin_status() once per sec */ 3925 if (ticks_now - softc->admin_ticks >= hz) { 3926 softc->admin_ticks = ticks_now; 3927 iflib_admin_intr_deferred(ctx); 3928 } 3929 3930 return; 3931 } 3932 3933 static void inline 3934 bnxt_do_enable_intr(struct bnxt_cp_ring *cpr) 3935 { 3936 struct bnxt_softc *softc = cpr->ring.softc; 3937 3938 3939 if (cpr->ring.phys_id == (uint16_t)HWRM_NA_SIGNATURE) 3940 return; 3941 3942 if (BNXT_CHIP_P5_PLUS(softc)) 3943 softc->db_ops.bnxt_db_nq(cpr, 1); 3944 else 3945 softc->db_ops.bnxt_db_rx_cq(cpr, 1); 3946 } 3947 3948 static void inline 3949 bnxt_do_disable_intr(struct bnxt_cp_ring *cpr) 3950 { 3951 struct bnxt_softc *softc = cpr->ring.softc; 3952 3953 if (cpr->ring.phys_id == (uint16_t)HWRM_NA_SIGNATURE) 3954 return; 3955 3956 if (BNXT_CHIP_P5_PLUS(softc)) 3957 softc->db_ops.bnxt_db_nq(cpr, 0); 3958 else 3959 softc->db_ops.bnxt_db_rx_cq(cpr, 0); 3960 } 3961 3962 /* Enable all interrupts */ 3963 static void 3964 bnxt_intr_enable(if_ctx_t ctx) 3965 { 3966 struct bnxt_softc *softc = iflib_get_softc(ctx); 3967 int i; 3968 3969 bnxt_do_enable_intr(&softc->def_cp_ring); 3970 for (i = 0; i < softc->nrxqsets; i++) 3971 if (BNXT_CHIP_P5_PLUS(softc)) 3972 softc->db_ops.bnxt_db_nq(&softc->nq_rings[i], 1); 3973 else 3974 softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[i], 1); 3975 3976 return; 3977 } 3978 3979 /* Enable interrupt for a single queue */ 3980 static int 3981 bnxt_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 3982 { 3983 struct bnxt_softc *softc = iflib_get_softc(ctx); 3984 3985 if (BNXT_CHIP_P5_PLUS(softc)) 3986 softc->db_ops.bnxt_db_nq(&softc->nq_rings[qid], 1); 3987 else 3988 softc->db_ops.bnxt_db_rx_cq(&softc->tx_cp_rings[qid], 1); 3989 3990 return 0; 3991 } 3992 3993 static void 3994 bnxt_process_cmd_cmpl(struct bnxt_softc *softc, hwrm_cmpl_t *cmd_cmpl) 3995 { 3996 device_printf(softc->dev, "cmd sequence number %d\n", 3997 cmd_cmpl->sequence_id); 3998 return; 3999 } 4000 4001 static void 4002 bnxt_process_async_msg(struct bnxt_cp_ring *cpr, tx_cmpl_t *cmpl) 4003 { 4004 struct bnxt_softc *softc = cpr->ring.softc; 4005 uint16_t type = cmpl->flags_type & TX_CMPL_TYPE_MASK; 4006 #ifdef PCI_IOV 4007 struct hwrm_fwd_req_cmpl *fwd_req_cmpl = (struct hwrm_fwd_req_cmpl *)cmpl; 4008 uint16_t vf_id; 4009 #endif 4010 4011 switch (type) { 4012 case HWRM_CMPL_TYPE_HWRM_DONE: 4013 bnxt_process_cmd_cmpl(softc, (hwrm_cmpl_t *)cmpl); 4014 break; 4015 case HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT: 4016 bnxt_handle_async_event(softc, (cmpl_base_t *) cmpl); 4017 break; 4018 #ifdef PCI_IOV 4019 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 4020 vf_id = le16_to_cpu(fwd_req_cmpl->source_id); 4021 4022 if ((vf_id < softc->pf.first_vf_id) || 4023 (vf_id >= softc->pf.first_vf_id + softc->pf.active_vfs)) 4024 return; 4025 4026 set_bit(vf_id - softc->pf.first_vf_id, softc->pf.vf_event_bmap); 4027 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &softc->sp_event); 4028 bnxt_queue_sp_work(softc); 4029 break; 4030 #endif 4031 default: 4032 device_printf(softc->dev, "%s:%d Unhandled async message %x\n", 4033 __FUNCTION__, __LINE__, type); 4034 break; 4035 } 4036 } 4037 4038 void 4039 process_nq(struct bnxt_softc *softc, uint16_t nqid) 4040 { 4041 struct bnxt_cp_ring *cpr = &softc->nq_rings[nqid]; 4042 nq_cn_t *cmp = (nq_cn_t *) cpr->ring.vaddr; 4043 struct bnxt_cp_ring *tx_cpr = &softc->tx_cp_rings[nqid]; 4044 struct bnxt_cp_ring *rx_cpr = &softc->rx_cp_rings[nqid]; 4045 bool v_bit = cpr->v_bit; 4046 uint32_t cons = cpr->cons; 4047 uint32_t raw_cons = cpr->raw_cons; 4048 uint16_t nq_type, nqe_cnt = 0; 4049 4050 while (1) { 4051 if (!NQ_VALID(&cmp[cons], v_bit)) { 4052 goto done; 4053 } 4054 4055 nq_type = NQ_CN_TYPE_MASK & cmp[cons].type; 4056 4057 if (NQE_CN_TYPE(nq_type) != NQ_CN_TYPE_CQ_NOTIFICATION) { 4058 bnxt_process_async_msg(cpr, (tx_cmpl_t *)&cmp[cons]); 4059 } else { 4060 tx_cpr->toggle = NQE_CN_TOGGLE(cmp[cons].type); 4061 rx_cpr->toggle = NQE_CN_TOGGLE(cmp[cons].type); 4062 } 4063 4064 NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); 4065 raw_cons++; 4066 nqe_cnt++; 4067 } 4068 done: 4069 if (nqe_cnt) { 4070 cpr->cons = cons; 4071 cpr->raw_cons = raw_cons; 4072 cpr->v_bit = v_bit; 4073 } 4074 } 4075 4076 static int 4077 bnxt_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 4078 { 4079 struct bnxt_softc *softc = iflib_get_softc(ctx); 4080 4081 if (BNXT_CHIP_P5_PLUS(softc)) { 4082 process_nq(softc, qid); 4083 softc->db_ops.bnxt_db_nq(&softc->nq_rings[qid], 1); 4084 } 4085 softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[qid], 1); 4086 return 0; 4087 } 4088 4089 /* Disable all interrupts */ 4090 static void 4091 bnxt_disable_intr(if_ctx_t ctx) 4092 { 4093 struct bnxt_softc *softc = iflib_get_softc(ctx); 4094 int i; 4095 4096 /* 4097 * NOTE: These TX interrupts should never get enabled, so don't 4098 * update the index 4099 */ 4100 for (i = 0; i < softc->nrxqsets; i++) 4101 if (BNXT_CHIP_P5_PLUS(softc)) 4102 softc->db_ops.bnxt_db_nq(&softc->nq_rings[i], 0); 4103 else 4104 softc->db_ops.bnxt_db_rx_cq(&softc->rx_cp_rings[i], 0); 4105 4106 4107 return; 4108 } 4109 4110 static int 4111 bnxt_msix_intr_assign(if_ctx_t ctx, int msix) 4112 { 4113 struct bnxt_softc *softc = iflib_get_softc(ctx); 4114 struct bnxt_cp_ring *ring; 4115 struct if_irq *irq; 4116 uint16_t id; 4117 int rc; 4118 int i; 4119 char irq_name[16]; 4120 4121 if (BNXT_CHIP_P5_PLUS(softc)) 4122 goto skip_default_cp; 4123 4124 rc = iflib_irq_alloc_generic(ctx, &softc->def_cp_ring.irq, 4125 softc->def_cp_ring.ring.id + 1, IFLIB_INTR_ADMIN, 4126 bnxt_handle_def_cp, softc, 0, "def_cp"); 4127 if (rc) { 4128 device_printf(iflib_get_dev(ctx), 4129 "Failed to register default completion ring handler\n"); 4130 return rc; 4131 } 4132 4133 skip_default_cp: 4134 for (i=0; i<softc->scctx->isc_nrxqsets; i++) { 4135 if (BNXT_CHIP_P5_PLUS(softc)) { 4136 irq = &softc->nq_rings[i].irq; 4137 id = softc->nq_rings[i].ring.id; 4138 ring = &softc->nq_rings[i]; 4139 } else { 4140 irq = &softc->rx_cp_rings[i].irq; 4141 id = softc->rx_cp_rings[i].ring.id ; 4142 ring = &softc->rx_cp_rings[i]; 4143 } 4144 snprintf(irq_name, sizeof(irq_name), "rxq%d", i); 4145 rc = iflib_irq_alloc_generic(ctx, irq, id + 1, IFLIB_INTR_RX, 4146 bnxt_handle_isr, ring, i, irq_name); 4147 if (rc) { 4148 device_printf(iflib_get_dev(ctx), 4149 "Failed to register RX completion ring handler\n"); 4150 i--; 4151 goto fail; 4152 } 4153 } 4154 4155 for (i=0; i<softc->scctx->isc_ntxqsets; i++) 4156 iflib_softirq_alloc_generic(ctx, NULL, IFLIB_INTR_TX, NULL, i, "tx_cp"); 4157 4158 return rc; 4159 4160 fail: 4161 for (; i>=0; i--) 4162 iflib_irq_free(ctx, &softc->rx_cp_rings[i].irq); 4163 iflib_irq_free(ctx, &softc->def_cp_ring.irq); 4164 return rc; 4165 } 4166 4167 /* 4168 * We're explicitly allowing duplicates here. They will need to be 4169 * removed as many times as they are added. 4170 */ 4171 static void 4172 bnxt_vlan_register(if_ctx_t ctx, uint16_t vtag) 4173 { 4174 struct bnxt_softc *softc = iflib_get_softc(ctx); 4175 struct bnxt_vlan_tag *new_tag; 4176 4177 new_tag = malloc(sizeof(struct bnxt_vlan_tag), M_DEVBUF, M_NOWAIT); 4178 if (new_tag == NULL) 4179 return; 4180 new_tag->tag = vtag; 4181 new_tag->filter_id = -1; 4182 SLIST_INSERT_HEAD(&softc->vnic_info.vlan_tags, new_tag, next); 4183 }; 4184 4185 static void 4186 bnxt_vlan_unregister(if_ctx_t ctx, uint16_t vtag) 4187 { 4188 struct bnxt_softc *softc = iflib_get_softc(ctx); 4189 struct bnxt_vlan_tag *vlan_tag; 4190 4191 SLIST_FOREACH(vlan_tag, &softc->vnic_info.vlan_tags, next) { 4192 if (vlan_tag->tag == vtag) { 4193 SLIST_REMOVE(&softc->vnic_info.vlan_tags, vlan_tag, 4194 bnxt_vlan_tag, next); 4195 free(vlan_tag, M_DEVBUF); 4196 break; 4197 } 4198 } 4199 } 4200 4201 static int 4202 bnxt_wol_config(if_ctx_t ctx) 4203 { 4204 struct bnxt_softc *softc = iflib_get_softc(ctx); 4205 if_t ifp = iflib_get_ifp(ctx); 4206 4207 if (!softc) 4208 return -EBUSY; 4209 4210 if (!bnxt_wol_supported(softc)) 4211 return -ENOTSUP; 4212 4213 if (if_getcapenable(ifp) & IFCAP_WOL_MAGIC) { 4214 if (!softc->wol) { 4215 if (bnxt_hwrm_alloc_wol_fltr(softc)) 4216 return -EBUSY; 4217 softc->wol = 1; 4218 } 4219 } else { 4220 if (softc->wol) { 4221 if (bnxt_hwrm_free_wol_fltr(softc)) 4222 return -EBUSY; 4223 softc->wol = 0; 4224 } 4225 } 4226 4227 return 0; 4228 } 4229 4230 static bool 4231 bnxt_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4232 { 4233 switch (event) { 4234 case IFLIB_RESTART_VLAN_CONFIG: 4235 default: 4236 return (false); 4237 } 4238 } 4239 4240 static int 4241 bnxt_shutdown(if_ctx_t ctx) 4242 { 4243 bnxt_wol_config(ctx); 4244 return 0; 4245 } 4246 4247 static int 4248 bnxt_suspend(if_ctx_t ctx) 4249 { 4250 bnxt_wol_config(ctx); 4251 return 0; 4252 } 4253 4254 static int 4255 bnxt_resume(if_ctx_t ctx) 4256 { 4257 struct bnxt_softc *softc = iflib_get_softc(ctx); 4258 4259 bnxt_get_wol_settings(softc); 4260 return 0; 4261 } 4262 4263 static int 4264 bnxt_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data) 4265 { 4266 struct bnxt_softc *softc = iflib_get_softc(ctx); 4267 struct ifreq *ifr = (struct ifreq *)data; 4268 struct bnxt_ioctl_header *ioh; 4269 size_t iol; 4270 int rc = ENOTSUP; 4271 struct bnxt_ioctl_data iod_storage, *iod = &iod_storage; 4272 4273 switch (command) { 4274 case SIOCGPRIVATE_0: 4275 if ((rc = priv_check(curthread, PRIV_DRIVER)) != 0) 4276 goto exit; 4277 4278 ioh = ifr_buffer_get_buffer(ifr); 4279 iol = ifr_buffer_get_length(ifr); 4280 if (iol > sizeof(iod_storage)) 4281 return (EINVAL); 4282 4283 if ((rc = copyin(ioh, iod, iol)) != 0) 4284 goto exit; 4285 4286 switch (iod->hdr.type) { 4287 case BNXT_HWRM_NVM_FIND_DIR_ENTRY: 4288 { 4289 struct bnxt_ioctl_hwrm_nvm_find_dir_entry *find = 4290 &iod->find; 4291 4292 rc = bnxt_hwrm_nvm_find_dir_entry(softc, find->type, 4293 &find->ordinal, find->ext, &find->index, 4294 find->use_index, find->search_opt, 4295 &find->data_length, &find->item_length, 4296 &find->fw_ver); 4297 if (rc) { 4298 iod->hdr.rc = rc; 4299 rc = copyout(&iod->hdr.rc, &ioh->rc, 4300 sizeof(ioh->rc)); 4301 } else { 4302 iod->hdr.rc = 0; 4303 rc = copyout(iod, ioh, iol); 4304 } 4305 4306 goto exit; 4307 } 4308 case BNXT_HWRM_NVM_READ: 4309 { 4310 struct bnxt_ioctl_hwrm_nvm_read *rd = &iod->read; 4311 struct iflib_dma_info dma_data; 4312 size_t offset; 4313 size_t remain; 4314 size_t csize; 4315 4316 /* 4317 * Some HWRM versions can't read more than 0x8000 bytes 4318 */ 4319 rc = iflib_dma_alloc(softc->ctx, 4320 min(rd->length, 0x8000), &dma_data, BUS_DMA_NOWAIT); 4321 if (rc) 4322 break; 4323 for (remain = rd->length, offset = 0; 4324 remain && offset < rd->length; offset += 0x8000) { 4325 csize = min(remain, 0x8000); 4326 rc = bnxt_hwrm_nvm_read(softc, rd->index, 4327 rd->offset + offset, csize, &dma_data); 4328 if (rc) { 4329 iod->hdr.rc = rc; 4330 rc = copyout(&iod->hdr.rc, &ioh->rc, 4331 sizeof(ioh->rc)); 4332 break; 4333 } else { 4334 rc = copyout(dma_data.idi_vaddr, 4335 rd->data + offset, csize); 4336 iod->hdr.rc = rc; 4337 } 4338 remain -= csize; 4339 } 4340 if (rc == 0) 4341 rc = copyout(iod, ioh, iol); 4342 4343 iflib_dma_free(&dma_data); 4344 goto exit; 4345 } 4346 case BNXT_HWRM_FW_RESET: 4347 { 4348 struct bnxt_ioctl_hwrm_fw_reset *rst = 4349 &iod->reset; 4350 4351 rc = bnxt_hwrm_fw_reset(softc, rst->processor, 4352 &rst->selfreset); 4353 if (rc) { 4354 iod->hdr.rc = rc; 4355 rc = copyout(&iod->hdr.rc, &ioh->rc, 4356 sizeof(ioh->rc)); 4357 } else { 4358 iod->hdr.rc = 0; 4359 rc = copyout(iod, ioh, iol); 4360 } 4361 4362 goto exit; 4363 } 4364 case BNXT_HWRM_FW_QSTATUS: 4365 { 4366 struct bnxt_ioctl_hwrm_fw_qstatus *qstat = 4367 &iod->status; 4368 4369 rc = bnxt_hwrm_fw_qstatus(softc, qstat->processor, 4370 &qstat->selfreset); 4371 if (rc) { 4372 iod->hdr.rc = rc; 4373 rc = copyout(&iod->hdr.rc, &ioh->rc, 4374 sizeof(ioh->rc)); 4375 } else { 4376 iod->hdr.rc = 0; 4377 rc = copyout(iod, ioh, iol); 4378 } 4379 4380 goto exit; 4381 } 4382 case BNXT_HWRM_NVM_WRITE: 4383 { 4384 struct bnxt_ioctl_hwrm_nvm_write *wr = 4385 &iod->write; 4386 4387 rc = bnxt_hwrm_nvm_write(softc, wr->data, true, 4388 wr->type, wr->ordinal, wr->ext, wr->attr, 4389 wr->option, wr->data_length, wr->keep, 4390 &wr->item_length, &wr->index); 4391 if (rc) { 4392 iod->hdr.rc = rc; 4393 rc = copyout(&iod->hdr.rc, &ioh->rc, 4394 sizeof(ioh->rc)); 4395 } 4396 else { 4397 iod->hdr.rc = 0; 4398 rc = copyout(iod, ioh, iol); 4399 } 4400 4401 goto exit; 4402 } 4403 case BNXT_HWRM_NVM_ERASE_DIR_ENTRY: 4404 { 4405 struct bnxt_ioctl_hwrm_nvm_erase_dir_entry *erase = 4406 &iod->erase; 4407 4408 rc = bnxt_hwrm_nvm_erase_dir_entry(softc, erase->index); 4409 if (rc) { 4410 iod->hdr.rc = rc; 4411 rc = copyout(&iod->hdr.rc, &ioh->rc, 4412 sizeof(ioh->rc)); 4413 } else { 4414 iod->hdr.rc = 0; 4415 rc = copyout(iod, ioh, iol); 4416 } 4417 4418 goto exit; 4419 } 4420 case BNXT_HWRM_NVM_GET_DIR_INFO: 4421 { 4422 struct bnxt_ioctl_hwrm_nvm_get_dir_info *info = 4423 &iod->dir_info; 4424 4425 rc = bnxt_hwrm_nvm_get_dir_info(softc, &info->entries, 4426 &info->entry_length); 4427 if (rc) { 4428 iod->hdr.rc = rc; 4429 rc = copyout(&iod->hdr.rc, &ioh->rc, 4430 sizeof(ioh->rc)); 4431 } else { 4432 iod->hdr.rc = 0; 4433 rc = copyout(iod, ioh, iol); 4434 } 4435 4436 goto exit; 4437 } 4438 case BNXT_HWRM_NVM_GET_DIR_ENTRIES: 4439 { 4440 struct bnxt_ioctl_hwrm_nvm_get_dir_entries *get = 4441 &iod->dir_entries; 4442 struct iflib_dma_info dma_data; 4443 4444 rc = iflib_dma_alloc(softc->ctx, get->max_size, 4445 &dma_data, BUS_DMA_NOWAIT); 4446 if (rc) 4447 break; 4448 rc = bnxt_hwrm_nvm_get_dir_entries(softc, &get->entries, 4449 &get->entry_length, &dma_data); 4450 if (rc) { 4451 iod->hdr.rc = rc; 4452 rc = copyout(&iod->hdr.rc, &ioh->rc, 4453 sizeof(ioh->rc)); 4454 } else { 4455 rc = copyout(dma_data.idi_vaddr, get->data, 4456 get->entry_length * get->entries); 4457 iod->hdr.rc = rc; 4458 if (rc == 0) 4459 rc = copyout(iod, ioh, iol); 4460 } 4461 iflib_dma_free(&dma_data); 4462 4463 goto exit; 4464 } 4465 case BNXT_HWRM_NVM_VERIFY_UPDATE: 4466 { 4467 struct bnxt_ioctl_hwrm_nvm_verify_update *vrfy = 4468 &iod->verify; 4469 4470 rc = bnxt_hwrm_nvm_verify_update(softc, vrfy->type, 4471 vrfy->ordinal, vrfy->ext); 4472 if (rc) { 4473 iod->hdr.rc = rc; 4474 rc = copyout(&iod->hdr.rc, &ioh->rc, 4475 sizeof(ioh->rc)); 4476 } else { 4477 iod->hdr.rc = 0; 4478 rc = copyout(iod, ioh, iol); 4479 } 4480 4481 goto exit; 4482 } 4483 case BNXT_HWRM_NVM_INSTALL_UPDATE: 4484 { 4485 struct bnxt_ioctl_hwrm_nvm_install_update *inst = 4486 &iod->install; 4487 4488 rc = bnxt_hwrm_nvm_install_update(softc, 4489 inst->install_type, &inst->installed_items, 4490 &inst->result, &inst->problem_item, 4491 &inst->reset_required); 4492 if (rc) { 4493 iod->hdr.rc = rc; 4494 rc = copyout(&iod->hdr.rc, &ioh->rc, 4495 sizeof(ioh->rc)); 4496 } else { 4497 iod->hdr.rc = 0; 4498 rc = copyout(iod, ioh, iol); 4499 } 4500 4501 goto exit; 4502 } 4503 case BNXT_HWRM_NVM_MODIFY: 4504 { 4505 struct bnxt_ioctl_hwrm_nvm_modify *mod = &iod->modify; 4506 4507 rc = bnxt_hwrm_nvm_modify(softc, mod->index, 4508 mod->offset, mod->data, true, mod->length); 4509 if (rc) { 4510 iod->hdr.rc = rc; 4511 rc = copyout(&iod->hdr.rc, &ioh->rc, 4512 sizeof(ioh->rc)); 4513 } else { 4514 iod->hdr.rc = 0; 4515 rc = copyout(iod, ioh, iol); 4516 } 4517 4518 goto exit; 4519 } 4520 case BNXT_HWRM_FW_GET_TIME: 4521 { 4522 struct bnxt_ioctl_hwrm_fw_get_time *gtm = 4523 &iod->get_time; 4524 4525 rc = bnxt_hwrm_fw_get_time(softc, >m->year, 4526 >m->month, >m->day, >m->hour, >m->minute, 4527 >m->second, >m->millisecond, >m->zone); 4528 if (rc) { 4529 iod->hdr.rc = rc; 4530 rc = copyout(&iod->hdr.rc, &ioh->rc, 4531 sizeof(ioh->rc)); 4532 } else { 4533 iod->hdr.rc = 0; 4534 rc = copyout(iod, ioh, iol); 4535 } 4536 4537 goto exit; 4538 } 4539 case BNXT_HWRM_FW_SET_TIME: 4540 { 4541 struct bnxt_ioctl_hwrm_fw_set_time *stm = 4542 &iod->set_time; 4543 4544 rc = bnxt_hwrm_fw_set_time(softc, stm->year, 4545 stm->month, stm->day, stm->hour, stm->minute, 4546 stm->second, stm->millisecond, stm->zone); 4547 if (rc) { 4548 iod->hdr.rc = rc; 4549 rc = copyout(&iod->hdr.rc, &ioh->rc, 4550 sizeof(ioh->rc)); 4551 } else { 4552 iod->hdr.rc = 0; 4553 rc = copyout(iod, ioh, iol); 4554 } 4555 4556 goto exit; 4557 } 4558 } 4559 break; 4560 } 4561 4562 exit: 4563 return rc; 4564 } 4565 4566 static int 4567 bnxt_i2c_req(if_ctx_t ctx, struct ifi2creq *i2c) 4568 { 4569 struct bnxt_softc *softc = iflib_get_softc(ctx); 4570 uint8_t *data = i2c->data; 4571 int rc; 4572 4573 /* No point in going further if phy status indicates 4574 * module is not inserted or if it is powered down or 4575 * if it is of type 10GBase-T 4576 */ 4577 if (softc->link_info.module_status > 4578 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) 4579 return -EOPNOTSUPP; 4580 4581 /* This feature is not supported in older firmware versions */ 4582 if (!BNXT_CHIP_P5_PLUS(softc) || 4583 (softc->hwrm_spec_code < 0x10202)) 4584 return -EOPNOTSUPP; 4585 4586 4587 rc = bnxt_read_sfp_module_eeprom_info(softc, i2c->dev_addr, 0, 0, 0, 4588 i2c->offset, i2c->len, data); 4589 4590 return rc; 4591 } 4592 4593 /* 4594 * Support functions 4595 */ 4596 static int 4597 bnxt_probe_phy(struct bnxt_softc *softc) 4598 { 4599 struct bnxt_link_info *link_info = &softc->link_info; 4600 int rc = 0; 4601 4602 softc->phy_flags = 0; 4603 rc = bnxt_hwrm_phy_qcaps(softc); 4604 if (rc) { 4605 device_printf(softc->dev, 4606 "Probe phy can't get phy capabilities (rc: %x)\n", rc); 4607 return rc; 4608 } 4609 4610 rc = bnxt_update_link(softc, false); 4611 if (rc) { 4612 device_printf(softc->dev, 4613 "Probe phy can't update link (rc: %x)\n", rc); 4614 return (rc); 4615 } 4616 4617 bnxt_get_port_module_status(softc); 4618 4619 /*initialize the ethool setting copy with NVM settings */ 4620 if (link_info->auto_mode != HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 4621 link_info->autoneg |= BNXT_AUTONEG_SPEED; 4622 4623 link_info->req_duplex = link_info->duplex_setting; 4624 4625 /* NRZ link speed */ 4626 if (link_info->autoneg & BNXT_AUTONEG_SPEED) 4627 link_info->req_link_speed = link_info->auto_link_speeds; 4628 else 4629 link_info->req_link_speed = link_info->force_link_speed; 4630 4631 /* PAM4 link speed */ 4632 if (link_info->auto_pam4_link_speeds) 4633 link_info->req_link_speed = link_info->auto_pam4_link_speeds; 4634 if (link_info->force_pam4_link_speed) 4635 link_info->req_link_speed = link_info->force_pam4_link_speed; 4636 4637 return (rc); 4638 } 4639 4640 static void 4641 add_media(struct bnxt_softc *softc, u8 media_type, u16 supported_NRZ_speeds, 4642 u16 supported_pam4_speeds, u16 supported_speeds2) 4643 { 4644 4645 switch (media_type) { 4646 case BNXT_MEDIA_CR: 4647 4648 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_50G, IFM_50G_CP); 4649 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_100G, IFM_100G_CP2); 4650 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_200G, IFM_200G_CR4_PAM4); 4651 4652 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_100GB, IFM_100G_CR4); 4653 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_50GB, IFM_50G_CR2); 4654 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_CR4); 4655 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_25GB, IFM_25G_CR); 4656 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_CR1); 4657 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_CX); 4658 /* thor2 nrz*/ 4659 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB, IFM_100G_CR4); 4660 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB, IFM_50G_CR2); 4661 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_40GB, IFM_40G_CR4); 4662 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_25GB, IFM_25G_CR); 4663 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_10GB, IFM_10G_CR1); 4664 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_1GB, IFM_1000_CX); 4665 /* thor2 PAM56 */ 4666 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB_PAM4_56, IFM_50G_CP); 4667 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_56, IFM_100G_CP2); 4668 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_56, IFM_200G_CR4_PAM4); 4669 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_56, IFM_400G_AUI8); 4670 /* thor2 PAM112 */ 4671 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_112, IFM_100G_CR_PAM4); 4672 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_112, IFM_200G_AUI4); 4673 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_112, IFM_400G_AUI8_AC); 4674 4675 break; 4676 4677 case BNXT_MEDIA_LR: 4678 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_50G, IFM_50G_LR); 4679 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_200G, IFM_200G_LR4); 4680 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_100GB, IFM_100G_LR4); 4681 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_50GB, IFM_50G_LR2); 4682 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_LR4); 4683 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_25GB, IFM_25G_LR); 4684 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_LR); 4685 /* thor2 nrz*/ 4686 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB, IFM_100G_LR4); 4687 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB, IFM_50G_LR2); 4688 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_40GB, IFM_40G_LR4); 4689 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_25GB, IFM_25G_LR); 4690 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_10GB, IFM_10G_LR); 4691 /* thor2 PAM56 */ 4692 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB_PAM4_56, IFM_50G_LR); 4693 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_56, IFM_100G_AUI2); 4694 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_56, IFM_200G_LR4); 4695 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_56, IFM_400G_LR8); 4696 /* thor2 PAM112 */ 4697 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_112, IFM_100G_AUI2_AC); 4698 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_112, IFM_200G_AUI4); 4699 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_112, IFM_400G_AUI8_AC); 4700 4701 break; 4702 4703 case BNXT_MEDIA_SR: 4704 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_50G, IFM_50G_SR); 4705 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_100G, IFM_100G_SR2); 4706 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_200G, IFM_200G_SR4); 4707 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_100GB, IFM_100G_SR4); 4708 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_50GB, IFM_50G_SR2); 4709 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_SR4); 4710 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_25GB, IFM_25G_SR); 4711 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_SR); 4712 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_SX); 4713 /* thor2 nrz*/ 4714 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB, IFM_100G_SR4); 4715 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB, IFM_50G_SR2); 4716 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_40GB, IFM_40G_SR4); 4717 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_25GB, IFM_25G_SR); 4718 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_10GB, IFM_10G_SR); 4719 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_1GB, IFM_1000_SX); 4720 /* thor2 PAM56 */ 4721 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB_PAM4_56, IFM_50G_SR); 4722 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_56, IFM_100G_SR2); 4723 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_56, IFM_200G_SR4); 4724 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_56, IFM_400G_AUI8); 4725 /* thor2 PAM112 */ 4726 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_112, IFM_100G_AUI2_AC); 4727 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_112, IFM_200G_AUI4); 4728 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_112, IFM_400G_DR4); 4729 break; 4730 4731 case BNXT_MEDIA_ER: 4732 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_ER4); 4733 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_100GB, IFM_100G_AUI4); 4734 /* thor2 PAM56 */ 4735 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_50GB_PAM4_56, IFM_50G_LR); 4736 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_56, IFM_100G_AUI2); 4737 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_56, IFM_200G_LR4); 4738 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_56, IFM_400G_FR8); 4739 /* thor2 PAM112 */ 4740 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_100GB_PAM4_112, IFM_100G_AUI2_AC); 4741 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_200GB_PAM4_112, IFM_200G_AUI4_AC); 4742 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_400GB_PAM4_112, IFM_400G_AUI8_AC); 4743 break; 4744 4745 case BNXT_MEDIA_KR: 4746 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_50G, IFM_50G_KR_PAM4); 4747 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_100G, IFM_100G_KR2_PAM4); 4748 BNXT_IFMEDIA_ADD(supported_pam4_speeds, PAM4_SPEEDS_200G, IFM_200G_KR4_PAM4); 4749 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_100GB, IFM_100G_KR4); 4750 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_50GB, IFM_50G_KR2); 4751 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_50GB, IFM_50G_KR4); 4752 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_KR4); 4753 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_25GB, IFM_25G_KR); 4754 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_20GB, IFM_20G_KR2); 4755 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_KR); 4756 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_KX); 4757 break; 4758 4759 case BNXT_MEDIA_AC: 4760 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_25GB, IFM_25G_ACC); 4761 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_AOC); 4762 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_XLAUI); 4763 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_40GB, IFM_40G_XLAUI_AC); 4764 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_25GB, IFM_25G_ACC); 4765 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_10GB, IFM_10G_AOC); 4766 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_40GB, IFM_40G_XLAUI); 4767 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_40GB, IFM_40G_XLAUI_AC); 4768 break; 4769 4770 case BNXT_MEDIA_BASECX: 4771 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_CX); 4772 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_1GB, IFM_1000_CX); 4773 break; 4774 4775 case BNXT_MEDIA_BASET: 4776 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_T); 4777 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_2_5GB, IFM_2500_T); 4778 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_T); 4779 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_100MB, IFM_100_T); 4780 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10MB, IFM_10_T); 4781 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_10GB, IFM_10G_T); 4782 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_1GB, IFM_1000_T); 4783 break; 4784 4785 case BNXT_MEDIA_BASEKX: 4786 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_10GB, IFM_10G_KR); 4787 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_2_5GB, IFM_2500_KX); 4788 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_KX); 4789 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_10GB, IFM_10G_KR); 4790 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_1GB, IFM_1000_KX); 4791 break; 4792 4793 case BNXT_MEDIA_BASESGMII: 4794 BNXT_IFMEDIA_ADD(supported_NRZ_speeds, SPEEDS_1GB, IFM_1000_SGMII); 4795 BNXT_IFMEDIA_ADD(supported_speeds2, SPEEDS2_1GB, IFM_1000_SGMII); 4796 break; 4797 4798 default: 4799 break; 4800 4801 } 4802 return; 4803 4804 } 4805 4806 static void 4807 bnxt_add_media_types(struct bnxt_softc *softc) 4808 { 4809 struct bnxt_link_info *link_info = &softc->link_info; 4810 uint16_t supported_NRZ_speeds = 0, supported_pam4_speeds = 0, supported_speeds2 = 0; 4811 uint8_t phy_type = get_phy_type(softc), media_type; 4812 4813 supported_NRZ_speeds = link_info->support_speeds; 4814 supported_speeds2 = link_info->support_speeds2; 4815 supported_pam4_speeds = link_info->support_pam4_speeds; 4816 4817 /* Auto is always supported */ 4818 ifmedia_add(softc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 4819 4820 if (softc->flags & BNXT_FLAG_NPAR) 4821 return; 4822 4823 switch (phy_type) { 4824 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4: 4825 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4: 4826 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L: 4827 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S: 4828 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N: 4829 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: 4830 4831 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR: 4832 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2: 4833 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4: 4834 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8: 4835 4836 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR: 4837 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2: 4838 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4: 4839 4840 media_type = BNXT_MEDIA_CR; 4841 break; 4842 4843 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4: 4844 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4: 4845 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR: 4846 4847 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR: 4848 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2: 4849 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4: 4850 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8: 4851 4852 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR: 4853 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2: 4854 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4: 4855 4856 media_type = BNXT_MEDIA_LR; 4857 break; 4858 4859 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10: 4860 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4: 4861 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4: 4862 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: 4863 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR: 4864 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX: 4865 4866 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR: 4867 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2: 4868 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4: 4869 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8: 4870 4871 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR: 4872 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2: 4873 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4: 4874 4875 media_type = BNXT_MEDIA_SR; 4876 break; 4877 4878 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4: 4879 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4: 4880 4881 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER: 4882 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2: 4883 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4: 4884 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8: 4885 4886 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER: 4887 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2: 4888 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4: 4889 4890 media_type = BNXT_MEDIA_ER; 4891 break; 4892 4893 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: 4894 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: 4895 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: 4896 media_type = BNXT_MEDIA_KR; 4897 break; 4898 4899 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE: 4900 media_type = BNXT_MEDIA_AC; 4901 break; 4902 4903 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX: 4904 media_type = BNXT_MEDIA_BASECX; 4905 break; 4906 4907 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET: 4908 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET: 4909 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE: 4910 media_type = BNXT_MEDIA_BASET; 4911 break; 4912 4913 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX: 4914 media_type = BNXT_MEDIA_BASEKX; 4915 break; 4916 4917 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY: 4918 media_type = BNXT_MEDIA_BASESGMII; 4919 break; 4920 4921 case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN: 4922 /* Only Autoneg is supported for TYPE_UNKNOWN */ 4923 break; 4924 4925 default: 4926 /* Only Autoneg is supported for new phy type values */ 4927 device_printf(softc->dev, "phy type %d not supported by driver\n", phy_type); 4928 break; 4929 } 4930 4931 switch (link_info->sig_mode) { 4932 case BNXT_SIG_MODE_NRZ: 4933 if (supported_NRZ_speeds != 0) 4934 add_media(softc, media_type, supported_NRZ_speeds, 0, 0); 4935 else 4936 add_media(softc, media_type, 0, 0, supported_speeds2); 4937 break; 4938 case BNXT_SIG_MODE_PAM4: 4939 if (supported_pam4_speeds != 0) 4940 add_media(softc, media_type, 0, supported_pam4_speeds, 0); 4941 else 4942 add_media(softc, media_type, 0, 0, supported_speeds2); 4943 break; 4944 case BNXT_SIG_MODE_PAM4_112: 4945 add_media(softc, media_type, 0, 0, supported_speeds2); 4946 break; 4947 } 4948 4949 return; 4950 } 4951 4952 static int 4953 bnxt_map_bar(struct bnxt_softc *softc, struct bnxt_bar_info *bar, int bar_num, bool shareable) 4954 { 4955 uint32_t flag; 4956 4957 if (bar->res != NULL) { 4958 device_printf(softc->dev, "Bar %d already mapped\n", bar_num); 4959 return EDOOFUS; 4960 } 4961 4962 bar->rid = PCIR_BAR(bar_num); 4963 flag = RF_ACTIVE; 4964 if (shareable) 4965 flag |= RF_SHAREABLE; 4966 4967 if ((bar->res = 4968 bus_alloc_resource_any(softc->dev, 4969 SYS_RES_MEMORY, 4970 &bar->rid, 4971 flag)) == NULL) { 4972 device_printf(softc->dev, 4973 "PCI BAR%d mapping failure\n", bar_num); 4974 return (ENXIO); 4975 } 4976 bar->tag = rman_get_bustag(bar->res); 4977 bar->handle = rman_get_bushandle(bar->res); 4978 bar->size = rman_get_size(bar->res); 4979 4980 return 0; 4981 } 4982 4983 static int 4984 bnxt_pci_mapping(struct bnxt_softc *softc) 4985 { 4986 int rc; 4987 4988 rc = bnxt_map_bar(softc, &softc->hwrm_bar, 0, true); 4989 if (rc) 4990 return rc; 4991 4992 rc = bnxt_map_bar(softc, &softc->doorbell_bar, 2, false); 4993 4994 return rc; 4995 } 4996 4997 static void 4998 bnxt_pci_mapping_free(struct bnxt_softc *softc) 4999 { 5000 if (softc->hwrm_bar.res != NULL) 5001 bus_release_resource(softc->dev, SYS_RES_MEMORY, 5002 softc->hwrm_bar.rid, softc->hwrm_bar.res); 5003 softc->hwrm_bar.res = NULL; 5004 5005 if (softc->doorbell_bar.res != NULL) 5006 bus_release_resource(softc->dev, SYS_RES_MEMORY, 5007 softc->doorbell_bar.rid, softc->doorbell_bar.res); 5008 softc->doorbell_bar.res = NULL; 5009 } 5010 5011 static int 5012 bnxt_update_link(struct bnxt_softc *softc, bool chng_link_state) 5013 { 5014 struct bnxt_link_info *link_info = &softc->link_info; 5015 uint8_t link_up = link_info->link_up; 5016 int rc = 0; 5017 5018 rc = bnxt_hwrm_port_phy_qcfg(softc); 5019 if (rc) 5020 goto exit; 5021 5022 /* TODO: need to add more logic to report VF link */ 5023 if (chng_link_state) { 5024 if (link_info->phy_link_status == 5025 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) 5026 link_info->link_up = 1; 5027 else 5028 link_info->link_up = 0; 5029 if (link_up != link_info->link_up) 5030 bnxt_report_link(softc); 5031 } else { 5032 /* always link down if not require to update link state */ 5033 link_info->link_up = 0; 5034 } 5035 5036 exit: 5037 return rc; 5038 } 5039 5040 #define ETHTOOL_SPEED_1000 1000 5041 #define ETHTOOL_SPEED_10000 10000 5042 #define ETHTOOL_SPEED_20000 20000 5043 #define ETHTOOL_SPEED_25000 25000 5044 #define ETHTOOL_SPEED_40000 40000 5045 #define ETHTOOL_SPEED_50000 50000 5046 #define ETHTOOL_SPEED_100000 100000 5047 #define ETHTOOL_SPEED_200000 200000 5048 #define ETHTOOL_SPEED_UNKNOWN -1 5049 5050 static u32 5051 bnxt_fw_to_ethtool_speed(u16 fw_link_speed) 5052 { 5053 switch (fw_link_speed) { 5054 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: 5055 return ETHTOOL_SPEED_1000; 5056 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: 5057 return ETHTOOL_SPEED_10000; 5058 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: 5059 return ETHTOOL_SPEED_20000; 5060 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: 5061 return ETHTOOL_SPEED_25000; 5062 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: 5063 return ETHTOOL_SPEED_40000; 5064 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: 5065 return ETHTOOL_SPEED_50000; 5066 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: 5067 return ETHTOOL_SPEED_100000; 5068 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB: 5069 return ETHTOOL_SPEED_200000; 5070 default: 5071 return ETHTOOL_SPEED_UNKNOWN; 5072 } 5073 } 5074 5075 void 5076 bnxt_report_link(struct bnxt_softc *softc) 5077 { 5078 struct bnxt_link_info *link_info = &softc->link_info; 5079 const char *duplex = NULL, *flow_ctrl = NULL; 5080 const char *signal_mode = ""; 5081 5082 if(softc->edev) { 5083 softc->edev->espeed = 5084 bnxt_fw_to_ethtool_speed(link_info->link_speed); 5085 softc->edev->lanes = link_info->active_lanes; 5086 } 5087 5088 if (link_info->link_up == link_info->last_link_up) { 5089 if (!link_info->link_up) 5090 return; 5091 if ((link_info->duplex == link_info->last_duplex) && 5092 (link_info->phy_type == link_info->last_phy_type) && 5093 (!(BNXT_IS_FLOW_CTRL_CHANGED(link_info)))) 5094 return; 5095 } 5096 5097 if (link_info->link_up) { 5098 if (link_info->duplex == 5099 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL) 5100 duplex = "full duplex"; 5101 else 5102 duplex = "half duplex"; 5103 if (link_info->flow_ctrl.tx & link_info->flow_ctrl.rx) 5104 flow_ctrl = "FC - receive & transmit"; 5105 else if (link_info->flow_ctrl.tx) 5106 flow_ctrl = "FC - transmit"; 5107 else if (link_info->flow_ctrl.rx) 5108 flow_ctrl = "FC - receive"; 5109 else 5110 flow_ctrl = "FC - none"; 5111 5112 if (softc->link_info.phy_qcfg_resp.option_flags & 5113 HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN) { 5114 uint8_t sig_mode = softc->link_info.active_fec_sig_mode & 5115 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK; 5116 switch (sig_mode) { 5117 case BNXT_SIG_MODE_NRZ: 5118 signal_mode = "(NRZ) "; 5119 break; 5120 case BNXT_SIG_MODE_PAM4: 5121 signal_mode = "(PAM4 56Gbps) "; 5122 break; 5123 case BNXT_SIG_MODE_PAM4_112: 5124 signal_mode = "(PAM4 112Gbps) "; 5125 break; 5126 default: 5127 break; 5128 } 5129 link_info->sig_mode = sig_mode; 5130 } 5131 5132 iflib_link_state_change(softc->ctx, LINK_STATE_UP, 5133 bnxt_get_baudrate(&softc->link_info)); 5134 device_printf(softc->dev, "Link is UP %s %s, %s - %d Mbps \n", duplex, signal_mode, 5135 flow_ctrl, (link_info->link_speed * 100)); 5136 } else { 5137 iflib_link_state_change(softc->ctx, LINK_STATE_DOWN, 5138 bnxt_get_baudrate(&softc->link_info)); 5139 device_printf(softc->dev, "Link is Down\n"); 5140 } 5141 5142 link_info->last_link_up = link_info->link_up; 5143 link_info->last_duplex = link_info->duplex; 5144 link_info->last_phy_type = link_info->phy_type; 5145 link_info->last_flow_ctrl.tx = link_info->flow_ctrl.tx; 5146 link_info->last_flow_ctrl.rx = link_info->flow_ctrl.rx; 5147 link_info->last_flow_ctrl.autoneg = link_info->flow_ctrl.autoneg; 5148 /* update media types */ 5149 ifmedia_removeall(softc->media); 5150 bnxt_add_media_types(softc); 5151 ifmedia_set(softc->media, IFM_ETHER | IFM_AUTO); 5152 } 5153 5154 static int 5155 bnxt_handle_isr(void *arg) 5156 { 5157 struct bnxt_cp_ring *cpr = arg; 5158 struct bnxt_softc *softc = cpr->ring.softc; 5159 5160 cpr->int_count++; 5161 /* Disable further interrupts for this queue */ 5162 if (!BNXT_CHIP_P5_PLUS(softc)) 5163 softc->db_ops.bnxt_db_rx_cq(cpr, 0); 5164 5165 return FILTER_SCHEDULE_THREAD; 5166 } 5167 5168 static int 5169 bnxt_handle_def_cp(void *arg) 5170 { 5171 struct bnxt_softc *softc = arg; 5172 5173 softc->db_ops.bnxt_db_rx_cq(&softc->def_cp_ring, 0); 5174 iflib_config_task_enqueue(softc->ctx, &softc->def_cp_task); 5175 return FILTER_HANDLED; 5176 } 5177 5178 static void 5179 bnxt_clear_ids(struct bnxt_softc *softc) 5180 { 5181 int i; 5182 5183 softc->def_cp_ring.stats_ctx_id = HWRM_NA_SIGNATURE; 5184 softc->def_cp_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; 5185 softc->def_nq_ring.stats_ctx_id = HWRM_NA_SIGNATURE; 5186 softc->def_nq_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; 5187 for (i = 0; i < softc->ntxqsets; i++) { 5188 softc->tx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; 5189 softc->tx_cp_rings[i].ring.phys_id = 5190 (uint16_t)HWRM_NA_SIGNATURE; 5191 softc->tx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; 5192 5193 if (!softc->nq_rings) 5194 continue; 5195 softc->nq_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; 5196 softc->nq_rings[i].ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; 5197 } 5198 for (i = 0; i < softc->nrxqsets; i++) { 5199 softc->rx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; 5200 softc->rx_cp_rings[i].ring.phys_id = 5201 (uint16_t)HWRM_NA_SIGNATURE; 5202 softc->rx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; 5203 softc->ag_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; 5204 softc->grp_info[i].grp_id = (uint16_t)HWRM_NA_SIGNATURE; 5205 } 5206 softc->vnic_info.filter_id = -1; 5207 softc->vnic_info.id = (uint16_t)HWRM_NA_SIGNATURE; 5208 softc->vnic_info.rss_id = (uint16_t)HWRM_NA_SIGNATURE; 5209 memset(softc->vnic_info.rss_grp_tbl.idi_vaddr, 0xff, 5210 softc->vnic_info.rss_grp_tbl.idi_size); 5211 } 5212 5213 static void 5214 bnxt_mark_cpr_invalid(struct bnxt_cp_ring *cpr) 5215 { 5216 struct cmpl_base *cmp = (void *)cpr->ring.vaddr; 5217 int i; 5218 5219 for (i = 0; i < cpr->ring.ring_size; i++) 5220 cmp[i].info3_v = !cpr->v_bit; 5221 } 5222 5223 static void bnxt_event_error_report(struct bnxt_softc *softc, u32 data1, u32 data2) 5224 { 5225 u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1); 5226 5227 switch (err_type) { 5228 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL: 5229 device_printf(softc->dev, 5230 "1PPS: Received invalid signal on pin%u from the external source. Please fix the signal and reconfigure the pin\n", 5231 BNXT_EVENT_INVALID_SIGNAL_DATA(data2)); 5232 break; 5233 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM: 5234 device_printf(softc->dev, 5235 "Pause Storm detected!\n"); 5236 break; 5237 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD: 5238 device_printf(softc->dev, 5239 "One or more MMIO doorbells dropped by the device! epoch: 0x%x\n", 5240 BNXT_EVENT_DBR_EPOCH(data1)); 5241 break; 5242 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM: { 5243 const char *nvm_err_str; 5244 5245 if (EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1)) 5246 nvm_err_str = "nvm write error"; 5247 else if (EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1)) 5248 nvm_err_str = "nvm erase error"; 5249 else 5250 nvm_err_str = "unrecognized nvm error"; 5251 5252 device_printf(softc->dev, 5253 "%s reported at address 0x%x\n", nvm_err_str, 5254 (u32)EVENT_DATA2_NVM_ERR_ADDR(data2)); 5255 break; 5256 } 5257 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD: { 5258 char *threshold_type; 5259 char *dir_str; 5260 5261 switch (EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1)) { 5262 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN: 5263 threshold_type = "warning"; 5264 break; 5265 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL: 5266 threshold_type = "critical"; 5267 break; 5268 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL: 5269 threshold_type = "fatal"; 5270 break; 5271 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN: 5272 threshold_type = "shutdown"; 5273 break; 5274 default: 5275 device_printf(softc->dev, 5276 "Unknown Thermal threshold type event\n"); 5277 return; 5278 } 5279 if (EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1)) 5280 dir_str = "above"; 5281 else 5282 dir_str = "below"; 5283 device_printf(softc->dev, 5284 "Chip temperature has gone %s the %s thermal threshold!\n", 5285 dir_str, threshold_type); 5286 device_printf(softc->dev, 5287 "Temperature (In Celsius), Current: %u, threshold: %u\n", 5288 BNXT_EVENT_THERMAL_CURRENT_TEMP(data2), 5289 BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2)); 5290 break; 5291 } 5292 case HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED: 5293 device_printf(softc->dev, 5294 "Speed change is not supported with dual rate transceivers on this board\n"); 5295 break; 5296 5297 default: 5298 device_printf(softc->dev, 5299 "FW reported unknown error type: %u, data1: 0x%x data2: 0x%x\n", 5300 err_type, data1, data2); 5301 break; 5302 } 5303 } 5304 5305 static void 5306 bnxt_handle_async_event(struct bnxt_softc *softc, struct cmpl_base *cmpl) 5307 { 5308 struct hwrm_async_event_cmpl *ae = (void *)cmpl; 5309 uint16_t async_id = le16toh(ae->event_id); 5310 struct ifmediareq ifmr; 5311 char *type_str; 5312 char *status_desc; 5313 struct bnxt_fw_health *fw_health; 5314 u32 data1 = le32toh(ae->event_data1); 5315 u32 data2 = le32toh(ae->event_data2); 5316 5317 switch (async_id) { 5318 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: 5319 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: 5320 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: 5321 if (BNXT_CHIP_P5_PLUS(softc)) 5322 bit_set(softc->state_bv, BNXT_STATE_LINK_CHANGE); 5323 else 5324 bnxt_media_status(softc->ctx, &ifmr); 5325 break; 5326 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: { 5327 bnxt_event_error_report(softc, data1, data2); 5328 goto async_event_process_exit; 5329 } 5330 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD: 5331 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE: 5332 break; 5333 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 5334 type_str = "Solicited"; 5335 5336 if (!softc->fw_health) 5337 goto async_event_process_exit; 5338 5339 softc->fw_reset_timestamp = jiffies; 5340 softc->fw_reset_min_dsecs = ae->timestamp_lo; 5341 if (!softc->fw_reset_min_dsecs) 5342 softc->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS; 5343 softc->fw_reset_max_dsecs = le16toh(ae->timestamp_hi); 5344 if (!softc->fw_reset_max_dsecs) 5345 softc->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 5346 if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) { 5347 set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &softc->state); 5348 } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 5349 type_str = "Fatal"; 5350 softc->fw_health->fatalities++; 5351 set_bit(BNXT_STATE_FW_FATAL_COND, &softc->state); 5352 } else if (data2 && BNXT_FW_STATUS_HEALTHY != 5353 EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) { 5354 type_str = "Non-fatal"; 5355 softc->fw_health->survivals++; 5356 set_bit(BNXT_STATE_FW_NON_FATAL_COND, &softc->state); 5357 } 5358 device_printf(softc->dev, 5359 "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n", 5360 type_str, data1, data2, 5361 softc->fw_reset_min_dsecs * 100, 5362 softc->fw_reset_max_dsecs * 100); 5363 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &softc->sp_event); 5364 break; 5365 } 5366 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 5367 fw_health = softc->fw_health; 5368 status_desc = "healthy"; 5369 u32 status; 5370 5371 if (!fw_health) 5372 goto async_event_process_exit; 5373 5374 if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) { 5375 fw_health->enabled = false; 5376 device_printf(softc->dev, "Driver recovery watchdog is disabled\n"); 5377 break; 5378 } 5379 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1); 5380 fw_health->tmr_multiplier = 5381 DIV_ROUND_UP(fw_health->polling_dsecs * HZ, 5382 HZ * 10); 5383 fw_health->tmr_counter = fw_health->tmr_multiplier; 5384 if (!fw_health->enabled) 5385 fw_health->last_fw_heartbeat = 5386 bnxt_fw_health_readl(softc, BNXT_FW_HEARTBEAT_REG); 5387 fw_health->last_fw_reset_cnt = 5388 bnxt_fw_health_readl(softc, BNXT_FW_RESET_CNT_REG); 5389 status = bnxt_fw_health_readl(softc, BNXT_FW_HEALTH_REG); 5390 if (status != BNXT_FW_STATUS_HEALTHY) 5391 status_desc = "unhealthy"; 5392 device_printf(softc->dev, 5393 "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n", 5394 fw_health->primary ? "primary" : "backup", status, 5395 status_desc, fw_health->last_fw_reset_cnt); 5396 if (!fw_health->enabled) { 5397 /* Make sure tmr_counter is set and seen by 5398 * bnxt_health_check() before setting enabled 5399 */ 5400 smp_mb(); 5401 fw_health->enabled = true; 5402 } 5403 goto async_event_process_exit; 5404 } 5405 5406 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE: 5407 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE: 5408 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: 5409 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED: 5410 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD: 5411 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD: 5412 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: 5413 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD: 5414 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR: 5415 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE: 5416 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE: 5417 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: 5418 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR: 5419 device_printf(softc->dev, 5420 "Unhandled async completion type %u\n", async_id); 5421 break; 5422 default: 5423 dev_dbg(softc->dev, "Unknown Async event completion type %u\n", 5424 async_id); 5425 break; 5426 } 5427 bnxt_queue_sp_work(softc); 5428 5429 async_event_process_exit: 5430 bnxt_ulp_async_events(softc, ae); 5431 } 5432 5433 static void 5434 bnxt_def_cp_task(void *context, int pending) 5435 { 5436 if_ctx_t ctx = context; 5437 struct bnxt_softc *softc = iflib_get_softc(ctx); 5438 struct bnxt_cp_ring *cpr = &softc->def_cp_ring; 5439 5440 /* Handle completions on the default completion ring */ 5441 struct cmpl_base *cmpl; 5442 uint32_t cons = cpr->cons; 5443 bool v_bit = cpr->v_bit; 5444 bool last_v_bit; 5445 uint32_t last_cons; 5446 uint16_t type; 5447 5448 for (;;) { 5449 last_cons = cons; 5450 last_v_bit = v_bit; 5451 NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); 5452 cmpl = &((struct cmpl_base *)cpr->ring.vaddr)[cons]; 5453 5454 if (!CMP_VALID(cmpl, v_bit)) 5455 break; 5456 5457 type = le16toh(cmpl->type) & CMPL_BASE_TYPE_MASK; 5458 switch (type) { 5459 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: 5460 bnxt_handle_async_event(softc, cmpl); 5461 break; 5462 case CMPL_BASE_TYPE_TX_L2: 5463 case CMPL_BASE_TYPE_RX_L2: 5464 case CMPL_BASE_TYPE_RX_L2_V3: 5465 case CMPL_BASE_TYPE_RX_AGG: 5466 case CMPL_BASE_TYPE_RX_TPA_START: 5467 case CMPL_BASE_TYPE_RX_TPA_START_V3: 5468 case CMPL_BASE_TYPE_RX_TPA_END: 5469 case CMPL_BASE_TYPE_STAT_EJECT: 5470 case CMPL_BASE_TYPE_HWRM_DONE: 5471 case CMPL_BASE_TYPE_HWRM_FWD_REQ: 5472 case CMPL_BASE_TYPE_HWRM_FWD_RESP: 5473 case CMPL_BASE_TYPE_CQ_NOTIFICATION: 5474 case CMPL_BASE_TYPE_SRQ_EVENT: 5475 case CMPL_BASE_TYPE_DBQ_EVENT: 5476 case CMPL_BASE_TYPE_QP_EVENT: 5477 case CMPL_BASE_TYPE_FUNC_EVENT: 5478 dev_dbg(softc->dev, "Unhandled Async event completion type %u\n", 5479 type); 5480 break; 5481 default: 5482 dev_dbg(softc->dev, "Unknown Async event completion type %u\n", 5483 type); 5484 break; 5485 } 5486 } 5487 5488 cpr->cons = last_cons; 5489 cpr->v_bit = last_v_bit; 5490 softc->db_ops.bnxt_db_rx_cq(cpr, 1); 5491 } 5492 5493 uint8_t 5494 get_phy_type(struct bnxt_softc *softc) 5495 { 5496 struct bnxt_link_info *link_info = &softc->link_info; 5497 uint8_t phy_type = link_info->phy_type; 5498 uint16_t supported; 5499 5500 if (phy_type != HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN) 5501 return phy_type; 5502 5503 /* Deduce the phy type from the media type and supported speeds */ 5504 supported = link_info->support_speeds; 5505 5506 if (link_info->media_type == 5507 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) 5508 return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET; 5509 if (link_info->media_type == 5510 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC) { 5511 if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 5512 return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX; 5513 if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 5514 return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR; 5515 return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR; 5516 } 5517 if (link_info->media_type == 5518 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE) 5519 return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR; 5520 5521 return phy_type; 5522 } 5523 5524 bool 5525 bnxt_check_hwrm_version(struct bnxt_softc *softc) 5526 { 5527 char buf[16]; 5528 5529 sprintf(buf, "%hhu.%hhu.%hhu", softc->ver_info->hwrm_min_major, 5530 softc->ver_info->hwrm_min_minor, softc->ver_info->hwrm_min_update); 5531 if (softc->ver_info->hwrm_min_major > softc->ver_info->hwrm_if_major) { 5532 device_printf(softc->dev, 5533 "WARNING: HWRM version %s is too old (older than %s)\n", 5534 softc->ver_info->hwrm_if_ver, buf); 5535 return false; 5536 } 5537 else if(softc->ver_info->hwrm_min_major == 5538 softc->ver_info->hwrm_if_major) { 5539 if (softc->ver_info->hwrm_min_minor > 5540 softc->ver_info->hwrm_if_minor) { 5541 device_printf(softc->dev, 5542 "WARNING: HWRM version %s is too old (older than %s)\n", 5543 softc->ver_info->hwrm_if_ver, buf); 5544 return false; 5545 } 5546 else if (softc->ver_info->hwrm_min_minor == 5547 softc->ver_info->hwrm_if_minor) { 5548 if (softc->ver_info->hwrm_min_update > 5549 softc->ver_info->hwrm_if_update) { 5550 device_printf(softc->dev, 5551 "WARNING: HWRM version %s is too old (older than %s)\n", 5552 softc->ver_info->hwrm_if_ver, buf); 5553 return false; 5554 } 5555 } 5556 } 5557 return true; 5558 } 5559 5560 static uint64_t 5561 bnxt_get_baudrate(struct bnxt_link_info *link) 5562 { 5563 switch (link->link_speed) { 5564 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB: 5565 return IF_Mbps(100); 5566 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: 5567 return IF_Gbps(1); 5568 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB: 5569 return IF_Gbps(2); 5570 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB: 5571 return IF_Mbps(2500); 5572 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: 5573 return IF_Gbps(10); 5574 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: 5575 return IF_Gbps(20); 5576 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: 5577 return IF_Gbps(25); 5578 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: 5579 return IF_Gbps(40); 5580 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: 5581 return IF_Gbps(50); 5582 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: 5583 return IF_Gbps(100); 5584 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB: 5585 return IF_Mbps(10); 5586 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB: 5587 return IF_Gbps(200); 5588 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB: 5589 return IF_Gbps(400); 5590 } 5591 return IF_Gbps(100); 5592 } 5593 5594 static void 5595 bnxt_get_wol_settings(struct bnxt_softc *softc) 5596 { 5597 uint16_t wol_handle = 0; 5598 5599 if (!bnxt_wol_supported(softc)) 5600 return; 5601 5602 do { 5603 wol_handle = bnxt_hwrm_get_wol_fltrs(softc, wol_handle); 5604 } while (wol_handle && wol_handle != BNXT_NO_MORE_WOL_FILTERS); 5605 } 5606