1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/kobj.h>
36 #include <sys/libkern.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
42 #include <sys/rman.h>
43 #include <sys/stdarg.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46 #include <sys/sbuf.h>
47
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50
51 #include <dev/mmc/bridge.h>
52 #include <dev/mmc/mmcreg.h>
53 #include <dev/mmc/mmcbrvar.h>
54
55 #include <dev/sdhci/sdhci.h>
56
57 #include <cam/cam.h>
58 #include <cam/cam_ccb.h>
59 #include <cam/cam_debug.h>
60 #include <cam/cam_sim.h>
61 #include <cam/cam_xpt_sim.h>
62
63 #include "mmcbr_if.h"
64 #include "sdhci_if.h"
65
66 #include "opt_mmccam.h"
67
68 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
69 "sdhci driver");
70
71 static int sdhci_debug = 0;
72 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
73 "Debug level");
74 u_int sdhci_quirk_clear = 0;
75 SYSCTL_UINT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear,
76 0, "Mask of quirks to clear");
77 u_int sdhci_quirk_set = 0;
78 SYSCTL_UINT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0,
79 "Mask of quirks to set");
80
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
84 #define RD_MULTI_4(slot, off, ptr, count) \
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
86
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
90 #define WR_MULTI_4(slot, off, ptr, count) \
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
92
93 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
94 static void sdhci_card_poll(void *arg);
95 static void sdhci_card_task(void *arg, int pending);
96 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
97 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
98 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
99 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
100 bool is_present);
101 static void sdhci_finish_command(struct sdhci_slot *slot);
102 static void sdhci_init(struct sdhci_slot *slot);
103 static void sdhci_read_block_pio(struct sdhci_slot *slot);
104 static void sdhci_req_done(struct sdhci_slot *slot);
105 static void sdhci_req_wakeup(struct mmc_request *req);
106 static void sdhci_retune(void *arg);
107 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
108 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
109 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
110 const struct mmc_data *data);
111 static void sdhci_start(struct sdhci_slot *slot);
112 static void sdhci_timeout(void *arg);
113 static void sdhci_start_command(struct sdhci_slot *slot,
114 struct mmc_command *cmd);
115 static void sdhci_start_data(struct sdhci_slot *slot,
116 const struct mmc_data *data);
117 static void sdhci_write_block_pio(struct sdhci_slot *slot);
118 static void sdhci_transfer_pio(struct sdhci_slot *slot);
119
120 #ifdef MMCCAM
121 /* CAM-related */
122 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb);
123 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
124 int proposed_clock);
125 static void sdhci_cam_poll(struct cam_sim *sim);
126 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
127 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
128 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
129 #endif
130
131 /* helper routines */
132 static int sdhci_dma_alloc(struct sdhci_slot *slot);
133 static void sdhci_dma_free(struct sdhci_slot *slot);
134 static void sdhci_dumpcaps(struct sdhci_slot *slot);
135 static void sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s);
136 static void sdhci_dumpregs(struct sdhci_slot *slot);
137 static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s);
138 static int sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS);
139 static int sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS);
140 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs,
141 int error);
142 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
143 __printflike(2, 3);
144 static int slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
145 const char * fmt, ...) __printflike(3, 4);
146 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
147
148 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
149 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
150 #define SDHCI_LOCK_INIT(_slot) \
151 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
152 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
153 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
154 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
155
156 #define SDHCI_DEFAULT_MAX_FREQ 50
157
158 #define SDHCI_200_MAX_DIVIDER 256
159 #define SDHCI_300_MAX_DIVIDER 2046
160
161 #define SDHCI_CARD_PRESENT_TICKS (hz / 5)
162 #define SDHCI_INSERT_DELAY_TICKS (hz / 2)
163
164 /*
165 * Broadcom BCM577xx Controller Constants
166 */
167 /* Maximum divider supported by the default clock source. */
168 #define BCM577XX_DEFAULT_MAX_DIVIDER 256
169 /* Alternative clock's base frequency. */
170 #define BCM577XX_ALT_CLOCK_BASE 63000000
171
172 #define BCM577XX_HOST_CONTROL 0x198
173 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
174 #define BCM577XX_CTRL_CLKSEL_SHIFT 12
175 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
176 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
177
178 static void
sdhci_getaddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)179 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
180 {
181
182 if (error != 0) {
183 printf("getaddr: error %d\n", error);
184 return;
185 }
186 *(bus_addr_t *)arg = segs[0].ds_addr;
187 }
188
189 static int
slot_printf(const struct sdhci_slot * slot,const char * fmt,...)190 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
191 {
192 char buf[128];
193 va_list ap;
194 int retval;
195
196 /*
197 * Make sure we print a single line all together rather than in two
198 * halves to avoid console gibberish bingo.
199 */
200 va_start(ap, fmt);
201 retval = vsnprintf(buf, sizeof(buf), fmt, ap);
202 va_end(ap);
203
204 retval += printf("%s-slot%d: %s",
205 device_get_nameunit(slot->bus), slot->num, buf);
206 return (retval);
207 }
208
209 static int
slot_sprintf(const struct sdhci_slot * slot,struct sbuf * s,const char * fmt,...)210 slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
211 const char * fmt, ...)
212 {
213 va_list ap;
214 int retval;
215
216 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num);
217
218 va_start(ap, fmt);
219 retval += sbuf_vprintf(s, fmt, ap);
220 va_end(ap);
221
222 return (retval);
223 }
224
225 static void
sdhci_dumpregs_buf(struct sdhci_slot * slot,struct sbuf * s)226 sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s)
227 {
228 slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n");
229
230 slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n",
231 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
232 slot_sprintf(slot, s, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
233 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
234 slot_sprintf(slot, s, "Argument: 0x%08x | Trn mode: 0x%08x\n",
235 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
236 slot_sprintf(slot, s, "Present: 0x%08x | Host ctl: 0x%08x\n",
237 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
238 slot_sprintf(slot, s, "Power: 0x%08x | Blk gap: 0x%08x\n",
239 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
240 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n",
241 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
242 slot_sprintf(slot, s, "Timeout: 0x%08x | Int stat: 0x%08x\n",
243 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
244 slot_sprintf(slot, s, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
245 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
246 slot_sprintf(slot, s, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
247 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
248 slot_sprintf(slot, s, "Caps: 0x%08x | Caps2: 0x%08x\n",
249 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
250 slot_sprintf(slot, s, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
251 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
252 slot_sprintf(slot, s, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
253 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
254
255 slot_sprintf(slot, s, "===========================================\n");
256 }
257
258 static void
sdhci_dumpregs(struct sdhci_slot * slot)259 sdhci_dumpregs(struct sdhci_slot *slot)
260 {
261 struct sbuf s;
262
263 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) {
264 slot_printf(slot, "sdhci_dumpregs: Failed to allocate memory for sbuf\n");
265 return;
266 }
267
268 sbuf_set_drain(&s, &sbuf_printf_drain, NULL);
269 sdhci_dumpregs_buf(slot, &s);
270 sbuf_finish(&s);
271 sbuf_delete(&s);
272 }
273
274 static int
sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS)275 sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS)
276 {
277 struct sdhci_slot *slot = arg1;
278 struct sbuf s;
279
280 sbuf_new_for_sysctl(&s, NULL, 1024, req);
281 sbuf_putc(&s, '\n');
282 sdhci_dumpregs_buf(slot, &s);
283 sbuf_finish(&s);
284 sbuf_delete(&s);
285
286 return (0);
287 }
288
289 static void
sdhci_dumpcaps_buf(struct sdhci_slot * slot,struct sbuf * s)290 sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s)
291 {
292 int host_caps = slot->host.caps;
293 int caps = slot->caps;
294
295 slot_sprintf(slot, s,
296 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
297 slot->max_clk / 1000000,
298 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
299 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
300 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
301 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
302 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
303 ((caps & SDHCI_CAN_VDD_180) &&
304 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
305 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
306 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
307 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
308 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
309 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
310 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
311 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
312 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
313 "removable");
314 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
315 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
316 slot_sprintf(slot, s, "eMMC:%s%s%s%s\n",
317 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "",
318 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "",
319 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "",
320 ((host_caps &
321 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ==
322 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ?
323 " HS400ES" : "");
324 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
325 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104))
326 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n",
327 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "",
328 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "",
329 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "",
330 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "",
331 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : "");
332 if (slot->opt & SDHCI_TUNING_SUPPORTED)
333 slot_sprintf(slot, s,
334 "Re-tuning count %d secs, mode %d\n",
335 slot->retune_count, slot->retune_mode + 1);
336 }
337
338 static void
sdhci_dumpcaps(struct sdhci_slot * slot)339 sdhci_dumpcaps(struct sdhci_slot *slot)
340 {
341 struct sbuf s;
342
343 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) {
344 slot_printf(slot, "sdhci_dumpcaps: Failed to allocate memory for sbuf\n");
345 return;
346 }
347
348 sbuf_set_drain(&s, &sbuf_printf_drain, NULL);
349 sdhci_dumpcaps_buf(slot, &s);
350 sbuf_finish(&s);
351 sbuf_delete(&s);
352 }
353
354 static int
sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS)355 sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS)
356 {
357 struct sdhci_slot *slot = arg1;
358 struct sbuf s;
359
360 sbuf_new_for_sysctl(&s, NULL, 1024, req);
361 sbuf_putc(&s, '\n');
362 sdhci_dumpcaps_buf(slot, &s);
363 sbuf_finish(&s);
364 sbuf_delete(&s);
365
366 return (0);
367 }
368
369 static uint32_t
sdhci_tuning_intmask(const struct sdhci_slot * slot)370 sdhci_tuning_intmask(const struct sdhci_slot *slot)
371 {
372 uint32_t intmask;
373
374 intmask = 0;
375 if (slot->opt & SDHCI_TUNING_ENABLED) {
376 intmask |= SDHCI_INT_TUNEERR;
377 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
378 slot->retune_mode == SDHCI_RETUNE_MODE_3)
379 intmask |= SDHCI_INT_RETUNE;
380 }
381 return (intmask);
382 }
383
384 static void
sdhci_init(struct sdhci_slot * slot)385 sdhci_init(struct sdhci_slot *slot)
386 {
387
388 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
389
390 /* Enable interrupts. */
391 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
392 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
393 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
394 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
395 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
396 SDHCI_INT_ACMD12ERR;
397
398 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
399 !(slot->opt & SDHCI_NON_REMOVABLE)) {
400 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
401 }
402
403 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
404 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
405 }
406
407 static void
sdhci_set_clock(struct sdhci_slot * slot,uint32_t clock)408 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
409 {
410 uint32_t clk_base;
411 uint32_t clk_sel;
412 uint32_t res;
413 uint16_t clk;
414 uint16_t div;
415 int timeout;
416
417 if (clock == slot->clock)
418 return;
419 clock = SDHCI_SET_CLOCK(slot->bus, slot, clock);
420 slot->clock = clock;
421
422 /* Turn off the clock. */
423 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
424 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
425 /* If no clock requested - leave it so. */
426 if (clock == 0)
427 return;
428
429 /* Determine the clock base frequency */
430 clk_base = slot->max_clk;
431 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
432 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
433 BCM577XX_CTRL_CLKSEL_MASK;
434
435 /*
436 * Select clock source appropriate for the requested frequency.
437 */
438 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {
439 clk_base = BCM577XX_ALT_CLOCK_BASE;
440 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ <<
441 BCM577XX_CTRL_CLKSEL_SHIFT);
442 } else {
443 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT <<
444 BCM577XX_CTRL_CLKSEL_SHIFT);
445 }
446
447 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
448 }
449
450 /* Recalculate timeout clock frequency based on the new sd clock. */
451 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
452 slot->timeout_clk = slot->clock / 1000;
453
454 if (slot->version < SDHCI_SPEC_300) {
455 /* Looking for highest freq <= clock. */
456 res = clk_base;
457 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
458 if (res <= clock)
459 break;
460 res >>= 1;
461 }
462 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
463 div >>= 1;
464 } else {
465 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */
466 if (clock >= clk_base)
467 div = 0;
468 else {
469 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
470 if ((clk_base / div) <= clock)
471 break;
472 }
473 }
474 div >>= 1;
475 }
476
477 if (bootverbose || sdhci_debug)
478 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
479 div, clock, clk_base);
480
481 /* Now we have got divider, set it. */
482 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
483 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
484 << SDHCI_DIVIDER_HI_SHIFT;
485
486 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
487 /* Enable clock. */
488 clk |= SDHCI_CLOCK_INT_EN;
489 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
490 /* Wait up to 10 ms until it stabilize. */
491 timeout = 10;
492 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
493 & SDHCI_CLOCK_INT_STABLE)) {
494 if (timeout == 0) {
495 slot_printf(slot,
496 "Internal clock never stabilised.\n");
497 sdhci_dumpregs(slot);
498 return;
499 }
500 timeout--;
501 DELAY(1000);
502 }
503 /* Pass clock signal to the bus. */
504 clk |= SDHCI_CLOCK_CARD_EN;
505 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
506 }
507
508 static void
sdhci_set_power(struct sdhci_slot * slot,u_char power)509 sdhci_set_power(struct sdhci_slot *slot, u_char power)
510 {
511 int i;
512 uint8_t pwr;
513
514 if (slot->power == power)
515 return;
516
517 slot->power = power;
518
519 /* Turn off the power. */
520 pwr = 0;
521 WR1(slot, SDHCI_POWER_CONTROL, pwr);
522 /* If power down requested - leave it so. */
523 if (power == 0)
524 return;
525 /* Set voltage. */
526 switch (1 << power) {
527 case MMC_OCR_LOW_VOLTAGE:
528 pwr |= SDHCI_POWER_180;
529 break;
530 case MMC_OCR_290_300:
531 case MMC_OCR_300_310:
532 pwr |= SDHCI_POWER_300;
533 break;
534 case MMC_OCR_320_330:
535 case MMC_OCR_330_340:
536 pwr |= SDHCI_POWER_330;
537 break;
538 }
539 WR1(slot, SDHCI_POWER_CONTROL, pwr);
540 /*
541 * Turn on VDD1 power. Note that at least some Intel controllers can
542 * fail to enable bus power on the first try after transiting from D3
543 * to D0, so we give them up to 2 ms.
544 */
545 pwr |= SDHCI_POWER_ON;
546 for (i = 0; i < 20; i++) {
547 WR1(slot, SDHCI_POWER_CONTROL, pwr);
548 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
549 break;
550 DELAY(100);
551 }
552 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
553 slot_printf(slot, "Bus power failed to enable\n");
554
555 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
556 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
557 DELAY(10);
558 WR1(slot, SDHCI_POWER_CONTROL, pwr);
559 DELAY(300);
560 }
561 }
562
563 static void
sdhci_read_block_pio(struct sdhci_slot * slot)564 sdhci_read_block_pio(struct sdhci_slot *slot)
565 {
566 uint32_t data;
567 char *buffer;
568 size_t left;
569
570 buffer = slot->curcmd->data->data;
571 buffer += slot->offset;
572 /* Transfer one block at a time. */
573 #ifdef MMCCAM
574 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE)
575 left = min(slot->curcmd->data->block_size,
576 slot->curcmd->data->len - slot->offset);
577 else
578 #endif
579 left = min(512, slot->curcmd->data->len - slot->offset);
580 slot->offset += left;
581
582 /* If we are too fast, broken controllers return zeroes. */
583 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
584 DELAY(10);
585 /* Handle unaligned and aligned buffer cases. */
586 if ((intptr_t)buffer & 3) {
587 while (left > 3) {
588 data = RD4(slot, SDHCI_BUFFER);
589 buffer[0] = data;
590 buffer[1] = (data >> 8);
591 buffer[2] = (data >> 16);
592 buffer[3] = (data >> 24);
593 buffer += 4;
594 left -= 4;
595 }
596 } else {
597 RD_MULTI_4(slot, SDHCI_BUFFER,
598 (uint32_t *)buffer, left >> 2);
599 left &= 3;
600 }
601 /* Handle uneven size case. */
602 if (left > 0) {
603 data = RD4(slot, SDHCI_BUFFER);
604 while (left > 0) {
605 *(buffer++) = data;
606 data >>= 8;
607 left--;
608 }
609 }
610 }
611
612 static void
sdhci_write_block_pio(struct sdhci_slot * slot)613 sdhci_write_block_pio(struct sdhci_slot *slot)
614 {
615 uint32_t data = 0;
616 char *buffer;
617 size_t left;
618
619 buffer = slot->curcmd->data->data;
620 buffer += slot->offset;
621 /* Transfer one block at a time. */
622 #ifdef MMCCAM
623 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) {
624 left = min(slot->curcmd->data->block_size,
625 slot->curcmd->data->len - slot->offset);
626 } else
627 #endif
628 left = min(512, slot->curcmd->data->len - slot->offset);
629 slot->offset += left;
630
631 /* Handle unaligned and aligned buffer cases. */
632 if ((intptr_t)buffer & 3) {
633 while (left > 3) {
634 data = buffer[0] +
635 (buffer[1] << 8) +
636 (buffer[2] << 16) +
637 (buffer[3] << 24);
638 left -= 4;
639 buffer += 4;
640 WR4(slot, SDHCI_BUFFER, data);
641 }
642 } else {
643 WR_MULTI_4(slot, SDHCI_BUFFER,
644 (uint32_t *)buffer, left >> 2);
645 left &= 3;
646 }
647 /* Handle uneven size case. */
648 if (left > 0) {
649 while (left > 0) {
650 data <<= 8;
651 data += *(buffer++);
652 left--;
653 }
654 WR4(slot, SDHCI_BUFFER, data);
655 }
656 }
657
658 static void
sdhci_transfer_pio(struct sdhci_slot * slot)659 sdhci_transfer_pio(struct sdhci_slot *slot)
660 {
661
662 /* Read as many blocks as possible. */
663 if (slot->curcmd->data->flags & MMC_DATA_READ) {
664 while (RD4(slot, SDHCI_PRESENT_STATE) &
665 SDHCI_DATA_AVAILABLE) {
666 sdhci_read_block_pio(slot);
667 if (slot->offset >= slot->curcmd->data->len)
668 break;
669 }
670 } else {
671 while (RD4(slot, SDHCI_PRESENT_STATE) &
672 SDHCI_SPACE_AVAILABLE) {
673 sdhci_write_block_pio(slot);
674 if (slot->offset >= slot->curcmd->data->len)
675 break;
676 }
677 }
678 }
679
680 static void
sdhci_card_task(void * arg,int pending __unused)681 sdhci_card_task(void *arg, int pending __unused)
682 {
683 struct sdhci_slot *slot = arg;
684 #ifndef MMCCAM
685 device_t d;
686 #endif
687
688 SDHCI_LOCK(slot);
689 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
690 #ifdef MMCCAM
691 if (slot->card_present == 0) {
692 #else
693 if (slot->dev == NULL) {
694 #endif
695 /* If card is present - attach mmc bus. */
696 if (bootverbose || sdhci_debug)
697 slot_printf(slot, "Card inserted\n");
698 #ifdef MMCCAM
699 slot->card_present = 1;
700 mmccam_start_discovery(slot->sim);
701 SDHCI_UNLOCK(slot);
702 #else
703 SDHCI_UNLOCK(slot);
704 bus_topo_lock();
705 d = slot->dev = device_add_child(slot->bus, "mmc", DEVICE_UNIT_ANY);
706 if (d) {
707 device_set_ivars(d, slot);
708 (void)device_probe_and_attach(d);
709 }
710 bus_topo_unlock();
711 #endif
712 } else
713 SDHCI_UNLOCK(slot);
714 } else {
715 #ifdef MMCCAM
716 if (slot->card_present == 1) {
717 #else
718 if (slot->dev != NULL) {
719 d = slot->dev;
720 #endif
721 /* If no card present - detach mmc bus. */
722 if (bootverbose || sdhci_debug)
723 slot_printf(slot, "Card removed\n");
724 slot->dev = NULL;
725 #ifdef MMCCAM
726 slot->card_present = 0;
727 mmccam_start_discovery(slot->sim);
728 SDHCI_UNLOCK(slot);
729 #else
730 slot->intmask &= ~sdhci_tuning_intmask(slot);
731 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
732 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
733 slot->opt &= ~SDHCI_TUNING_ENABLED;
734 SDHCI_UNLOCK(slot);
735 callout_drain(&slot->retune_callout);
736 bus_topo_lock();
737 device_delete_child(slot->bus, d);
738 bus_topo_unlock();
739 #endif
740 } else
741 SDHCI_UNLOCK(slot);
742 }
743 }
744
745 static void
746 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
747 {
748 bool was_present;
749
750 /*
751 * If there was no card and now there is one, schedule the task to
752 * create the child device after a short delay. The delay is to
753 * debounce the card insert (sometimes the card detect pin stabilizes
754 * before the other pins have made good contact).
755 *
756 * If there was a card present and now it's gone, immediately schedule
757 * the task to delete the child device. No debouncing -- gone is gone,
758 * because once power is removed, a full card re-init is needed, and
759 * that happens by deleting and recreating the child device.
760 */
761 #ifdef MMCCAM
762 was_present = slot->card_present;
763 #else
764 was_present = slot->dev != NULL;
765 #endif
766 if (!was_present && is_present) {
767 taskqueue_enqueue_timeout(taskqueue_bus,
768 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
769 } else if (was_present && !is_present) {
770 taskqueue_enqueue(taskqueue_bus, &slot->card_task);
771 }
772 }
773
774 void
775 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
776 {
777
778 SDHCI_LOCK(slot);
779 sdhci_handle_card_present_locked(slot, is_present);
780 SDHCI_UNLOCK(slot);
781 }
782
783 static void
784 sdhci_card_poll(void *arg)
785 {
786 struct sdhci_slot *slot = arg;
787
788 sdhci_handle_card_present(slot,
789 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
790 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
791 sdhci_card_poll, slot);
792 }
793
794 static int
795 sdhci_dma_alloc(struct sdhci_slot *slot)
796 {
797 int err;
798
799 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
800 if (maxphys <= 1024 * 4)
801 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
802 else if (maxphys <= 1024 * 8)
803 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
804 else if (maxphys <= 1024 * 16)
805 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
806 else if (maxphys <= 1024 * 32)
807 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
808 else if (maxphys <= 1024 * 64)
809 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
810 else if (maxphys <= 1024 * 128)
811 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
812 else if (maxphys <= 1024 * 256)
813 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
814 else
815 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
816 }
817 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
818
819 /*
820 * Allocate the DMA tag for an SDMA bounce buffer.
821 * Note that the SDHCI specification doesn't state any alignment
822 * constraint for the SDMA system address. However, controllers
823 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when
824 * forming the actual address of data, requiring the SDMA buffer to
825 * be aligned to the SDMA boundary.
826 */
827 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
828 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
829 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
830 NULL, NULL, &slot->dmatag);
831 if (err != 0) {
832 slot_printf(slot, "Can't create DMA tag for SDMA\n");
833 return (err);
834 }
835 /* Allocate DMA memory for the SDMA bounce buffer. */
836 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
837 BUS_DMA_NOWAIT, &slot->dmamap);
838 if (err != 0) {
839 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
840 bus_dma_tag_destroy(slot->dmatag);
841 return (err);
842 }
843 /* Map the memory of the SDMA bounce buffer. */
844 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
845 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
846 &slot->paddr, 0);
847 if (err != 0 || slot->paddr == 0) {
848 slot_printf(slot, "Can't load DMA memory for SDMA\n");
849 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
850 bus_dma_tag_destroy(slot->dmatag);
851 if (err)
852 return (err);
853 else
854 return (EFAULT);
855 }
856
857 return (0);
858 }
859
860 static void
861 sdhci_dma_free(struct sdhci_slot *slot)
862 {
863
864 bus_dmamap_unload(slot->dmatag, slot->dmamap);
865 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
866 bus_dma_tag_destroy(slot->dmatag);
867 }
868
869 int
870 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
871 {
872 kobjop_desc_t kobj_desc;
873 kobj_method_t *kobj_method;
874 uint32_t caps, caps2, freq, host_caps;
875 int err;
876 char node_name[8];
877 struct sysctl_oid *node_oid;
878
879 SDHCI_LOCK_INIT(slot);
880
881 slot->num = num;
882 slot->bus = dev;
883
884 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
885 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
886 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
887 caps = slot->caps;
888 caps2 = slot->caps2;
889 } else {
890 caps = RD4(slot, SDHCI_CAPABILITIES);
891 if (slot->version >= SDHCI_SPEC_300)
892 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
893 else
894 caps2 = 0;
895 }
896 if (slot->version >= SDHCI_SPEC_300) {
897 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
898 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
899 slot_printf(slot,
900 "Driver doesn't support shared bus slots\n");
901 SDHCI_LOCK_DESTROY(slot);
902 return (ENXIO);
903 } else if ((caps & SDHCI_SLOTTYPE_MASK) ==
904 SDHCI_SLOTTYPE_EMBEDDED &&
905 !(slot->quirks & SDHCI_QUIRK_SLOTTYPE_BROKEN)) {
906 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
907 }
908 }
909 /* Calculate base clock frequency. */
910 if (slot->version >= SDHCI_SPEC_300)
911 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
912 SDHCI_CLOCK_BASE_SHIFT;
913 else
914 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
915 SDHCI_CLOCK_BASE_SHIFT;
916 if (freq != 0)
917 slot->max_clk = freq * 1000000;
918 /*
919 * If the frequency wasn't in the capabilities and the hardware driver
920 * hasn't already set max_clk we're probably not going to work right
921 * with an assumption, so complain about it.
922 */
923 if (slot->max_clk == 0) {
924 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
925 slot_printf(slot, "Hardware doesn't specify base clock "
926 "frequency, using %dMHz as default.\n",
927 SDHCI_DEFAULT_MAX_FREQ);
928 }
929 /* Calculate/set timeout clock frequency. */
930 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
931 slot->timeout_clk = slot->max_clk / 1000;
932 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
933 slot->timeout_clk = 1000;
934 } else {
935 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
936 SDHCI_TIMEOUT_CLK_SHIFT;
937 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
938 slot->timeout_clk *= 1000;
939 }
940 /*
941 * If the frequency wasn't in the capabilities and the hardware driver
942 * hasn't already set timeout_clk we'll probably work okay using the
943 * max timeout, but still mention it.
944 */
945 if (slot->timeout_clk == 0) {
946 slot_printf(slot, "Hardware doesn't specify timeout clock "
947 "frequency, setting BROKEN_TIMEOUT quirk.\n");
948 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
949 }
950
951 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
952 slot->host.f_max = slot->max_clk;
953 slot->host.host_ocr = 0;
954 if (caps & SDHCI_CAN_VDD_330)
955 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
956 if (caps & SDHCI_CAN_VDD_300)
957 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
958 /*
959 * 1.8V VDD is not supposed to be used for removable cards. Hardware
960 * prior to v3.0 had no way to indicate embedded slots, but did
961 * sometimes support 1.8v for non-removable devices.
962 */
963 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 ||
964 (slot->opt & SDHCI_SLOT_EMBEDDED)))
965 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
966 if (slot->host.host_ocr == 0) {
967 slot_printf(slot, "Hardware doesn't report any "
968 "support voltages.\n");
969 }
970
971 host_caps = slot->host.caps;
972 host_caps |= MMC_CAP_4_BIT_DATA;
973 if (caps & SDHCI_CAN_DO_8BITBUS)
974 host_caps |= MMC_CAP_8_BIT_DATA;
975 if (caps & SDHCI_CAN_DO_HISPD)
976 host_caps |= MMC_CAP_HSPEED;
977 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
978 host_caps |= MMC_CAP_BOOT_NOACC;
979 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
980 host_caps |= MMC_CAP_WAIT_WHILE_BUSY;
981
982 /* Determine supported UHS-I and eMMC modes. */
983 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50))
984 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
985 if (caps2 & SDHCI_CAN_SDR104) {
986 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
987 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
988 host_caps |= MMC_CAP_MMC_HS200;
989 } else if (caps2 & SDHCI_CAN_SDR50)
990 host_caps |= MMC_CAP_UHS_SDR50;
991 if (caps2 & SDHCI_CAN_DDR50 &&
992 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
993 host_caps |= MMC_CAP_UHS_DDR50;
994 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
995 host_caps |= MMC_CAP_MMC_DDR52;
996 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
997 caps2 & SDHCI_CAN_MMC_HS400)
998 host_caps |= MMC_CAP_MMC_HS400;
999 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
1000 caps2 & SDHCI_CAN_SDR104)
1001 host_caps |= MMC_CAP_MMC_HS400;
1002
1003 /*
1004 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the
1005 * default NULL implementation.
1006 */
1007 kobj_desc = &sdhci_set_uhs_timing_desc;
1008 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1009 kobj_desc);
1010 if (kobj_method == &kobj_desc->deflt)
1011 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1012 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1013 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400);
1014
1015 #define SDHCI_CAP_MODES_TUNING(caps2) \
1016 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \
1017 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \
1018 MMC_CAP_MMC_HS400)
1019
1020 /*
1021 * Disable UHS-I and eMMC modes that require (re-)tuning if either
1022 * the tune or re-tune method is the default NULL implementation.
1023 */
1024 kobj_desc = &mmcbr_tune_desc;
1025 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1026 kobj_desc);
1027 if (kobj_method == &kobj_desc->deflt)
1028 goto no_tuning;
1029 kobj_desc = &mmcbr_retune_desc;
1030 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1031 kobj_desc);
1032 if (kobj_method == &kobj_desc->deflt) {
1033 no_tuning:
1034 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2));
1035 }
1036
1037 /* Allocate tuning structures and determine tuning parameters. */
1038 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) {
1039 slot->opt |= SDHCI_TUNING_SUPPORTED;
1040 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
1041 M_WAITOK);
1042 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
1043 M_WAITOK);
1044 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
1045 M_WAITOK);
1046 if (caps2 & SDHCI_TUNE_SDR50)
1047 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
1048 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
1049 SDHCI_RETUNE_MODES_SHIFT;
1050 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
1051 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
1052 SDHCI_RETUNE_CNT_SHIFT;
1053 if (slot->retune_count > 0xb) {
1054 slot_printf(slot, "Unknown re-tuning count "
1055 "%x, using 1 sec\n", slot->retune_count);
1056 slot->retune_count = 1;
1057 } else if (slot->retune_count != 0)
1058 slot->retune_count =
1059 1 << (slot->retune_count - 1);
1060 }
1061 }
1062
1063 #undef SDHCI_CAP_MODES_TUNING
1064
1065 /* Determine supported VCCQ signaling levels. */
1066 host_caps |= MMC_CAP_SIGNALING_330;
1067 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
1068 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
1069 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 |
1070 MMC_CAP_MMC_HS400_180))
1071 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180;
1072
1073 /*
1074 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the
1075 * default NULL implementation. Disable 1.2 V support if it's the
1076 * generic SDHCI implementation.
1077 */
1078 kobj_desc = &mmcbr_switch_vccq_desc;
1079 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL,
1080 kobj_desc);
1081 if (kobj_method == &kobj_desc->deflt)
1082 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180);
1083 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq)
1084 host_caps &= ~MMC_CAP_SIGNALING_120;
1085
1086 /* Determine supported driver types (type B is always mandatory). */
1087 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A)
1088 host_caps |= MMC_CAP_DRIVER_TYPE_A;
1089 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C)
1090 host_caps |= MMC_CAP_DRIVER_TYPE_C;
1091 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D)
1092 host_caps |= MMC_CAP_DRIVER_TYPE_D;
1093 slot->host.caps = host_caps;
1094
1095 /* Decide if we have usable DMA. */
1096 if (caps & SDHCI_CAN_DO_DMA)
1097 slot->opt |= SDHCI_HAVE_DMA;
1098
1099 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
1100 slot->opt &= ~SDHCI_HAVE_DMA;
1101 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
1102 slot->opt |= SDHCI_HAVE_DMA;
1103 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
1104 slot->opt |= SDHCI_NON_REMOVABLE;
1105
1106 /*
1107 * Use platform-provided transfer backend
1108 * with PIO as a fallback mechanism
1109 */
1110 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
1111 slot->opt &= ~SDHCI_HAVE_DMA;
1112
1113 if (slot->opt & SDHCI_HAVE_DMA) {
1114 err = sdhci_dma_alloc(slot);
1115 if (err != 0) {
1116 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1117 free(slot->tune_req, M_DEVBUF);
1118 free(slot->tune_cmd, M_DEVBUF);
1119 free(slot->tune_data, M_DEVBUF);
1120 }
1121 SDHCI_LOCK_DESTROY(slot);
1122 return (err);
1123 }
1124 }
1125
1126 if (bootverbose || sdhci_debug) {
1127 sdhci_dumpcaps(slot);
1128 sdhci_dumpregs(slot);
1129 }
1130
1131 slot->timeout = 10;
1132 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1133 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1134 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0,
1135 "Maximum timeout for SDHCI transfers (in secs)");
1136 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1137 TIMEOUT_TASK_INIT(taskqueue_bus, &slot->card_delayed_task, 0,
1138 sdhci_card_task, slot);
1139 callout_init(&slot->card_poll_callout, 1);
1140 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1141 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1142
1143 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1144 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1145 callout_reset(&slot->card_poll_callout,
1146 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1147 }
1148
1149 sdhci_init(slot);
1150
1151 snprintf(node_name, sizeof(node_name), "slot%d", slot->num);
1152
1153 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev),
1154 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1155 OID_AUTO, node_name, CTLFLAG_RW, 0, "slot specific node");
1156
1157 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1158 OID_AUTO, "quirks", CTLFLAG_RD, &slot->quirks, 0, "Slot quirks");
1159
1160 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev),
1161 SYSCTL_CHILDREN(node_oid), OID_AUTO, "debug", CTLFLAG_RW, 0,
1162 "Debugging node");
1163
1164 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1165 OID_AUTO, "dumpregs", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1166 slot, 0, &sdhci_syctl_dumpregs,
1167 "A", "Dump SDHCI registers");
1168
1169 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid),
1170 OID_AUTO, "dumpcaps", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
1171 slot, 0, &sdhci_syctl_dumpcaps,
1172 "A", "Dump SDHCI capabilites");
1173
1174 return (0);
1175 }
1176
1177 #ifndef MMCCAM
1178 void
1179 sdhci_start_slot(struct sdhci_slot *slot)
1180 {
1181
1182 sdhci_card_task(slot, 0);
1183 }
1184 #endif
1185
1186 int
1187 sdhci_cleanup_slot(struct sdhci_slot *slot)
1188 {
1189 device_t d;
1190
1191 callout_drain(&slot->timeout_callout);
1192 callout_drain(&slot->card_poll_callout);
1193 callout_drain(&slot->retune_callout);
1194 taskqueue_drain(taskqueue_bus, &slot->card_task);
1195 taskqueue_drain_timeout(taskqueue_bus, &slot->card_delayed_task);
1196
1197 SDHCI_LOCK(slot);
1198 d = slot->dev;
1199 slot->dev = NULL;
1200 SDHCI_UNLOCK(slot);
1201 if (d != NULL)
1202 device_delete_child(slot->bus, d);
1203
1204 SDHCI_LOCK(slot);
1205 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1206 SDHCI_UNLOCK(slot);
1207 if (slot->opt & SDHCI_HAVE_DMA)
1208 sdhci_dma_free(slot);
1209 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1210 free(slot->tune_req, M_DEVBUF);
1211 free(slot->tune_cmd, M_DEVBUF);
1212 free(slot->tune_data, M_DEVBUF);
1213 }
1214
1215 SDHCI_LOCK_DESTROY(slot);
1216
1217 return (0);
1218 }
1219
1220 int
1221 sdhci_generic_suspend(struct sdhci_slot *slot)
1222 {
1223
1224 /*
1225 * We expect the MMC layer to issue initial tuning after resume.
1226 * Otherwise, we'd need to indicate re-tuning including circuit reset
1227 * being required at least for re-tuning modes 1 and 2 ourselves.
1228 */
1229 callout_drain(&slot->retune_callout);
1230 SDHCI_LOCK(slot);
1231 slot->opt &= ~SDHCI_TUNING_ENABLED;
1232 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1233 SDHCI_UNLOCK(slot);
1234
1235 return (0);
1236 }
1237
1238 int
1239 sdhci_generic_resume(struct sdhci_slot *slot)
1240 {
1241
1242 SDHCI_LOCK(slot);
1243 sdhci_init(slot);
1244 SDHCI_UNLOCK(slot);
1245
1246 return (0);
1247 }
1248
1249 void
1250 sdhci_generic_reset(device_t brdev __unused, struct sdhci_slot *slot,
1251 uint8_t mask)
1252 {
1253 int timeout;
1254 uint32_t clock;
1255
1256 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
1257 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
1258 return;
1259 }
1260
1261 /* Some controllers need this kick or reset won't work. */
1262 if ((mask & SDHCI_RESET_ALL) == 0 &&
1263 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
1264 /* This is to force an update */
1265 clock = slot->clock;
1266 slot->clock = 0;
1267 sdhci_set_clock(slot, clock);
1268 }
1269
1270 if (mask & SDHCI_RESET_ALL) {
1271 slot->clock = 0;
1272 slot->power = 0;
1273 }
1274
1275 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
1276
1277 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
1278 /*
1279 * Resets on TI OMAPs and AM335x are incompatible with SDHCI
1280 * specification. The reset bit has internal propagation delay,
1281 * so a fast read after write returns 0 even if reset process is
1282 * in progress. The workaround is to poll for 1 before polling
1283 * for 0. In the worst case, if we miss seeing it asserted the
1284 * time we spent waiting is enough to ensure the reset finishes.
1285 */
1286 timeout = 10000;
1287 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
1288 if (timeout <= 0)
1289 break;
1290 timeout--;
1291 DELAY(1);
1292 }
1293 }
1294
1295 /* Wait max 100 ms */
1296 timeout = 10000;
1297 /* Controller clears the bits when it's done */
1298 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
1299 if (timeout <= 0) {
1300 slot_printf(slot, "Reset 0x%x never completed.\n",
1301 mask);
1302 sdhci_dumpregs(slot);
1303 return;
1304 }
1305 timeout--;
1306 DELAY(10);
1307 }
1308 }
1309
1310 uint32_t
1311 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1312 {
1313
1314 if (slot->version >= SDHCI_SPEC_300)
1315 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1316 else
1317 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1318 }
1319
1320 bool
1321 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1322 {
1323
1324 if (slot->opt & SDHCI_NON_REMOVABLE)
1325 return true;
1326
1327 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1328 }
1329
1330 void
1331 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1332 {
1333 const struct mmc_ios *ios;
1334 uint16_t hostctrl2;
1335
1336 if (slot->version < SDHCI_SPEC_300)
1337 return;
1338
1339 SDHCI_ASSERT_LOCKED(slot);
1340 ios = &slot->host.ios;
1341 sdhci_set_clock(slot, 0);
1342 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1343 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
1344 if (ios->clock > SD_SDR50_MAX) {
1345 if (ios->timing == bus_timing_mmc_hs400 ||
1346 ios->timing == bus_timing_mmc_hs400es)
1347 hostctrl2 |= SDHCI_CTRL2_MMC_HS400;
1348 else
1349 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
1350 }
1351 else if (ios->clock > SD_SDR25_MAX)
1352 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
1353 else if (ios->clock > SD_SDR12_MAX) {
1354 if (ios->timing == bus_timing_uhs_ddr50 ||
1355 ios->timing == bus_timing_mmc_ddr52)
1356 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
1357 else
1358 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
1359 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1360 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
1361 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1362 sdhci_set_clock(slot, ios->clock);
1363 }
1364
1365 int
1366 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
1367 {
1368 struct sdhci_slot *slot = device_get_ivars(reqdev);
1369 struct mmc_ios *ios = &slot->host.ios;
1370
1371 SDHCI_LOCK(slot);
1372 /* Do full reset on bus power down to clear from any state. */
1373 if (ios->power_mode == power_off) {
1374 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1375 sdhci_init(slot);
1376 }
1377 /* Configure the bus. */
1378 sdhci_set_clock(slot, ios->clock);
1379 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1380 if (ios->bus_width == bus_width_8) {
1381 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1382 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1383 } else if (ios->bus_width == bus_width_4) {
1384 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1385 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1386 } else if (ios->bus_width == bus_width_1) {
1387 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1388 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1389 } else {
1390 panic("Invalid bus width: %d", ios->bus_width);
1391 }
1392 if (ios->clock > SD_SDR12_MAX &&
1393 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1394 slot->hostctrl |= SDHCI_CTRL_HISPD;
1395 else
1396 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1397 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1398 SDHCI_SET_UHS_TIMING(brdev, slot);
1399 /* Some controllers like reset after bus changes. */
1400 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1401 SDHCI_RESET(slot->bus, slot,
1402 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1403
1404 SDHCI_UNLOCK(slot);
1405 return (0);
1406 }
1407
1408 int
1409 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev)
1410 {
1411 struct sdhci_slot *slot = device_get_ivars(reqdev);
1412 enum mmc_vccq vccq;
1413 int err;
1414 uint16_t hostctrl2;
1415
1416 if (slot->version < SDHCI_SPEC_300)
1417 return (0);
1418
1419 err = 0;
1420 vccq = slot->host.ios.vccq;
1421 SDHCI_LOCK(slot);
1422 sdhci_set_clock(slot, 0);
1423 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1424 switch (vccq) {
1425 case vccq_330:
1426 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1427 goto done;
1428 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE;
1429 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1430 DELAY(5000);
1431 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1432 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE))
1433 goto done;
1434 err = EAGAIN;
1435 break;
1436 case vccq_180:
1437 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1438 err = EINVAL;
1439 goto done;
1440 }
1441 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1442 goto done;
1443 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE;
1444 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1445 DELAY(5000);
1446 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1447 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE)
1448 goto done;
1449 err = EAGAIN;
1450 break;
1451 default:
1452 slot_printf(slot,
1453 "Attempt to set unsupported signaling voltage\n");
1454 err = EINVAL;
1455 break;
1456 }
1457 done:
1458 sdhci_set_clock(slot, slot->host.ios.clock);
1459 SDHCI_UNLOCK(slot);
1460 return (err);
1461 }
1462
1463 int
1464 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400)
1465 {
1466 struct sdhci_slot *slot = device_get_ivars(reqdev);
1467 const struct mmc_ios *ios = &slot->host.ios;
1468 struct mmc_command *tune_cmd;
1469 struct mmc_data *tune_data;
1470 uint32_t opcode;
1471 int err;
1472
1473 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1474 return (0);
1475
1476 slot->retune_ticks = slot->retune_count * hz;
1477 opcode = MMC_SEND_TUNING_BLOCK;
1478 SDHCI_LOCK(slot);
1479 switch (ios->timing) {
1480 case bus_timing_mmc_hs400:
1481 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1482 SDHCI_UNLOCK(slot);
1483 return (EINVAL);
1484 case bus_timing_mmc_hs200:
1485 /*
1486 * In HS400 mode, controllers use the data strobe line to
1487 * latch data from the devices so periodic re-tuning isn't
1488 * expected to be required.
1489 */
1490 if (hs400)
1491 slot->retune_ticks = 0;
1492 opcode = MMC_SEND_TUNING_BLOCK_HS200;
1493 break;
1494 case bus_timing_uhs_ddr50:
1495 case bus_timing_uhs_sdr104:
1496 break;
1497 case bus_timing_uhs_sdr50:
1498 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1499 break;
1500 SDHCI_UNLOCK(slot);
1501 return (0);
1502 default:
1503 slot_printf(slot, "Tuning requested but not required.\n");
1504 SDHCI_UNLOCK(slot);
1505 return (EINVAL);
1506 }
1507
1508 tune_cmd = slot->tune_cmd;
1509 memset(tune_cmd, 0, sizeof(*tune_cmd));
1510 tune_cmd->opcode = opcode;
1511 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1512 tune_data = tune_cmd->data = slot->tune_data;
1513 memset(tune_data, 0, sizeof(*tune_data));
1514 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
1515 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
1516 MMC_TUNING_LEN;
1517 tune_data->flags = MMC_DATA_READ;
1518 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1519
1520 slot->opt &= ~SDHCI_TUNING_ENABLED;
1521 err = sdhci_exec_tuning(slot, true);
1522 if (err == 0) {
1523 slot->opt |= SDHCI_TUNING_ENABLED;
1524 slot->intmask |= sdhci_tuning_intmask(slot);
1525 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1526 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1527 if (slot->retune_ticks) {
1528 callout_reset(&slot->retune_callout, slot->retune_ticks,
1529 sdhci_retune, slot);
1530 }
1531 }
1532 SDHCI_UNLOCK(slot);
1533 return (err);
1534 }
1535
1536 int
1537 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)
1538 {
1539 struct sdhci_slot *slot = device_get_ivars(reqdev);
1540 int err;
1541
1542 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1543 return (0);
1544
1545 /* HS400 must be tuned in HS200 mode. */
1546 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1547 return (EINVAL);
1548
1549 SDHCI_LOCK(slot);
1550 err = sdhci_exec_tuning(slot, reset);
1551 /*
1552 * There are two ways sdhci_exec_tuning() can fail:
1553 * EBUSY should not actually happen when requests are only issued
1554 * with the host properly acquired, and
1555 * EIO re-tuning failed (but it did work initially).
1556 *
1557 * In both cases, we should retry at later point if periodic re-tuning
1558 * is enabled. Note that due to slot->retune_req not being cleared in
1559 * these failure cases, the MMC layer should trigger another attempt at
1560 * re-tuning with the next request anyway, though.
1561 */
1562 if (slot->retune_ticks) {
1563 callout_reset(&slot->retune_callout, slot->retune_ticks,
1564 sdhci_retune, slot);
1565 }
1566 SDHCI_UNLOCK(slot);
1567 return (err);
1568 }
1569
1570 static int
1571 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1572 {
1573 struct mmc_request *tune_req;
1574 struct mmc_command *tune_cmd;
1575 int i;
1576 uint32_t intmask;
1577 uint16_t hostctrl2;
1578 u_char opt;
1579
1580 SDHCI_ASSERT_LOCKED(slot);
1581 if (slot->req != NULL)
1582 return (EBUSY);
1583
1584 /* Tuning doesn't work with DMA enabled. */
1585 opt = slot->opt;
1586 slot->opt = opt & ~SDHCI_HAVE_DMA;
1587
1588 /*
1589 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only
1590 * kind of interrupt we receive in response to a tuning request.
1591 */
1592 intmask = slot->intmask;
1593 slot->intmask = SDHCI_INT_DATA_AVAIL;
1594 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1595 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1596
1597 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1598 if (reset)
1599 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK;
1600 else
1601 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK;
1602 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1603
1604 tune_req = slot->tune_req;
1605 tune_cmd = slot->tune_cmd;
1606 for (i = 0; i < MMC_TUNING_MAX; i++) {
1607 memset(tune_req, 0, sizeof(*tune_req));
1608 tune_req->cmd = tune_cmd;
1609 tune_req->done = sdhci_req_wakeup;
1610 tune_req->done_data = slot;
1611 slot->req = tune_req;
1612 slot->flags = 0;
1613 sdhci_start(slot);
1614 while (!(tune_req->flags & MMC_REQ_DONE))
1615 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1616 if (!(tune_req->flags & MMC_TUNE_DONE))
1617 break;
1618 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1619 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING))
1620 break;
1621 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK)
1622 DELAY(1000);
1623 }
1624
1625 /*
1626 * Restore DMA usage and interrupts.
1627 * Note that the interrupt aggregation code might have cleared
1628 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1629 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE
1630 * doesn't lose these.
1631 */
1632 slot->opt = opt;
1633 slot->intmask = intmask;
1634 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1635 SDHCI_INT_RESPONSE);
1636 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1637
1638 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING |
1639 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) {
1640 slot->retune_req = 0;
1641 return (0);
1642 }
1643
1644 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1645 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1646 SDHCI_CTRL2_SAMPLING_CLOCK));
1647 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1648 return (EIO);
1649 }
1650
1651 static void
1652 sdhci_retune(void *arg)
1653 {
1654 struct sdhci_slot *slot = arg;
1655
1656 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1657 }
1658
1659 #ifdef MMCCAM
1660 static void
1661 sdhci_req_done(struct sdhci_slot *slot)
1662 {
1663 union ccb *ccb;
1664
1665 if (__predict_false(sdhci_debug > 1))
1666 slot_printf(slot, "%s\n", __func__);
1667 if (slot->ccb != NULL && slot->curcmd != NULL) {
1668 callout_stop(&slot->timeout_callout);
1669 ccb = slot->ccb;
1670 slot->ccb = NULL;
1671 slot->curcmd = NULL;
1672
1673 /* Tell CAM the request is finished */
1674 struct ccb_mmcio *mmcio;
1675 mmcio = &ccb->mmcio;
1676
1677 ccb->ccb_h.status =
1678 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
1679 xpt_done(ccb);
1680 }
1681 }
1682 #else
1683 static void
1684 sdhci_req_done(struct sdhci_slot *slot)
1685 {
1686 struct mmc_request *req;
1687
1688 if (slot->req != NULL && slot->curcmd != NULL) {
1689 callout_stop(&slot->timeout_callout);
1690 req = slot->req;
1691 slot->req = NULL;
1692 slot->curcmd = NULL;
1693 req->done(req);
1694 }
1695 }
1696 #endif
1697
1698 static void
1699 sdhci_req_wakeup(struct mmc_request *req)
1700 {
1701
1702 req->flags |= MMC_REQ_DONE;
1703 wakeup(req);
1704 }
1705
1706 static void
1707 sdhci_timeout(void *arg)
1708 {
1709 struct sdhci_slot *slot = arg;
1710
1711 if (slot->curcmd != NULL) {
1712 slot_printf(slot, "Controller timeout\n");
1713 sdhci_dumpregs(slot);
1714 SDHCI_RESET(slot->bus, slot,
1715 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1716 slot->curcmd->error = MMC_ERR_TIMEOUT;
1717 sdhci_req_done(slot);
1718 } else {
1719 slot_printf(slot, "Spurious timeout - no active command\n");
1720 }
1721 }
1722
1723 static void
1724 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data)
1725 {
1726 uint16_t mode;
1727
1728 if (data == NULL)
1729 return;
1730
1731 mode = SDHCI_TRNS_BLK_CNT_EN;
1732 if (data->len > 512 || data->block_count > 1) {
1733 mode |= SDHCI_TRNS_MULTI;
1734 if (data->block_count == 0 && __predict_true(
1735 #ifdef MMCCAM
1736 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION &&
1737 #else
1738 slot->req->stop != NULL &&
1739 #endif
1740 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1741 mode |= SDHCI_TRNS_ACMD12;
1742 }
1743 if (data->flags & MMC_DATA_READ)
1744 mode |= SDHCI_TRNS_READ;
1745 if (slot->flags & SDHCI_USE_DMA)
1746 mode |= SDHCI_TRNS_DMA;
1747
1748 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1749 }
1750
1751 static void
1752 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1753 {
1754 int flags, timeout;
1755 uint32_t mask;
1756
1757 slot->curcmd = cmd;
1758 slot->cmd_done = 0;
1759
1760 cmd->error = MMC_ERR_NONE;
1761
1762 /* This flags combination is not supported by controller. */
1763 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1764 slot_printf(slot, "Unsupported response type!\n");
1765 cmd->error = MMC_ERR_FAILED;
1766 sdhci_req_done(slot);
1767 return;
1768 }
1769
1770 /*
1771 * Do not issue command if there is no card, clock or power.
1772 * Controller will not detect timeout without clock active.
1773 */
1774 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1775 slot->power == 0 ||
1776 slot->clock == 0) {
1777 slot_printf(slot,
1778 "Cannot issue a command (power=%d clock=%d)\n",
1779 slot->power, slot->clock);
1780 cmd->error = MMC_ERR_FAILED;
1781 sdhci_req_done(slot);
1782 return;
1783 }
1784 /* Always wait for free CMD bus. */
1785 mask = SDHCI_CMD_INHIBIT;
1786 /* Wait for free DAT if we have data or busy signal. */
1787 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY))
1788 mask |= SDHCI_DAT_INHIBIT;
1789 /*
1790 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note
1791 * that these latter are also special in that SDHCI_CMD_DATA should
1792 * be set below but no actual data is ever read from the controller.
1793 */
1794 #ifdef MMCCAM
1795 if (cmd == &slot->ccb->mmcio.stop ||
1796 #else
1797 if (cmd == slot->req->stop ||
1798 #endif
1799 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1800 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))
1801 mask &= ~SDHCI_DAT_INHIBIT;
1802 /*
1803 * Wait for bus no more then 250 ms. Typically there will be no wait
1804 * here at all, but when writing a crash dump we may be bypassing the
1805 * host platform's interrupt handler, and in some cases that handler
1806 * may be working around hardware quirks such as not respecting r1b
1807 * busy indications. In those cases, this wait-loop serves the purpose
1808 * of waiting for the prior command and data transfers to be done, and
1809 * SD cards are allowed to take up to 250ms for write and erase ops.
1810 * (It's usually more like 20-30ms in the real world.)
1811 */
1812 timeout = 250;
1813 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1814 if (timeout == 0) {
1815 slot_printf(slot, "Controller never released "
1816 "inhibit bit(s).\n");
1817 sdhci_dumpregs(slot);
1818 cmd->error = MMC_ERR_FAILED;
1819 sdhci_req_done(slot);
1820 return;
1821 }
1822 timeout--;
1823 DELAY(1000);
1824 }
1825
1826 /* Prepare command flags. */
1827 if (!(cmd->flags & MMC_RSP_PRESENT))
1828 flags = SDHCI_CMD_RESP_NONE;
1829 else if (cmd->flags & MMC_RSP_136)
1830 flags = SDHCI_CMD_RESP_LONG;
1831 else if (cmd->flags & MMC_RSP_BUSY)
1832 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1833 else
1834 flags = SDHCI_CMD_RESP_SHORT;
1835 if (cmd->flags & MMC_RSP_CRC)
1836 flags |= SDHCI_CMD_CRC;
1837 if (cmd->flags & MMC_RSP_OPCODE)
1838 flags |= SDHCI_CMD_INDEX;
1839 if (cmd->data != NULL)
1840 flags |= SDHCI_CMD_DATA;
1841 if (cmd->opcode == MMC_STOP_TRANSMISSION)
1842 flags |= SDHCI_CMD_TYPE_ABORT;
1843 /* Prepare data. */
1844 sdhci_start_data(slot, cmd->data);
1845 /*
1846 * Interrupt aggregation: To reduce total number of interrupts
1847 * group response interrupt with data interrupt when possible.
1848 * If there going to be data interrupt, mask response one.
1849 */
1850 if (slot->data_done == 0) {
1851 WR4(slot, SDHCI_SIGNAL_ENABLE,
1852 slot->intmask &= ~SDHCI_INT_RESPONSE);
1853 }
1854 /* Set command argument. */
1855 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1856 /* Set data transfer mode. */
1857 sdhci_set_transfer_mode(slot, cmd->data);
1858 if (__predict_false(sdhci_debug > 1))
1859 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n",
1860 cmd->opcode, flags);
1861
1862 /* Start command. */
1863 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1864 /* Start timeout callout. */
1865 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1866 sdhci_timeout, slot);
1867 }
1868
1869 static void
1870 sdhci_finish_command(struct sdhci_slot *slot)
1871 {
1872 int i;
1873 uint32_t val;
1874 uint8_t extra;
1875
1876 if (__predict_false(sdhci_debug > 1))
1877 slot_printf(slot, "%s: called, err %d flags %#04x\n",
1878 __func__, slot->curcmd->error, slot->curcmd->flags);
1879 slot->cmd_done = 1;
1880 /*
1881 * Interrupt aggregation: Restore command interrupt.
1882 * Main restore point for the case when command interrupt
1883 * happened first.
1884 */
1885 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1886 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1887 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1888 SDHCI_INT_RESPONSE);
1889 /* In case of error - reset host and return. */
1890 if (slot->curcmd->error) {
1891 if (slot->curcmd->error == MMC_ERR_BADCRC)
1892 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1893 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
1894 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
1895 sdhci_start(slot);
1896 return;
1897 }
1898 /* If command has response - fetch it. */
1899 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1900 if (slot->curcmd->flags & MMC_RSP_136) {
1901 /* CRC is stripped so we need one byte shift. */
1902 extra = 0;
1903 for (i = 0; i < 4; i++) {
1904 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1905 if (slot->quirks &
1906 SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
1907 slot->curcmd->resp[3 - i] = val;
1908 else {
1909 slot->curcmd->resp[3 - i] =
1910 (val << 8) | extra;
1911 extra = val >> 24;
1912 }
1913 }
1914 } else
1915 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1916 }
1917 if (__predict_false(sdhci_debug > 1))
1918 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n",
1919 slot->curcmd->resp[0], slot->curcmd->resp[1],
1920 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1921
1922 /* If data ready - finish. */
1923 if (slot->data_done)
1924 sdhci_start(slot);
1925 }
1926
1927 static void
1928 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data)
1929 {
1930 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout;
1931 uint8_t div;
1932
1933 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1934 slot->data_done = 1;
1935 return;
1936 }
1937
1938 slot->data_done = 0;
1939
1940 /* Calculate and set data timeout.*/
1941 /* XXX: We should have this from mmc layer, now assume 1 sec. */
1942 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1943 div = 0xE;
1944 } else {
1945 target_timeout = 1000000;
1946 div = 0;
1947 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1948 while (current_timeout < target_timeout && div < 0xE) {
1949 ++div;
1950 current_timeout <<= 1;
1951 }
1952 /* Compensate for an off-by-one error in the CaFe chip.*/
1953 if (div < 0xE &&
1954 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1955 ++div;
1956 }
1957 }
1958 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1959
1960 if (data == NULL)
1961 return;
1962
1963 /* Use DMA if possible. */
1964 if ((slot->opt & SDHCI_HAVE_DMA))
1965 slot->flags |= SDHCI_USE_DMA;
1966 /* If data is small, broken DMA may return zeroes instead of data. */
1967 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1968 (data->len <= 512))
1969 slot->flags &= ~SDHCI_USE_DMA;
1970 /* Some controllers require even block sizes. */
1971 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1972 ((data->len) & 0x3))
1973 slot->flags &= ~SDHCI_USE_DMA;
1974 /* Load DMA buffer. */
1975 if (slot->flags & SDHCI_USE_DMA) {
1976 sdma_bbufsz = slot->sdma_bbufsz;
1977 if (data->flags & MMC_DATA_READ)
1978 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1979 BUS_DMASYNC_PREREAD);
1980 else {
1981 memcpy(slot->dmamem, data->data, ulmin(data->len,
1982 sdma_bbufsz));
1983 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1984 BUS_DMASYNC_PREWRITE);
1985 }
1986 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1987 /*
1988 * Interrupt aggregation: Mask border interrupt for the last
1989 * bounce buffer and unmask otherwise.
1990 */
1991 if (data->len == sdma_bbufsz)
1992 slot->intmask &= ~SDHCI_INT_DMA_END;
1993 else
1994 slot->intmask |= SDHCI_INT_DMA_END;
1995 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1996 }
1997 /* Current data offset for both PIO and DMA. */
1998 slot->offset = 0;
1999 #ifdef MMCCAM
2000 if (data->flags & MMC_DATA_BLOCK_SIZE) {
2001 /* Set block size and request border interrupts on the SDMA boundary. */
2002 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size);
2003 blkcnt = data->block_count;
2004 if (__predict_false(sdhci_debug > 0))
2005 slot_printf(slot, "SDIO Custom block params: blksz: "
2006 "%#10x, blk cnt: %#10x\n", blksz, blkcnt);
2007 } else
2008 #endif
2009 {
2010 /* Set block size and request border interrupts on the SDMA boundary. */
2011 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
2012 blkcnt = howmany(data->len, 512);
2013 }
2014
2015 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
2016 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
2017 if (__predict_false(sdhci_debug > 1))
2018 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
2019 blksz, blkcnt);
2020 }
2021
2022 void
2023 sdhci_finish_data(struct sdhci_slot *slot)
2024 {
2025 struct mmc_data *data = slot->curcmd->data;
2026 size_t left;
2027
2028 /* Interrupt aggregation: Restore command interrupt.
2029 * Auxiliary restore point for the case when data interrupt
2030 * happened first. */
2031 if (!slot->cmd_done) {
2032 WR4(slot, SDHCI_SIGNAL_ENABLE,
2033 slot->intmask |= SDHCI_INT_RESPONSE);
2034 }
2035 /* Unload rest of data from DMA buffer. */
2036 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
2037 slot->curcmd->data != NULL) {
2038 if (data->flags & MMC_DATA_READ) {
2039 left = data->len - slot->offset;
2040 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2041 BUS_DMASYNC_POSTREAD);
2042 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2043 ulmin(left, slot->sdma_bbufsz));
2044 } else
2045 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2046 BUS_DMASYNC_POSTWRITE);
2047 }
2048 slot->data_done = 1;
2049 /* If there was error - reset the host. */
2050 if (slot->curcmd->error) {
2051 if (slot->curcmd->error == MMC_ERR_BADCRC)
2052 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2053 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2054 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2055 sdhci_start(slot);
2056 return;
2057 }
2058 /* If we already have command response - finish. */
2059 if (slot->cmd_done)
2060 sdhci_start(slot);
2061 }
2062
2063 #ifdef MMCCAM
2064 static void
2065 sdhci_start(struct sdhci_slot *slot)
2066 {
2067 union ccb *ccb;
2068 struct ccb_mmcio *mmcio;
2069
2070 ccb = slot->ccb;
2071 if (ccb == NULL)
2072 return;
2073
2074 mmcio = &ccb->mmcio;
2075 if (!(slot->flags & CMD_STARTED)) {
2076 slot->flags |= CMD_STARTED;
2077 sdhci_start_command(slot, &mmcio->cmd);
2078 return;
2079 }
2080
2081 /*
2082 * Old stack doesn't use this!
2083 * Enabling this code causes significant performance degradation
2084 * and IRQ storms on BBB, Wandboard behaves fine.
2085 * Not using this code does no harm...
2086 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) {
2087 slot->flags |= STOP_STARTED;
2088 sdhci_start_command(slot, &mmcio->stop);
2089 return;
2090 }
2091 */
2092 if (__predict_false(sdhci_debug > 1))
2093 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
2094 if (mmcio->cmd.error == 0 &&
2095 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
2096 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2097 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2098 }
2099
2100 sdhci_req_done(slot);
2101 }
2102 #else
2103 static void
2104 sdhci_start(struct sdhci_slot *slot)
2105 {
2106 const struct mmc_request *req;
2107
2108 req = slot->req;
2109 if (req == NULL)
2110 return;
2111
2112 if (!(slot->flags & CMD_STARTED)) {
2113 slot->flags |= CMD_STARTED;
2114 sdhci_start_command(slot, req->cmd);
2115 return;
2116 }
2117 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
2118 !(slot->flags & STOP_STARTED) && req->stop) {
2119 slot->flags |= STOP_STARTED;
2120 sdhci_start_command(slot, req->stop);
2121 return;
2122 }
2123 if (__predict_false(sdhci_debug > 1))
2124 slot_printf(slot, "result: %d\n", req->cmd->error);
2125 if (!req->cmd->error &&
2126 ((slot->curcmd == req->stop &&
2127 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
2128 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2129 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2130 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2131 }
2132
2133 sdhci_req_done(slot);
2134 }
2135 #endif
2136
2137 int
2138 sdhci_generic_request(device_t brdev __unused, device_t reqdev,
2139 struct mmc_request *req)
2140 {
2141 struct sdhci_slot *slot = device_get_ivars(reqdev);
2142
2143 SDHCI_LOCK(slot);
2144 if (slot->req != NULL) {
2145 SDHCI_UNLOCK(slot);
2146 return (EBUSY);
2147 }
2148 if (__predict_false(sdhci_debug > 1)) {
2149 slot_printf(slot,
2150 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
2151 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
2152 (req->cmd->data)?(u_int)req->cmd->data->len:0,
2153 (req->cmd->data)?req->cmd->data->flags:0);
2154 }
2155 slot->req = req;
2156 slot->flags = 0;
2157 sdhci_start(slot);
2158 SDHCI_UNLOCK(slot);
2159 if (dumping) {
2160 while (slot->req != NULL) {
2161 sdhci_generic_intr(slot);
2162 DELAY(10);
2163 }
2164 }
2165 return (0);
2166 }
2167
2168 int
2169 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev)
2170 {
2171 struct sdhci_slot *slot = device_get_ivars(reqdev);
2172 uint32_t val;
2173
2174 SDHCI_LOCK(slot);
2175 val = RD4(slot, SDHCI_PRESENT_STATE);
2176 SDHCI_UNLOCK(slot);
2177 return (!(val & SDHCI_WRITE_PROTECT));
2178 }
2179
2180 int
2181 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev)
2182 {
2183 struct sdhci_slot *slot = device_get_ivars(reqdev);
2184 int err = 0;
2185
2186 SDHCI_LOCK(slot);
2187 /*
2188 * If the bus is busy at dump time, it may have stopped in the middle of
2189 * a transaction. Try to complete that transaction before continuing.
2190 */
2191 if (slot->bus_busy && dumping) {
2192 SDHCI_UNLOCK(slot);
2193 while (slot->req != NULL) {
2194 sdhci_generic_intr(slot);
2195 DELAY(10);
2196 }
2197 return (0);
2198 }
2199 while (slot->bus_busy)
2200 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
2201 slot->bus_busy++;
2202 /* Activate led. */
2203 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2204 SDHCI_UNLOCK(slot);
2205 return (err);
2206 }
2207
2208 int
2209 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev)
2210 {
2211 struct sdhci_slot *slot = device_get_ivars(reqdev);
2212
2213 SDHCI_LOCK(slot);
2214 /* Deactivate led. */
2215 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2216 slot->bus_busy--;
2217 wakeup(slot);
2218 SDHCI_UNLOCK(slot);
2219 return (0);
2220 }
2221
2222 static void
2223 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
2224 {
2225
2226 if (!slot->curcmd) {
2227 slot_printf(slot, "Got command interrupt 0x%08x, but "
2228 "there is no active command.\n", intmask);
2229 sdhci_dumpregs(slot);
2230 return;
2231 }
2232 if (intmask & SDHCI_INT_TIMEOUT)
2233 slot->curcmd->error = MMC_ERR_TIMEOUT;
2234 else if (intmask & SDHCI_INT_CRC)
2235 slot->curcmd->error = MMC_ERR_BADCRC;
2236 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
2237 slot->curcmd->error = MMC_ERR_FIFO;
2238
2239 sdhci_finish_command(slot);
2240 }
2241
2242 static void
2243 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
2244 {
2245 struct mmc_data *data;
2246 size_t left;
2247 uint32_t sdma_bbufsz;
2248
2249 if (!slot->curcmd) {
2250 slot_printf(slot, "Got data interrupt 0x%08x, but "
2251 "there is no active command.\n", intmask);
2252 sdhci_dumpregs(slot);
2253 return;
2254 }
2255 if (slot->curcmd->data == NULL &&
2256 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2257 slot_printf(slot, "Got data interrupt 0x%08x, but "
2258 "there is no active data operation.\n",
2259 intmask);
2260 sdhci_dumpregs(slot);
2261 return;
2262 }
2263 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2264 slot->curcmd->error = MMC_ERR_TIMEOUT;
2265 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
2266 slot->curcmd->error = MMC_ERR_BADCRC;
2267 if (slot->curcmd->data == NULL &&
2268 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2269 SDHCI_INT_DMA_END))) {
2270 slot_printf(slot, "Got data interrupt 0x%08x, but "
2271 "there is busy-only command.\n", intmask);
2272 sdhci_dumpregs(slot);
2273 slot->curcmd->error = MMC_ERR_INVALID;
2274 }
2275 if (slot->curcmd->error) {
2276 /* No need to continue after any error. */
2277 goto done;
2278 }
2279
2280 /* Handle tuning completion interrupt. */
2281 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) &&
2282 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2283 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2284 slot->req->flags |= MMC_TUNE_DONE;
2285 sdhci_finish_command(slot);
2286 sdhci_finish_data(slot);
2287 return;
2288 }
2289 /* Handle PIO interrupt. */
2290 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
2291 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2292 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2293 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2294 &intmask);
2295 slot->flags |= PLATFORM_DATA_STARTED;
2296 } else
2297 sdhci_transfer_pio(slot);
2298 }
2299 /* Handle DMA border. */
2300 if (intmask & SDHCI_INT_DMA_END) {
2301 data = slot->curcmd->data;
2302 sdma_bbufsz = slot->sdma_bbufsz;
2303
2304 /* Unload DMA buffer ... */
2305 left = data->len - slot->offset;
2306 if (data->flags & MMC_DATA_READ) {
2307 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2308 BUS_DMASYNC_POSTREAD);
2309 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2310 ulmin(left, sdma_bbufsz));
2311 } else {
2312 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2313 BUS_DMASYNC_POSTWRITE);
2314 }
2315 /* ... and reload it again. */
2316 slot->offset += sdma_bbufsz;
2317 left = data->len - slot->offset;
2318 if (data->flags & MMC_DATA_READ) {
2319 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2320 BUS_DMASYNC_PREREAD);
2321 } else {
2322 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2323 ulmin(left, sdma_bbufsz));
2324 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2325 BUS_DMASYNC_PREWRITE);
2326 }
2327 /*
2328 * Interrupt aggregation: Mask border interrupt for the last
2329 * bounce buffer.
2330 */
2331 if (left == sdma_bbufsz) {
2332 slot->intmask &= ~SDHCI_INT_DMA_END;
2333 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2334 }
2335 /* Restart DMA. */
2336 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2337 }
2338 /* We have got all data. */
2339 if (intmask & SDHCI_INT_DATA_END) {
2340 if (slot->flags & PLATFORM_DATA_STARTED) {
2341 slot->flags &= ~PLATFORM_DATA_STARTED;
2342 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2343 } else
2344 sdhci_finish_data(slot);
2345 }
2346 done:
2347 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2348 if (slot->flags & PLATFORM_DATA_STARTED) {
2349 slot->flags &= ~PLATFORM_DATA_STARTED;
2350 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2351 } else
2352 sdhci_finish_data(slot);
2353 }
2354 }
2355
2356 static void
2357 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
2358 {
2359
2360 if (!slot->curcmd) {
2361 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2362 "there is no active command.\n", acmd_err);
2363 sdhci_dumpregs(slot);
2364 return;
2365 }
2366 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2367 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2368 }
2369
2370 void
2371 sdhci_generic_intr(struct sdhci_slot *slot)
2372 {
2373 uint32_t intmask, present;
2374 uint16_t val16;
2375
2376 SDHCI_LOCK(slot);
2377 /* Read slot interrupt status. */
2378 intmask = RD4(slot, SDHCI_INT_STATUS);
2379 if (intmask == 0 || intmask == 0xffffffff) {
2380 SDHCI_UNLOCK(slot);
2381 return;
2382 }
2383 if (__predict_false(sdhci_debug > 2))
2384 slot_printf(slot, "Interrupt %#x\n", intmask);
2385
2386 /* Handle tuning error interrupt. */
2387 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) {
2388 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2389 slot_printf(slot, "Tuning error indicated\n");
2390 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2391 if (slot->curcmd) {
2392 slot->curcmd->error = MMC_ERR_BADCRC;
2393 sdhci_finish_command(slot);
2394 }
2395 }
2396 /* Handle re-tuning interrupt. */
2397 if (__predict_false(intmask & SDHCI_INT_RETUNE))
2398 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2399 /* Handle card presence interrupts. */
2400 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2401 present = (intmask & SDHCI_INT_CARD_INSERT) != 0;
2402 slot->intmask &=
2403 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2404 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2405 SDHCI_INT_CARD_INSERT;
2406 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2407 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2408 WR4(slot, SDHCI_INT_STATUS, intmask &
2409 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
2410 sdhci_handle_card_present_locked(slot, present);
2411 }
2412 /* Handle command interrupts. */
2413 if (intmask & SDHCI_INT_CMD_MASK) {
2414 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2415 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2416 }
2417 /* Handle data interrupts. */
2418 if (intmask & SDHCI_INT_DATA_MASK) {
2419 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2420 /* Don't call data_irq in case of errored command. */
2421 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
2422 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2423 }
2424 /* Handle AutoCMD12 error interrupt. */
2425 if (intmask & SDHCI_INT_ACMD12ERR) {
2426 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */
2427 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2428 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2429 sdhci_acmd_irq(slot, val16);
2430 }
2431 /* Handle bus power interrupt. */
2432 if (intmask & SDHCI_INT_BUS_POWER) {
2433 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2434 slot_printf(slot, "Card is consuming too much power!\n");
2435 }
2436 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE |
2437 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK |
2438 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER);
2439 /* The rest is unknown. */
2440 if (intmask) {
2441 WR4(slot, SDHCI_INT_STATUS, intmask);
2442 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2443 intmask);
2444 sdhci_dumpregs(slot);
2445 }
2446
2447 SDHCI_UNLOCK(slot);
2448 }
2449
2450 int
2451 sdhci_generic_read_ivar(device_t bus, device_t child, int which,
2452 uintptr_t *result)
2453 {
2454 const struct sdhci_slot *slot = device_get_ivars(child);
2455
2456 switch (which) {
2457 default:
2458 return (EINVAL);
2459 case MMCBR_IVAR_BUS_MODE:
2460 *result = slot->host.ios.bus_mode;
2461 break;
2462 case MMCBR_IVAR_BUS_WIDTH:
2463 *result = slot->host.ios.bus_width;
2464 break;
2465 case MMCBR_IVAR_CHIP_SELECT:
2466 *result = slot->host.ios.chip_select;
2467 break;
2468 case MMCBR_IVAR_CLOCK:
2469 *result = slot->host.ios.clock;
2470 break;
2471 case MMCBR_IVAR_F_MIN:
2472 *result = slot->host.f_min;
2473 break;
2474 case MMCBR_IVAR_F_MAX:
2475 *result = slot->host.f_max;
2476 break;
2477 case MMCBR_IVAR_HOST_OCR:
2478 *result = slot->host.host_ocr;
2479 break;
2480 case MMCBR_IVAR_MODE:
2481 *result = slot->host.mode;
2482 break;
2483 case MMCBR_IVAR_OCR:
2484 *result = slot->host.ocr;
2485 break;
2486 case MMCBR_IVAR_POWER_MODE:
2487 *result = slot->host.ios.power_mode;
2488 break;
2489 case MMCBR_IVAR_VDD:
2490 *result = slot->host.ios.vdd;
2491 break;
2492 case MMCBR_IVAR_RETUNE_REQ:
2493 if (slot->opt & SDHCI_TUNING_ENABLED) {
2494 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2495 *result = retune_req_reset;
2496 break;
2497 }
2498 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2499 *result = retune_req_normal;
2500 break;
2501 }
2502 }
2503 *result = retune_req_none;
2504 break;
2505 case MMCBR_IVAR_VCCQ:
2506 *result = slot->host.ios.vccq;
2507 break;
2508 case MMCBR_IVAR_CAPS:
2509 *result = slot->host.caps;
2510 break;
2511 case MMCBR_IVAR_TIMING:
2512 *result = slot->host.ios.timing;
2513 break;
2514 case MMCBR_IVAR_MAX_DATA:
2515 /*
2516 * Re-tuning modes 1 and 2 restrict the maximum data length
2517 * per read/write command to 4 MiB.
2518 */
2519 if (slot->opt & SDHCI_TUNING_ENABLED &&
2520 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2521 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2522 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2523 break;
2524 }
2525 *result = 65535;
2526 break;
2527 case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
2528 /*
2529 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs.
2530 */
2531 *result = 1000000;
2532 break;
2533 }
2534 return (0);
2535 }
2536
2537 int
2538 sdhci_generic_write_ivar(device_t bus, device_t child, int which,
2539 uintptr_t value)
2540 {
2541 struct sdhci_slot *slot = device_get_ivars(child);
2542 uint32_t clock, max_clock;
2543 int i;
2544
2545 if (sdhci_debug > 1)
2546 slot_printf(slot, "%s: var=%d\n", __func__, which);
2547 switch (which) {
2548 default:
2549 return (EINVAL);
2550 case MMCBR_IVAR_BUS_MODE:
2551 slot->host.ios.bus_mode = value;
2552 break;
2553 case MMCBR_IVAR_BUS_WIDTH:
2554 slot->host.ios.bus_width = value;
2555 break;
2556 case MMCBR_IVAR_CHIP_SELECT:
2557 slot->host.ios.chip_select = value;
2558 break;
2559 case MMCBR_IVAR_CLOCK:
2560 if (value > 0) {
2561 max_clock = slot->max_clk;
2562 clock = max_clock;
2563
2564 if (slot->version < SDHCI_SPEC_300) {
2565 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
2566 i <<= 1) {
2567 if (clock <= value)
2568 break;
2569 clock >>= 1;
2570 }
2571 } else {
2572 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
2573 i += 2) {
2574 if (clock <= value)
2575 break;
2576 clock = max_clock / (i + 2);
2577 }
2578 }
2579
2580 slot->host.ios.clock = clock;
2581 } else
2582 slot->host.ios.clock = 0;
2583 break;
2584 case MMCBR_IVAR_MODE:
2585 slot->host.mode = value;
2586 break;
2587 case MMCBR_IVAR_OCR:
2588 slot->host.ocr = value;
2589 break;
2590 case MMCBR_IVAR_POWER_MODE:
2591 slot->host.ios.power_mode = value;
2592 break;
2593 case MMCBR_IVAR_VDD:
2594 slot->host.ios.vdd = value;
2595 break;
2596 case MMCBR_IVAR_VCCQ:
2597 slot->host.ios.vccq = value;
2598 break;
2599 case MMCBR_IVAR_TIMING:
2600 slot->host.ios.timing = value;
2601 break;
2602 case MMCBR_IVAR_CAPS:
2603 case MMCBR_IVAR_HOST_OCR:
2604 case MMCBR_IVAR_F_MIN:
2605 case MMCBR_IVAR_F_MAX:
2606 case MMCBR_IVAR_MAX_DATA:
2607 case MMCBR_IVAR_RETUNE_REQ:
2608 return (EINVAL);
2609 }
2610 return (0);
2611 }
2612
2613 #ifdef MMCCAM
2614 void
2615 sdhci_start_slot(struct sdhci_slot *slot)
2616 {
2617
2618 if ((slot->devq = cam_simq_alloc(1)) == NULL)
2619 goto fail;
2620
2621 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2622 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2623 "sdhci_slot", slot, device_get_unit(slot->bus),
2624 &slot->sim_mtx, 1, 1, slot->devq);
2625
2626 if (slot->sim == NULL) {
2627 cam_simq_free(slot->devq);
2628 slot_printf(slot, "cannot allocate CAM SIM\n");
2629 goto fail;
2630 }
2631
2632 mtx_lock(&slot->sim_mtx);
2633 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2634 slot_printf(slot, "cannot register SCSI pass-through bus\n");
2635 cam_sim_free(slot->sim, FALSE);
2636 cam_simq_free(slot->devq);
2637 mtx_unlock(&slot->sim_mtx);
2638 goto fail;
2639 }
2640 mtx_unlock(&slot->sim_mtx);
2641
2642 /* End CAM-specific init */
2643 slot->card_present = 0;
2644 sdhci_card_task(slot, 0);
2645 return;
2646
2647 fail:
2648 if (slot->sim != NULL) {
2649 mtx_lock(&slot->sim_mtx);
2650 xpt_bus_deregister(cam_sim_path(slot->sim));
2651 cam_sim_free(slot->sim, FALSE);
2652 mtx_unlock(&slot->sim_mtx);
2653 }
2654
2655 if (slot->devq != NULL)
2656 cam_simq_free(slot->devq);
2657 }
2658
2659 void
2660 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb)
2661 {
2662 struct sdhci_slot *slot;
2663
2664 slot = cam_sim_softc(sim);
2665 if (slot == NULL) {
2666 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2667 xpt_done(ccb);
2668 return;
2669 }
2670
2671 mtx_assert(&slot->sim_mtx, MA_OWNED);
2672
2673 switch (ccb->ccb_h.func_code) {
2674 case XPT_PATH_INQ:
2675 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, maxphys);
2676 break;
2677
2678 case XPT_MMC_GET_TRAN_SETTINGS:
2679 case XPT_GET_TRAN_SETTINGS:
2680 {
2681 struct ccb_trans_settings *cts = &ccb->cts;
2682 uint32_t max_data;
2683
2684 if (sdhci_debug > 1)
2685 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2686
2687 cts->protocol = PROTO_MMCSD;
2688 cts->protocol_version = 1;
2689 cts->transport = XPORT_MMCSD;
2690 cts->transport_version = 1;
2691 cts->xport_specific.valid = 0;
2692 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2693 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2694 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2695 cts->proto_specific.mmc.host_caps = slot->host.caps;
2696 /*
2697 * Re-tuning modes 1 and 2 restrict the maximum data length
2698 * per read/write command to 4 MiB.
2699 */
2700 if (slot->opt & SDHCI_TUNING_ENABLED &&
2701 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2702 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2703 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE;
2704 } else {
2705 max_data = 65535;
2706 }
2707 cts->proto_specific.mmc.host_max_data = max_data;
2708
2709 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2710 ccb->ccb_h.status = CAM_REQ_CMP;
2711 break;
2712 }
2713 case XPT_MMC_SET_TRAN_SETTINGS:
2714 case XPT_SET_TRAN_SETTINGS:
2715 if (sdhci_debug > 1)
2716 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2717 sdhci_cam_settran_settings(slot, ccb);
2718 ccb->ccb_h.status = CAM_REQ_CMP;
2719 break;
2720 case XPT_RESET_BUS:
2721 if (sdhci_debug > 1)
2722 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2723 ccb->ccb_h.status = CAM_REQ_CMP;
2724 break;
2725 case XPT_MMC_IO:
2726 /*
2727 * Here is the HW-dependent part of
2728 * sending the command to the underlying h/w
2729 * At some point in the future an interrupt comes.
2730 * Then the request will be marked as completed.
2731 */
2732 if (__predict_false(sdhci_debug > 1))
2733 slot_printf(slot, "Got XPT_MMC_IO\n");
2734 ccb->ccb_h.status = CAM_REQ_INPROG;
2735
2736 sdhci_cam_request(cam_sim_softc(sim), ccb);
2737 return;
2738 default:
2739 ccb->ccb_h.status = CAM_REQ_INVALID;
2740 break;
2741 }
2742 xpt_done(ccb);
2743 return;
2744 }
2745
2746 void
2747 sdhci_cam_poll(struct cam_sim *sim)
2748 {
2749 sdhci_generic_intr(cam_sim_softc(sim));
2750 }
2751
2752 static int
2753 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
2754 int proposed_clock)
2755 {
2756 int max_clock, clock, i;
2757
2758 if (proposed_clock == 0)
2759 return 0;
2760 max_clock = slot->max_clk;
2761 clock = max_clock;
2762
2763 if (slot->version < SDHCI_SPEC_300) {
2764 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) {
2765 if (clock <= proposed_clock)
2766 break;
2767 clock >>= 1;
2768 }
2769 } else {
2770 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) {
2771 if (clock <= proposed_clock)
2772 break;
2773 clock = max_clock / (i + 2);
2774 }
2775 }
2776 return clock;
2777 }
2778
2779 static int
2780 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb)
2781 {
2782 struct mmc_ios *ios;
2783 const struct mmc_ios *new_ios;
2784 const struct ccb_trans_settings_mmc *cts;
2785
2786 ios = &slot->host.ios;
2787 cts = &ccb->cts.proto_specific.mmc;
2788 new_ios = &cts->ios;
2789
2790 /* Update only requested fields */
2791 if (cts->ios_valid & MMC_CLK) {
2792 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2793 if (sdhci_debug > 1)
2794 slot_printf(slot, "Clock => %d\n", ios->clock);
2795 }
2796 if (cts->ios_valid & MMC_VDD) {
2797 ios->vdd = new_ios->vdd;
2798 if (sdhci_debug > 1)
2799 slot_printf(slot, "VDD => %d\n", ios->vdd);
2800 }
2801 if (cts->ios_valid & MMC_CS) {
2802 ios->chip_select = new_ios->chip_select;
2803 if (sdhci_debug > 1)
2804 slot_printf(slot, "CS => %d\n", ios->chip_select);
2805 }
2806 if (cts->ios_valid & MMC_BW) {
2807 ios->bus_width = new_ios->bus_width;
2808 if (sdhci_debug > 1)
2809 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2810 }
2811 if (cts->ios_valid & MMC_PM) {
2812 ios->power_mode = new_ios->power_mode;
2813 if (sdhci_debug > 1)
2814 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2815 }
2816 if (cts->ios_valid & MMC_BT) {
2817 ios->timing = new_ios->timing;
2818 if (sdhci_debug > 1)
2819 slot_printf(slot, "Timing => %d\n", ios->timing);
2820 }
2821 if (cts->ios_valid & MMC_BM) {
2822 ios->bus_mode = new_ios->bus_mode;
2823 if (sdhci_debug > 1)
2824 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2825 }
2826 if (cts->ios_valid & MMC_VCCQ) {
2827 ios->vccq = new_ios->vccq;
2828 if (sdhci_debug > 1)
2829 slot_printf(slot, "VCCQ => %d\n", ios->vccq);
2830 }
2831
2832 /* XXX Provide a way to call a chip-specific IOS update, required for TI */
2833 return (sdhci_cam_update_ios(slot));
2834 }
2835
2836 static int
2837 sdhci_cam_update_ios(struct sdhci_slot *slot)
2838 {
2839 struct mmc_ios *ios = &slot->host.ios;
2840
2841 if (sdhci_debug > 1)
2842 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2843 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
2844 SDHCI_LOCK(slot);
2845 /* Do full reset on bus power down to clear from any state. */
2846 if (ios->power_mode == power_off) {
2847 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2848 sdhci_init(slot);
2849 }
2850 /* Configure the bus. */
2851 sdhci_set_clock(slot, ios->clock);
2852 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2853 if (ios->bus_width == bus_width_8) {
2854 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2855 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2856 } else if (ios->bus_width == bus_width_4) {
2857 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2858 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2859 } else if (ios->bus_width == bus_width_1) {
2860 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2861 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2862 } else {
2863 panic("Invalid bus width: %d", ios->bus_width);
2864 }
2865 if (ios->timing == bus_timing_hs &&
2866 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2867 slot->hostctrl |= SDHCI_CTRL_HISPD;
2868 else
2869 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2870 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2871 /* Some controllers like reset after bus changes. */
2872 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2873 SDHCI_RESET(slot->bus, slot,
2874 SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2875
2876 SDHCI_UNLOCK(slot);
2877 return (0);
2878 }
2879
2880 static int
2881 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb)
2882 {
2883 const struct ccb_mmcio *mmcio;
2884
2885 mmcio = &ccb->mmcio;
2886
2887 SDHCI_LOCK(slot);
2888 /* if (slot->req != NULL) {
2889 SDHCI_UNLOCK(slot);
2890 return (EBUSY);
2891 }
2892 */
2893 if (__predict_false(sdhci_debug > 1)) {
2894 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x "
2895 "blksz=%zu blkcnt=%zu\n",
2896 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
2897 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
2898 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0,
2899 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0,
2900 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0);
2901 }
2902 if (mmcio->cmd.data != NULL) {
2903 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
2904 panic("data->len = %d, data->flags = %d -- something is b0rked",
2905 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
2906 }
2907 slot->ccb = ccb;
2908 slot->flags = 0;
2909 sdhci_start(slot);
2910 SDHCI_UNLOCK(slot);
2911 return (0);
2912 }
2913 #endif /* MMCCAM */
2914
2915 MODULE_VERSION(sdhci, SDHCI_VERSION);
2916