1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
10 #include <linux/debugfs.h>
11 #include <linux/of_address.h>
12 #include <linux/uaccess.h>
13
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_of.h>
18
19 #include "msm_drv.h"
20 #include "msm_debugfs.h"
21 #include "msm_gem.h"
22 #include "msm_gpu.h"
23 #include "msm_kms.h"
24
25 /*
26 * MSM driver version:
27 * - 1.0.0 - initial interface
28 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
29 * - 1.2.0 - adds explicit fence support for submit ioctl
30 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
31 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
32 * MSM_GEM_INFO ioctl.
33 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
34 * GEM object's debug name
35 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
36 * - 1.6.0 - Syncobj support
37 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
38 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
39 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
40 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
41 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)
42 * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA
43 * - 1.13.0 - Add VM_BIND
44 */
45 #define MSM_VERSION_MAJOR 1
46 #define MSM_VERSION_MINOR 13
47 #define MSM_VERSION_PATCHLEVEL 0
48
49 bool dumpstate;
50 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
51 module_param(dumpstate, bool, 0600);
52
53 static bool modeset = true;
54 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
55 module_param(modeset, bool, 0600);
56
57 static bool separate_gpu_kms;
58 MODULE_PARM_DESC(separate_gpu_kms, "Use separate DRM device for the GPU (0=single DRM device for both GPU and display (default), 1=two DRM devices)");
59 module_param(separate_gpu_kms, bool, 0400);
60
61 DECLARE_FAULT_ATTR(fail_gem_alloc);
62 DECLARE_FAULT_ATTR(fail_gem_iova);
63
msm_gpu_no_components(void)64 bool msm_gpu_no_components(void)
65 {
66 return separate_gpu_kms;
67 }
68
msm_drm_uninit(struct device * dev,const struct component_ops * gpu_ops)69 static int msm_drm_uninit(struct device *dev, const struct component_ops *gpu_ops)
70 {
71 struct platform_device *pdev = to_platform_device(dev);
72 struct msm_drm_private *priv = platform_get_drvdata(pdev);
73 struct drm_device *ddev = priv->dev;
74
75 /*
76 * Shutdown the hw if we're far enough along where things might be on.
77 * If we run this too early, we'll end up panicking in any variety of
78 * places. Since we don't register the drm device until late in
79 * msm_drm_init, drm_dev->registered is used as an indicator that the
80 * shutdown will be successful.
81 */
82 if (ddev->registered) {
83 drm_dev_unregister(ddev);
84 if (priv->kms)
85 msm_drm_kms_unregister(dev);
86 }
87
88 msm_gem_shrinker_cleanup(ddev);
89
90 msm_rd_debugfs_cleanup(priv);
91
92 if (priv->kms)
93 msm_drm_kms_uninit(dev);
94
95 if (gpu_ops)
96 gpu_ops->unbind(dev, dev, NULL);
97 else
98 component_unbind_all(dev, ddev);
99
100 ddev->dev_private = NULL;
101 drm_dev_put(ddev);
102
103 return 0;
104 }
105
msm_drm_init(struct device * dev,const struct drm_driver * drv,const struct component_ops * gpu_ops)106 static int msm_drm_init(struct device *dev, const struct drm_driver *drv,
107 const struct component_ops *gpu_ops)
108 {
109 struct msm_drm_private *priv = dev_get_drvdata(dev);
110 struct drm_device *ddev;
111 int ret;
112
113 if (drm_firmware_drivers_only())
114 return -ENODEV;
115
116 ddev = drm_dev_alloc(drv, dev);
117 if (IS_ERR(ddev)) {
118 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
119 return PTR_ERR(ddev);
120 }
121 ddev->dev_private = priv;
122 priv->dev = ddev;
123
124 INIT_LIST_HEAD(&priv->objects);
125 mutex_init(&priv->obj_lock);
126
127 /*
128 * Initialize the LRUs:
129 */
130 drm_gem_lru_init(&priv->lru.unbacked);
131 drm_gem_lru_init(&priv->lru.pinned);
132 drm_gem_lru_init(&priv->lru.willneed);
133 drm_gem_lru_init(&priv->lru.dontneed);
134
135 /* Initialize stall-on-fault */
136 spin_lock_init(&priv->fault_stall_lock);
137 priv->stall_enabled = true;
138
139 /* Teach lockdep about lock ordering wrt. shrinker: */
140 fs_reclaim_acquire(GFP_KERNEL);
141 might_lock(&ddev->gem_lru_mutex);
142 fs_reclaim_release(GFP_KERNEL);
143
144 if (priv->kms_init) {
145 ret = drmm_mode_config_init(ddev);
146 if (ret)
147 goto err_put_dev;
148 }
149
150 dma_set_max_seg_size(dev, UINT_MAX);
151
152 /* Bind all our sub-components: */
153 if (gpu_ops)
154 ret = gpu_ops->bind(dev, dev, NULL);
155 else
156 ret = component_bind_all(dev, ddev);
157 if (ret)
158 goto err_put_dev;
159
160 ret = msm_gem_shrinker_init(ddev);
161 if (ret)
162 goto err_msm_uninit;
163
164 if (priv->kms_init) {
165 ret = msm_drm_kms_init(dev, drv);
166 if (ret)
167 goto err_msm_uninit;
168 }
169
170 ret = drm_dev_register(ddev, 0);
171 if (ret)
172 goto err_msm_uninit;
173
174 ret = msm_debugfs_late_init(ddev);
175 if (ret)
176 goto err_msm_uninit;
177
178 if (priv->kms_init)
179 msm_drm_kms_post_init(dev);
180
181 return 0;
182
183 err_msm_uninit:
184 msm_drm_uninit(dev, gpu_ops);
185
186 return ret;
187
188 err_put_dev:
189 drm_dev_put(ddev);
190
191 return ret;
192 }
193
194 /*
195 * DRM operations:
196 */
197
load_gpu(struct drm_device * dev)198 static void load_gpu(struct drm_device *dev)
199 {
200 static DEFINE_MUTEX(init_lock);
201 struct msm_drm_private *priv = dev->dev_private;
202
203 mutex_lock(&init_lock);
204
205 if (!priv->gpu)
206 priv->gpu = adreno_load_gpu(dev);
207
208 mutex_unlock(&init_lock);
209 }
210
211 /**
212 * msm_context_vm - lazily create the context's VM
213 *
214 * @dev: the drm device
215 * @ctx: the context
216 *
217 * The VM is lazily created, so that userspace has a chance to opt-in to having
218 * a userspace managed VM before the VM is created.
219 *
220 * Note that this does not return a reference to the VM. Once the VM is created,
221 * it exists for the lifetime of the context.
222 */
msm_context_vm(struct drm_device * dev,struct msm_context * ctx)223 struct drm_gpuvm *msm_context_vm(struct drm_device *dev, struct msm_context *ctx)
224 {
225 struct msm_drm_private *priv = dev->dev_private;
226 struct drm_gpuvm *vm = smp_load_acquire(&ctx->vm);
227
228 /* Once ctx->vm is created it is valid for the lifetime of the context: */
229 if (vm)
230 return vm;
231
232 guard(rwsem_write)(&ctx->ctxlock);
233
234 if (!ctx->vm) {
235 vm = msm_gpu_create_private_vm(
236 priv->gpu, current, !ctx->userspace_managed_vm);
237 if (!IS_ERR_OR_NULL(vm))
238 smp_store_release(&ctx->vm, vm);
239 }
240
241 return ctx->vm;
242 }
243
context_init(struct drm_device * dev,struct drm_file * file)244 static int context_init(struct drm_device *dev, struct drm_file *file)
245 {
246 static atomic_t ident = ATOMIC_INIT(0);
247 struct msm_context *ctx;
248
249 ctx = kzalloc_obj(*ctx);
250 if (!ctx)
251 return -ENOMEM;
252
253 INIT_LIST_HEAD(&ctx->submitqueues);
254 init_rwsem(&ctx->ctxlock);
255
256 kref_init(&ctx->ref);
257 msm_submitqueue_init(dev, ctx);
258
259 file->driver_priv = ctx;
260
261 ctx->seqno = atomic_inc_return(&ident);
262
263 return 0;
264 }
265
msm_open(struct drm_device * dev,struct drm_file * file)266 static int msm_open(struct drm_device *dev, struct drm_file *file)
267 {
268 /* For now, load gpu on open.. to avoid the requirement of having
269 * firmware in the initrd.
270 */
271 load_gpu(dev);
272
273 return context_init(dev, file);
274 }
275
context_close(struct msm_context * ctx)276 static void context_close(struct msm_context *ctx)
277 {
278 ctx->closed = true;
279 msm_submitqueue_close(ctx);
280 msm_context_put(ctx);
281 }
282
msm_postclose(struct drm_device * dev,struct drm_file * file)283 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
284 {
285 struct msm_drm_private *priv = dev->dev_private;
286 struct msm_context *ctx = file->driver_priv;
287
288 /*
289 * It is not possible to set sysprof param to non-zero if gpu
290 * is not initialized:
291 */
292 if (priv->gpu)
293 msm_context_set_sysprof(ctx, priv->gpu, 0);
294
295 context_close(ctx);
296 }
297
298 /*
299 * DRM ioctls:
300 */
301
msm_ioctl_get_param(struct drm_device * dev,void * data,struct drm_file * file)302 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
303 struct drm_file *file)
304 {
305 struct msm_drm_private *priv = dev->dev_private;
306 struct drm_msm_param *args = data;
307 struct msm_gpu *gpu;
308
309 /* for now, we just have 3d pipe.. eventually this would need to
310 * be more clever to dispatch to appropriate gpu module:
311 */
312 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
313 return -EINVAL;
314
315 gpu = priv->gpu;
316
317 if (!gpu)
318 return -ENXIO;
319
320 return gpu->funcs->get_param(gpu, file->driver_priv,
321 args->param, &args->value, &args->len);
322 }
323
msm_ioctl_set_param(struct drm_device * dev,void * data,struct drm_file * file)324 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
325 struct drm_file *file)
326 {
327 struct msm_drm_private *priv = dev->dev_private;
328 struct drm_msm_param *args = data;
329 struct msm_gpu *gpu;
330
331 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
332 return -EINVAL;
333
334 gpu = priv->gpu;
335
336 if (!gpu)
337 return -ENXIO;
338
339 return gpu->funcs->set_param(gpu, file->driver_priv,
340 args->param, args->value, args->len);
341 }
342
msm_ioctl_gem_new(struct drm_device * dev,void * data,struct drm_file * file)343 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
344 struct drm_file *file)
345 {
346 struct drm_msm_gem_new *args = data;
347 uint32_t flags = args->flags;
348
349 if (args->flags & ~MSM_BO_FLAGS) {
350 DRM_ERROR("invalid flags: %08x\n", args->flags);
351 return -EINVAL;
352 }
353
354 /*
355 * Uncached CPU mappings are deprecated, as of:
356 *
357 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
358 *
359 * So promote them to WC.
360 */
361 if (flags & MSM_BO_UNCACHED) {
362 flags &= ~MSM_BO_CACHED;
363 flags |= MSM_BO_WC;
364 }
365
366 if (should_fail(&fail_gem_alloc, args->size))
367 return -ENOMEM;
368
369 return msm_gem_new_handle(dev, file, args->size,
370 args->flags, &args->handle, NULL);
371 }
372
to_ktime(struct drm_msm_timespec timeout)373 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
374 {
375 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
376 }
377
msm_ioctl_gem_cpu_prep(struct drm_device * dev,void * data,struct drm_file * file)378 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
379 struct drm_file *file)
380 {
381 struct drm_msm_gem_cpu_prep *args = data;
382 struct drm_gem_object *obj;
383 ktime_t timeout = to_ktime(args->timeout);
384 int ret;
385
386 if (args->op & ~MSM_PREP_FLAGS) {
387 DRM_ERROR("invalid op: %08x\n", args->op);
388 return -EINVAL;
389 }
390
391 obj = drm_gem_object_lookup(file, args->handle);
392 if (!obj)
393 return -ENOENT;
394
395 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
396
397 drm_gem_object_put(obj);
398
399 return ret;
400 }
401
msm_ioctl_gem_cpu_fini(struct drm_device * dev,void * data,struct drm_file * file)402 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
403 struct drm_file *file)
404 {
405 struct drm_msm_gem_cpu_fini *args = data;
406 struct drm_gem_object *obj;
407 int ret;
408
409 obj = drm_gem_object_lookup(file, args->handle);
410 if (!obj)
411 return -ENOENT;
412
413 ret = msm_gem_cpu_fini(obj);
414
415 drm_gem_object_put(obj);
416
417 return ret;
418 }
419
msm_ioctl_gem_info_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t * iova)420 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
421 struct drm_file *file, struct drm_gem_object *obj,
422 uint64_t *iova)
423 {
424 struct msm_drm_private *priv = dev->dev_private;
425 struct msm_context *ctx = file->driver_priv;
426 struct drm_gpuvm *vm = msm_context_vm(dev, ctx);
427
428 if (!priv->gpu)
429 return -EINVAL;
430
431 if (!vm)
432 return UERR(ENOMEM, dev, "no VM");
433
434 if (msm_context_is_vmbind(ctx))
435 return UERR(EINVAL, dev, "VM_BIND is enabled");
436
437 if (should_fail(&fail_gem_iova, obj->size))
438 return -ENOMEM;
439
440 /*
441 * Don't pin the memory here - just get an address so that userspace can
442 * be productive
443 */
444 return msm_gem_get_iova(obj, vm, iova);
445 }
446
msm_ioctl_gem_info_set_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t iova)447 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
448 struct drm_file *file, struct drm_gem_object *obj,
449 uint64_t iova)
450 {
451 struct msm_drm_private *priv = dev->dev_private;
452 struct msm_context *ctx = file->driver_priv;
453 struct drm_gpuvm *vm = msm_context_vm(dev, ctx);
454
455 if (!priv->gpu)
456 return -EINVAL;
457
458 if (!vm)
459 return UERR(ENOMEM, dev, "no VM");
460
461 if (msm_context_is_vmbind(ctx))
462 return UERR(EINVAL, dev, "VM_BIND is enabled");
463
464 /* Only supported if per-process address space is supported: */
465 if (priv->gpu->vm == vm)
466 return UERR(EOPNOTSUPP, dev, "requires per-process pgtables");
467
468 if (should_fail(&fail_gem_iova, obj->size))
469 return -ENOMEM;
470
471 return msm_gem_set_iova(obj, vm, iova);
472 }
473
msm_ioctl_gem_info_set_metadata(struct drm_gem_object * obj,__user void * metadata,u32 metadata_size)474 static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,
475 __user void *metadata,
476 u32 metadata_size)
477 {
478 struct msm_gem_object *msm_obj = to_msm_bo(obj);
479 void *new_metadata;
480 void *buf;
481 int ret;
482
483 /* Impose a moderate upper bound on metadata size: */
484 if (metadata_size > 128) {
485 return -EOVERFLOW;
486 }
487
488 /* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */
489 buf = memdup_user(metadata, metadata_size);
490 if (IS_ERR(buf))
491 return PTR_ERR(buf);
492
493 ret = msm_gem_lock_interruptible(obj);
494 if (ret)
495 goto out;
496
497 new_metadata =
498 krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL);
499 if (!new_metadata) {
500 ret = -ENOMEM;
501 goto out;
502 }
503
504 msm_obj->metadata = new_metadata;
505 msm_obj->metadata_size = metadata_size;
506 memcpy(msm_obj->metadata, buf, metadata_size);
507
508 msm_gem_unlock(obj);
509
510 out:
511 kfree(buf);
512
513 return ret;
514 }
515
msm_ioctl_gem_info_get_metadata(struct drm_gem_object * obj,__user void * metadata,u32 * metadata_size)516 static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj,
517 __user void *metadata,
518 u32 *metadata_size)
519 {
520 struct msm_gem_object *msm_obj = to_msm_bo(obj);
521 void *buf;
522 int ret, len;
523
524 if (!metadata) {
525 /*
526 * Querying the size is inherently racey, but
527 * EXT_external_objects expects the app to confirm
528 * via device and driver UUIDs that the exporter and
529 * importer versions match. All we can do from the
530 * kernel side is check the length under obj lock
531 * when userspace tries to retrieve the metadata
532 */
533 *metadata_size = msm_obj->metadata_size;
534 return 0;
535 }
536
537 ret = msm_gem_lock_interruptible(obj);
538 if (ret)
539 return ret;
540
541 /* Avoid copy_to_user() under gem obj lock: */
542 len = msm_obj->metadata_size;
543 buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL);
544
545 if (!buf) {
546 msm_gem_unlock(obj);
547 return -ENOMEM;
548 }
549
550 msm_gem_unlock(obj);
551
552 if (*metadata_size < len) {
553 ret = -ETOOSMALL;
554 } else if (copy_to_user(metadata, buf, len)) {
555 ret = -EFAULT;
556 } else {
557 *metadata_size = len;
558 }
559
560 kfree(buf);
561
562 return ret;
563 }
564
msm_ioctl_gem_info(struct drm_device * dev,void * data,struct drm_file * file)565 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
566 struct drm_file *file)
567 {
568 struct drm_msm_gem_info *args = data;
569 struct drm_gem_object *obj;
570 struct msm_gem_object *msm_obj;
571 int i, ret = 0;
572
573 if (args->pad)
574 return -EINVAL;
575
576 switch (args->info) {
577 case MSM_INFO_GET_OFFSET:
578 case MSM_INFO_GET_IOVA:
579 case MSM_INFO_SET_IOVA:
580 case MSM_INFO_GET_FLAGS:
581 /* value returned as immediate, not pointer, so len==0: */
582 if (args->len)
583 return -EINVAL;
584 break;
585 case MSM_INFO_SET_NAME:
586 case MSM_INFO_GET_NAME:
587 case MSM_INFO_SET_METADATA:
588 case MSM_INFO_GET_METADATA:
589 break;
590 default:
591 return -EINVAL;
592 }
593
594 obj = drm_gem_object_lookup(file, args->handle);
595 if (!obj)
596 return -ENOENT;
597
598 msm_obj = to_msm_bo(obj);
599
600 switch (args->info) {
601 case MSM_INFO_GET_OFFSET:
602 ret = drm_gem_create_mmap_offset(obj);
603 if (ret == 0)
604 args->value = drm_vma_node_offset_addr(&obj->vma_node);
605 break;
606 case MSM_INFO_GET_IOVA:
607 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
608 break;
609 case MSM_INFO_SET_IOVA:
610 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
611 break;
612 case MSM_INFO_GET_FLAGS:
613 if (drm_gem_is_imported(obj)) {
614 ret = -EINVAL;
615 break;
616 }
617 /* Hide internal kernel-only flags: */
618 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
619 ret = 0;
620 break;
621 case MSM_INFO_SET_NAME:
622 /* length check should leave room for terminating null: */
623 if (args->len >= sizeof(msm_obj->name)) {
624 ret = -EINVAL;
625 break;
626 }
627 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
628 args->len)) {
629 msm_obj->name[0] = '\0';
630 ret = -EFAULT;
631 break;
632 }
633 msm_obj->name[args->len] = '\0';
634 for (i = 0; i < args->len; i++) {
635 if (!isprint(msm_obj->name[i])) {
636 msm_obj->name[i] = '\0';
637 break;
638 }
639 }
640 break;
641 case MSM_INFO_GET_NAME:
642 if (args->value && (args->len < strlen(msm_obj->name))) {
643 ret = -ETOOSMALL;
644 break;
645 }
646 args->len = strlen(msm_obj->name);
647 if (args->value) {
648 if (copy_to_user(u64_to_user_ptr(args->value),
649 msm_obj->name, args->len))
650 ret = -EFAULT;
651 }
652 break;
653 case MSM_INFO_SET_METADATA:
654 ret = msm_ioctl_gem_info_set_metadata(
655 obj, u64_to_user_ptr(args->value), args->len);
656 break;
657 case MSM_INFO_GET_METADATA:
658 ret = msm_ioctl_gem_info_get_metadata(
659 obj, u64_to_user_ptr(args->value), &args->len);
660 break;
661 }
662
663 drm_gem_object_put(obj);
664
665 return ret;
666 }
667
wait_fence(struct msm_gpu_submitqueue * queue,uint32_t fence_id,ktime_t timeout,uint32_t flags)668 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
669 ktime_t timeout, uint32_t flags)
670 {
671 struct dma_fence *fence;
672 int ret;
673
674 if (fence_after(fence_id, queue->last_fence)) {
675 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
676 fence_id, queue->last_fence);
677 return -EINVAL;
678 }
679
680 /*
681 * Map submitqueue scoped "seqno" (which is actually an idr key)
682 * back to underlying dma-fence
683 *
684 * The fence is removed from the fence_idr when the submit is
685 * retired, so if the fence is not found it means there is nothing
686 * to wait for
687 */
688 spin_lock(&queue->idr_lock);
689 fence = idr_find(&queue->fence_idr, fence_id);
690 if (fence)
691 fence = dma_fence_get_rcu(fence);
692 spin_unlock(&queue->idr_lock);
693
694 if (!fence)
695 return 0;
696
697 if (flags & MSM_WAIT_FENCE_BOOST)
698 dma_fence_set_deadline(fence, ktime_get());
699
700 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
701 if (ret == 0) {
702 ret = -ETIMEDOUT;
703 } else if (ret != -ERESTARTSYS) {
704 ret = 0;
705 }
706
707 dma_fence_put(fence);
708
709 return ret;
710 }
711
msm_ioctl_wait_fence(struct drm_device * dev,void * data,struct drm_file * file)712 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
713 struct drm_file *file)
714 {
715 struct msm_drm_private *priv = dev->dev_private;
716 struct drm_msm_wait_fence *args = data;
717 struct msm_gpu_submitqueue *queue;
718 int ret;
719
720 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) {
721 DRM_ERROR("invalid flags: %08x\n", args->flags);
722 return -EINVAL;
723 }
724
725 if (!priv->gpu)
726 return 0;
727
728 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
729 if (!queue)
730 return -ENOENT;
731
732 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags);
733
734 msm_submitqueue_put(queue);
735
736 return ret;
737 }
738
msm_ioctl_gem_madvise(struct drm_device * dev,void * data,struct drm_file * file)739 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
740 struct drm_file *file)
741 {
742 struct drm_msm_gem_madvise *args = data;
743 struct drm_gem_object *obj;
744 int ret;
745
746 switch (args->madv) {
747 case MSM_MADV_DONTNEED:
748 case MSM_MADV_WILLNEED:
749 break;
750 default:
751 return -EINVAL;
752 }
753
754 obj = drm_gem_object_lookup(file, args->handle);
755 if (!obj) {
756 return -ENOENT;
757 }
758
759 ret = msm_gem_madvise(obj, args->madv);
760 if (ret >= 0) {
761 args->retained = ret;
762 ret = 0;
763 }
764
765 drm_gem_object_put(obj);
766
767 return ret;
768 }
769
770
msm_ioctl_submitqueue_new(struct drm_device * dev,void * data,struct drm_file * file)771 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
772 struct drm_file *file)
773 {
774 struct drm_msm_submitqueue *args = data;
775
776 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
777 return -EINVAL;
778
779 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
780 args->flags, &args->id);
781 }
782
msm_ioctl_submitqueue_query(struct drm_device * dev,void * data,struct drm_file * file)783 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
784 struct drm_file *file)
785 {
786 return msm_submitqueue_query(dev, file->driver_priv, data);
787 }
788
msm_ioctl_submitqueue_close(struct drm_device * dev,void * data,struct drm_file * file)789 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
790 struct drm_file *file)
791 {
792 u32 id = *(u32 *) data;
793
794 return msm_submitqueue_remove(file->driver_priv, id);
795 }
796
797 static const struct drm_ioctl_desc msm_ioctls[] = {
798 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
799 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
800 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
801 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
802 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
803 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
804 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
805 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
806 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
807 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
808 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
809 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
810 DRM_IOCTL_DEF_DRV(MSM_VM_BIND, msm_ioctl_vm_bind, DRM_RENDER_ALLOW),
811 DRM_IOCTL_DEF_DRV(MSM_PERFCNTR_CONFIG, msm_ioctl_perfcntr_config, DRM_RENDER_ALLOW),
812 };
813
msm_show_fdinfo(struct drm_printer * p,struct drm_file * file)814 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file)
815 {
816 struct drm_device *dev = file->minor->dev;
817 struct msm_drm_private *priv = dev->dev_private;
818
819 if (!priv->gpu)
820 return;
821
822 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p);
823
824 drm_show_memory_stats(p, file);
825 }
826
827 static const struct file_operations fops = {
828 .owner = THIS_MODULE,
829 DRM_GEM_FOPS,
830 .show_fdinfo = drm_show_fdinfo,
831 };
832
833 #define DRIVER_FEATURES_GPU ( \
834 DRIVER_GEM | \
835 DRIVER_RENDER | \
836 DRIVER_SYNCOBJ | \
837 DRIVER_SYNCOBJ_TIMELINE | \
838 0 )
839
840 #define DRIVER_FEATURES_KMS ( \
841 DRIVER_GEM | \
842 DRIVER_ATOMIC | \
843 DRIVER_MODESET | \
844 0 )
845
846 static const struct drm_driver msm_driver = {
847 .driver_features = DRIVER_FEATURES_GPU | DRIVER_FEATURES_KMS,
848 .open = msm_open,
849 .postclose = msm_postclose,
850 .dumb_create = msm_gem_dumb_create,
851 .dumb_map_offset = drm_gem_dumb_map_offset,
852 .gem_prime_import = msm_gem_prime_import,
853 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
854 #ifdef CONFIG_DEBUG_FS
855 .debugfs_init = msm_debugfs_init,
856 #endif
857 MSM_FBDEV_DRIVER_OPS,
858 .show_fdinfo = msm_show_fdinfo,
859 .ioctls = msm_ioctls,
860 .num_ioctls = ARRAY_SIZE(msm_ioctls),
861 .fops = &fops,
862 .name = "msm",
863 .desc = "MSM Snapdragon DRM",
864 .major = MSM_VERSION_MAJOR,
865 .minor = MSM_VERSION_MINOR,
866 .patchlevel = MSM_VERSION_PATCHLEVEL,
867 };
868
869 static const struct drm_driver msm_kms_driver = {
870 .driver_features = DRIVER_FEATURES_KMS,
871 .open = msm_open,
872 .postclose = msm_postclose,
873 .dumb_create = msm_gem_dumb_create,
874 .dumb_map_offset = drm_gem_dumb_map_offset,
875 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
876 #ifdef CONFIG_DEBUG_FS
877 .debugfs_init = msm_debugfs_init,
878 #endif
879 MSM_FBDEV_DRIVER_OPS,
880 .show_fdinfo = msm_show_fdinfo,
881 .fops = &fops,
882 .name = "msm-kms",
883 .desc = "MSM Snapdragon DRM",
884 .major = MSM_VERSION_MAJOR,
885 .minor = MSM_VERSION_MINOR,
886 .patchlevel = MSM_VERSION_PATCHLEVEL,
887 };
888
889 static const struct drm_driver msm_gpu_driver = {
890 .driver_features = DRIVER_FEATURES_GPU,
891 .open = msm_open,
892 .postclose = msm_postclose,
893 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
894 #ifdef CONFIG_DEBUG_FS
895 .debugfs_init = msm_debugfs_init,
896 #endif
897 .show_fdinfo = msm_show_fdinfo,
898 .ioctls = msm_ioctls,
899 .num_ioctls = ARRAY_SIZE(msm_ioctls),
900 .fops = &fops,
901 .name = "msm",
902 .desc = "MSM Snapdragon DRM",
903 .major = MSM_VERSION_MAJOR,
904 .minor = MSM_VERSION_MINOR,
905 .patchlevel = MSM_VERSION_PATCHLEVEL,
906 };
907
908 /*
909 * Componentized driver support:
910 */
911
912 /*
913 * Identify what components need to be added by parsing what remote-endpoints
914 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
915 * is no external component that we need to add since LVDS is within MDP4
916 * itself.
917 */
add_mdp_components(struct device * master_dev,struct component_match ** matchptr)918 static int add_mdp_components(struct device *master_dev,
919 struct component_match **matchptr)
920 {
921 struct device_node *np = master_dev->of_node;
922 struct device_node *ep_node;
923
924 for_each_endpoint_of_node(np, ep_node) {
925 struct device_node *intf;
926 struct of_endpoint ep;
927 int ret;
928
929 ret = of_graph_parse_endpoint(ep_node, &ep);
930 if (ret) {
931 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
932 of_node_put(ep_node);
933 return ret;
934 }
935
936 /*
937 * The LCDC/LVDS port on MDP4 is a speacial case where the
938 * remote-endpoint isn't a component that we need to add
939 */
940 if (of_device_is_compatible(np, "qcom,mdp4") &&
941 ep.port == 0)
942 continue;
943
944 /*
945 * It's okay if some of the ports don't have a remote endpoint
946 * specified. It just means that the port isn't connected to
947 * any external interface.
948 */
949 intf = of_graph_get_remote_port_parent(ep_node);
950 if (!intf)
951 continue;
952
953 if (of_device_is_available(intf))
954 drm_of_component_match_add(master_dev, matchptr,
955 component_compare_of, intf);
956
957 of_node_put(intf);
958 }
959
960 return 0;
961 }
962
963 #if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)
msm_disp_drv_should_bind(struct device * dev,bool dpu_driver)964 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
965 {
966 /* If just a single driver is enabled, use it no matter what */
967 return true;
968 }
969 #else
970
971 static bool prefer_mdp5 = true;
972 MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
973 module_param(prefer_mdp5, bool, 0444);
974
975 /* list all platforms that have been migrated from mdp5 to dpu driver */
976 static const char *const msm_mdp5_dpu_migrated[] = {
977 /* there never was qcom,msm8998-mdp5 */
978 "qcom,sdm630-mdp5",
979 "qcom,sdm660-mdp5",
980 NULL
981 };
982
983 /* list all platforms supported by both mdp5 and dpu drivers */
984 static const char *const msm_mdp5_dpu_migration[] = {
985 "qcom,msm8917-mdp5",
986 "qcom,msm8937-mdp5",
987 "qcom,msm8953-mdp5",
988 "qcom,msm8996-mdp5",
989 NULL,
990 };
991
msm_disp_drv_should_bind(struct device * dev,bool dpu_driver)992 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
993 {
994 /* If it is not an MDP5 device, use DPU */
995 if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
996 return dpu_driver;
997
998 /* If it is no longer supported by MDP5, use DPU */
999 if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated))
1000 return dpu_driver;
1001
1002 /* If it is not in the migration list, use MDP5 */
1003 if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration))
1004 return !dpu_driver;
1005
1006 return prefer_mdp5 ? !dpu_driver : dpu_driver;
1007 }
1008 #endif
1009
1010 /*
1011 * We don't know what's the best binding to link the gpu with the drm device.
1012 * Fow now, we just hunt for all the possible gpus that we support, and add them
1013 * as components.
1014 */
1015 static const struct of_device_id msm_gpu_match[] = {
1016 { .compatible = "qcom,adreno" },
1017 { .compatible = "qcom,adreno-3xx" },
1018 { .compatible = "amd,imageon" },
1019 { .compatible = "qcom,kgsl-3d0" },
1020 { },
1021 };
1022
add_gpu_components(struct device * dev,struct component_match ** matchptr)1023 static int add_gpu_components(struct device *dev,
1024 struct component_match **matchptr)
1025 {
1026 struct device_node *np;
1027
1028 np = of_find_matching_node(NULL, msm_gpu_match);
1029 if (!np)
1030 return 0;
1031
1032 if (of_device_is_available(np) && adreno_has_gpu(np))
1033 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1034
1035 of_node_put(np);
1036
1037 return 0;
1038 }
1039
msm_drm_bind(struct device * dev)1040 static int msm_drm_bind(struct device *dev)
1041 {
1042 return msm_drm_init(dev,
1043 msm_gpu_no_components() ?
1044 &msm_kms_driver :
1045 &msm_driver,
1046 NULL);
1047 }
1048
msm_drm_unbind(struct device * dev)1049 static void msm_drm_unbind(struct device *dev)
1050 {
1051 msm_drm_uninit(dev, NULL);
1052 }
1053
1054 const struct component_master_ops msm_drm_ops = {
1055 .bind = msm_drm_bind,
1056 .unbind = msm_drm_unbind,
1057 };
1058
msm_drv_probe(struct device * master_dev,int (* kms_init)(struct drm_device * dev),struct msm_kms * kms)1059 int msm_drv_probe(struct device *master_dev,
1060 int (*kms_init)(struct drm_device *dev),
1061 struct msm_kms *kms)
1062 {
1063 struct msm_drm_private *priv;
1064 struct component_match *match = NULL;
1065 int ret;
1066
1067 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1068 if (!priv)
1069 return -ENOMEM;
1070
1071 priv->kms = kms;
1072 priv->kms_init = kms_init;
1073 dev_set_drvdata(master_dev, priv);
1074
1075 /* Add mdp components if we have KMS. */
1076 if (kms_init) {
1077 ret = add_mdp_components(master_dev, &match);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 if (!msm_gpu_no_components()) {
1083 ret = add_gpu_components(master_dev, &match);
1084 if (ret)
1085 return ret;
1086 }
1087
1088 /* on all devices that I am aware of, iommu's which can map
1089 * any address the cpu can see are used:
1090 */
1091 ret = dma_set_mask_and_coherent(master_dev, ~0);
1092 if (ret)
1093 return ret;
1094
1095 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1096 if (ret)
1097 return ret;
1098
1099 return 0;
1100 }
1101
msm_gpu_probe(struct platform_device * pdev,const struct component_ops * ops)1102 int msm_gpu_probe(struct platform_device *pdev,
1103 const struct component_ops *ops)
1104 {
1105 struct msm_drm_private *priv;
1106 int ret;
1107
1108 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1109 if (!priv)
1110 return -ENOMEM;
1111
1112 platform_set_drvdata(pdev, priv);
1113
1114 /* on all devices that I am aware of, iommu's which can map
1115 * any address the cpu can see are used:
1116 */
1117 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1118 if (ret)
1119 return ret;
1120
1121 return msm_drm_init(&pdev->dev, &msm_gpu_driver, ops);
1122 }
1123
msm_gpu_remove(struct platform_device * pdev,const struct component_ops * ops)1124 void msm_gpu_remove(struct platform_device *pdev,
1125 const struct component_ops *ops)
1126 {
1127 msm_drm_uninit(&pdev->dev, ops);
1128 }
1129
msm_drm_register(void)1130 static int __init msm_drm_register(void)
1131 {
1132 if (!modeset)
1133 return -EINVAL;
1134
1135 DBG("init");
1136 msm_mdp_register();
1137 msm_dpu_register();
1138 msm_dsi_register();
1139 msm_hdmi_register();
1140 msm_dp_register();
1141 adreno_register();
1142 msm_mdp4_register();
1143 msm_mdss_register();
1144
1145 return 0;
1146 }
1147
msm_drm_unregister(void)1148 static void __exit msm_drm_unregister(void)
1149 {
1150 DBG("fini");
1151 msm_mdss_unregister();
1152 msm_mdp4_unregister();
1153 msm_dp_unregister();
1154 msm_hdmi_unregister();
1155 adreno_unregister();
1156 msm_dsi_unregister();
1157 msm_mdp_unregister();
1158 msm_dpu_unregister();
1159 }
1160
1161 module_init(msm_drm_register);
1162 module_exit(msm_drm_unregister);
1163
1164 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1165 MODULE_DESCRIPTION("MSM DRM Driver");
1166 MODULE_LICENSE("GPL");
1167