1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 4 * 5 * Copyright (C) 2016 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 serial0 = &uart0; 20 serial1 = &uart1; 21 }; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 /* 29 * The PSCI firmware region depicted below is the default one 30 * and should be updated by the bootloader. 31 */ 32 psci-area@4000000 { 33 reg = <0 0x4000000 0 0x200000>; 34 no-map; 35 }; 36 37 tee@4400000 { 38 reg = <0 0x4400000 0 0x1000000>; 39 no-map; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0>; 50 clocks = <&nb_periph_clk 16>; 51 enable-method = "psci"; 52 }; 53 }; 54 55 psci { 56 compatible = "arm,psci-0.2"; 57 method = "smc"; 58 }; 59 60 timer { 61 compatible = "arm,armv8-timer"; 62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 66 }; 67 68 pmu { 69 compatible = "arm,cortex-a53-pmu"; 70 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 71 }; 72 73 soc { 74 compatible = "simple-bus"; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 bus@d0000000 { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 compatible = "simple-bus"; 83 /* 32M internal register @ 0xd000_0000 */ 84 ranges = <0x0 0x0 0xd0000000 0x2000000>; 85 86 wdt: watchdog@8300 { 87 compatible = "marvell,armada-3700-wdt"; 88 reg = <0x8300 0x40>; 89 marvell,system-controller = <&cpu_misc>; 90 clocks = <&xtalclk>; 91 }; 92 93 cpu_misc: system-controller@d000 { 94 compatible = "marvell,armada-3700-cpu-misc", 95 "syscon"; 96 reg = <0xd000 0x1000>; 97 }; 98 99 spi0: spi@10600 { 100 compatible = "marvell,armada-3700-spi"; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 reg = <0x10600 0xA00>; 104 clocks = <&nb_periph_clk 7>; 105 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 106 num-cs = <4>; 107 status = "disabled"; 108 }; 109 110 i2c0: i2c@11000 { 111 compatible = "marvell,armada-3700-i2c"; 112 reg = <0x11000 0x24>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 clocks = <&nb_periph_clk 10>; 116 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 117 mrvl,i2c-fast-mode; 118 status = "disabled"; 119 }; 120 121 i2c1: i2c@11080 { 122 compatible = "marvell,armada-3700-i2c"; 123 reg = <0x11080 0x24>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 clocks = <&nb_periph_clk 9>; 127 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 128 mrvl,i2c-fast-mode; 129 status = "disabled"; 130 }; 131 132 avs: avs@11500 { 133 compatible = "marvell,armada-3700-avs", 134 "syscon"; 135 reg = <0x11500 0x40>; 136 }; 137 138 uartclk: clock-controller@12010 { 139 compatible = "marvell,armada-3700-uart-clock"; 140 reg = <0x12010 0x4>, <0x12210 0x4>; 141 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 142 <&tbg 3>, <&xtalclk>; 143 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", 144 "TBG-B-S", "xtal"; 145 #clock-cells = <1>; 146 }; 147 148 uart0: serial@12000 { 149 compatible = "marvell,armada-3700-uart"; 150 reg = <0x12000 0x18>; 151 clocks = <&uartclk 0>; 152 interrupts = 153 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 157 status = "disabled"; 158 }; 159 160 uart1: serial@12200 { 161 compatible = "marvell,armada-3700-uart-ext"; 162 reg = <0x12200 0x30>; 163 clocks = <&uartclk 1>; 164 interrupts = 165 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 166 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 167 interrupt-names = "uart-tx", "uart-rx"; 168 status = "disabled"; 169 }; 170 171 nb_periph_clk: nb-periph-clk@13000 { 172 compatible = "marvell,armada-3700-periph-clock-nb", 173 "syscon"; 174 reg = <0x13000 0x100>; 175 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 176 <&tbg 3>, <&xtalclk>; 177 #clock-cells = <1>; 178 }; 179 180 sb_periph_clk: sb-periph-clk@18000 { 181 compatible = "marvell,armada-3700-periph-clock-sb"; 182 reg = <0x18000 0x100>; 183 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 184 <&tbg 3>, <&xtalclk>; 185 #clock-cells = <1>; 186 }; 187 188 tbg: tbg@13200 { 189 compatible = "marvell,armada-3700-tbg-clock"; 190 reg = <0x13200 0x100>; 191 clocks = <&xtalclk>; 192 #clock-cells = <1>; 193 }; 194 195 pinctrl_nb: pinctrl@13800 { 196 compatible = "marvell,armada3710-nb-pinctrl", 197 "syscon", "simple-mfd"; 198 reg = <0x13800 0x100>, <0x13C00 0x20>; 199 /* MPP1[19:0] */ 200 gpionb: gpio { 201 #gpio-cells = <2>; 202 gpio-ranges = <&pinctrl_nb 0 0 36>; 203 gpio-controller; 204 interrupt-controller; 205 #interrupt-cells = <2>; 206 interrupts = 207 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 xtalclk: xtal-clk { 222 compatible = "marvell,armada-3700-xtal-clock"; 223 clock-output-names = "xtal"; 224 #clock-cells = <0>; 225 }; 226 227 spi_quad_pins: spi-quad-pins { 228 groups = "spi_quad"; 229 function = "spi"; 230 }; 231 232 spi_cs1_pins: spi-cs1-pins { 233 groups = "spi_cs1"; 234 function = "spi"; 235 }; 236 237 i2c1_pins: i2c1-pins { 238 groups = "i2c1"; 239 function = "i2c"; 240 }; 241 242 i2c2_pins: i2c2-pins { 243 groups = "i2c2"; 244 function = "i2c"; 245 }; 246 247 uart1_pins: uart1-pins { 248 groups = "uart1"; 249 function = "uart"; 250 }; 251 252 uart2_pins: uart2-pins { 253 groups = "uart2"; 254 function = "uart"; 255 }; 256 257 mmc_pins: mmc-pins { 258 groups = "emmc_nb"; 259 function = "emmc"; 260 }; 261 }; 262 263 nb_pm: syscon@14000 { 264 compatible = "marvell,armada-3700-nb-pm", 265 "syscon"; 266 reg = <0x14000 0x60>; 267 }; 268 269 comphy: phy@18300 { 270 compatible = "marvell,comphy-a3700"; 271 reg = <0x18300 0x300>, 272 <0x1F000 0x400>, 273 <0x5C000 0x400>, 274 <0xe0178 0x8>; 275 reg-names = "comphy", 276 "lane1_pcie_gbe", 277 "lane0_usb3_gbe", 278 "lane2_sata_usb3"; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 clocks = <&xtalclk>; 282 clock-names = "xtal"; 283 284 comphy0: phy@0 { 285 reg = <0>; 286 #phy-cells = <1>; 287 }; 288 289 comphy1: phy@1 { 290 reg = <1>; 291 #phy-cells = <1>; 292 }; 293 294 comphy2: phy@2 { 295 reg = <2>; 296 #phy-cells = <1>; 297 }; 298 }; 299 300 pinctrl_sb: pinctrl@18800 { 301 compatible = "marvell,armada3710-sb-pinctrl", 302 "syscon", "simple-mfd"; 303 reg = <0x18800 0x100>, <0x18C00 0x20>; 304 /* MPP2[23:0] */ 305 gpiosb: gpio { 306 #gpio-cells = <2>; 307 gpio-ranges = <&pinctrl_sb 0 0 30>; 308 gpio-controller; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 interrupts = 312 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 rgmii_pins: mii-pins { 320 groups = "rgmii"; 321 function = "mii"; 322 }; 323 324 smi_pins: smi-pins { 325 groups = "smi"; 326 function = "smi"; 327 }; 328 329 sdio_pins: sdio-pins { 330 groups = "sdio_sb"; 331 function = "sdio"; 332 }; 333 334 pcie_reset_pins: pcie-reset-pins { 335 groups = "pcie1"; /* this actually controls "pcie1_reset" */ 336 function = "gpio"; 337 }; 338 339 pcie_clkreq_pins: pcie-clkreq-pins { 340 groups = "pcie1_clkreq"; 341 function = "pcie"; 342 }; 343 }; 344 345 eth0: ethernet@30000 { 346 compatible = "marvell,armada-3700-neta"; 347 reg = <0x30000 0x4000>; 348 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&sb_periph_clk 8>; 350 status = "disabled"; 351 }; 352 353 mdio: mdio@32004 { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 compatible = "marvell,orion-mdio"; 357 reg = <0x32004 0x4>; 358 }; 359 360 eth1: ethernet@40000 { 361 compatible = "marvell,armada-3700-neta"; 362 reg = <0x40000 0x4000>; 363 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&sb_periph_clk 7>; 365 status = "disabled"; 366 }; 367 368 usb3: usb@58000 { 369 compatible = "marvell,armada3700-xhci", 370 "generic-xhci"; 371 reg = <0x58000 0x4000>; 372 marvell,usb-misc-reg = <&usb32_syscon>; 373 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&sb_periph_clk 12>; 375 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; 376 phy-names = "usb3-phy", "usb2-utmi-otg-phy"; 377 status = "disabled"; 378 }; 379 380 usb2_utmi_otg_phy: phy@5d000 { 381 compatible = "marvell,a3700-utmi-otg-phy"; 382 reg = <0x5d000 0x800>; 383 marvell,usb-misc-reg = <&usb32_syscon>; 384 #phy-cells = <0>; 385 }; 386 387 usb32_syscon: system-controller@5d800 { 388 compatible = "marvell,armada-3700-usb2-host-device-misc", 389 "syscon"; 390 reg = <0x5d800 0x800>; 391 }; 392 393 usb2: usb@5e000 { 394 compatible = "marvell,armada-3700-ehci"; 395 reg = <0x5e000 0x1000>; 396 marvell,usb-misc-reg = <&usb2_syscon>; 397 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 398 phys = <&usb2_utmi_host_phy>; 399 phy-names = "usb2-utmi-host-phy"; 400 status = "disabled"; 401 }; 402 403 usb2_utmi_host_phy: phy@5f000 { 404 compatible = "marvell,a3700-utmi-host-phy"; 405 reg = <0x5f000 0x800>; 406 marvell,usb-misc-reg = <&usb2_syscon>; 407 #phy-cells = <0>; 408 }; 409 410 usb2_syscon: system-controller@5f800 { 411 compatible = "marvell,armada-3700-usb2-host-misc", 412 "syscon"; 413 reg = <0x5f800 0x800>; 414 }; 415 416 xor@60900 { 417 compatible = "marvell,armada-3700-xor"; 418 reg = <0x60900 0x100>, 419 <0x60b00 0x100>; 420 421 xor10 { 422 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 423 }; 424 xor11 { 425 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 426 }; 427 }; 428 429 crypto: crypto@90000 { 430 compatible = "inside-secure,safexcel-eip97ies"; 431 reg = <0x90000 0x20000>; 432 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 438 interrupt-names = "ring0", "ring1", "ring2", 439 "ring3", "eip", "mem"; 440 clocks = <&nb_periph_clk 15>; 441 }; 442 443 rwtm: mailbox@b0000 { 444 compatible = "marvell,armada-3700-rwtm-mailbox"; 445 reg = <0xb0000 0x100>; 446 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 447 #mbox-cells = <1>; 448 }; 449 450 sdhci1: mmc@d0000 { 451 compatible = "marvell,armada-3700-sdhci", 452 "marvell,sdhci-xenon"; 453 reg = <0xd0000 0x300>, 454 <0x1e808 0x4>; 455 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&nb_periph_clk 0>; 457 clock-names = "core"; 458 status = "disabled"; 459 }; 460 461 sdhci0: mmc@d8000 { 462 compatible = "marvell,armada-3700-sdhci", 463 "marvell,sdhci-xenon"; 464 reg = <0xd8000 0x300>, 465 <0x17808 0x4>; 466 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&nb_periph_clk 0>; 468 clock-names = "core"; 469 status = "disabled"; 470 }; 471 472 sata: sata@e0000 { 473 compatible = "marvell,armada-3700-ahci"; 474 reg = <0xe0000 0x178>; 475 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&nb_periph_clk 1>; 477 phys = <&comphy2 0>; 478 phy-names = "sata-phy"; 479 status = "disabled"; 480 }; 481 482 gic: interrupt-controller@1d00000 { 483 compatible = "arm,gic-v3"; 484 #interrupt-cells = <3>; 485 interrupt-controller; 486 reg = <0x1d00000 0x10000>, /* GICD */ 487 <0x1d40000 0x40000>, /* GICR */ 488 <0x1d80000 0x2000>, /* GICC */ 489 <0x1d90000 0x2000>, /* GICH */ 490 <0x1da0000 0x20000>; /* GICV */ 491 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 492 }; 493 }; 494 495 pcie0: pcie@d0070000 { 496 compatible = "marvell,armada-3700-pcie"; 497 device_type = "pci"; 498 status = "disabled"; 499 reg = <0 0xd0070000 0 0x20000>; 500 #address-cells = <3>; 501 #size-cells = <2>; 502 bus-range = <0x00 0xff>; 503 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 504 #interrupt-cells = <1>; 505 clocks = <&sb_periph_clk 13>; 506 msi-parent = <&pcie0>; 507 msi-controller; 508 /* 509 * The 128 MiB address range [0xe8000000-0xf0000000] is 510 * dedicated for PCIe and can be assigned to 8 windows 511 * with size a power of two. Use one 64 KiB window for 512 * IO at the end and the remaining seven windows 513 * (totaling 127 MiB) for MEM. 514 */ 515 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ 516 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ 517 interrupt-map-mask = <0 0 0 7>; 518 interrupt-map = <0 0 0 1 &pcie_intc 0>, 519 <0 0 0 2 &pcie_intc 1>, 520 <0 0 0 3 &pcie_intc 2>, 521 <0 0 0 4 &pcie_intc 3>; 522 max-link-speed = <2>; 523 phys = <&comphy1 0>; 524 pcie_intc: interrupt-controller { 525 interrupt-controller; 526 #interrupt-cells = <1>; 527 }; 528 }; 529 }; 530 531 firmware { 532 armada-3700-rwtm { 533 compatible = "marvell,armada-3700-rwtm-firmware"; 534 mboxes = <&rwtm 0>; 535 status = "okay"; 536 }; 537 }; 538}; 539