xref: /freebsd/sys/dev/usb/wlan/if_mtw.c (revision f981fa12b760a5f0983eeec8065a4dec5295ab24)
1 /*-
2  * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr>
3  * Copyright (c) 2013-2014 Kevin Lo
4  * Copyright (c) 2021 James Hastings
5  * Ported to FreeBSD by Jesper Schmitz Mouridsen jsm@FreeBSD.org
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 /*
21  * MediaTek MT7601U 802.11b/g/n WLAN.
22  */
23 
24 #include "opt_wlan.h"
25 
26 #include <sys/param.h>
27 #include <sys/systm.h>
28 #include <sys/bus.h>
29 #include <sys/endian.h>
30 #include <sys/eventhandler.h>
31 #include <sys/firmware.h>
32 #include <sys/kdb.h>
33 #include <sys/kernel.h>
34 #include <sys/linker.h>
35 #include <sys/lock.h>
36 #include <sys/malloc.h>
37 #include <sys/mbuf.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
43 
44 #include <net/bpf.h>
45 #include <net/ethernet.h>
46 #include <net/if.h>
47 #include <net/if_arp.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51 #include <net/if_var.h>
52 #include <net80211/ieee80211_var.h>
53 #include <net80211/ieee80211_radiotap.h>
54 #include <net80211/ieee80211_ratectl.h>
55 #include <net80211/ieee80211_regdomain.h>
56 #ifdef	IEEE80211_SUPPORT_SUPERG
57 #include <net80211/ieee80211_superg.h>
58 #endif
59 #include <netinet/if_ether.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
67 #include <dev/usb/usb_request.h>
68 
69 #include "usbdevs.h"
70 
71 #define USB_DEBUG_VAR mtw_debug
72 #include <dev/usb/usb_debug.h>
73 #include <dev/usb/usb_msctest.h>
74 
75 #include "if_mtwreg.h"
76 #include "if_mtwvar.h"
77 
78 #define MTW_DEBUG
79 
80 #ifdef MTW_DEBUG
81 int mtw_debug;
82 static SYSCTL_NODE(_hw_usb, OID_AUTO, mtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
83     "USB mtw");
84 SYSCTL_INT(_hw_usb_mtw, OID_AUTO, debug, CTLFLAG_RWTUN, &mtw_debug, 0,
85     "mtw debug level");
86 
87 enum {
88 	MTW_DEBUG_XMIT = 0x00000001,	  /* basic xmit operation */
89 	MTW_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
90 	MTW_DEBUG_RECV = 0x00000004,	  /* basic recv operation */
91 	MTW_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
92 	MTW_DEBUG_STATE = 0x00000010,	  /* 802.11 state transitions */
93 	MTW_DEBUG_RATE = 0x00000020,	  /* rate adaptation */
94 	MTW_DEBUG_USB = 0x00000040,	  /* usb requests */
95 	MTW_DEBUG_FIRMWARE = 0x00000080,  /* firmware(9) loading debug */
96 	MTW_DEBUG_BEACON = 0x00000100,	  /* beacon handling */
97 	MTW_DEBUG_INTR = 0x00000200,	  /* ISR */
98 	MTW_DEBUG_TEMP = 0x00000400,	  /* temperature calibration */
99 	MTW_DEBUG_ROM = 0x00000800,	  /* various ROM info */
100 	MTW_DEBUG_KEY = 0x00001000,	  /* crypto keys management */
101 	MTW_DEBUG_TXPWR = 0x00002000,	  /* dump Tx power values */
102 	MTW_DEBUG_RSSI = 0x00004000,	  /* dump RSSI lookups */
103 	MTW_DEBUG_RESET = 0x00008000,	  /* initialization progress */
104 	MTW_DEBUG_CALIB = 0x00010000,	  /* calibration progress */
105 	MTW_DEBUG_CMD = 0x00020000,	  /* command queue */
106 	MTW_DEBUG_ANY = 0xffffffff
107 };
108 
109 #define MTW_DPRINTF(_sc, _m, ...)                                  \
110 	do {                                                       \
111 		if (mtw_debug & (_m))                              \
112 			device_printf((_sc)->sc_dev, __VA_ARGS__); \
113 	} while (0)
114 
115 #else
116 #define MTW_DPRINTF(_sc, _m, ...) \
117 	do {                      \
118 		(void)_sc;        \
119 	} while (0)
120 #endif
121 
122 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh)
123 
124 /* NB: "11" is the maximum number of padding bytes needed for Tx */
125 #define MTW_MAX_TXSZ \
126 	(sizeof(struct mtw_txd) + sizeof(struct mtw_txwi) + MCLBYTES + 11)
127 
128 #define	MTW_FW_READY_RETRIES	500
129 #define	MTW_FW_READY_DELAY_MS	30
130 #define	MTW_FWLOAD_TIMEOUT	\
131 	(((MTW_FW_READY_RETRIES * MTW_FW_READY_DELAY_MS) / 1000 + 5) * hz)
132 
133 /*
134  * Because of LOR in mtw_key_delete(), use atomic instead.
135  * '& MTW_CMDQ_MASQ' is to loop cmdq[].
136  */
137 #define MTW_CMDQ_GET(c) (atomic_fetchadd_32((c), 1) & MTW_CMDQ_MASQ)
138 
139 static const STRUCT_USB_HOST_ID mtw_devs[] = {
140 #define MTW_DEV(v, p)                                         \
141 	{                                                     \
142 		USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) \
143 	}
144 	MTW_DEV(EDIMAX, MT7601U),
145 	MTW_DEV(RALINK, MT7601U),
146 	MTW_DEV(XIAOMI, MT7601U)
147 };
148 #undef MTW_DEV
149 
150 static device_probe_t mtw_match;
151 static device_attach_t mtw_attach;
152 static device_detach_t mtw_detach;
153 
154 static usb_callback_t mtw_bulk_rx_callback;
155 static usb_callback_t mtw_bulk_tx_callback0;
156 static usb_callback_t mtw_bulk_tx_callback1;
157 static usb_callback_t mtw_bulk_tx_callback2;
158 static usb_callback_t mtw_bulk_tx_callback3;
159 static usb_callback_t mtw_bulk_tx_callback4;
160 static usb_callback_t mtw_bulk_tx_callback5;
161 static usb_callback_t mtw_fw_callback;
162 
163 static void mtw_autoinst(void *, struct usb_device *, struct usb_attach_arg *);
164 static int mtw_driver_loaded(struct module *, int, void *);
165 static void mtw_bulk_tx_callbackN(struct usb_xfer *xfer, usb_error_t error,
166 				  u_int index);
167 static struct ieee80211vap *mtw_vap_create(struct ieee80211com *,
168 	const char[IFNAMSIZ], int, enum ieee80211_opmode, int,
169 	const uint8_t[IEEE80211_ADDR_LEN], const uint8_t[IEEE80211_ADDR_LEN]);
170 static void mtw_vap_delete(struct ieee80211vap *);
171 static void mtw_cmdq_cb(void *, int);
172 static void mtw_setup_tx_list(struct mtw_softc *, struct mtw_endpoint_queue *);
173 static void mtw_unsetup_tx_list(struct mtw_softc *,
174 				struct mtw_endpoint_queue *);
175 static void mtw_load_microcode(void *arg);
176 
177 static usb_error_t mtw_do_request(struct mtw_softc *,
178 				  struct usb_device_request *, void *);
179 static int mtw_read(struct mtw_softc *, uint16_t, uint32_t *);
180 static int mtw_read_region_1(struct mtw_softc *, uint16_t, uint8_t *, int);
181 static int mtw_write_2(struct mtw_softc *, uint16_t, uint16_t);
182 static int mtw_write(struct mtw_softc *, uint16_t, uint32_t);
183 static int mtw_write_region_1(struct mtw_softc *, uint16_t, const uint8_t *, int);
184 static int mtw_set_region_4(struct mtw_softc *, uint16_t, uint32_t, int);
185 static int mtw_efuse_read_2(struct mtw_softc *, uint16_t, uint16_t *);
186 static int mtw_bbp_read(struct mtw_softc *, uint8_t, uint8_t *);
187 static int mtw_bbp_write(struct mtw_softc *, uint8_t, uint8_t);
188 static int mtw_mcu_cmd(struct mtw_softc *sc, uint8_t cmd, void *buf, int len);
189 static void mtw_get_txpower(struct mtw_softc *);
190 static int mtw_read_eeprom(struct mtw_softc *);
191 static struct ieee80211_node *mtw_node_alloc(struct ieee80211vap *,
192     const uint8_t mac[IEEE80211_ADDR_LEN]);
193 static int mtw_media_change(if_t);
194 static int mtw_newstate(struct ieee80211vap *, enum ieee80211_state, int);
195 static int mtw_wme_update(struct ieee80211com *);
196 static void mtw_key_set_cb(void *);
197 static int mtw_key_set(struct ieee80211vap *, struct ieee80211_key *);
198 static void mtw_key_delete_cb(void *);
199 static int mtw_key_delete(struct ieee80211vap *, struct ieee80211_key *);
200 static void mtw_ratectl_to(void *);
201 static void mtw_ratectl_cb(void *, int);
202 static void mtw_drain_fifo(void *);
203 static void mtw_iter_func(void *, struct ieee80211_node *);
204 static void mtw_newassoc_cb(void *);
205 static void mtw_newassoc(struct ieee80211_node *, int);
206 static int mtw_mcu_radio(struct mtw_softc *sc, int func, uint32_t val);
207 static void mtw_recv_mgmt(struct ieee80211_node *, struct mbuf *, int,
208     const struct ieee80211_rx_stats *, int, int);
209 static void mtw_rx_frame(struct mtw_softc *, struct mbuf *, uint32_t);
210 static void mtw_tx_free(struct mtw_endpoint_queue *pq, struct mtw_tx_data *,
211     int);
212 static void mtw_set_tx_desc(struct mtw_softc *, struct mtw_tx_data *);
213 static int mtw_tx(struct mtw_softc *, struct mbuf *, struct ieee80211_node *);
214 static int mtw_tx_mgt(struct mtw_softc *, struct mbuf *,
215     struct ieee80211_node *);
216 static int mtw_sendprot(struct mtw_softc *, const struct mbuf *,
217     struct ieee80211_node *, int, int);
218 static int mtw_tx_param(struct mtw_softc *, struct mbuf *,
219     struct ieee80211_node *, const struct ieee80211_bpf_params *);
220 static int mtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
221     const struct ieee80211_bpf_params *);
222 static int mtw_transmit(struct ieee80211com *, struct mbuf *);
223 static void mtw_start(struct mtw_softc *);
224 static void mtw_parent(struct ieee80211com *);
225 static void mtw_select_chan_group(struct mtw_softc *, int);
226 
227 static int mtw_set_chan(struct mtw_softc *, struct ieee80211_channel *);
228 static void mtw_set_channel(struct ieee80211com *);
229 static void mtw_getradiocaps(struct ieee80211com *, int, int *,
230     struct ieee80211_channel[]);
231 static void mtw_scan_start(struct ieee80211com *);
232 static void mtw_scan_end(struct ieee80211com *);
233 static void mtw_update_beacon(struct ieee80211vap *, int);
234 static void mtw_update_beacon_cb(void *);
235 static void mtw_updateprot(struct ieee80211com *);
236 static void mtw_updateprot_cb(void *);
237 static void mtw_usb_timeout_cb(void *);
238 static int mtw_reset(struct mtw_softc *sc);
239 static void mtw_enable_tsf_sync(struct mtw_softc *);
240 
241 
242 static void mtw_enable_mrr(struct mtw_softc *);
243 static void mtw_set_txpreamble(struct mtw_softc *);
244 static void mtw_set_basicrates(struct mtw_softc *);
245 static void mtw_set_leds(struct mtw_softc *, uint16_t);
246 static void mtw_set_bssid(struct mtw_softc *, const uint8_t *);
247 static void mtw_set_macaddr(struct mtw_softc *, const uint8_t *);
248 static void mtw_updateslot(struct ieee80211com *);
249 static void mtw_updateslot_cb(void *);
250 static void mtw_update_mcast(struct ieee80211com *);
251 static int8_t mtw_rssi2dbm(struct mtw_softc *, uint8_t, uint8_t);
252 static void mtw_update_promisc_locked(struct mtw_softc *);
253 static void mtw_update_promisc(struct ieee80211com *);
254 static int mtw_txrx_enable(struct mtw_softc *);
255 static void mtw_init_locked(struct mtw_softc *);
256 static void mtw_stop(void *);
257 static void mtw_delay(struct mtw_softc *, u_int);
258 static void mtw_update_chw(struct ieee80211com *ic);
259 static int mtw_ampdu_enable(struct ieee80211_node *ni,
260     struct ieee80211_tx_ampdu *tap);
261 
262 static eventhandler_tag mtw_etag;
263 
264 static const struct {
265 	uint8_t reg;
266 	uint8_t val;
267 } mt7601_rf_bank0[] = { MT7601_BANK0_RF },
268   mt7601_rf_bank4[] = { MT7601_BANK4_RF },
269   mt7601_rf_bank5[] = { MT7601_BANK5_RF };
270 static const struct {
271 	uint32_t reg;
272 	uint32_t val;
273 } mt7601_def_mac[] = { MT7601_DEF_MAC };
274 static const struct {
275 	uint8_t reg;
276 	uint8_t val;
277 } mt7601_def_bbp[] = { MT7601_DEF_BBP };
278 
279 
280 static const struct {
281 	u_int chan;
282 	uint8_t r17, r18, r19, r20;
283 } mt7601_rf_chan[] = { MT7601_RF_CHAN };
284 
285 
286 static const struct usb_config mtw_config[MTW_N_XFER] = {
287 	[MTW_BULK_RX] = {
288 		.type = UE_BULK,
289 		.endpoint = UE_ADDR_ANY,
290 		.direction = UE_DIR_IN,
291 		.bufsize = MTW_MAX_RXSZ,
292 		.flags = {.pipe_bof = 1,
293 			  .short_xfer_ok = 1,},
294 		.callback = mtw_bulk_rx_callback,
295 	},
296 	[MTW_BULK_TX_BE] = {
297 		.type = UE_BULK,
298 		.endpoint = UE_ADDR_ANY,
299 		.direction = UE_DIR_OUT,
300 		.bufsize = MTW_MAX_TXSZ,
301 		.flags = {.pipe_bof = 1,
302 			  .force_short_xfer = 0,},
303 		.callback = mtw_bulk_tx_callback0,
304 		.timeout = 5000,	/* ms */
305     },
306 	[MTW_BULK_TX_BK] = {
307 		.type = UE_BULK,
308 		.endpoint = UE_ADDR_ANY,
309 		.direction = UE_DIR_OUT,
310 		.bufsize = MTW_MAX_TXSZ,
311 		.flags = {.pipe_bof = 1,
312 			  .force_short_xfer = 1,},
313 		.callback = mtw_bulk_tx_callback1,
314 		.timeout = 5000,	/* ms */
315 	},
316 	[MTW_BULK_TX_VI] = {
317 	    .type = UE_BULK,
318 	    .endpoint = UE_ADDR_ANY,
319 	    .direction = UE_DIR_OUT,
320 	    .bufsize = MTW_MAX_TXSZ,
321 	    .flags = {.pipe_bof = 1,
322 		      .force_short_xfer = 1,},
323 	    .callback = mtw_bulk_tx_callback2,
324 	    .timeout = 5000,	/* ms */
325 	},
326 	[MTW_BULK_TX_VO] = {
327 		.type = UE_BULK,
328 		.endpoint = UE_ADDR_ANY,
329 		.direction = UE_DIR_OUT,
330 		.bufsize = MTW_MAX_TXSZ,
331 		.flags = {.pipe_bof = 1,
332 			  .force_short_xfer = 1,},
333 		.callback = mtw_bulk_tx_callback3,
334 		.timeout = 5000,	/* ms */
335     },
336 	[MTW_BULK_TX_HCCA] = {
337 		.type = UE_BULK,
338 		.endpoint = UE_ADDR_ANY,
339 		.direction = UE_DIR_OUT,
340 		.bufsize = MTW_MAX_TXSZ,
341 		.flags = {.pipe_bof = 1,
342 			  .force_short_xfer = 1, .no_pipe_ok = 1,},
343 		.callback = mtw_bulk_tx_callback4,
344 		.timeout = 5000,	/* ms */
345     },
346 	[MTW_BULK_TX_PRIO] = {
347 		.type = UE_BULK,
348 		.endpoint = UE_ADDR_ANY,
349 		.direction = UE_DIR_OUT,
350 		.bufsize = MTW_MAX_TXSZ,
351 		.flags = {.pipe_bof = 1,
352 			  .force_short_xfer = 1, .no_pipe_ok = 1,},
353 		.callback = mtw_bulk_tx_callback5,
354 		.timeout = 5000,	/* ms */
355 	},
356 
357 	[MTW_BULK_FW_CMD] = {
358 		.type = UE_BULK,
359 		.endpoint = UE_ADDR_ANY,
360 		.direction = UE_DIR_OUT,
361 		.bufsize = 0x2c44,
362 		.flags = {.pipe_bof = 1,
363 			  .force_short_xfer = 1, .no_pipe_ok = 1,},
364 		.callback = mtw_fw_callback,
365 
366 	},
367 
368 	[MTW_BULK_RAW_TX] = {
369 		.type = UE_BULK,
370 		.ep_index = 0,
371 		.endpoint = UE_ADDR_ANY,
372 		.direction = UE_DIR_OUT,
373 		.bufsize = MTW_MAX_TXSZ,
374 		.flags = {.pipe_bof = 1,
375 			  .force_short_xfer = 1, .no_pipe_ok = 1,},
376 		.callback = mtw_bulk_tx_callback0,
377 		.timeout = 5000,	/* ms */
378 	},
379 
380 };
381 static uint8_t mtw_wme_ac_xfer_map[4] = {
382 	[WME_AC_BE] = MTW_BULK_TX_BE,
383 	[WME_AC_BK] = MTW_BULK_TX_BK,
384 	[WME_AC_VI] = MTW_BULK_TX_VI,
385 	[WME_AC_VO] = MTW_BULK_TX_VO,
386 };
387 static void
mtw_autoinst(void * arg,struct usb_device * udev,struct usb_attach_arg * uaa)388 mtw_autoinst(void *arg, struct usb_device *udev, struct usb_attach_arg *uaa)
389 {
390 	struct usb_interface *iface;
391 	struct usb_interface_descriptor *id;
392 
393 	if (uaa->dev_state != UAA_DEV_READY)
394 		return;
395 
396 	iface = usbd_get_iface(udev, 0);
397 	if (iface == NULL)
398 		return;
399 	id = iface->idesc;
400 	if (id == NULL || id->bInterfaceClass != UICLASS_MASS)
401 		return;
402 	if (usbd_lookup_id_by_uaa(mtw_devs, sizeof(mtw_devs), uaa))
403 		return;
404 
405 	if (usb_msc_eject(udev, 0, MSC_EJECT_STOPUNIT) == 0)
406 		uaa->dev_state = UAA_DEV_EJECTING;
407 }
408 
409 static int
mtw_driver_loaded(struct module * mod,int what,void * arg)410 mtw_driver_loaded(struct module *mod, int what, void *arg)
411 {
412 	switch (what) {
413 	case MOD_LOAD:
414 		mtw_etag = EVENTHANDLER_REGISTER(usb_dev_configured,
415 		    mtw_autoinst, NULL, EVENTHANDLER_PRI_ANY);
416 		break;
417 	case MOD_UNLOAD:
418 		EVENTHANDLER_DEREGISTER(usb_dev_configured, mtw_etag);
419 		break;
420 	default:
421 		return (EOPNOTSUPP);
422 	}
423 	return (0);
424 }
425 
426 static const char *
mtw_get_rf(int rev)427 mtw_get_rf(int rev)
428 {
429 	switch (rev) {
430 	case MT7601_RF_7601:
431 		return ("MT7601");
432 	case MT7610_RF_7610:
433 		return ("MT7610");
434 	case MT7612_RF_7612:
435 		return ("MT7612");
436 	}
437 	return ("unknown");
438 }
439 static int
mtw_wlan_enable(struct mtw_softc * sc,int enable)440 mtw_wlan_enable(struct mtw_softc *sc, int enable)
441 {
442 	uint32_t tmp;
443 	int error = 0;
444 
445 	if (enable) {
446 		mtw_read(sc, MTW_WLAN_CTRL, &tmp);
447 		if (sc->asic_ver == 0x7612)
448 			tmp &= ~0xfffff000;
449 
450 		tmp &= ~MTW_WLAN_CLK_EN;
451 		tmp |= MTW_WLAN_EN;
452 		mtw_write(sc, MTW_WLAN_CTRL, tmp);
453 		mtw_delay(sc, 2);
454 
455 		tmp |= MTW_WLAN_CLK_EN;
456 		if (sc->asic_ver == 0x7612) {
457 			tmp |= (MTW_WLAN_RESET | MTW_WLAN_RESET_RF);
458 		}
459 		mtw_write(sc, MTW_WLAN_CTRL, tmp);
460 		mtw_delay(sc, 2);
461 
462 		mtw_read(sc, MTW_OSC_CTRL, &tmp);
463 		tmp |= MTW_OSC_EN;
464 		mtw_write(sc, MTW_OSC_CTRL, tmp);
465 		tmp |= MTW_OSC_CAL_REQ;
466 		mtw_write(sc, MTW_OSC_CTRL, tmp);
467 	} else {
468 		mtw_read(sc, MTW_WLAN_CTRL, &tmp);
469 		tmp &= ~(MTW_WLAN_CLK_EN | MTW_WLAN_EN);
470 		mtw_write(sc, MTW_WLAN_CTRL, tmp);
471 
472 		mtw_read(sc, MTW_OSC_CTRL, &tmp);
473 		tmp &= ~MTW_OSC_EN;
474 		mtw_write(sc, MTW_OSC_CTRL, tmp);
475 	}
476 	return (error);
477 }
478 
479 static int
mtw_read_cfg(struct mtw_softc * sc,uint16_t reg,uint32_t * val)480 mtw_read_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t *val)
481 {
482 	usb_device_request_t req;
483 	uint32_t tmp;
484 	uint16_t actlen;
485 	int error;
486 
487 	req.bmRequestType = UT_READ_VENDOR_DEVICE;
488 	req.bRequest = MTW_READ_CFG;
489 	USETW(req.wValue, 0);
490 	USETW(req.wIndex, reg);
491 	USETW(req.wLength, 4);
492 	error = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, &tmp, 0,
493 	    &actlen, 1000);
494 
495 	if (error == 0)
496 		*val = le32toh(tmp);
497 	else
498 		*val = 0xffffffff;
499 	return (error);
500 }
501 
502 static int
mtw_match(device_t self)503 mtw_match(device_t self)
504 {
505 	struct usb_attach_arg *uaa = device_get_ivars(self);
506 
507 	if (uaa->usb_mode != USB_MODE_HOST)
508 		return (ENXIO);
509 	if (uaa->info.bConfigIndex != 0)
510 		return (ENXIO);
511 	if (uaa->info.bIfaceIndex != 0)
512 		return (ENXIO);
513 
514 	return (usbd_lookup_id_by_uaa(mtw_devs, sizeof(mtw_devs), uaa));
515 }
516 
517 static int
mtw_attach(device_t self)518 mtw_attach(device_t self)
519 {
520 	struct mtw_softc *sc = device_get_softc(self);
521 	struct usb_attach_arg *uaa = device_get_ivars(self);
522 	struct ieee80211com *ic = &sc->sc_ic;
523 	uint32_t ver;
524 	int i;
525 	uint32_t tmp;
526 	uint8_t iface_index;
527 	int ntries, error;
528 
529 	device_set_usb_desc(self);
530 	sc->sc_udev = uaa->device;
531 	sc->sc_dev = self;
532 	sc->sc_sent = 0;
533 
534 	/*
535 	 * Reset the device to clear any stale state left over from
536 	 * a previous warm reboot. Some MT7601U devices fail otherwise.
537 	 */
538 	error = usbd_req_re_enumerate(uaa->device, NULL);
539 	if (error != 0)
540 		device_printf(self, "USB re-enumerate failed, continuing\n");
541 	DELAY(100000);	/* 100ms settle time */
542 
543 	mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev),
544 	    MTX_NETWORK_LOCK, MTX_DEF);
545 
546 	iface_index = 0;
547 
548 	error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
549 	    mtw_config, MTW_N_XFER, sc, &sc->sc_mtx);
550 	if (error) {
551 		device_printf(sc->sc_dev,
552 		    "could not allocate USB transfers, "
553 		    "err=%s\n",
554 		    usbd_errstr(error));
555 		goto detach;
556 	}
557 	for (i = 0; i < 4; i++) {
558 		sc->txd_fw[i] = (struct mtw_txd_fw *)
559 		    malloc(sizeof(struct mtw_txd_fw),
560 			M_USBDEV, M_NOWAIT | M_ZERO);
561 	}
562 	MTW_LOCK(sc);
563 	sc->sc_idx = 0;
564 	mbufq_init(&sc->sc_snd, ifqmaxlen);
565 
566 	/*enable WLAN core */
567 	if ((error = mtw_wlan_enable(sc, 1)) != 0) {
568 		device_printf(sc->sc_dev, "could not enable WLAN core\n");
569 		return (ENXIO);
570 	}
571 
572 	/* wait for the chip to settle */
573 	DELAY(100);
574 	for (ntries = 0; ntries < 100; ntries++) {
575 		if (mtw_read(sc, MTW_ASIC_VER, &ver) != 0) {
576 			goto detach;
577 		}
578 		if (ver != 0 && ver != 0xffffffff)
579 			break;
580 		DELAY(10);
581 	}
582 	if (ntries == 100) {
583 		device_printf(sc->sc_dev,
584 		    "timeout waiting for NIC to initialize\n");
585 		goto detach;
586 	}
587 	sc->asic_ver = ver >> 16;
588 	sc->asic_rev = ver & 0xffff;
589 	DELAY(100);
590 	if (sc->asic_ver != 0x7601) {
591 		device_printf(sc->sc_dev,
592 		    "Your revision 0x04%x is not supported yet\n",
593 		 sc->asic_rev);
594 		goto detach;
595 	}
596 
597 
598 	if (mtw_read(sc, MTW_MAC_VER_ID, &tmp) != 0)
599 		goto detach;
600 	sc->mac_rev = tmp & 0xffff;
601 
602 	mtw_load_microcode(sc);
603 	if (sc->fwloading != 1)
604 		(void)msleep(&sc->fwloading, &sc->sc_mtx, 0, "fwload",
605 		    MTW_FWLOAD_TIMEOUT);
606 	if (sc->fwloading != 1) {
607 		device_printf(sc->sc_dev,
608 		    "timeout waiting for MCU to initialize\n");
609 		goto detach;
610 	}
611 
612 	sc->sc_srom_read = mtw_efuse_read_2;
613 	/* retrieve RF rev. no and various other things from EEPROM */
614 	mtw_read_eeprom(sc);
615 
616 	device_printf(sc->sc_dev,
617 	    "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n",
618 	    sc->asic_ver, sc->mac_rev, mtw_get_rf(sc->rf_rev), sc->ntxchains,
619 	    sc->nrxchains, ether_sprintf(ic->ic_macaddr));
620 	DELAY(100);
621 
622 	//mtw_set_leds(sc,5);
623 	// mtw_mcu_radio(sc,0x31,0);
624 	MTW_UNLOCK(sc);
625 
626 
627 	ic->ic_softc = sc;
628 	ic->ic_name = device_get_nameunit(self);
629 	ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
630 	ic->ic_opmode = IEEE80211_M_STA;   /* default to BSS mode */
631 
632 	ic->ic_caps = IEEE80211_C_STA | /* station mode supported */
633 		IEEE80211_C_MONITOR |	/* monitor mode supported */
634 		IEEE80211_C_IBSS |
635 		IEEE80211_C_HOSTAP |
636 		IEEE80211_C_WDS | /* 4-address traffic works */
637 		IEEE80211_C_MBSS |
638 		IEEE80211_C_SHPREAMBLE | /* short preamble supported */
639 		IEEE80211_C_SHSLOT |     /* short slot time supported */
640 		IEEE80211_C_WME |             /* WME */
641 		IEEE80211_C_WPA;	     /* WPA1|WPA2(RSN) */
642 	    device_printf(sc->sc_dev, "[HT] Enabling 802.11n\n");
643 	    ic->ic_htcaps = IEEE80211_HTC_HT
644 		| IEEE80211_HTC_AMPDU
645 		| IEEE80211_HTC_AMSDU
646 		| IEEE80211_HTCAP_MAXAMSDU_3839
647 		| IEEE80211_HTCAP_SMPS_OFF;
648 
649 	ic->ic_rxstream = sc->nrxchains;
650 	ic->ic_txstream = sc->ntxchains;
651 
652 	ic->ic_cryptocaps = IEEE80211_CRYPTO_WEP | IEEE80211_CRYPTO_AES_CCM |
653 	    IEEE80211_CRYPTO_AES_OCB | IEEE80211_CRYPTO_TKIP |
654 	    IEEE80211_CRYPTO_TKIPMIC;
655 
656 	ic->ic_flags |= IEEE80211_F_DATAPAD;
657 	ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
658 	ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD;
659 
660 	mtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
661 	    ic->ic_channels);
662 
663 	ieee80211_ifattach(ic);
664 
665 	ic->ic_scan_start = mtw_scan_start;
666 	ic->ic_scan_end = mtw_scan_end;
667 	ic->ic_set_channel = mtw_set_channel;
668 	ic->ic_getradiocaps = mtw_getradiocaps;
669 	ic->ic_node_alloc = mtw_node_alloc;
670 	ic->ic_newassoc = mtw_newassoc;
671 	ic->ic_update_mcast = mtw_update_mcast;
672 	ic->ic_updateslot = mtw_updateslot;
673 	ic->ic_wme.wme_update = mtw_wme_update;
674 	ic->ic_raw_xmit = mtw_raw_xmit;
675 	ic->ic_update_promisc = mtw_update_promisc;
676 	ic->ic_vap_create = mtw_vap_create;
677 	ic->ic_vap_delete = mtw_vap_delete;
678 	ic->ic_transmit = mtw_transmit;
679 	ic->ic_parent = mtw_parent;
680 
681 	ic->ic_update_chw = mtw_update_chw;
682 	ic->ic_ampdu_enable = mtw_ampdu_enable;
683 
684 	ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
685 	    sizeof(sc->sc_txtap), MTW_TX_RADIOTAP_PRESENT,
686 	    &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
687 	    MTW_RX_RADIOTAP_PRESENT);
688 	TASK_INIT(&sc->cmdq_task, 0, mtw_cmdq_cb, sc);
689 	TASK_INIT(&sc->ratectl_task, 0, mtw_ratectl_cb, sc);
690 	usb_callout_init_mtx(&sc->ratectl_ch, &sc->sc_mtx, 0);
691 
692 	if (bootverbose)
693 		ieee80211_announce(ic);
694 
695 	return (0);
696 
697 detach:
698 	MTW_UNLOCK(sc);
699 	mtw_detach(self);
700 	return (ENXIO);
701 }
702 
703 static void
mtw_drain_mbufq(struct mtw_softc * sc)704 mtw_drain_mbufq(struct mtw_softc *sc)
705 {
706 	struct mbuf *m;
707 	struct ieee80211_node *ni;
708 
709 	MTW_LOCK_ASSERT(sc, MA_OWNED);
710 	while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
711 		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
712 		m->m_pkthdr.rcvif = NULL;
713 		ieee80211_free_node(ni);
714 		m_freem(m);
715 	}
716 }
717 
718 static int
mtw_detach(device_t self)719 mtw_detach(device_t self)
720 {
721 	struct mtw_softc *sc = device_get_softc(self);
722 	struct ieee80211com *ic = &sc->sc_ic;
723 	int i;
724 	MTW_LOCK(sc);
725 	mtw_reset(sc);
726 	DELAY(10000);
727 	sc->sc_detached = 1;
728 	MTW_UNLOCK(sc);
729 
730 
731 	/* stop all USB transfers */
732 	for (i = 0; i < MTW_N_XFER; i++)
733 		usbd_transfer_drain(sc->sc_xfer[i]);
734 
735 	MTW_LOCK(sc);
736 	sc->ratectl_run = MTW_RATECTL_OFF;
737 	sc->cmdq_run = sc->cmdq_key_set = MTW_CMDQ_ABORT;
738 
739 	/* free TX list, if any */
740 	if (ic->ic_nrunning > 0)
741 		for (i = 0; i < MTW_EP_QUEUES; i++)
742 			mtw_unsetup_tx_list(sc, &sc->sc_epq[i]);
743 
744 	/* Free TX queue */
745 	mtw_drain_mbufq(sc);
746 	MTW_UNLOCK(sc);
747 	if (sc->sc_ic.ic_softc == sc) {
748 		/* drain tasks */
749 		usb_callout_drain(&sc->ratectl_ch);
750 		ieee80211_draintask(ic, &sc->cmdq_task);
751 		ieee80211_draintask(ic, &sc->ratectl_task);
752 		ieee80211_ifdetach(ic);
753 	}
754 	for (i = 0; i < 4; i++) {
755 		free(sc->txd_fw[i], M_USBDEV);
756 	}
757 	firmware_unregister("/mediatek/mt7601u");
758 	mtx_destroy(&sc->sc_mtx);
759 
760 	return (0);
761 }
762 
763 static struct ieee80211vap *
mtw_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])764 mtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
765     enum ieee80211_opmode opmode, int flags,
766     const uint8_t bssid[IEEE80211_ADDR_LEN],
767     const uint8_t mac[IEEE80211_ADDR_LEN])
768 {
769 	struct mtw_softc *sc = ic->ic_softc;
770 	struct mtw_vap *rvp;
771 	struct ieee80211vap *vap;
772 	int i;
773 
774 	if (sc->rvp_cnt >= MTW_VAP_MAX) {
775 		device_printf(sc->sc_dev, "number of VAPs maxed out\n");
776 		return (NULL);
777 	}
778 
779 	switch (opmode) {
780 	case IEEE80211_M_STA:
781 		/* enable s/w bmiss handling for sta mode */
782 		flags |= IEEE80211_CLONE_NOBEACONS;
783 		/* fall though */
784 	case IEEE80211_M_IBSS:
785 	case IEEE80211_M_MONITOR:
786 	case IEEE80211_M_HOSTAP:
787 	case IEEE80211_M_MBSS:
788 		/* other than WDS vaps, only one at a time */
789 		if (!TAILQ_EMPTY(&ic->ic_vaps))
790 			return (NULL);
791 		break;
792 	case IEEE80211_M_WDS:
793 		TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
794 			if (vap->iv_opmode != IEEE80211_M_HOSTAP)
795 				continue;
796 			/* WDS vap's always share the local mac address. */
797 			flags &= ~IEEE80211_CLONE_BSSID;
798 			break;
799 		}
800 		if (vap == NULL) {
801 			device_printf(sc->sc_dev,
802 			    "wds only supported in ap mode\n");
803 			return (NULL);
804 		}
805 		break;
806 	default:
807 		device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
808 		return (NULL);
809 	}
810 
811 	rvp = malloc(sizeof(struct mtw_vap), M_80211_VAP, M_WAITOK | M_ZERO);
812 	vap = &rvp->vap;
813 
814 	if (ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid) !=
815 	    0) {
816 		/* out of memory */
817 		free(rvp, M_80211_VAP);
818 		return (NULL);
819 	}
820 
821 	vap->iv_update_beacon = mtw_update_beacon;
822 	vap->iv_max_aid = MTW_WCID_MAX;
823 
824 	/*
825 	 * The linux rt2800 driver limits 1 stream devices to a 32KB
826 	 * RX AMPDU.
827 	 */
828 	if (ic->ic_rxstream > 1)
829 		vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
830 	else
831 		vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
832 	vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_2; /* 2uS */
833 
834 	/*
835 	 * To delete the right key from h/w, we need wcid.
836 	 * Luckily, there is unused space in ieee80211_key{}, wk_pad,
837 	 * and matching wcid will be written into there. So, cast
838 	 * some spells to remove 'const' from ieee80211_key{}
839 	 */
840 	vap->iv_key_delete = (void *)mtw_key_delete;
841 	vap->iv_key_set = (void *)mtw_key_set;
842 
843 	// override state transition machine
844 	rvp->newstate = vap->iv_newstate;
845 	vap->iv_newstate = mtw_newstate;
846 	if (opmode == IEEE80211_M_IBSS) {
847 		rvp->recv_mgmt = vap->iv_recv_mgmt;
848 		vap->iv_recv_mgmt = mtw_recv_mgmt;
849 	}
850 
851 	ieee80211_ratectl_init(vap);
852 	ieee80211_ratectl_setinterval(vap, 1000); // 1 second
853 
854 	/* complete setup */
855 	ieee80211_vap_attach(vap, mtw_media_change, ieee80211_media_status,
856 	    mac);
857 
858 	/* make sure id is always unique */
859 	for (i = 0; i < MTW_VAP_MAX; i++) {
860 		if ((sc->rvp_bmap & 1 << i) == 0) {
861 			sc->rvp_bmap |= 1 << i;
862 			rvp->rvp_id = i;
863 			break;
864 		}
865 	}
866 	if (sc->rvp_cnt++ == 0)
867 		ic->ic_opmode = opmode;
868 
869 	if (opmode == IEEE80211_M_HOSTAP)
870 		sc->cmdq_run = MTW_CMDQ_GO;
871 
872 	MTW_DPRINTF(sc, MTW_DEBUG_STATE, "rvp_id=%d bmap=%x rvp_cnt=%d\n",
873 	    rvp->rvp_id, sc->rvp_bmap, sc->rvp_cnt);
874 
875 	return (vap);
876 }
877 
878 static void
mtw_vap_delete(struct ieee80211vap * vap)879 mtw_vap_delete(struct ieee80211vap *vap)
880 {
881 	struct mtw_vap *rvp = MTW_VAP(vap);
882 	struct ieee80211com *ic;
883 	struct mtw_softc *sc;
884 	uint8_t rvp_id;
885 
886 	if (vap == NULL)
887 		return;
888 
889 	ic = vap->iv_ic;
890 	sc = ic->ic_softc;
891 
892 	MTW_LOCK(sc);
893 	m_freem(rvp->beacon_mbuf);
894 	rvp->beacon_mbuf = NULL;
895 
896 	rvp_id = rvp->rvp_id;
897 	sc->ratectl_run &= ~(1 << rvp_id);
898 	sc->rvp_bmap &= ~(1 << rvp_id);
899 	mtw_set_region_4(sc, MTW_SKEY(rvp_id, 0), 0, 256);
900 	mtw_set_region_4(sc, (0x7800 + (rvp_id) * 512), 0, 512);
901 	--sc->rvp_cnt;
902 
903 	MTW_DPRINTF(sc, MTW_DEBUG_STATE,
904 	    "vap=%p rvp_id=%d bmap=%x rvp_cnt=%d\n", vap, rvp_id, sc->rvp_bmap,
905 	    sc->rvp_cnt);
906 
907 	MTW_UNLOCK(sc);
908 
909 	ieee80211_ratectl_deinit(vap);
910 	ieee80211_vap_detach(vap);
911 	free(rvp, M_80211_VAP);
912 }
913 
914 /*
915  * There are numbers of functions need to be called in context thread.
916  * Rather than creating taskqueue event for each of those functions,
917  * here is all-for-one taskqueue callback function. This function
918  * guarantees deferred functions are executed in the same order they
919  * were enqueued.
920  * '& MTW_CMDQ_MASQ' is to loop cmdq[].
921  */
922 static void
mtw_cmdq_cb(void * arg,int pending)923 mtw_cmdq_cb(void *arg, int pending)
924 {
925 	struct mtw_softc *sc = arg;
926 	uint8_t i;
927 	/* call cmdq[].func locked */
928 	MTW_LOCK(sc);
929 	for (i = sc->cmdq_exec; sc->cmdq[i].func && pending;
930 	     i = sc->cmdq_exec, pending--) {
931 		MTW_DPRINTF(sc, MTW_DEBUG_CMD, "cmdq_exec=%d pending=%d\n", i,
932 		    pending);
933 		if (sc->cmdq_run == MTW_CMDQ_GO) {
934 			/*
935 			 * If arg0 is NULL, callback func needs more
936 			 * than one arg. So, pass ptr to cmdq struct.
937 			 */
938 			if (sc->cmdq[i].arg0)
939 				sc->cmdq[i].func(sc->cmdq[i].arg0);
940 			else
941 				sc->cmdq[i].func(&sc->cmdq[i]);
942 		}
943 		sc->cmdq[i].arg0 = NULL;
944 		sc->cmdq[i].func = NULL;
945 		sc->cmdq_exec++;
946 		sc->cmdq_exec &= MTW_CMDQ_MASQ;
947 	}
948 	MTW_UNLOCK(sc);
949 }
950 
951 static void
mtw_setup_tx_list(struct mtw_softc * sc,struct mtw_endpoint_queue * pq)952 mtw_setup_tx_list(struct mtw_softc *sc, struct mtw_endpoint_queue *pq)
953 {
954 	struct mtw_tx_data *data;
955 
956 	memset(pq, 0, sizeof(*pq));
957 
958 	STAILQ_INIT(&pq->tx_qh);
959 	STAILQ_INIT(&pq->tx_fh);
960 
961 	for (data = &pq->tx_data[0]; data < &pq->tx_data[MTW_TX_RING_COUNT];
962 	     data++) {
963 		data->sc = sc;
964 		STAILQ_INSERT_TAIL(&pq->tx_fh, data, next);
965 	}
966 	pq->tx_nfree = MTW_TX_RING_COUNT;
967 }
968 
969 static void
mtw_unsetup_tx_list(struct mtw_softc * sc,struct mtw_endpoint_queue * pq)970 mtw_unsetup_tx_list(struct mtw_softc *sc, struct mtw_endpoint_queue *pq)
971 {
972 	struct mtw_tx_data *data;
973 	/* make sure any subsequent use of the queues will fail */
974 	pq->tx_nfree = 0;
975 
976 	STAILQ_INIT(&pq->tx_fh);
977 	STAILQ_INIT(&pq->tx_qh);
978 
979 	/* free up all node references and mbufs */
980 	for (data = &pq->tx_data[0]; data < &pq->tx_data[MTW_TX_RING_COUNT];
981 	     data++) {
982 		if (data->m != NULL) {
983 			m_freem(data->m);
984 			data->m = NULL;
985 		}
986 		if (data->ni != NULL) {
987 			ieee80211_free_node(data->ni);
988 			data->ni = NULL;
989 		}
990 	}
991 }
992 
993 static int
mtw_write_ivb(struct mtw_softc * sc,void * buf,uint16_t len)994 mtw_write_ivb(struct mtw_softc *sc, void *buf, uint16_t len)
995 {
996 	usb_device_request_t req;
997 	uint16_t actlen;
998 	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
999 	req.bRequest = MTW_RESET;
1000 	USETW(req.wValue, 0x12);
1001 	USETW(req.wIndex, 0);
1002 	USETW(req.wLength, len);
1003 
1004 	int error = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, &req, buf,
1005 	    0, &actlen, 1000);
1006 
1007 	return (error);
1008 }
1009 
1010 static int
mtw_write_cfg(struct mtw_softc * sc,uint16_t reg,uint32_t val)1011 mtw_write_cfg(struct mtw_softc *sc, uint16_t reg, uint32_t val)
1012 {
1013 	usb_device_request_t req;
1014 	int error;
1015 
1016 	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1017 	req.bRequest = MTW_WRITE_CFG;
1018 	USETW(req.wValue, 0);
1019 	USETW(req.wIndex, reg);
1020 	USETW(req.wLength, 4);
1021 	val = htole32(val);
1022 	error = usbd_do_request(sc->sc_udev, &sc->sc_mtx, &req, &val);
1023 	return (error);
1024 }
1025 
1026 static int
mtw_usb_dma_write(struct mtw_softc * sc,uint32_t val)1027 mtw_usb_dma_write(struct mtw_softc *sc, uint32_t val)
1028 {
1029 	// if (sc->asic_ver == 0x7612)
1030 	//		return mtw_write_cfg(sc, MTW_USB_U3DMA_CFG, val);
1031 	//	else
1032 	return (mtw_write(sc, MTW_USB_DMA_CFG, val));
1033 }
1034 
1035 static void
mtw_ucode_setup(struct mtw_softc * sc)1036 mtw_ucode_setup(struct mtw_softc *sc)
1037 {
1038 
1039 	mtw_usb_dma_write(sc, (MTW_USB_TX_EN | MTW_USB_RX_EN));
1040 	mtw_write(sc, MTW_FCE_PSE_CTRL, 1);
1041 	mtw_write(sc, MTW_TX_CPU_FCE_BASE, 0x400230);
1042 	mtw_write(sc, MTW_TX_CPU_FCE_MAX_COUNT, 1);
1043 	mtw_write(sc, MTW_MCU_FW_IDX, 1);
1044 	mtw_write(sc, MTW_FCE_PDMA, 0x44);
1045 	mtw_write(sc, MTW_FCE_SKIP_FS, 3);
1046 }
1047 static int
mtw_ucode_write(struct mtw_softc * sc,const uint8_t * fw,const uint8_t * ivb,int32_t len,uint32_t offset)1048 mtw_ucode_write(struct mtw_softc *sc, const uint8_t *fw, const uint8_t *ivb,
1049     int32_t len, uint32_t offset)
1050 {
1051 
1052 	// struct usb_attach_arg *uaa = device_get_ivars(sc->sc_dev);
1053 #if 0 // firmware not tested
1054 
1055 	if (sc->asic_ver == 0x7612 && offset >= 0x90000)
1056 		blksz = 0x800; /* MT7612 ROM Patch */
1057 
1058 	xfer = usbd_alloc_xfer(sc->sc_udev);
1059 	if (xfer == NULL) {
1060 		error = ENOMEM;
1061 		goto fail;
1062 	}
1063 	buf = usbd_alloc_buffer(xfer, blksz + 12);
1064 	if (buf == NULL) {
1065 		error = ENOMEM;
1066 		goto fail;
1067 	}
1068 #endif
1069 
1070 
1071 
1072 	int mlen;
1073 	int idx = 0;
1074 
1075 	mlen = 0x2c44;
1076 
1077 	while (len > 0) {
1078 
1079 		if (len < 0x2c44 && len > 0) {
1080 			mlen = len;
1081 		}
1082 
1083 		sc->txd_fw[idx]->len = htole16(mlen);
1084 		sc->txd_fw[idx]->flags = htole16(MTW_TXD_DATA | MTW_TXD_MCU);
1085 
1086 		memcpy(&sc->txd_fw[idx]->fw, fw, mlen);
1087 		// memcpy(&txd[1], fw, mlen);
1088 		//	memset(&txd[1]  + mlen, 0, MTW_DMA_PAD);
1089 		//		mtw_write_cfg(sc, MTW_MCU_DMA_ADDR, offset
1090 		//+sent); 1mtw_write_cfg(sc, MTW_MCU_DMA_LEN, (mlen << 16));
1091 
1092 		//	  sc->sc_fw_data[idx]->len=htole16(mlen);
1093 
1094 		// memcpy(tmpbuf,fw,mlen);
1095 		// memset(tmpbuf+mlen,0,MTW_DMA_PAD);
1096 		// memcpy(sc->sc_fw_data[idx].buf, fw, mlen);
1097 
1098 		fw += mlen;
1099 		len -= mlen;
1100 		// sent+=mlen;
1101 		idx++;
1102 	}
1103 	sc->sc_sent = 0;
1104 	memcpy(sc->sc_ivb_1, ivb, MTW_MCU_IVB_LEN);
1105 
1106 	usbd_transfer_start(sc->sc_xfer[7]);
1107 
1108 	return (0);
1109 }
1110 
1111 static void
mtw_load_microcode(void * arg)1112 mtw_load_microcode(void *arg)
1113 {
1114 
1115 	struct mtw_softc *sc = (struct mtw_softc *)arg;
1116 	const struct mtw_ucode_hdr *hdr;
1117 	const struct firmware *firmware_rom = NULL, *firmware = NULL;
1118 	// onst struct mtw_ucode *fw = NULL;
1119 	const char *fwname;
1120 	size_t size;
1121 	int error = 0;
1122 	uint32_t tmp, iofs = 0x40;
1123 	//	int ntries;
1124 	int dlen, ilen;
1125 	MTW_DPRINTF(sc, MTW_DEBUG_FIRMWARE, "version:0x%hx\n", sc->asic_ver);
1126 	/* Check if MCU is already initialized and skip firmware reload */
1127 	mtw_read_cfg(sc, MTW_MCU_DMA_ADDR, &tmp);
1128 	if (tmp == MTW_MCU_READY) {
1129 		MTW_DPRINTF(sc, MTW_DEBUG_FIRMWARE,
1130 		    "MCU already running, skipping firmware reload\n");
1131 		sc->fwloading = 1;
1132 		wakeup(&sc->fwloading);
1133 		return;
1134 	}
1135 
1136 	if (sc->asic_ver == 0x7612) {
1137 		fwname = "mtw-mt7662u_rom_patch";
1138 
1139 		firmware_rom = firmware_get_flags(fwname, FIRMWARE_GET_NOWARN);
1140 		if (firmware_rom == NULL) {
1141 			device_printf(sc->sc_dev,
1142 			    "failed to load firmware file %s\n",
1143 			    fwname);
1144 			return;
1145 		}
1146 		size = firmware_rom->datasize;
1147 
1148 		const struct mtw_ucode *fw = (const struct mtw_ucode *)
1149 		    firmware_rom->data;
1150 		hdr = (const struct mtw_ucode_hdr *)&fw->hdr;
1151 		// memcpy(fw,(const unsigned char*)firmware_rom->data +
1152 		//    0x1e,size-0x1e);
1153 		ilen = size - 0x1e;
1154 
1155 		mtw_ucode_setup(sc);
1156 
1157 		if ((error = mtw_ucode_write(sc, firmware_rom->data, fw->ivb,
1158 		    ilen, 0x90000)) != 0) {
1159 			device_printf(sc->sc_dev,
1160 			    "Could not write ROM patch\n");
1161 			goto fail_rom;
1162 		}
1163 		mtw_usb_dma_write(sc, 0x00e41814);
1164 	}
1165 
1166 	fwname = "/mediatek/mt7601u.bin";
1167 	iofs = 0x40;
1168 	// dofs = 0;
1169 	if (sc->asic_ver == 0x7612) {
1170 		fwname = "mtw-mt7662u";
1171 		iofs = 0x80040;
1172 		//	dofs = 0x110800;
1173 	} else if (sc->asic_ver == 0x7610) {
1174 		fwname = "mt7610u";
1175 		// dofs = 0x80000;
1176 	}
1177 	MTW_UNLOCK(sc);
1178 	firmware = firmware_get_flags(fwname, FIRMWARE_GET_NOWARN);
1179 
1180 	if (firmware == NULL) {
1181 		device_printf(sc->sc_dev,
1182 		    "failed to load firmware file %s\n",
1183 		    fwname);
1184 		MTW_LOCK(sc);
1185 		if (firmware_rom != NULL)
1186 			firmware_put(firmware_rom, FIRMWARE_UNLOAD);
1187 		return;
1188 	}
1189 	MTW_LOCK(sc);
1190 	size = firmware->datasize;
1191 	MTW_DPRINTF(sc, MTW_DEBUG_FIRMWARE, "firmware size:%zu\n", size);
1192 	const struct mtw_ucode *fw = (const struct mtw_ucode *)firmware->data;
1193 
1194 	if (size < sizeof(struct mtw_ucode_hdr)) {
1195 		device_printf(sc->sc_dev, "firmware header too short\n");
1196 		goto fail;
1197 	}
1198 
1199 	hdr = (const struct mtw_ucode_hdr *)&fw->hdr;
1200 
1201 	if (size < sizeof(struct mtw_ucode_hdr) + le32toh(hdr->ilm_len) +
1202 		le32toh(hdr->dlm_len)) {
1203 		device_printf(sc->sc_dev, "firmware payload too short\n");
1204 		goto fail;
1205 	}
1206 
1207 	ilen = le32toh(hdr->ilm_len) - MTW_MCU_IVB_LEN;
1208 	dlen = le32toh(hdr->dlm_len);
1209 
1210 	if (ilen > size || dlen > size) {
1211 		device_printf(sc->sc_dev, "firmware payload too large\n");
1212 		goto fail;
1213 	}
1214 
1215 	mtw_write(sc, MTW_FCE_PDMA, 0);
1216 	mtw_write(sc, MTW_FCE_PSE_CTRL, 0);
1217 	mtw_ucode_setup(sc);
1218 
1219 	if ((error = mtw_ucode_write(sc, fw->data, fw->ivb, ilen, iofs)) != 0)
1220 		device_printf(sc->sc_dev, "Could not write ucode errro=%d\n",
1221 		    error);
1222 
1223 	MTW_DPRINTF(sc, MTW_DEBUG_FIRMWARE,
1224 	    "loaded firmware ver %.8x %.8x %s\n",
1225 	    le32toh(hdr->fw_ver), le32toh(hdr->build_ver), hdr->build_time);
1226 
1227 	/* Release firmware objects */
1228 	firmware_put(firmware, FIRMWARE_UNLOAD);
1229 	if (firmware_rom != NULL)
1230 		firmware_put(firmware_rom, FIRMWARE_UNLOAD);
1231 	return;
1232 
1233 fail:
1234 	firmware_put(firmware, FIRMWARE_UNLOAD);
1235 fail_rom:
1236 	if (firmware_rom != NULL)
1237 		firmware_put(firmware_rom, FIRMWARE_UNLOAD);
1238 	return;
1239 }
1240 static usb_error_t
mtw_do_request(struct mtw_softc * sc,struct usb_device_request * req,void * data)1241 mtw_do_request(struct mtw_softc *sc, struct usb_device_request *req, void *data)
1242 {
1243 	usb_error_t err;
1244 	int ntries = 5;
1245 
1246 	MTW_LOCK_ASSERT(sc, MA_OWNED);
1247 
1248 	while (ntries--) {
1249 		err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, req, data,
1250 		    0, NULL, 2000); // ms seconds
1251 		if (err == 0)
1252 			break;
1253 		MTW_DPRINTF(sc, MTW_DEBUG_USB,
1254 		    "Control request failed, %s (retrying)\n",
1255 		    usbd_errstr(err));
1256 		mtw_delay(sc, 10);
1257 	}
1258 	return (err);
1259 }
1260 
1261 static int
mtw_read(struct mtw_softc * sc,uint16_t reg,uint32_t * val)1262 mtw_read(struct mtw_softc *sc, uint16_t reg, uint32_t *val)
1263 {
1264 	uint32_t tmp;
1265 	int error;
1266 
1267 	error = mtw_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);
1268 	if (error == 0)
1269 		*val = le32toh(tmp);
1270 	else
1271 		*val = 0xffffffff;
1272 	return (error);
1273 }
1274 
1275 static int
mtw_read_region_1(struct mtw_softc * sc,uint16_t reg,uint8_t * buf,int len)1276 mtw_read_region_1(struct mtw_softc *sc, uint16_t reg, uint8_t *buf, int len)
1277 {
1278 	usb_device_request_t req;
1279 
1280 	req.bmRequestType = UT_READ_VENDOR_DEVICE;
1281 	req.bRequest = MTW_READ_REGION_1;
1282 	USETW(req.wValue, 0);
1283 	USETW(req.wIndex, reg);
1284 	USETW(req.wLength, len);
1285 
1286 	return (mtw_do_request(sc, &req, buf));
1287 }
1288 
1289 static int
mtw_write_2(struct mtw_softc * sc,uint16_t reg,uint16_t val)1290 mtw_write_2(struct mtw_softc *sc, uint16_t reg, uint16_t val)
1291 {
1292 
1293 	usb_device_request_t req;
1294 	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1295 	req.bRequest = MTW_WRITE_2;
1296 	USETW(req.wValue, val);
1297 	USETW(req.wIndex, reg);
1298 	USETW(req.wLength, 0);
1299 	return (usbd_do_request(sc->sc_udev, &sc->sc_mtx, &req, NULL));
1300 }
1301 
1302 static int
mtw_write(struct mtw_softc * sc,uint16_t reg,uint32_t val)1303 mtw_write(struct mtw_softc *sc, uint16_t reg, uint32_t val)
1304 {
1305 
1306 	int error;
1307 
1308 	if ((error = mtw_write_2(sc, reg, val & 0xffff)) == 0) {
1309 
1310 		error = mtw_write_2(sc, reg + 2, val >> 16);
1311 	}
1312 
1313 	return (error);
1314 }
1315 
1316 static int
mtw_write_region_1(struct mtw_softc * sc,uint16_t reg,const uint8_t * buf,int len)1317 mtw_write_region_1(struct mtw_softc *sc, uint16_t reg, const uint8_t *buf,
1318     int len)
1319 {
1320 
1321 	usb_device_request_t req;
1322 	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1323 	req.bRequest = MTW_WRITE_REGION_1;
1324 	USETW(req.wValue, 0);
1325 	USETW(req.wIndex, reg);
1326 	USETW(req.wLength, len);
1327 	return (usbd_do_request(sc->sc_udev, &sc->sc_mtx, &req,
1328 	    __DECONST(uint8_t *, buf)));
1329 }
1330 
1331 static int
mtw_set_region_4(struct mtw_softc * sc,uint16_t reg,uint32_t val,int count)1332 mtw_set_region_4(struct mtw_softc *sc, uint16_t reg, uint32_t val, int count)
1333 {
1334 	int i, error = 0;
1335 
1336 	KASSERT((count & 3) == 0, ("mte_set_region_4: Invalid data length.\n"));
1337 	for (i = 0; i < count && error == 0; i += 4)
1338 		error = mtw_write(sc, reg + i, val);
1339 	return (error);
1340 }
1341 
1342 static int
mtw_efuse_read_2(struct mtw_softc * sc,uint16_t addr,uint16_t * val)1343 mtw_efuse_read_2(struct mtw_softc *sc, uint16_t addr, uint16_t *val)
1344 {
1345 
1346 	uint32_t tmp;
1347 	uint16_t reg;
1348 	int error, ntries;
1349 
1350 	if ((error = mtw_read(sc, MTW_EFUSE_CTRL, &tmp)) != 0)
1351 		return (error);
1352 
1353 	addr *= 2;
1354 	/*
1355 	 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1356 	 * DATA0: 3 2 1 0
1357 	 * DATA1: 7 6 5 4
1358 	 * DATA2: B A 9 8
1359 	 * DATA3: F E D C
1360 	 */
1361 	tmp &= ~(MTW_EFSROM_MODE_MASK | MTW_EFSROM_AIN_MASK);
1362 	tmp |= (addr & ~0xf) << MTW_EFSROM_AIN_SHIFT | MTW_EFSROM_KICK;
1363 	mtw_write(sc, MTW_EFUSE_CTRL, tmp);
1364 	for (ntries = 0; ntries < 100; ntries++) {
1365 		if ((error = mtw_read(sc, MTW_EFUSE_CTRL, &tmp)) != 0)
1366 			return (error);
1367 		if (!(tmp & MTW_EFSROM_KICK))
1368 			break;
1369 		DELAY(2);
1370 	}
1371 	if (ntries == 100)
1372 		return (ETIMEDOUT);
1373 
1374 	if ((tmp & MTW_EFUSE_AOUT_MASK) == MTW_EFUSE_AOUT_MASK) {
1375 		*val = 0xffff; // address not found
1376 		return (0);
1377 	}
1378 // determine to which 32-bit register our 16-bit word belongs
1379 	reg = MTW_EFUSE_DATA0 + (addr & 0xc);
1380 	if ((error = mtw_read(sc, reg, &tmp)) != 0)
1381 		return (error);
1382 
1383 	*val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1384 	return (0);
1385 }
1386 
1387 static __inline int
mtw_srom_read(struct mtw_softc * sc,uint16_t addr,uint16_t * val)1388 mtw_srom_read(struct mtw_softc *sc, uint16_t addr, uint16_t *val)
1389 {
1390 	/* either eFUSE ROM or EEPROM */
1391 	return (sc->sc_srom_read(sc, addr, val));
1392 }
1393 
1394 static int
mtw_bbp_read(struct mtw_softc * sc,uint8_t reg,uint8_t * val)1395 mtw_bbp_read(struct mtw_softc *sc, uint8_t reg, uint8_t *val)
1396 {
1397 	uint32_t tmp;
1398 	int ntries, error;
1399 
1400 	for (ntries = 0; ntries < 10; ntries++) {
1401 		if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
1402 			return (error);
1403 		if (!(tmp & MTW_BBP_CSR_KICK))
1404 			break;
1405 	}
1406 	if (ntries == 10)
1407 		return (ETIMEDOUT);
1408 
1409 	tmp = MTW_BBP_CSR_READ | MTW_BBP_CSR_KICK | reg << 8;
1410 	if ((error = mtw_write(sc, MTW_BBP_CSR, tmp)) != 0)
1411 		return (error);
1412 
1413 	for (ntries = 0; ntries < 10; ntries++) {
1414 		if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
1415 			return (error);
1416 		if (!(tmp & MTW_BBP_CSR_KICK))
1417 			break;
1418 	}
1419 	if (ntries == 10)
1420 		return (ETIMEDOUT);
1421 
1422 	*val = tmp & 0xff;
1423 	return (0);
1424 }
1425 
1426 static int
mtw_bbp_write(struct mtw_softc * sc,uint8_t reg,uint8_t val)1427 mtw_bbp_write(struct mtw_softc *sc, uint8_t reg, uint8_t val)
1428 {
1429 	uint32_t tmp;
1430 	int ntries, error;
1431 
1432 	for (ntries = 0; ntries < 10; ntries++) {
1433 		if ((error = mtw_read(sc, MTW_BBP_CSR, &tmp)) != 0)
1434 			return (error);
1435 		if (!(tmp & MTW_BBP_CSR_KICK))
1436 			break;
1437 	}
1438 	if (ntries == 10)
1439 		return (ETIMEDOUT);
1440 
1441 	tmp = MTW_BBP_CSR_KICK | reg << 8 | val;
1442 	return (mtw_write(sc, MTW_BBP_CSR, tmp));
1443 }
1444 
1445 static int
mtw_mcu_cmd(struct mtw_softc * sc,u_int8_t cmd,void * buf,int len)1446 mtw_mcu_cmd(struct mtw_softc *sc, u_int8_t cmd, void *buf, int len)
1447 {
1448 	sc->sc_idx = 0;
1449 	sc->txd_fw[sc->sc_idx]->len = htole16(
1450 	    len + 8);
1451 	sc->txd_fw[sc->sc_idx]->flags = htole16(MTW_TXD_CMD | MTW_TXD_MCU |
1452 	    (cmd & 0x1f) << MTW_TXD_CMD_SHIFT | (0 & 0xf));
1453 
1454 	memset(&sc->txd_fw[sc->sc_idx]->fw, 0, 2004);
1455 	memcpy(&sc->txd_fw[sc->sc_idx]->fw, buf, len);
1456 	usbd_transfer_start(sc->sc_xfer[7]);
1457 	return (0);
1458 }
1459 
1460 /*
1461  * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
1462  * Used to adjust per-rate Tx power registers.
1463  */
1464 static __inline uint32_t
b4inc(uint32_t b32,int8_t delta)1465 b4inc(uint32_t b32, int8_t delta)
1466 {
1467 	int8_t i, b4;
1468 
1469 	for (i = 0; i < 8; i++) {
1470 		b4 = b32 & 0xf;
1471 		b4 += delta;
1472 		if (b4 < 0)
1473 			b4 = 0;
1474 		else if (b4 > 0xf)
1475 			b4 = 0xf;
1476 		b32 = b32 >> 4 | b4 << 28;
1477 	}
1478 	return (b32);
1479 }
1480 static void
mtw_get_txpower(struct mtw_softc * sc)1481 mtw_get_txpower(struct mtw_softc *sc)
1482 {
1483 	uint16_t val;
1484 	int i;
1485 
1486 	/* Read power settings for 2GHz channels. */
1487 	for (i = 0; i < 14; i += 2) {
1488 		mtw_srom_read(sc, MTW_EEPROM_PWR2GHZ_BASE1 + i / 2, &val);
1489 		sc->txpow1[i + 0] = (int8_t)(val & 0xff);
1490 		sc->txpow1[i + 1] = (int8_t)(val >> 8);
1491 		mtw_srom_read(sc, MTW_EEPROM_PWR2GHZ_BASE2 + i / 2, &val);
1492 		sc->txpow2[i + 0] = (int8_t)(val & 0xff);
1493 		sc->txpow2[i + 1] = (int8_t)(val >> 8);
1494 	}
1495 	/* Fix broken Tx power entries. */
1496 	for (i = 0; i < 14; i++) {
1497 		if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27)
1498 			sc->txpow1[i] = 5;
1499 		if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27)
1500 			sc->txpow2[i] = 5;
1501 		MTW_DPRINTF(sc, MTW_DEBUG_TXPWR,
1502 		"chan %d: power1=%d, power2=%d\n", mt7601_rf_chan[i].chan,
1503 		sc->txpow1[i], sc->txpow2[i]);
1504 	}
1505 }
1506 
1507 struct ieee80211_node *
mtw_node_alloc(struct ieee80211vap * vap,const uint8_t mac[IEEE80211_ADDR_LEN])1508 mtw_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
1509 {
1510 	return (malloc(sizeof(struct mtw_node), M_80211_NODE,
1511 		M_NOWAIT | M_ZERO));
1512 }
1513 static int
mtw_read_eeprom(struct mtw_softc * sc)1514 mtw_read_eeprom(struct mtw_softc *sc)
1515 {
1516 	struct ieee80211com *ic = &sc->sc_ic;
1517 	int8_t delta_2ghz, delta_5ghz;
1518 	uint16_t val;
1519 	int ridx, ant;
1520 
1521 	sc->sc_srom_read = mtw_efuse_read_2;
1522 
1523 	/* read RF information */
1524 	mtw_srom_read(sc, MTW_EEPROM_CHIPID, &val);
1525 	sc->rf_rev = val;
1526 	mtw_srom_read(sc, MTW_EEPROM_ANTENNA, &val);
1527 	sc->ntxchains = (val >> 4) & 0xf;
1528 	sc->nrxchains = val & 0xf;
1529 	MTW_DPRINTF(sc, MTW_DEBUG_ROM, "EEPROM RF rev=0x%02x chains=%dT%dR\n",
1530 	    sc->rf_rev, sc->ntxchains, sc->nrxchains);
1531 
1532 	/* read ROM version */
1533 	mtw_srom_read(sc, MTW_EEPROM_VERSION, &val);
1534 	MTW_DPRINTF(sc, MTW_DEBUG_ROM, "EEPROM rev=%d, FAE=%d\n", val & 0xff,
1535 	    val >> 8);
1536 
1537 	/* read MAC address */
1538 	mtw_srom_read(sc, MTW_EEPROM_MAC01, &val);
1539 	ic->ic_macaddr[0] = val & 0xff;
1540 	ic->ic_macaddr[1] = val >> 8;
1541 	mtw_srom_read(sc, MTW_EEPROM_MAC23, &val);
1542 	ic->ic_macaddr[2] = val & 0xff;
1543 	ic->ic_macaddr[3] = val >> 8;
1544 	mtw_srom_read(sc, MTW_EEPROM_MAC45, &val);
1545 	ic->ic_macaddr[4] = val & 0xff;
1546 	ic->ic_macaddr[5] = val >> 8;
1547 #if 0
1548 	printf("eFUSE ROM\n00: ");
1549 	for (int i = 0; i < 256; i++) {
1550 		if (((i % 8) == 0) && i > 0)
1551 			printf("\n%02x: ", i);
1552 		mtw_srom_read(sc, i, &val);
1553 		printf(" %04x", val);
1554 	}
1555 	printf("\n");
1556 #endif
1557 	/* check if RF supports automatic Tx access gain control */
1558 	mtw_srom_read(sc, MTW_EEPROM_CONFIG, &val);
1559 	device_printf(sc->sc_dev, "EEPROM CFG 0x%04x\n", val);
1560 	if ((val & 0xff) != 0xff) {
1561 		sc->ext_5ghz_lna = (val >> 3) & 1;
1562 		sc->ext_2ghz_lna = (val >> 2) & 1;
1563 		/* check if RF supports automatic Tx access gain control */
1564 		sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1;
1565 		/* check if we have a hardware radio switch */
1566 		sc->rfswitch = val & 1;
1567 	}
1568 
1569 	/* read RF frequency offset from EEPROM */
1570 	mtw_srom_read(sc, MTW_EEPROM_FREQ_OFFSET, &val);
1571 	if ((val & 0xff) != 0xff)
1572 		sc->rf_freq_offset = val;
1573 	else
1574 		sc->rf_freq_offset = 0;
1575 	MTW_DPRINTF(sc, MTW_DEBUG_ROM, "frequency offset 0x%x\n",
1576 	    sc->rf_freq_offset);
1577 
1578 	/* Read Tx power settings. */
1579 	mtw_get_txpower(sc);
1580 
1581 	/* read Tx power compensation for each Tx rate */
1582 	mtw_srom_read(sc, MTW_EEPROM_DELTAPWR, &val);
1583 	delta_2ghz = delta_5ghz = 0;
1584 	if ((val & 0xff) != 0xff && (val & 0x80)) {
1585 		delta_2ghz = val & 0xf;
1586 		if (!(val & 0x40)) /* negative number */
1587 			delta_2ghz = -delta_2ghz;
1588 	}
1589 	val >>= 8;
1590 	if ((val & 0xff) != 0xff && (val & 0x80)) {
1591 		delta_5ghz = val & 0xf;
1592 		if (!(val & 0x40)) /* negative number */
1593 			delta_5ghz = -delta_5ghz;
1594 	}
1595 	MTW_DPRINTF(sc, MTW_DEBUG_ROM | MTW_DEBUG_TXPWR,
1596 	    "power compensation=%d (2GHz), %d (5GHz)\n", delta_2ghz,
1597 	    delta_5ghz);
1598 
1599 	for (ridx = 0; ridx < 5; ridx++) {
1600 		uint32_t reg;
1601 
1602 		mtw_srom_read(sc, MTW_EEPROM_RPWR + ridx * 2, &val);
1603 		reg = val;
1604 		mtw_srom_read(sc, MTW_EEPROM_RPWR + ridx * 2 + 1, &val);
1605 		reg |= (uint32_t)val << 16;
1606 
1607 		sc->txpow20mhz[ridx] = reg;
1608 		sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
1609 		sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
1610 
1611 		MTW_DPRINTF(sc, MTW_DEBUG_ROM | MTW_DEBUG_TXPWR,
1612 		    "ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
1613 		    "40MHz/5GHz=0x%08x\n",
1614 		    ridx, sc->txpow20mhz[ridx], sc->txpow40mhz_2ghz[ridx],
1615 		    sc->txpow40mhz_5ghz[ridx]);
1616 	}
1617 
1618 	/* read RSSI offsets and LNA gains from EEPROM */
1619 	val = 0;
1620 	mtw_srom_read(sc, MTW_EEPROM_RSSI1_2GHZ, &val);
1621 	sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
1622 	sc->rssi_2ghz[1] = val >> 8;   /* Ant B */
1623 	mtw_srom_read(sc, MTW_EEPROM_RSSI2_2GHZ, &val);
1624 	/*
1625 	 * On RT3070 chips (limited to 2 Rx chains), this ROM
1626 	 * field contains the Tx mixer gain for the 2GHz band.
1627 	 */
1628 	if ((val & 0xff) != 0xff)
1629 		sc->txmixgain_2ghz = val & 0x7;
1630 	MTW_DPRINTF(sc, MTW_DEBUG_ROM, "tx mixer gain=%u (2GHz)\n",
1631 	    sc->txmixgain_2ghz);
1632 	sc->lna[2] = val >> 8; /* channel group 2 */
1633 	mtw_srom_read(sc, MTW_EEPROM_RSSI1_5GHZ, &val);
1634 	sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
1635 	sc->rssi_5ghz[1] = val >> 8;   /* Ant B */
1636 	mtw_srom_read(sc, MTW_EEPROM_RSSI2_5GHZ, &val);
1637 	sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
1638 
1639 	sc->lna[3] = val >> 8; /* channel group 3 */
1640 
1641 	mtw_srom_read(sc, MTW_EEPROM_LNA, &val);
1642 	sc->lna[0] = val & 0xff; /* channel group 0 */
1643 	sc->lna[1] = val >> 8;	 /* channel group 1 */
1644 	MTW_DPRINTF(sc, MTW_DEBUG_ROM, "LNA0 0x%x\n", sc->lna[0]);
1645 
1646 	/* fix broken 5GHz LNA entries */
1647 	if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
1648 		MTW_DPRINTF(sc, MTW_DEBUG_ROM,
1649 		    "invalid LNA for channel group %d\n", 2);
1650 		sc->lna[2] = sc->lna[1];
1651 	}
1652 	if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
1653 		MTW_DPRINTF(sc, MTW_DEBUG_ROM,
1654 		    "invalid LNA for channel group %d\n", 3);
1655 		sc->lna[3] = sc->lna[1];
1656 	}
1657 
1658 	/* fix broken RSSI offset entries */
1659 	for (ant = 0; ant < 3; ant++) {
1660 		if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
1661 			MTW_DPRINTF(sc, MTW_DEBUG_ROM,
1662 			    "invalid RSSI%d offset: %d (2GHz)\n", ant + 1,
1663 			    sc->rssi_2ghz[ant]);
1664 			sc->rssi_2ghz[ant] = 0;
1665 		}
1666 		if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
1667 			MTW_DPRINTF(sc, MTW_DEBUG_ROM,
1668 			    "invalid RSSI%d offset: %d (5GHz)\n", ant + 1,
1669 			    sc->rssi_5ghz[ant]);
1670 			sc->rssi_5ghz[ant] = 0;
1671 		}
1672 	}
1673 	return (0);
1674 }
1675 static int
mtw_media_change(if_t ifp)1676 mtw_media_change(if_t ifp)
1677 {
1678 	struct ieee80211vap *vap = if_getsoftc(ifp);
1679 	struct ieee80211com *ic = vap->iv_ic;
1680 	const struct ieee80211_txparam *tp;
1681 	struct mtw_softc *sc = ic->ic_softc;
1682 	uint8_t rate, ridx;
1683 
1684 	MTW_LOCK(sc);
1685 	ieee80211_media_change(ifp);
1686 	//tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
1687 	tp = &vap->iv_txparms[ic->ic_curmode];
1688 	if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1689 		struct ieee80211_node *ni;
1690 		struct mtw_node	*rn;
1691 		/* XXX TODO: methodize with MCS rates */
1692 		rate =
1693 		    ic->ic_sup_rates[ic->ic_curmode].rs_rates[tp->ucastrate] &
1694 		    IEEE80211_RATE_VAL;
1695 		for (ridx = 0; ridx < MTW_RIDX_MAX; ridx++) {
1696 			if (rt2860_rates[ridx].rate == rate)
1697 				break;
1698 		}
1699 		ni = ieee80211_ref_node(vap->iv_bss);
1700 		rn = MTW_NODE(ni);
1701 		rn->fix_ridx = ridx;
1702 
1703 		MTW_DPRINTF(sc, MTW_DEBUG_RATE, "rate=%d, fix_ridx=%d\n", rate,
1704 		    rn->fix_ridx);
1705 		ieee80211_free_node(ni);
1706 	}
1707 	MTW_UNLOCK(sc);
1708 
1709 	return (0);
1710 }
1711 
1712 void
mtw_set_leds(struct mtw_softc * sc,uint16_t which)1713 mtw_set_leds(struct mtw_softc *sc, uint16_t which)
1714 {
1715 	struct mtw_mcu_cmd_8 cmd;
1716 	cmd.func = htole32(0x1);
1717 	cmd.val = htole32(which);
1718 	mtw_mcu_cmd(sc, CMD_LED_MODE, &cmd, sizeof(struct mtw_mcu_cmd_8));
1719 }
1720 static void
mtw_abort_tsf_sync(struct mtw_softc * sc)1721 mtw_abort_tsf_sync(struct mtw_softc *sc)
1722 {
1723 	uint32_t tmp;
1724 
1725 	mtw_read(sc, MTW_BCN_TIME_CFG, &tmp);
1726 	tmp &= ~(MTW_BCN_TX_EN | MTW_TSF_TIMER_EN | MTW_TBTT_TIMER_EN);
1727 	mtw_write(sc, MTW_BCN_TIME_CFG, tmp);
1728 }
1729 static int
mtw_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1730 mtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1731 {
1732 	const struct ieee80211_txparam *tp;
1733 	struct ieee80211com *ic = vap->iv_ic;
1734 	struct mtw_softc *sc = ic->ic_softc;
1735 	struct mtw_vap *rvp = MTW_VAP(vap);
1736 	enum ieee80211_state ostate;
1737 	uint32_t sta[3];
1738 	uint8_t ratectl = 0;
1739 	uint8_t restart_ratectl = 0;
1740 	uint8_t bid = 1 << rvp->rvp_id;
1741 
1742 
1743 	ostate = vap->iv_state;
1744 	MTW_DPRINTF(sc, MTW_DEBUG_STATE, "%s -> %s\n",
1745 	    ieee80211_state_name[ostate], ieee80211_state_name[nstate]);
1746 	IEEE80211_UNLOCK(ic);
1747 	MTW_LOCK(sc);
1748 	ratectl = sc->ratectl_run; /* remember current state */
1749 	usb_callout_stop(&sc->ratectl_ch);
1750 	sc->ratectl_run = MTW_RATECTL_OFF;
1751 	if (ostate == IEEE80211_S_RUN) {
1752 		/* turn link LED off */
1753 	}
1754 
1755 	switch (nstate) {
1756 	case IEEE80211_S_INIT:
1757 	restart_ratectl = 1;
1758 		if (ostate != IEEE80211_S_RUN)
1759 			break;
1760 
1761 		ratectl &= ~bid;
1762 		sc->runbmap &= ~bid;
1763 
1764 		/* abort TSF synchronization if there is no vap running  */
1765 		if (--sc->running == 0)
1766 			mtw_abort_tsf_sync(sc);
1767 		break;
1768 
1769 	case IEEE80211_S_RUN:
1770 		if (!(sc->runbmap & bid)) {
1771 			if (sc->running++)
1772 				restart_ratectl = 1;
1773 			sc->runbmap |= bid;
1774 		}
1775 
1776 		m_freem(rvp->beacon_mbuf);
1777 		rvp->beacon_mbuf = NULL;
1778 
1779 		switch (vap->iv_opmode) {
1780 		case IEEE80211_M_HOSTAP:
1781 		case IEEE80211_M_MBSS:
1782 			sc->ap_running |= bid;
1783 			ic->ic_opmode = vap->iv_opmode;
1784 			mtw_update_beacon_cb(vap);
1785 			break;
1786 		case IEEE80211_M_IBSS:
1787 			sc->adhoc_running |= bid;
1788 			if (!sc->ap_running)
1789 				ic->ic_opmode = vap->iv_opmode;
1790 			mtw_update_beacon_cb(vap);
1791 			break;
1792 		case IEEE80211_M_STA:
1793 			sc->sta_running |= bid;
1794 			if (!sc->ap_running && !sc->adhoc_running)
1795 				ic->ic_opmode = vap->iv_opmode;
1796 
1797 			/* read statistic counters (clear on read) */
1798 			mtw_read_region_1(sc, MTW_TX_STA_CNT0, (uint8_t *)sta,
1799 			    sizeof sta);
1800 
1801 			break;
1802 		default:
1803 			ic->ic_opmode = vap->iv_opmode;
1804 			break;
1805 		}
1806 
1807 		if (vap->iv_opmode != IEEE80211_M_MONITOR) {
1808 			struct ieee80211_node *ni;
1809 
1810 			if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) {
1811 				MTW_UNLOCK(sc);
1812 				IEEE80211_LOCK(ic);
1813 				return (-1);
1814 			}
1815 			mtw_updateslot(ic);
1816 			mtw_enable_mrr(sc);
1817 			mtw_set_txpreamble(sc);
1818 			mtw_set_basicrates(sc);
1819 			ni = ieee80211_ref_node(vap->iv_bss);
1820 			IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid);
1821 			mtw_set_bssid(sc, sc->sc_bssid);
1822 			ieee80211_free_node(ni);
1823 			mtw_enable_tsf_sync(sc);
1824 
1825 			/* enable automatic rate adaptation */
1826 			tp = &vap->iv_txparms[ieee80211_chan2mode(
1827 			    ic->ic_curchan)];
1828 			if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE)
1829 				ratectl |= bid;
1830 		} else {
1831 		mtw_enable_tsf_sync(sc);
1832 		}
1833 
1834 		break;
1835 	default:
1836 		MTW_DPRINTF(sc, MTW_DEBUG_STATE, "undefined state\n");
1837 		break;
1838 	}
1839 
1840 	/* restart amrr for running VAPs */
1841 	if ((sc->ratectl_run = ratectl) && restart_ratectl) {
1842 		usb_callout_reset(&sc->ratectl_ch, hz, mtw_ratectl_to, sc);
1843 	}
1844 	MTW_UNLOCK(sc);
1845 	IEEE80211_LOCK(ic);
1846 	return (rvp->newstate(vap, nstate, arg));
1847 }
1848 
1849 static int
mtw_wme_update(struct ieee80211com * ic)1850 mtw_wme_update(struct ieee80211com *ic)
1851 {
1852 	struct chanAccParams chp;
1853 	struct mtw_softc *sc = ic->ic_softc;
1854 	const struct wmeParams *ac;
1855 	int aci, error = 0;
1856 	ieee80211_wme_ic_getparams(ic, &chp);
1857 	ac = chp.cap_wmeParams;
1858 
1859 	MTW_LOCK(sc);
1860 	/* update MAC TX configuration registers */
1861 	for (aci = 0; aci < WME_NUM_AC; aci++) {
1862 		error = mtw_write(sc, MTW_EDCA_AC_CFG(aci),
1863 		    ac[aci].wmep_logcwmax << 16 | ac[aci].wmep_logcwmin << 12 |
1864 			ac[aci].wmep_aifsn << 8 | ac[aci].wmep_txopLimit);
1865 		if (error)
1866 			goto err;
1867 	}
1868 
1869 	/* update SCH/DMA registers too */
1870 	error = mtw_write(sc, MTW_WMM_AIFSN_CFG,
1871 	    ac[WME_AC_VO].wmep_aifsn << 12 | ac[WME_AC_VI].wmep_aifsn << 8 |
1872 		ac[WME_AC_BK].wmep_aifsn << 4 | ac[WME_AC_BE].wmep_aifsn);
1873 	if (error)
1874 		goto err;
1875 	error = mtw_write(sc, MTW_WMM_CWMIN_CFG,
1876 	    ac[WME_AC_VO].wmep_logcwmin << 12 |
1877 		ac[WME_AC_VI].wmep_logcwmin << 8 |
1878 		ac[WME_AC_BK].wmep_logcwmin << 4 | ac[WME_AC_BE].wmep_logcwmin);
1879 	if (error)
1880 		goto err;
1881 	error = mtw_write(sc, MTW_WMM_CWMAX_CFG,
1882 	    ac[WME_AC_VO].wmep_logcwmax << 12 |
1883 		ac[WME_AC_VI].wmep_logcwmax << 8 |
1884 		ac[WME_AC_BK].wmep_logcwmax << 4 | ac[WME_AC_BE].wmep_logcwmax);
1885 	if (error)
1886 		goto err;
1887 	error = mtw_write(sc, MTW_WMM_TXOP0_CFG,
1888 	    ac[WME_AC_BK].wmep_txopLimit << 16 | ac[WME_AC_BE].wmep_txopLimit);
1889 	if (error)
1890 		goto err;
1891 	error = mtw_write(sc, MTW_WMM_TXOP1_CFG,
1892 	    ac[WME_AC_VO].wmep_txopLimit << 16 | ac[WME_AC_VI].wmep_txopLimit);
1893 
1894 err:
1895 	MTW_UNLOCK(sc);
1896 	if (error)
1897 		MTW_DPRINTF(sc, MTW_DEBUG_USB, "WME update failed\n");
1898 
1899 	return (error);
1900 }
1901 
1902 static int
mtw_key_set(struct ieee80211vap * vap,struct ieee80211_key * k)1903 mtw_key_set(struct ieee80211vap *vap, struct ieee80211_key *k)
1904 {
1905 	struct ieee80211com *ic = vap->iv_ic;
1906 	struct mtw_softc *sc = ic->ic_softc;
1907 	uint32_t i;
1908 
1909 	i = MTW_CMDQ_GET(&sc->cmdq_store);
1910 	MTW_DPRINTF(sc, MTW_DEBUG_KEY, "cmdq_store=%d\n", i);
1911 	sc->cmdq[i].func = mtw_key_set_cb;
1912 	sc->cmdq[i].arg0 = NULL;
1913 	sc->cmdq[i].arg1 = vap;
1914 	sc->cmdq[i].k = k;
1915 	IEEE80211_ADDR_COPY(sc->cmdq[i].mac, k->wk_macaddr);
1916 	ieee80211_runtask(ic, &sc->cmdq_task);
1917 
1918 	/*
1919 	 * To make sure key will be set when hostapd
1920 	 * calls iv_key_set() before if_init().
1921 	 */
1922 	if (vap->iv_opmode == IEEE80211_M_HOSTAP) {
1923 		MTW_LOCK(sc);
1924 		sc->cmdq_key_set = MTW_CMDQ_GO;
1925 		MTW_UNLOCK(sc);
1926 	}
1927 
1928 	return (1);
1929 }
1930 static void
mtw_key_set_cb(void * arg)1931 mtw_key_set_cb(void *arg)
1932 {
1933 	struct mtw_cmdq *cmdq = arg;
1934 	struct ieee80211vap *vap = cmdq->arg1;
1935 	struct ieee80211_key *k = cmdq->k;
1936 	struct ieee80211com *ic = vap->iv_ic;
1937 	struct mtw_softc *sc = ic->ic_softc;
1938 	struct ieee80211_node *ni;
1939 	u_int cipher = k->wk_cipher->ic_cipher;
1940 	uint32_t attr;
1941 	uint16_t base;
1942 	uint8_t mode, wcid, iv[8];
1943 	MTW_LOCK_ASSERT(sc, MA_OWNED);
1944 
1945 	if (vap->iv_opmode == IEEE80211_M_HOSTAP)
1946 		ni = ieee80211_find_vap_node(&ic->ic_sta, vap, cmdq->mac);
1947 	else
1948 		ni = vap->iv_bss;
1949 
1950 	/* map net80211 cipher to RT2860 security mode */
1951 	switch (cipher) {
1952 	case IEEE80211_CIPHER_WEP:
1953 		if (ieee80211_crypto_get_key_len(k) < 8)
1954 			mode = MTW_MODE_WEP40;
1955 		else
1956 			mode = MTW_MODE_WEP104;
1957 		break;
1958 	case IEEE80211_CIPHER_TKIP:
1959 		mode = MTW_MODE_TKIP;
1960 		break;
1961 	case IEEE80211_CIPHER_AES_CCM:
1962 		mode = MTW_MODE_AES_CCMP;
1963 		break;
1964 	default:
1965 		MTW_DPRINTF(sc, MTW_DEBUG_KEY, "undefined case\n");
1966 		return;
1967 	}
1968 
1969 	if (k->wk_flags & IEEE80211_KEY_GROUP) {
1970 		wcid = 0; /* NB: update WCID0 for group keys */
1971 		base = MTW_SKEY(0, k->wk_keyix);
1972 	} else {
1973 		wcid = (ni != NULL) ? MTW_AID2WCID(ni->ni_associd) : 0;
1974 		base = MTW_PKEY(wcid);
1975 	}
1976 
1977 	if (cipher == IEEE80211_CIPHER_TKIP) {
1978 		/* TODO: note the direct use of tx/rx mic offsets! ew! */
1979 		mtw_write_region_1(sc, base,
1980 		    ieee80211_crypto_get_key_data(k), 16);
1981 		/* rxmic */
1982 		mtw_write_region_1(sc, base + 16,
1983 		    ieee80211_crypto_get_key_rxmic_data(k), 8);
1984 		/* txmic */
1985 		mtw_write_region_1(sc, base + 24,
1986 		    ieee80211_crypto_get_key_txmic_data(k), 8);
1987 	} else {
1988 		/* roundup len to 16-bit: XXX fix write_region_1() instead */
1989 		mtw_write_region_1(sc, base, k->wk_key,
1990 		    (ieee80211_crypto_get_key_len(k) + 1) & ~1);
1991 	}
1992 
1993 	if (!(k->wk_flags & IEEE80211_KEY_GROUP) ||
1994 	    (k->wk_flags & (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV))) {
1995 		/* set initial packet number in IV+EIV */
1996 		if (cipher == IEEE80211_CIPHER_WEP) {
1997 			memset(iv, 0, sizeof iv);
1998 			iv[3] = vap->iv_def_txkey << 6;
1999 		} else {
2000 			if (cipher == IEEE80211_CIPHER_TKIP) {
2001 				iv[0] = k->wk_keytsc >> 8;
2002 				iv[1] = (iv[0] | 0x20) & 0x7f;
2003 				iv[2] = k->wk_keytsc;
2004 			} else  { //CCMP
2005 				iv[0] = k->wk_keytsc;
2006 				iv[1] = k->wk_keytsc >> 8;
2007 				iv[2] = 0;
2008 			}
2009 			iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV;
2010 			iv[4] = k->wk_keytsc >> 16;
2011 			iv[5] = k->wk_keytsc >> 24;
2012 			iv[6] = k->wk_keytsc >> 32;
2013 			iv[7] = k->wk_keytsc >> 40;
2014 		}
2015 		mtw_write_region_1(sc, MTW_IVEIV(wcid), iv, 8);
2016 	}
2017 
2018 	if (k->wk_flags & IEEE80211_KEY_GROUP) {
2019 		/* install group key */
2020 		mtw_read(sc, MTW_SKEY_MODE_0_7, &attr);
2021 		attr &= ~(0xf << (k->wk_keyix * 4));
2022 		attr |= mode << (k->wk_keyix * 4);
2023 		mtw_write(sc, MTW_SKEY_MODE_0_7, attr);
2024 
2025 		if (cipher & (IEEE80211_CIPHER_WEP)) {
2026 			mtw_read(sc, MTW_WCID_ATTR(wcid + 1), &attr);
2027 			attr = (attr & ~0xf) | (mode << 1);
2028 			mtw_write(sc, MTW_WCID_ATTR(wcid + 1), attr);
2029 
2030 			mtw_set_region_4(sc, MTW_IVEIV(0), 0, 4);
2031 
2032 			mtw_read(sc, MTW_WCID_ATTR(wcid), &attr);
2033 			attr = (attr & ~0xf) | (mode << 1);
2034 			mtw_write(sc, MTW_WCID_ATTR(wcid), attr);
2035 		}
2036 	} else {
2037 		/* install pairwise key */
2038 		mtw_read(sc, MTW_WCID_ATTR(wcid), &attr);
2039 		attr = (attr & ~0xf) | (mode << 1) | MTW_RX_PKEY_EN;
2040 		mtw_write(sc, MTW_WCID_ATTR(wcid), attr);
2041 	}
2042 	k->wk_pad = wcid;
2043 }
2044 
2045 /*
2046  * If wlan is destroyed without being brought down i.e. without
2047  * wlan down or wpa_cli terminate, this function is called after
2048  * vap is gone. Don't refer it.
2049  */
2050 static void
mtw_key_delete_cb(void * arg)2051 mtw_key_delete_cb(void *arg)
2052 {
2053 	struct mtw_cmdq *cmdq = arg;
2054 	struct mtw_softc *sc = cmdq->arg1;
2055 	struct ieee80211_key *k = &cmdq->key;
2056 	uint32_t attr;
2057 	uint8_t wcid;
2058 
2059 	MTW_LOCK_ASSERT(sc, MA_OWNED);
2060 
2061 	if (k->wk_flags & IEEE80211_KEY_GROUP) {
2062 		/* remove group key */
2063 		MTW_DPRINTF(sc, MTW_DEBUG_KEY, "removing group key\n");
2064 		mtw_read(sc, MTW_SKEY_MODE_0_7, &attr);
2065 		attr &= ~(0xf << (k->wk_keyix * 4));
2066 		mtw_write(sc, MTW_SKEY_MODE_0_7, attr);
2067 	} else {
2068 		/* remove pairwise key */
2069 		MTW_DPRINTF(sc, MTW_DEBUG_KEY, "removing key for wcid %x\n",
2070 		    k->wk_pad);
2071 		/* matching wcid was written to wk_pad in mtw_key_set() */
2072 		wcid = k->wk_pad;
2073 		mtw_read(sc, MTW_WCID_ATTR(wcid), &attr);
2074 		attr &= ~0xf;
2075 		mtw_write(sc, MTW_WCID_ATTR(wcid), attr);
2076 	}
2077 
2078 	k->wk_pad = 0;
2079 }
2080 
2081 /*
2082  * return 0 on error
2083  */
2084 static int
mtw_key_delete(struct ieee80211vap * vap,struct ieee80211_key * k)2085 mtw_key_delete(struct ieee80211vap *vap, struct ieee80211_key *k)
2086 {
2087 	struct ieee80211com *ic = vap->iv_ic;
2088 	struct mtw_softc *sc = ic->ic_softc;
2089 	struct ieee80211_key *k0;
2090 	uint32_t i;
2091 	if (sc->sc_flags & MTW_RUNNING)
2092 		return (1);
2093 
2094 	/*
2095 	 * When called back, key might be gone. So, make a copy
2096 	 * of some values need to delete keys before deferring.
2097 	 * But, because of LOR with node lock, cannot use lock here.
2098 	 * So, use atomic instead.
2099 	 */
2100 	i = MTW_CMDQ_GET(&sc->cmdq_store);
2101 	MTW_DPRINTF(sc, MTW_DEBUG_KEY, "cmdq_store=%d\n", i);
2102 	sc->cmdq[i].func = mtw_key_delete_cb;
2103 	sc->cmdq[i].arg0 = NULL;
2104 	sc->cmdq[i].arg1 = sc;
2105 	k0 = &sc->cmdq[i].key;
2106 	k0->wk_flags = k->wk_flags;
2107 	k0->wk_keyix = k->wk_keyix;
2108 	/* matching wcid was written to wk_pad in mtw_key_set() */
2109 	k0->wk_pad = k->wk_pad;
2110 	ieee80211_runtask(ic, &sc->cmdq_task);
2111 	return (1); /* return fake success */
2112 }
2113 
2114 static void
mtw_ratectl_to(void * arg)2115 mtw_ratectl_to(void *arg)
2116 {
2117 	struct mtw_softc *sc = arg;
2118 	/* do it in a process context, so it can go sleep */
2119 	ieee80211_runtask(&sc->sc_ic, &sc->ratectl_task);
2120 	/* next timeout will be rescheduled in the callback task */
2121 }
2122 
2123 /* ARGSUSED */
2124 static void
mtw_ratectl_cb(void * arg,int pending)2125 mtw_ratectl_cb(void *arg, int pending)
2126 {
2127 
2128 	struct mtw_softc *sc = arg;
2129 	struct ieee80211com *ic = &sc->sc_ic;
2130 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2131 
2132 	if (vap == NULL)
2133 		return;
2134 
2135 	ieee80211_iterate_nodes(&ic->ic_sta, mtw_iter_func, sc);
2136 
2137 	usb_callout_reset(&sc->ratectl_ch, hz, mtw_ratectl_to, sc);
2138 
2139 
2140 }
2141 
2142 static void
mtw_drain_fifo(void * arg)2143 mtw_drain_fifo(void *arg)
2144 {
2145 	struct mtw_softc *sc = arg;
2146 	uint32_t stat;
2147 	uint16_t(*wstat)[3];
2148 	uint8_t wcid, mcs, pid;
2149 	int8_t retry;
2150 
2151 	MTW_LOCK_ASSERT(sc, MA_OWNED);
2152 
2153 	for (;;) {
2154 		/* drain Tx status FIFO (maxsize = 16) */
2155 		mtw_read(sc, MTW_TX_STAT_FIFO, &stat);
2156 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "tx stat 0x%08x\n", stat);
2157 		if (!(stat & MTW_TXQ_VLD))
2158 			break;
2159 
2160 		wcid = (stat >> MTW_TXQ_WCID_SHIFT) & 0xff;
2161 
2162 		/* if no ACK was requested, no feedback is available */
2163 		if (!(stat & MTW_TXQ_ACKREQ) || wcid > MTW_WCID_MAX ||
2164 		    wcid == 0)
2165 			continue;
2166 
2167 		/*
2168 		 * Even though each stat is Tx-complete-status like format,
2169 		 * the device can poll stats. Because there is no guarantee
2170 		 * that the referring node is still around when read the stats.
2171 		 * So that, if we use ieee80211_ratectl_tx_update(), we will
2172 		 * have hard time not to refer already freed node.
2173 		 *
2174 		 * To eliminate such page faults, we poll stats in softc.
2175 		 * Then, update the rates later with
2176 		 * ieee80211_ratectl_tx_update().
2177 		 */
2178 		wstat = &(sc->wcid_stats[wcid]);
2179 		(*wstat)[MTW_TXCNT]++;
2180 		if (stat & MTW_TXQ_OK)
2181 			(*wstat)[MTW_SUCCESS]++;
2182 		else
2183 			counter_u64_add(sc->sc_ic.ic_oerrors, 1);
2184 		/*
2185 		 * Check if there were retries, ie if the Tx success rate is
2186 		 * different from the requested rate. Note that it works only
2187 		 * because we do not allow rate fallback from OFDM to CCK.
2188 		 */
2189 		mcs = (stat >> MTW_TXQ_MCS_SHIFT) & 0x7f;
2190 		pid = (stat >> MTW_TXQ_PID_SHIFT) & 0xf;
2191 		if ((retry = pid - 1 - mcs) > 0) {
2192 			(*wstat)[MTW_TXCNT] += retry;
2193 			(*wstat)[MTW_RETRY] += retry;
2194 		}
2195 	}
2196 	MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "count=%d\n", sc->fifo_cnt);
2197 
2198 	sc->fifo_cnt = 0;
2199 }
2200 
2201 static void
mtw_iter_func(void * arg,struct ieee80211_node * ni)2202 mtw_iter_func(void *arg, struct ieee80211_node *ni)
2203 {
2204 	struct mtw_softc *sc = arg;
2205 	MTW_LOCK(sc);
2206 	struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs;
2207 	struct ieee80211vap *vap = ni->ni_vap;
2208 	struct mtw_node *rn = MTW_NODE(ni);
2209 	uint32_t sta[3];
2210 	uint16_t(*wstat)[3];
2211 	int error, ridx;
2212 	uint8_t txrate = 0;
2213 
2214 	/* Check for special case */
2215 	if (sc->rvp_cnt <= 1 && vap->iv_opmode == IEEE80211_M_STA &&
2216 	    ni != vap->iv_bss)
2217 		goto fail;
2218 
2219 	txs->flags = IEEE80211_RATECTL_TX_STATS_NODE |
2220 	    IEEE80211_RATECTL_TX_STATS_RETRIES;
2221 	txs->ni = ni;
2222 	if (sc->rvp_cnt <= 1 &&
2223 	    (vap->iv_opmode == IEEE80211_M_IBSS ||
2224 		vap->iv_opmode == IEEE80211_M_STA)) {
2225 		/*
2226 		 * read statistic counters (clear on read) and update AMRR state
2227 		 */
2228 		error = mtw_read_region_1(sc, MTW_TX_STA_CNT0, (uint8_t *)sta,
2229 		    sizeof sta);
2230 		MTW_DPRINTF(sc, MTW_DEBUG_RATE, "error:%d\n", error);
2231 		if (error != 0)
2232 			goto fail;
2233 
2234 		/* count failed TX as errors */
2235 		if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS,
2236 		    le32toh(sta[0]) & 0xffff);
2237 
2238 		txs->nretries = (le32toh(sta[1]) >> 16);
2239 		txs->nsuccess = (le32toh(sta[1]) & 0xffff);
2240 		/* nretries??? */
2241 		txs->nframes = txs->nsuccess + (le32toh(sta[0]) & 0xffff);
2242 
2243 		MTW_DPRINTF(sc, MTW_DEBUG_RATE,
2244 		    "retrycnt=%d success=%d failcnt=%d\n", txs->nretries,
2245 		    txs->nsuccess, le32toh(sta[0]) & 0xffff);
2246 	} else {
2247 		wstat = &(sc->wcid_stats[MTW_AID2WCID(ni->ni_associd)]);
2248 
2249 		if (wstat == &(sc->wcid_stats[0]) ||
2250 		    wstat > &(sc->wcid_stats[MTW_WCID_MAX]))
2251 			goto fail;
2252 
2253 		txs->nretries = (*wstat)[MTW_RETRY];
2254 		txs->nsuccess = (*wstat)[MTW_SUCCESS];
2255 		txs->nframes = (*wstat)[MTW_TXCNT];
2256 		MTW_DPRINTF(sc, MTW_DEBUG_RATE,
2257 		    "wstat retrycnt=%d txcnt=%d success=%d\n", txs->nretries,
2258 		    txs->nframes, txs->nsuccess);
2259 
2260 		memset(wstat, 0, sizeof(*wstat));
2261 	}
2262 
2263 	ieee80211_ratectl_tx_update(vap, txs);
2264 	ieee80211_ratectl_rate(ni, NULL, 0);
2265 	txrate = ieee80211_node_get_txrate_dot11rate(ni);
2266 
2267 	/* XXX TODO: methodize with MCS rates */
2268 	for (ridx = 0; ridx < MTW_RIDX_MAX; ridx++) {
2269 		MTW_DPRINTF(sc, MTW_DEBUG_RATE, "ni_txrate=0x%x\n",
2270 			     txrate);
2271 		if (rt2860_rates[ridx].rate == txrate) {
2272 			break;
2273 		}
2274 	}
2275 	rn->amrr_ridx = ridx;
2276 fail:
2277 	MTW_UNLOCK(sc);
2278 
2279 	MTW_DPRINTF(sc, MTW_DEBUG_RATE, "rate=%d, ridx=%d\n",
2280 		    txrate, rn->amrr_ridx);
2281 }
2282 
2283 static void
mtw_newassoc_cb(void * arg)2284 mtw_newassoc_cb(void *arg)
2285 {
2286 	struct mtw_cmdq *cmdq = arg;
2287 	struct ieee80211_node *ni = cmdq->arg1;
2288 	struct mtw_softc *sc = ni->ni_vap->iv_ic->ic_softc;
2289 
2290 	uint8_t wcid = cmdq->wcid;
2291 
2292 	MTW_LOCK_ASSERT(sc, MA_OWNED);
2293 
2294 	mtw_write_region_1(sc, MTW_WCID_ENTRY(wcid), ni->ni_macaddr,
2295 	    IEEE80211_ADDR_LEN);
2296 
2297 	memset(&(sc->wcid_stats[wcid]), 0, sizeof(sc->wcid_stats[wcid]));
2298 }
2299 
2300 static void
mtw_newassoc(struct ieee80211_node * ni,int isnew)2301 mtw_newassoc(struct ieee80211_node *ni, int isnew)
2302 {
2303 
2304 	struct mtw_node *mn = MTW_NODE(ni);
2305 	struct ieee80211vap *vap = ni->ni_vap;
2306 	struct ieee80211com *ic = vap->iv_ic;
2307 	struct mtw_softc *sc = ic->ic_softc;
2308 
2309 	uint8_t rate;
2310 	uint8_t ridx;
2311 	uint8_t wcid;
2312 	//int i;
2313 	// int i,j;
2314 	wcid = MTW_AID2WCID(ni->ni_associd);
2315 
2316 	if (wcid > MTW_WCID_MAX) {
2317 		device_printf(sc->sc_dev, "wcid=%d out of range\n", wcid);
2318 		return;
2319 	}
2320 
2321 	/* only interested in true associations */
2322 	if (isnew && ni->ni_associd != 0) {
2323 		/*
2324 		 * This function could is called though timeout function.
2325 		 * Need to deferggxr.
2326 		 */
2327 
2328 		uint32_t cnt = MTW_CMDQ_GET(&sc->cmdq_store);
2329 		MTW_DPRINTF(sc, MTW_DEBUG_STATE, "cmdq_store=%d\n", cnt);
2330 		sc->cmdq[cnt].func = mtw_newassoc_cb;
2331 		sc->cmdq[cnt].arg0 = NULL;
2332 		sc->cmdq[cnt].arg1 = ni;
2333 		sc->cmdq[cnt].wcid = wcid;
2334 		ieee80211_runtask(ic, &sc->cmdq_task);
2335 	}
2336 
2337 	MTW_DPRINTF(sc, MTW_DEBUG_STATE,
2338 	    "new assoc isnew=%d associd=%x addr=%s\n", isnew, ni->ni_associd,
2339 	    ether_sprintf(ni->ni_macaddr));
2340 	rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate;
2341 	/* XXX TODO: methodize with MCS rates */
2342 	for (ridx = 0; ridx < MTW_RIDX_MAX; ridx++)
2343 		if (rt2860_rates[ridx].rate == rate)
2344 			break;
2345 	mn->mgt_ridx = ridx;
2346 	MTW_DPRINTF(sc, MTW_DEBUG_STATE | MTW_DEBUG_RATE,
2347 	    "rate=%d, ctl_ridx=%d\n", rate, ridx);
2348 	MTW_LOCK(sc);
2349 	if (sc->ratectl_run != MTW_RATECTL_OFF) {
2350 		usb_callout_reset(&sc->ratectl_ch, hz, &mtw_ratectl_to, sc);
2351 	}
2352 	MTW_UNLOCK(sc);
2353 
2354 }
2355 
2356 /*
2357  * Return the Rx chain with the highest RSSI for a given frame.
2358  */
2359 static __inline uint8_t
mtw_maxrssi_chain(struct mtw_softc * sc,const struct mtw_rxwi * rxwi)2360 mtw_maxrssi_chain(struct mtw_softc *sc, const struct mtw_rxwi *rxwi)
2361 {
2362 	uint8_t rxchain = 0;
2363 
2364 	if (sc->nrxchains > 1) {
2365 		if (rxwi->rssi[1] > rxwi->rssi[rxchain])
2366 			rxchain = 1;
2367 		if (sc->nrxchains > 2)
2368 			if (rxwi->rssi[2] > rxwi->rssi[rxchain])
2369 				rxchain = 2;
2370 	}
2371 	return (rxchain);
2372 }
2373 static void
mtw_get_tsf(struct mtw_softc * sc,uint64_t * buf)2374 mtw_get_tsf(struct mtw_softc *sc, uint64_t *buf)
2375 {
2376 	mtw_read_region_1(sc, MTW_TSF_TIMER_DW0, (uint8_t *)buf, sizeof(*buf));
2377 }
2378 
2379 static void
mtw_recv_mgmt(struct ieee80211_node * ni,struct mbuf * m,int subtype,const struct ieee80211_rx_stats * rxs,int rssi,int nf)2380 mtw_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype,
2381     const struct ieee80211_rx_stats *rxs, int rssi, int nf)
2382 {
2383 	struct ieee80211vap *vap = ni->ni_vap;
2384 	struct mtw_softc *sc = vap->iv_ic->ic_softc;
2385 	struct mtw_vap *rvp = MTW_VAP(vap);
2386 	uint64_t ni_tstamp, rx_tstamp;
2387 
2388 	rvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf);
2389 
2390 	if (vap->iv_state == IEEE80211_S_RUN &&
2391 	    (subtype == IEEE80211_FC0_SUBTYPE_BEACON ||
2392 		subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) {
2393 		ni_tstamp = le64toh(ni->ni_tstamp.tsf);
2394 		MTW_LOCK(sc);
2395 		mtw_get_tsf(sc, &rx_tstamp);
2396 		MTW_UNLOCK(sc);
2397 		rx_tstamp = le64toh(rx_tstamp);
2398 
2399 		if (ni_tstamp >= rx_tstamp) {
2400 			MTW_DPRINTF(sc, MTW_DEBUG_RECV | MTW_DEBUG_BEACON,
2401 			    "ibss merge, tsf %ju tstamp %ju\n",
2402 			    (uintmax_t)rx_tstamp, (uintmax_t)ni_tstamp);
2403 			(void)ieee80211_ibss_merge(ni);
2404 		}
2405 	}
2406 }
2407 static void
mtw_rx_frame(struct mtw_softc * sc,struct mbuf * m,uint32_t dmalen)2408 mtw_rx_frame(struct mtw_softc *sc, struct mbuf *m, uint32_t dmalen)
2409 {
2410 	struct ieee80211com *ic = &sc->sc_ic;
2411 	struct ieee80211_frame *wh;
2412 	struct ieee80211_node *ni;
2413 	struct epoch_tracker et;
2414 
2415 	struct mtw_rxwi *rxwi;
2416 	uint32_t flags;
2417 	uint16_t len, rxwisize;
2418 	uint8_t ant, rssi;
2419 	int8_t nf;
2420 
2421 	rxwisize = sizeof(struct mtw_rxwi);
2422 
2423 	if (__predict_false(
2424 		dmalen < rxwisize + sizeof(struct ieee80211_frame_ack))) {
2425 		MTW_DPRINTF(sc, MTW_DEBUG_RECV,
2426 		    "payload is too short: dma length %u < %zu\n", dmalen,
2427 		    rxwisize + sizeof(struct ieee80211_frame_ack));
2428 		goto fail;
2429 	}
2430 
2431 	rxwi = mtod(m, struct mtw_rxwi *);
2432 	len = le16toh(rxwi->len) & 0xfff;
2433 	flags = le32toh(rxwi->flags);
2434 	if (__predict_false(len > dmalen - rxwisize)) {
2435 		MTW_DPRINTF(sc, MTW_DEBUG_RECV, "bad RXWI length %u > %u\n",
2436 		    len, dmalen);
2437 		goto fail;
2438 	}
2439 
2440 	if (__predict_false(flags & (MTW_RX_CRCERR | MTW_RX_ICVERR))) {
2441 		MTW_DPRINTF(sc, MTW_DEBUG_RECV, "%s error.\n",
2442 		    (flags & MTW_RX_CRCERR) ? "CRC" : "ICV");
2443 		goto fail;
2444 	}
2445 
2446 	if (flags & MTW_RX_L2PAD) {
2447 		MTW_DPRINTF(sc, MTW_DEBUG_RECV,
2448 		    "received RT2860_RX_L2PAD frame\n");
2449 		len += 2;
2450 	}
2451 
2452 	m->m_data += rxwisize;
2453 	m->m_pkthdr.len = m->m_len = len;
2454 
2455 	wh = mtod(m, struct ieee80211_frame *);
2456 	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
2457 		wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
2458 		m->m_flags |= M_WEP;
2459 	}
2460 
2461 	if (len >= sizeof(struct ieee80211_frame_min)) {
2462 		ni = ieee80211_find_rxnode(ic,
2463 		    mtod(m, struct ieee80211_frame_min *));
2464 	} else
2465 		ni = NULL;
2466 
2467 	if (ni && ni->ni_flags & IEEE80211_NODE_HT) {
2468 		m->m_flags |= M_AMPDU;
2469 	}
2470 
2471 	if (__predict_false(flags & MTW_RX_MICERR)) {
2472 		/* report MIC failures to net80211 for TKIP */
2473 		if (ni != NULL)
2474 			ieee80211_notify_michael_failure(ni->ni_vap, wh,
2475 			    rxwi->keyidx);
2476 		MTW_DPRINTF(sc, MTW_DEBUG_RECV,
2477 		    "MIC error. Someone is lying.\n");
2478 		goto fail;
2479 	}
2480 
2481 	ant = mtw_maxrssi_chain(sc, rxwi);
2482 	rssi = rxwi->rssi[ant];
2483 	nf = mtw_rssi2dbm(sc, rssi, ant);
2484 
2485 	if (__predict_false(ieee80211_radiotap_active(ic))) {
2486 		struct mtw_rx_radiotap_header *tap = &sc->sc_rxtap;
2487 		uint16_t phy;
2488 
2489 		tap->wr_flags = 0;
2490 		if (flags & MTW_RX_L2PAD)
2491 			tap->wr_flags |= IEEE80211_RADIOTAP_F_DATAPAD;
2492 		tap->wr_antsignal = rssi;
2493 		tap->wr_antenna = ant;
2494 		tap->wr_dbm_antsignal = mtw_rssi2dbm(sc, rssi, ant);
2495 		tap->wr_rate = 2; /* in case it can't be found below */
2496 		//MTW_LOCK(sc);
2497 
2498 	//	MTW_UNLOCK(sc);
2499 		phy = le16toh(rxwi->phy);
2500 		switch (phy >> MT7601_PHY_SHIFT) {
2501 		case MTW_PHY_CCK:
2502 			switch ((phy & MTW_PHY_MCS) & ~MTW_PHY_SHPRE) {
2503 			case 0:
2504 				tap->wr_rate = 2;
2505 				break;
2506 			case 1:
2507 				tap->wr_rate = 4;
2508 				break;
2509 			case 2:
2510 				tap->wr_rate = 11;
2511 				break;
2512 			case 3:
2513 				tap->wr_rate = 22;
2514 				break;
2515 			}
2516 			if (phy & MTW_PHY_SHPRE)
2517 				tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2518 			break;
2519 		case MTW_PHY_OFDM:
2520 			switch (phy & MTW_PHY_MCS) {
2521 			case 0:
2522 				tap->wr_rate = 12;
2523 				break;
2524 			case 1:
2525 				tap->wr_rate = 18;
2526 				break;
2527 			case 2:
2528 				tap->wr_rate = 24;
2529 				break;
2530 			case 3:
2531 				tap->wr_rate = 36;
2532 				break;
2533 			case 4:
2534 				tap->wr_rate = 48;
2535 				break;
2536 			case 5:
2537 				tap->wr_rate = 72;
2538 				break;
2539 			case 6:
2540 				tap->wr_rate = 96;
2541 				break;
2542 			case 7:
2543 				tap->wr_rate = 108;
2544 				break;
2545 			}
2546 			break;
2547 		}
2548 	}
2549 
2550 	NET_EPOCH_ENTER(et);
2551 	if (ni != NULL) {
2552 		(void)ieee80211_input(ni, m, rssi, nf);
2553 		ieee80211_free_node(ni);
2554 	} else {
2555 		(void)ieee80211_input_all(ic, m, rssi, nf);
2556 	}
2557 	NET_EPOCH_EXIT(et);
2558 
2559 	return;
2560 
2561 fail:
2562 	m_freem(m);
2563 	counter_u64_add(ic->ic_ierrors, 1);
2564 }
2565 
2566 static void
mtw_bulk_rx_callback(struct usb_xfer * xfer,usb_error_t error)2567 mtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
2568 {
2569 	struct mtw_softc *sc = usbd_xfer_softc(xfer);
2570 	struct ieee80211com *ic = &sc->sc_ic;
2571 	struct mbuf *m = NULL;
2572 	struct mbuf *m0;
2573 	uint32_t dmalen, mbuf_len;
2574 	uint16_t rxwisize;
2575 	int xferlen;
2576 
2577 	rxwisize = sizeof(struct mtw_rxwi);
2578 
2579 	usbd_xfer_status(xfer, &xferlen, NULL, NULL, NULL);
2580 
2581 	switch (USB_GET_STATE(xfer)) {
2582 	case USB_ST_TRANSFERRED:
2583 		MTW_DPRINTF(sc, MTW_DEBUG_RECV, "rx done, actlen=%d\n",
2584 		    xferlen);
2585 		if (xferlen < (int)(sizeof(uint32_t) + rxwisize +
2586 				  sizeof(struct mtw_rxd))) {
2587 			MTW_DPRINTF(sc, MTW_DEBUG_RECV_DESC | MTW_DEBUG_USB,
2588 			    "xfer too short %d %d\n", xferlen,
2589 			    (int)(sizeof(uint32_t) + rxwisize +
2590 				sizeof(struct mtw_rxd)));
2591 			goto tr_setup;
2592 		}
2593 
2594 		m = sc->rx_m;
2595 		sc->rx_m = NULL;
2596 
2597 		/* FALLTHROUGH */
2598 	case USB_ST_SETUP:
2599 	tr_setup:
2600 
2601 		if (sc->rx_m == NULL) {
2602 			sc->rx_m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2603 			    MTW_MAX_RXSZ);
2604 		}
2605 		if (sc->rx_m == NULL) {
2606 			MTW_DPRINTF(sc,
2607 			    MTW_DEBUG_RECV | MTW_DEBUG_RECV_DESC |
2608 				MTW_DEBUG_USB,
2609 			    "could not allocate mbuf - idle with stall\n");
2610 			counter_u64_add(ic->ic_ierrors, 1);
2611 			usbd_xfer_set_stall(xfer);
2612 			usbd_xfer_set_frames(xfer, 0);
2613 		} else {
2614 			/*
2615 			 * Directly loading a mbuf cluster into DMA to
2616 			 * save some data copying. This works because
2617 			 * there is only one cluster.
2618 			 */
2619 			usbd_xfer_set_frame_data(xfer, 0,
2620 			    mtod(sc->rx_m, caddr_t), MTW_MAX_RXSZ);
2621 			usbd_xfer_set_frames(xfer, 1);
2622 		}
2623 		usbd_transfer_submit(xfer);
2624 		break;
2625 
2626 	default: /* Error */
2627 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT | MTW_DEBUG_USB,
2628 		    "USB transfer error, %s\n", usbd_errstr(error));
2629 
2630 		if (error != USB_ERR_CANCELLED) {
2631 			/* try to clear stall first */
2632 			usbd_xfer_set_stall(xfer);
2633 			if (error == USB_ERR_TIMEOUT)
2634 				device_printf(sc->sc_dev, "device timeout %s\n",
2635 				    __func__);
2636 			counter_u64_add(ic->ic_ierrors, 1);
2637 			goto tr_setup;
2638 		}
2639 		if (sc->rx_m != NULL) {
2640 			m_freem(sc->rx_m);
2641 			sc->rx_m = NULL;
2642 		}
2643 		break;
2644 	}
2645 
2646 	if (m == NULL)
2647 		return;
2648 
2649 	/* inputting all the frames must be last */
2650 
2651 	MTW_UNLOCK(sc);
2652 
2653 	m->m_pkthdr.len = m->m_len = xferlen;
2654 
2655 	/* HW can aggregate multiple 802.11 frames in a single USB xfer */
2656 	for (;;) {
2657 		dmalen = le32toh(*mtod(m, uint32_t *)) & 0xffff;
2658 
2659 		if ((dmalen >= (uint32_t)-8) || (dmalen == 0) ||
2660 		    ((dmalen & 3) != 0)) {
2661 			MTW_DPRINTF(sc, MTW_DEBUG_RECV_DESC | MTW_DEBUG_USB,
2662 			    "bad DMA length %u\n", dmalen);
2663 			break;
2664 		}
2665 		if ((dmalen + 8) > (uint32_t)xferlen) {
2666 			MTW_DPRINTF(sc, MTW_DEBUG_RECV_DESC | MTW_DEBUG_USB,
2667 			    "bad DMA length %u > %d\n", dmalen + 8, xferlen);
2668 			break;
2669 		}
2670 
2671 		/* If it is the last one or a single frame, we won't copy. */
2672 		if ((xferlen -= dmalen + 8) <= 8) {
2673 			/* trim 32-bit DMA-len header */
2674 			m->m_data += 4;
2675 			m->m_pkthdr.len = m->m_len -= 4;
2676 			mtw_rx_frame(sc, m, dmalen);
2677 			m = NULL; /* don't free source buffer */
2678 			break;
2679 		}
2680 
2681 		mbuf_len = dmalen + sizeof(struct mtw_rxd);
2682 		if (__predict_false(mbuf_len > MCLBYTES)) {
2683 			MTW_DPRINTF(sc, MTW_DEBUG_RECV_DESC | MTW_DEBUG_USB,
2684 			    "payload is too big: mbuf_len %u\n", mbuf_len);
2685 			counter_u64_add(ic->ic_ierrors, 1);
2686 			break;
2687 		}
2688 
2689 		/* copy aggregated frames to another mbuf */
2690 		m0 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2691 		if (__predict_false(m0 == NULL)) {
2692 			MTW_DPRINTF(sc, MTW_DEBUG_RECV_DESC,
2693 			    "could not allocate mbuf\n");
2694 			counter_u64_add(ic->ic_ierrors, 1);
2695 			break;
2696 		}
2697 		m_copydata(m, 4 /* skip 32-bit DMA-len header */, mbuf_len,
2698 		    mtod(m0, caddr_t));
2699 		m0->m_pkthdr.len = m0->m_len = mbuf_len;
2700 		mtw_rx_frame(sc, m0, dmalen);
2701 
2702 		/* update data ptr */
2703 		m->m_data += mbuf_len + 4;
2704 		m->m_pkthdr.len = m->m_len -= mbuf_len + 4;
2705 	}
2706 
2707 	/* make sure we free the source buffer, if any */
2708 	m_freem(m);
2709 
2710 #ifdef IEEE80211_SUPPORT_SUPERG
2711 	ieee80211_ff_age_all(ic, 100);
2712 #endif
2713 	MTW_LOCK(sc);
2714 }
2715 
2716 static void
mtw_tx_free(struct mtw_endpoint_queue * pq,struct mtw_tx_data * data,int txerr)2717 mtw_tx_free(struct mtw_endpoint_queue *pq, struct mtw_tx_data *data, int txerr)
2718 {
2719 
2720 	ieee80211_tx_complete(data->ni, data->m, txerr);
2721 	data->m = NULL;
2722 	data->ni = NULL;
2723 
2724 	STAILQ_INSERT_TAIL(&pq->tx_fh, data, next);
2725 	pq->tx_nfree++;
2726 }
2727 static void
mtw_bulk_tx_callbackN(struct usb_xfer * xfer,usb_error_t error,u_int index)2728 mtw_bulk_tx_callbackN(struct usb_xfer *xfer, usb_error_t error, u_int index)
2729 {
2730 	struct mtw_softc *sc = usbd_xfer_softc(xfer);
2731 	struct ieee80211com *ic = &sc->sc_ic;
2732 	struct mtw_tx_data *data;
2733 	struct ieee80211vap *vap = NULL;
2734 	struct usb_page_cache *pc;
2735 	struct mtw_endpoint_queue *pq = &sc->sc_epq[index];
2736 	struct mbuf *m;
2737 	usb_frlength_t size;
2738 	int actlen;
2739 	int sumlen;
2740 	usbd_xfer_status(xfer, &actlen, &sumlen, NULL, NULL);
2741 
2742 	switch (USB_GET_STATE(xfer)) {
2743 	case USB_ST_TRANSFERRED:
2744 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT | MTW_DEBUG_USB,
2745 		    "transfer complete: %d bytes @ index %d\n", actlen, index);
2746 
2747 		data = usbd_xfer_get_priv(xfer);
2748 		mtw_tx_free(pq, data, 0);
2749 		usbd_xfer_set_priv(xfer, NULL);
2750 
2751 		/* FALLTHROUGH */
2752 	case USB_ST_SETUP:
2753 	tr_setup:
2754 		data = STAILQ_FIRST(&pq->tx_qh);
2755 		if (data == NULL)
2756 			break;
2757 
2758 		STAILQ_REMOVE_HEAD(&pq->tx_qh, next);
2759 
2760 		m = data->m;
2761 
2762 		size = sizeof(data->desc);
2763 		if ((m->m_pkthdr.len + size + 3 + 8) > MTW_MAX_TXSZ) {
2764 			MTW_DPRINTF(sc, MTW_DEBUG_XMIT_DESC | MTW_DEBUG_USB,
2765 			    "data overflow, %u bytes\n", m->m_pkthdr.len);
2766 			mtw_tx_free(pq, data, 1);
2767 			goto tr_setup;
2768 		}
2769 
2770 		pc = usbd_xfer_get_frame(xfer, 0);
2771 		usbd_copy_in(pc, 0, &data->desc, size);
2772 		usbd_m_copy_in(pc, size, m, 0, m->m_pkthdr.len);
2773 		size += m->m_pkthdr.len;
2774 		/*
2775 		 * Align end on a 4-byte boundary, pad 8 bytes (CRC +
2776 		 * 4-byte padding), and be sure to zero those trailing
2777 		 * bytes:
2778 		 */
2779 		usbd_frame_zero(pc, size, ((-size) & 3) + MTW_DMA_PAD);
2780 		size += ((-size) & 3) + MTW_DMA_PAD;
2781 
2782 		vap = data->ni->ni_vap;
2783 		if (ieee80211_radiotap_active_vap(vap)) {
2784 			const struct ieee80211_frame *wh;
2785 			struct mtw_tx_radiotap_header *tap = &sc->sc_txtap;
2786 			struct mtw_txwi *txwi =
2787 			    (struct mtw_txwi *)(&data->desc +
2788 				sizeof(struct mtw_txd));
2789 			int has_l2pad;
2790 
2791 			wh = mtod(m, struct ieee80211_frame *);
2792 			has_l2pad = IEEE80211_HAS_ADDR4(wh) !=
2793 			    IEEE80211_QOS_HAS_SEQ(wh);
2794 
2795 			tap->wt_flags = 0;
2796 			tap->wt_rate = rt2860_rates[data->ridx].rate;
2797 			tap->wt_hwqueue = index;
2798 			if (le16toh(txwi->phy) & MTW_PHY_SHPRE)
2799 				tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2800 			if (has_l2pad)
2801 				tap->wt_flags |= IEEE80211_RADIOTAP_F_DATAPAD;
2802 
2803 			ieee80211_radiotap_tx(vap, m);
2804 		}
2805 
2806 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT | MTW_DEBUG_USB,
2807 		    "sending frame len=%u/%u @ index %d\n", m->m_pkthdr.len,
2808 		    size, index);
2809 
2810 		usbd_xfer_set_frame_len(xfer, 0, size);
2811 		usbd_xfer_set_priv(xfer, data);
2812 		usbd_transfer_submit(xfer);
2813 		mtw_start(sc);
2814 
2815 		break;
2816 
2817 	default:
2818 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT | MTW_DEBUG_USB,
2819 		    "USB transfer error, %s\n", usbd_errstr(error));
2820 
2821 		data = usbd_xfer_get_priv(xfer);
2822 
2823 		if (data != NULL) {
2824 			if (data->ni != NULL)
2825 				vap = data->ni->ni_vap;
2826 			mtw_tx_free(pq, data, error);
2827 			usbd_xfer_set_priv(xfer, NULL);
2828 		}
2829 
2830 		if (vap == NULL)
2831 			vap = TAILQ_FIRST(&ic->ic_vaps);
2832 
2833 		if (error != USB_ERR_CANCELLED) {
2834 			if (error == USB_ERR_TIMEOUT) {
2835 				device_printf(sc->sc_dev, "device timeout %s\n",
2836 				    __func__);
2837 				uint32_t i = MTW_CMDQ_GET(&sc->cmdq_store);
2838 				MTW_DPRINTF(sc, MTW_DEBUG_XMIT | MTW_DEBUG_USB,
2839 				    "cmdq_store=%d\n", i);
2840 				sc->cmdq[i].func = mtw_usb_timeout_cb;
2841 				sc->cmdq[i].arg0 = vap;
2842 				ieee80211_runtask(ic, &sc->cmdq_task);
2843 			}
2844 
2845 			/*
2846 			 * Try to clear stall first, also if other
2847 			 * errors occur, hence clearing stall
2848 			 * introduces a 50 ms delay:
2849 			 */
2850 			usbd_xfer_set_stall(xfer);
2851 			goto tr_setup;
2852 		}
2853 		break;
2854 	}
2855 #ifdef IEEE80211_SUPPORT_SUPERG
2856 	/* XXX TODO: make this deferred rather than unlock/relock */
2857 	/* XXX TODO: should only do the QoS AC this belongs to */
2858 	if (pq->tx_nfree >= MTW_TX_RING_COUNT) {
2859 		MTW_UNLOCK(sc);
2860 		ieee80211_ff_flush_all(ic);
2861 		MTW_LOCK(sc);
2862 	}
2863 #endif
2864 }
2865 
2866 static void
mtw_fw_callback(struct usb_xfer * xfer,usb_error_t error)2867 mtw_fw_callback(struct usb_xfer *xfer, usb_error_t error)
2868 {
2869 	struct mtw_softc *sc = usbd_xfer_softc(xfer);
2870 
2871 	int actlen;
2872 	int ntries, tmp;
2873 	// struct mtw_txd *data;
2874 
2875 	usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
2876 	// data = usbd_xfer_get_priv(xfer);
2877 	usbd_xfer_set_priv(xfer, NULL);
2878 	switch (USB_GET_STATE(xfer)) {
2879 
2880 	case USB_ST_TRANSFERRED:
2881 		sc->sc_sent += actlen;
2882 		memset(sc->txd_fw[sc->sc_idx], 0, actlen);
2883 
2884 		if (actlen < 0x2c44 && sc->sc_idx == 0) {
2885 			return;
2886 		}
2887 		if (sc->sc_idx == 3) {
2888 
2889 			if ((error = mtw_write_ivb(sc, sc->sc_ivb_1,
2890 				    MTW_MCU_IVB_LEN)) != 0) {
2891 				device_printf(sc->sc_dev,
2892 				    "Could not write ivb error:  %d\n", error);
2893 			}
2894 
2895 			mtw_delay(sc, 10);
2896 			for (ntries = 0; ntries < MTW_FW_READY_RETRIES;
2897 			    ntries++) {
2898 				if ((error = mtw_read_cfg(sc, MTW_MCU_DMA_ADDR,
2899 				    &tmp)) != 0) {
2900 					device_printf(sc->sc_dev,
2901 					    "Could not read cfg error:  %d\n",
2902 					    error);
2903 				}
2904 				if (tmp == MTW_MCU_READY) {
2905 					MTW_DPRINTF(sc, MTW_DEBUG_FIRMWARE,
2906 					    "mcu reaady %d\n", tmp);
2907 					sc->fwloading = 1;
2908 					break;
2909 				}
2910 
2911 				mtw_delay(sc, MTW_FW_READY_DELAY_MS);
2912 			}
2913 			if (ntries == MTW_FW_READY_RETRIES)
2914 				sc->fwloading = 0;
2915 			wakeup(&sc->fwloading);
2916 			return;
2917 		}
2918 
2919 		if (actlen == 0x2c44) {
2920 			sc->sc_idx++;
2921 			DELAY(1000);
2922 		}
2923 
2924 	case USB_ST_SETUP: {
2925 		int dlen = 0;
2926 		dlen = sc->txd_fw[sc->sc_idx]->len;
2927 
2928 		mtw_write_cfg(sc, MTW_MCU_DMA_ADDR, 0x40 + sc->sc_sent);
2929 		mtw_write_cfg(sc, MTW_MCU_DMA_LEN, (dlen << 16));
2930 
2931 		usbd_xfer_set_frame_len(xfer, 0, dlen);
2932 		usbd_xfer_set_frame_data(xfer, 0, sc->txd_fw[sc->sc_idx], dlen);
2933 
2934 		// usbd_xfer_set_priv(xfer,sc->txd[sc->sc_idx]);
2935 		usbd_transfer_submit(xfer);
2936 		break;
2937 
2938 	default: /* Error */
2939 		device_printf(sc->sc_dev, "%s:%d %s\n", __FILE__, __LINE__,
2940 		    usbd_errstr(error));
2941 		sc->fwloading = 0;
2942 		wakeup(&sc->fwloading);
2943 		/*
2944 		 * Print error message and clear stall
2945 		 * for example.
2946 		 */
2947 		break;
2948 	}
2949 		/*
2950 		 * Here it is safe to do something without the private
2951 		 * USB mutex	locked.
2952 		 */
2953 	}
2954 	return;
2955 }
2956 static void
mtw_bulk_tx_callback0(struct usb_xfer * xfer,usb_error_t error)2957 mtw_bulk_tx_callback0(struct usb_xfer *xfer, usb_error_t error)
2958 {
2959 	mtw_bulk_tx_callbackN(xfer, error, 0);
2960 }
2961 
2962 static void
mtw_bulk_tx_callback1(struct usb_xfer * xfer,usb_error_t error)2963 mtw_bulk_tx_callback1(struct usb_xfer *xfer, usb_error_t error)
2964 {
2965 
2966 
2967 	mtw_bulk_tx_callbackN(xfer, error, 1);
2968 }
2969 
2970 static void
mtw_bulk_tx_callback2(struct usb_xfer * xfer,usb_error_t error)2971 mtw_bulk_tx_callback2(struct usb_xfer *xfer, usb_error_t error)
2972 {
2973 	mtw_bulk_tx_callbackN(xfer, error, 2);
2974 }
2975 
2976 static void
mtw_bulk_tx_callback3(struct usb_xfer * xfer,usb_error_t error)2977 mtw_bulk_tx_callback3(struct usb_xfer *xfer, usb_error_t error)
2978 {
2979 	mtw_bulk_tx_callbackN(xfer, error, 3);
2980 }
2981 
2982 static void
mtw_bulk_tx_callback4(struct usb_xfer * xfer,usb_error_t error)2983 mtw_bulk_tx_callback4(struct usb_xfer *xfer, usb_error_t error)
2984 {
2985 	mtw_bulk_tx_callbackN(xfer, error, 4);
2986 }
2987 
2988 static void
mtw_bulk_tx_callback5(struct usb_xfer * xfer,usb_error_t error)2989 mtw_bulk_tx_callback5(struct usb_xfer *xfer, usb_error_t error)
2990 {
2991 	mtw_bulk_tx_callbackN(xfer, error, 5);
2992 }
2993 
2994 static void
mtw_set_tx_desc(struct mtw_softc * sc,struct mtw_tx_data * data)2995 mtw_set_tx_desc(struct mtw_softc *sc, struct mtw_tx_data *data)
2996 {
2997 	struct mbuf *m = data->m;
2998 	struct ieee80211com *ic = &sc->sc_ic;
2999 	struct ieee80211vap *vap = data->ni->ni_vap;
3000 	struct ieee80211_frame *wh;
3001 	struct mtw_txd *txd;
3002 	struct mtw_txwi *txwi;
3003 	uint16_t xferlen, txwisize;
3004 	uint16_t mcs;
3005 	uint8_t ridx = data->ridx;
3006 	uint8_t pad;
3007 
3008 	/* get MCS code from rate index */
3009 	mcs = rt2860_rates[ridx].mcs;
3010 
3011 	txwisize = sizeof(*txwi);
3012 	xferlen = txwisize + m->m_pkthdr.len;
3013 
3014 	/* roundup to 32-bit alignment */
3015 	xferlen = (xferlen + 3) & ~3;
3016 
3017 	txd = (struct mtw_txd *)&data->desc;
3018 	txd->len = htole16(xferlen);
3019 
3020 	wh = mtod(m, struct ieee80211_frame *);
3021 
3022 	/*
3023 	 * Ether both are true or both are false, the header
3024 	 * are nicely aligned to 32-bit. So, no L2 padding.
3025 	 */
3026 	if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh))
3027 		pad = 0;
3028 	else
3029 		pad = 2;
3030 
3031 	/* setup TX Wireless Information */
3032 	txwi = (struct mtw_txwi *)(txd + 1);
3033 	txwi->len = htole16(m->m_pkthdr.len - pad);
3034 	if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
3035 		mcs |=	MTW_PHY_CCK;
3036 		if (ridx != MTW_RIDX_CCK1 &&
3037 		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
3038 			mcs |=	MTW_PHY_SHPRE;
3039 	} else if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) {
3040 		mcs |=	MTW_PHY_OFDM;
3041 	} else if (rt2860_rates[ridx].phy == IEEE80211_T_HT) {
3042 		/* XXX TODO: [adrian] set short preamble for MCS? */
3043 		mcs |=	MTW_PHY_HT; /* Mixed, not greenfield */
3044 	}
3045 	txwi->phy = htole16(mcs);
3046 
3047 	/* check if RTS/CTS or CTS-to-self protection is required */
3048 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
3049 	    ((m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) ||
3050 	     ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3051 	      rt2860_rates[ridx].phy == IEEE80211_T_OFDM) ||
3052 	     ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) &&
3053 	      rt2860_rates[ridx].phy == IEEE80211_T_HT)))
3054 		txwi->txop |= MTW_TX_TXOP_HT;
3055 	else
3056 		txwi->txop |=	MTW_TX_TXOP_BACKOFF;
3057 
3058 }
3059 
3060 /* This function must be called locked */
3061 static int
mtw_tx(struct mtw_softc * sc,struct mbuf * m,struct ieee80211_node * ni)3062 mtw_tx(struct mtw_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
3063 {
3064 	struct ieee80211com *ic = &sc->sc_ic;
3065 	struct ieee80211vap *vap = ni->ni_vap;
3066 	struct ieee80211_frame *wh;
3067 
3068 
3069 	//const struct ieee80211_txparam *tp = ni->ni_txparms;
3070 	struct mtw_node *rn = MTW_NODE(ni);
3071 	struct mtw_tx_data *data;
3072 	struct mtw_txd *txd;
3073 	struct mtw_txwi *txwi;
3074 	uint16_t qos;
3075 	uint16_t dur;
3076 	uint16_t qid;
3077 	uint8_t type;
3078 	uint8_t tid;
3079 	uint16_t ridx;
3080 	uint8_t ctl_ridx;
3081 	uint16_t qflags;
3082 	uint8_t xflags = 0;
3083 
3084 	int hasqos;
3085 
3086 	MTW_LOCK_ASSERT(sc, MA_OWNED);
3087 
3088 	wh = mtod(m, struct ieee80211_frame *);
3089 	const struct ieee80211_txparam *tp = ni->ni_txparms;
3090 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3091 
3092 	qflags = htole16(MTW_TXD_DATA | MTW_TXD_80211 |
3093 			 MTW_TXD_WLAN | MTW_TXD_QSEL_HCCA);
3094 
3095 	if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) {
3096 		uint8_t *frm;
3097 		frm = ieee80211_getqos(wh);
3098 
3099 
3100 		//device_printf(sc->sc_dev,"JSS:frm:%d",*frm);
3101 		qos = le16toh(*(const uint16_t *)frm);
3102 		tid = ieee80211_gettid(wh);
3103 		qid = TID_TO_WME_AC(tid);
3104 		qflags |= MTW_TXD_QSEL_EDCA;
3105 	} else {
3106 		qos = 0;
3107 		tid = 0;
3108 		qid = WME_AC_BE;
3109 	}
3110 	if (type & IEEE80211_FC0_TYPE_MGT) {
3111 		qid = 0;
3112 	}
3113 
3114 	if (type != IEEE80211_FC0_TYPE_DATA)
3115 		qflags |= htole16(MTW_TXD_WIV);
3116 
3117 	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3118 	    type != IEEE80211_FC0_TYPE_DATA || m->m_flags & M_EAPOL) {
3119 		/* XXX TODO: methodize for 11n; use MCS0 for 11NA/11NG */
3120 		ridx = (ic->ic_curmode == IEEE80211_MODE_11A
3121 			|| ic->ic_curmode == IEEE80211_MODE_11NA) ?
3122 			MTW_RIDX_OFDM6 : MTW_RIDX_CCK1;
3123 		if (type == IEEE80211_MODE_11NG) {
3124 			ridx = 12;
3125 		}
3126 		ctl_ridx = rt2860_rates[ridx].ctl_ridx;
3127 	} else {
3128 		if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
3129 			ridx = rn->fix_ridx;
3130 
3131 		} else {
3132 			ridx = rn->amrr_ridx;
3133 			ctl_ridx = rt2860_rates[ridx].ctl_ridx;
3134 		}
3135 	}
3136 
3137 	if (hasqos)
3138 		xflags = 0;
3139 	else
3140 		xflags = MTW_TX_NSEQ;
3141 
3142 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
3143 	    (!hasqos ||
3144 		(qos & IEEE80211_QOS_ACKPOLICY) !=
3145 		    IEEE80211_QOS_ACKPOLICY_NOACK)) {
3146 		xflags |= MTW_TX_ACK;
3147 		if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
3148 			dur = rt2860_rates[ctl_ridx].sp_ack_dur;
3149 		else
3150 			dur = rt2860_rates[ctl_ridx].lp_ack_dur;
3151 		USETW(wh->i_dur, dur);
3152 	}
3153 	/* reserve slots for mgmt packets, just in case */
3154 	if (sc->sc_epq[qid].tx_nfree < 3) {
3155 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "tx ring %d is full\n", qid);
3156 		return (-1);
3157 	}
3158 
3159 	data = STAILQ_FIRST(&sc->sc_epq[qid].tx_fh);
3160 	STAILQ_REMOVE_HEAD(&sc->sc_epq[qid].tx_fh, next);
3161 	sc->sc_epq[qid].tx_nfree--;
3162 
3163 	txd = (struct mtw_txd *)&data->desc;
3164 	txd->flags = qflags;
3165 
3166 	txwi = (struct mtw_txwi *)(txd + 1);
3167 	txwi->xflags = xflags;
3168 	txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ?
3169 
3170 	   MTW_AID2WCID(ni->ni_associd) :
3171 	    0xff;
3172 
3173 	/* clear leftover garbage bits */
3174 	txwi->flags = 0;
3175 	txwi->txop = 0;
3176 
3177 	data->m = m;
3178 	data->ni = ni;
3179 	data->ridx = ridx;
3180 
3181 	ieee80211_output_seqno_assign(ni, -1, m);
3182 
3183 	mtw_set_tx_desc(sc, data);
3184 
3185 	/*
3186 	 * The chip keeps track of 2 kind of Tx stats,
3187 	 *  * TX_STAT_FIFO, for per WCID stats, and
3188 	 *  * TX_STA_CNT0 for all-TX-in-one stats.
3189 	 *
3190 	 * To use FIFO stats, we need to store MCS into the driver-private
3191 	 * PacketID field. So that, we can tell whose stats when we read them.
3192 	 * We add 1 to the MCS because setting the PacketID field to 0 means
3193 	 * that we don't want feedback in TX_STAT_FIFO.
3194 	 * And, that's what we want for STA mode, since TX_STA_CNT0 does the
3195 	 * job.
3196 	 *
3197 	 * FIFO stats doesn't count Tx with WCID 0xff, so we do this in
3198 	 * run_tx().
3199 	 */
3200 
3201 	if (sc->rvp_cnt > 1 || vap->iv_opmode == IEEE80211_M_HOSTAP ||
3202 	    vap->iv_opmode == IEEE80211_M_MBSS) {
3203 
3204 		/*
3205 		 * Unlike PCI based devices, we don't get any interrupt from
3206 		 * USB devices, so we simulate FIFO-is-full interrupt here.
3207 		 * Ralink recommends to drain FIFO stats every 100 ms, but 16
3208 		 * slots quickly get fulled. To prevent overflow, increment a
3209 		 * counter on every FIFO stat request, so we know how many slots
3210 		 * are left. We do this only in HOSTAP or multiple vap mode
3211 		 * since FIFO stats are used only in those modes. We just drain
3212 		 * stats. AMRR gets updated every 1 sec by run_ratectl_cb() via
3213 		 * callout. Call it early. Otherwise overflow.
3214 		 */
3215 		if (sc->fifo_cnt++ == 10) {
3216 			/*
3217 			 * With multiple vaps or if_bridge, if_start() is called
3218 			 * with a non-sleepable lock, tcpinp. So, need to defer.
3219 			 */
3220 			uint32_t i = MTW_CMDQ_GET(&sc->cmdq_store);
3221 			MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "cmdq_store=%d\n", i);
3222 			sc->cmdq[i].func = mtw_drain_fifo;
3223 			sc->cmdq[i].arg0 = sc;
3224 			ieee80211_runtask(ic, &sc->cmdq_task);
3225 		}
3226 	}
3227 
3228 	STAILQ_INSERT_TAIL(&sc->sc_epq[qid].tx_qh, data, next);
3229 	usbd_transfer_start(sc->sc_xfer[mtw_wme_ac_xfer_map[qid]]);
3230 
3231 	MTW_DPRINTF(sc, MTW_DEBUG_XMIT,
3232 	    "sending data frame len=%d rate=%d qid=%d\n",
3233 	    m->m_pkthdr.len +
3234 		(int)(sizeof(struct mtw_txd) + sizeof(struct mtw_txwi)),
3235 	    rt2860_rates[ridx].rate, qid);
3236 
3237 	return (0);
3238 	}
3239 
3240 static int
mtw_tx_mgt(struct mtw_softc * sc,struct mbuf * m,struct ieee80211_node * ni)3241 mtw_tx_mgt(struct mtw_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
3242 {
3243 	struct ieee80211com *ic = &sc->sc_ic;
3244 	struct mtw_node *rn = MTW_NODE(ni);
3245 	struct mtw_tx_data *data;
3246 	struct ieee80211_frame *wh;
3247 	struct mtw_txd *txd;
3248 	struct mtw_txwi *txwi;
3249 	uint8_t type;
3250 	uint16_t dur;
3251 	uint8_t ridx = rn->mgt_ridx;
3252 	uint8_t xflags = 0;
3253 	uint8_t wflags = 0;
3254 
3255 	MTW_LOCK_ASSERT(sc, MA_OWNED);
3256 
3257 	wh = mtod(m, struct ieee80211_frame *);
3258 
3259 	/* tell hardware to add timestamp for probe responses  */
3260 	if ((wh->i_fc[0] &
3261 		(IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
3262 	    (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
3263 		wflags |= MTW_TX_TS;
3264 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3265 		xflags |= MTW_TX_ACK;
3266 
3267 		dur = ieee80211_ack_duration(ic->ic_rt, rt2860_rates[ridx].rate,
3268 		    ic->ic_flags & IEEE80211_F_SHPREAMBLE);
3269 		USETW(wh->i_dur, dur);
3270 	}
3271 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3272 	if (sc->sc_epq[0].tx_nfree == 0)
3273 		/* let caller free mbuf */
3274 		return (EIO);
3275 	data = STAILQ_FIRST(&sc->sc_epq[0].tx_fh);
3276 	STAILQ_REMOVE_HEAD(&sc->sc_epq[0].tx_fh, next);
3277 	sc->sc_epq[0].tx_nfree--;
3278 
3279 	txd = (struct mtw_txd *)&data->desc;
3280 	txd->flags = htole16(
3281 	    MTW_TXD_DATA | MTW_TXD_80211 | MTW_TXD_WLAN | MTW_TXD_QSEL_EDCA);
3282 	if (type != IEEE80211_FC0_TYPE_DATA)
3283 		txd->flags |= htole16(MTW_TXD_WIV);
3284 
3285 	txwi = (struct mtw_txwi *)(txd + 1);
3286 	txwi->wcid = 0xff;
3287 	txwi->xflags = xflags;
3288 	txwi->flags = wflags;
3289 
3290 	txwi->txop = 0; /* clear leftover garbage bits */
3291 
3292 	data->m = m;
3293 	data->ni = ni;
3294 	data->ridx = ridx;
3295 
3296 	MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "sending mgt frame len=%d rate=%d\n",
3297 	    m->m_pkthdr.len +
3298 		(int)(sizeof(struct mtw_txd) + sizeof(struct mtw_txwi)),
3299 	    rt2860_rates[ridx].rate);
3300 
3301 	STAILQ_INSERT_TAIL(&sc->sc_epq[0].tx_qh, data, next);
3302 
3303 	usbd_transfer_start(sc->sc_xfer[MTW_BULK_TX_BE]);
3304 
3305 	return (0);
3306 }
3307 
3308 static int
mtw_sendprot(struct mtw_softc * sc,const struct mbuf * m,struct ieee80211_node * ni,int prot,int rate)3309 mtw_sendprot(struct mtw_softc *sc, const struct mbuf *m,
3310     struct ieee80211_node *ni, int prot, int rate)
3311 {
3312 	struct ieee80211com *ic = ni->ni_ic;
3313 	struct mtw_tx_data *data;
3314 	struct mtw_txd *txd;
3315 	struct mtw_txwi *txwi;
3316 	struct mbuf *mprot;
3317 	int ridx;
3318 	int protrate;
3319 	uint8_t wflags = 0;
3320 	uint8_t xflags = 0;
3321 
3322 	MTW_LOCK_ASSERT(sc, MA_OWNED);
3323 
3324 	/* check that there are free slots before allocating the mbuf */
3325 	if (sc->sc_epq[0].tx_nfree == 0)
3326 		/* let caller free mbuf */
3327 		return (ENOBUFS);
3328 
3329 	mprot = ieee80211_alloc_prot(ni, m, rate, prot);
3330 	if (mprot == NULL) {
3331 		if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
3332 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "could not allocate mbuf\n");
3333 		return (ENOBUFS);
3334 	}
3335 
3336 	protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
3337 	wflags = MTW_TX_FRAG;
3338 	xflags = 0;
3339 	if (prot == IEEE80211_PROT_RTSCTS)
3340 		xflags |= MTW_TX_ACK;
3341 
3342 	data = STAILQ_FIRST(&sc->sc_epq[0].tx_fh);
3343 	STAILQ_REMOVE_HEAD(&sc->sc_epq[0].tx_fh, next);
3344 	sc->sc_epq[0].tx_nfree--;
3345 
3346 	txd = (struct mtw_txd *)&data->desc;
3347 	txd->flags = RT2860_TX_QSEL_EDCA;
3348 	txwi = (struct mtw_txwi *)(txd + 1);
3349 	txwi->wcid = 0xff;
3350 	txwi->flags = wflags;
3351 	txwi->xflags = xflags;
3352 	txwi->txop = 0; /* clear leftover garbage bits */
3353 
3354 	data->m = mprot;
3355 	data->ni = ieee80211_ref_node(ni);
3356 
3357 	/* XXX TODO: methodize with MCS rates */
3358 	for (ridx = 0; ridx < MTW_RIDX_MAX; ridx++)
3359 		if (rt2860_rates[ridx].rate == protrate)
3360 			break;
3361 	data->ridx = ridx;
3362 
3363 	mtw_set_tx_desc(sc, data);
3364 	MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "sending prot len=%u rate=%u\n",
3365 	    m->m_pkthdr.len, rate);
3366 
3367 	STAILQ_INSERT_TAIL(&sc->sc_epq[0].tx_qh, data, next);
3368 
3369 	usbd_transfer_start(sc->sc_xfer[0]);
3370 
3371 	return (0);
3372 }
3373 
3374 static int
mtw_tx_param(struct mtw_softc * sc,struct mbuf * m,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)3375 mtw_tx_param(struct mtw_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
3376     const struct ieee80211_bpf_params *params)
3377 {
3378 	struct ieee80211com *ic = ni->ni_ic;
3379 	struct mtw_tx_data *data;
3380 	struct mtw_txd *txd;
3381 	struct mtw_txwi *txwi;
3382 	uint8_t ridx;
3383 	uint8_t rate;
3384 	uint8_t opflags = 0;
3385 	uint8_t xflags = 0;
3386 	int error;
3387 
3388 	MTW_LOCK_ASSERT(sc, MA_OWNED);
3389 
3390 	KASSERT(params != NULL, ("no raw xmit params"));
3391 
3392 	rate = params->ibp_rate0;
3393 	if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3394 		/* let caller free mbuf */
3395 		return (EINVAL);
3396 	}
3397 
3398 	if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3399 		xflags |= MTW_TX_ACK;
3400 	if (params->ibp_flags & (IEEE80211_BPF_RTS | IEEE80211_BPF_CTS)) {
3401 		error = mtw_sendprot(sc, m, ni,
3402 		    params->ibp_flags & IEEE80211_BPF_RTS ?
3403 			IEEE80211_PROT_RTSCTS :
3404 			IEEE80211_PROT_CTSONLY,
3405 		    rate);
3406 		if (error) {
3407 			device_printf(sc->sc_dev, "%s:%d %d\n", __FILE__,
3408 			    __LINE__, error);
3409 			return (error);
3410 		}
3411 		opflags |=  MTW_TX_TXOP_SIFS;
3412 	}
3413 
3414 	if (sc->sc_epq[0].tx_nfree == 0) {
3415 		/* let caller free mbuf */
3416 		MTW_DPRINTF(sc, MTW_DEBUG_XMIT,
3417 		    "sending raw frame, but tx ring is full\n");
3418 		return (EIO);
3419 	}
3420 	data = STAILQ_FIRST(&sc->sc_epq[0].tx_fh);
3421 	STAILQ_REMOVE_HEAD(&sc->sc_epq[0].tx_fh, next);
3422 	sc->sc_epq[0].tx_nfree--;
3423 
3424 	txd = (struct mtw_txd *)&data->desc;
3425 	txd->flags = htole16(
3426 	    MTW_TXD_DATA | MTW_TXD_80211 | MTW_TXD_WLAN | MTW_TXD_QSEL_EDCA);
3427 	// txd->flags = htole16(MTW_TXD_QSEL_EDCA);
3428 	txwi = (struct mtw_txwi *)(txd + 1);
3429 	txwi->wcid = 0xff;
3430 	txwi->xflags = xflags;
3431 	txwi->txop = opflags;
3432 	txwi->flags = 0; /* clear leftover garbage bits */
3433 
3434 	data->m = m;
3435 	data->ni = ni;
3436 	/* XXX TODO: methodize with MCS rates */
3437 	for (ridx = 0; ridx < MTW_RIDX_MAX; ridx++)
3438 		if (rt2860_rates[ridx].rate == rate)
3439 			break;
3440 	data->ridx = ridx;
3441 
3442 	ieee80211_output_seqno_assign(ni, -1, m);
3443 
3444 	mtw_set_tx_desc(sc, data);
3445 
3446 	MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "sending raw frame len=%u rate=%u\n",
3447 	    m->m_pkthdr.len, rate);
3448 
3449 	STAILQ_INSERT_TAIL(&sc->sc_epq[0].tx_qh, data, next);
3450 
3451 	usbd_transfer_start(sc->sc_xfer[MTW_BULK_RAW_TX]);
3452 
3453 	return (0);
3454 }
3455 
3456 static int
mtw_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)3457 mtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3458     const struct ieee80211_bpf_params *params)
3459 {
3460 	struct mtw_softc *sc = ni->ni_ic->ic_softc;
3461 	int error = 0;
3462 	MTW_LOCK(sc);
3463 	/* prevent management frames from being sent if we're not ready */
3464 	if (!(sc->sc_flags & MTW_RUNNING)) {
3465 		error = ENETDOWN;
3466 		goto done;
3467 	}
3468 
3469 	if (params == NULL) {
3470 		/* tx mgt packet */
3471 		if ((error = mtw_tx_mgt(sc, m, ni)) != 0) {
3472 			MTW_DPRINTF(sc, MTW_DEBUG_XMIT, "mgt tx failed\n");
3473 			goto done;
3474 		}
3475 	} else {
3476 		/* tx raw packet with param */
3477 		if ((error = mtw_tx_param(sc, m, ni, params)) != 0) {
3478 			MTW_DPRINTF(sc, MTW_DEBUG_XMIT,
3479 			    "tx with param failed\n");
3480 			goto done;
3481 		}
3482 	}
3483 
3484 done:
3485 
3486 	MTW_UNLOCK(sc);
3487 
3488 	if (error != 0) {
3489 		if (m != NULL)
3490 			m_freem(m);
3491 	}
3492 
3493 	return (error);
3494 }
3495 
3496 static int
mtw_transmit(struct ieee80211com * ic,struct mbuf * m)3497 mtw_transmit(struct ieee80211com *ic, struct mbuf *m)
3498 {
3499 	struct mtw_softc *sc = ic->ic_softc;
3500 	int error;
3501 	MTW_LOCK(sc);
3502 	if ((sc->sc_flags & MTW_RUNNING) == 0) {
3503 		MTW_UNLOCK(sc);
3504 		return (ENXIO);
3505 	}
3506 	error = mbufq_enqueue(&sc->sc_snd, m);
3507 	if (error) {
3508 		MTW_UNLOCK(sc);
3509 		return (error);
3510 	}
3511 	mtw_start(sc);
3512 	MTW_UNLOCK(sc);
3513 
3514 	return (0);
3515 }
3516 
3517 static void
mtw_start(struct mtw_softc * sc)3518 mtw_start(struct mtw_softc *sc)
3519 {
3520 	struct ieee80211_node *ni;
3521 	struct mbuf *m;
3522 
3523 	MTW_LOCK_ASSERT(sc, MA_OWNED);
3524 
3525 	if ((sc->sc_flags & MTW_RUNNING) == 0) {
3526 
3527 		return;
3528 	}
3529 	while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
3530 		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3531 		if (mtw_tx(sc, m, ni) != 0) {
3532 			mbufq_prepend(&sc->sc_snd, m);
3533 			break;
3534 		}
3535 	}
3536 }
3537 
3538 static void
mtw_parent(struct ieee80211com * ic)3539 mtw_parent(struct ieee80211com *ic)
3540 {
3541 
3542 	struct mtw_softc *sc = ic->ic_softc;
3543 
3544 	MTW_LOCK(sc);
3545 	if (sc->sc_detached) {
3546 		MTW_UNLOCK(sc);
3547 		return;
3548 	}
3549 
3550 	if (!(sc->sc_flags & MTW_RUNNING) && ic->ic_nrunning > 0) {
3551 		mtw_init_locked(sc);
3552 		MTW_UNLOCK(sc);
3553 		ieee80211_start_all(ic);
3554 		return;
3555 	}
3556 	if (!(sc->sc_flags & MTW_RUNNING) && ic->ic_nrunning > 0) {
3557 		mtw_update_promisc_locked(sc);
3558 		MTW_UNLOCK(sc);
3559 		return;
3560 	}
3561 	if ((sc->sc_flags & MTW_RUNNING) && sc->rvp_cnt <= 1 &&
3562 	    ic->ic_nrunning == 0) {
3563 		mtw_stop(sc);
3564 		MTW_UNLOCK(sc);
3565 		return;
3566 	}
3567 	return;
3568 }
3569 
3570 static void
mt7601_set_agc(struct mtw_softc * sc,uint8_t agc)3571 mt7601_set_agc(struct mtw_softc *sc, uint8_t agc)
3572 {
3573 	uint8_t bbp;
3574 
3575 	mtw_bbp_write(sc, 66, agc);
3576 	mtw_bbp_write(sc, 195, 0x87);
3577 	bbp = (agc & 0xf0) | 0x08;
3578 	mtw_bbp_write(sc, 196, bbp);
3579 }
3580 
3581 static int
mtw_mcu_calibrate(struct mtw_softc * sc,int func,uint32_t val)3582 mtw_mcu_calibrate(struct mtw_softc *sc, int func, uint32_t val)
3583 {
3584 	struct mtw_mcu_cmd_8 cmd;
3585 
3586 	cmd.func = htole32(func);
3587 	cmd.val = htole32(val);
3588 	return (mtw_mcu_cmd(sc, 31, &cmd, sizeof(struct mtw_mcu_cmd_8)));
3589 }
3590 
3591 static int
mtw_rf_write(struct mtw_softc * sc,uint8_t bank,uint8_t reg,uint8_t val)3592 mtw_rf_write(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t val)
3593 {
3594 	uint32_t tmp;
3595 	int error, ntries, shift;
3596 
3597 	for (ntries = 0; ntries < 10; ntries++) {
3598 		if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
3599 			return (error);
3600 		if (!(tmp & MTW_RF_CSR_KICK))
3601 			break;
3602 	}
3603 	if (ntries == 10)
3604 		return (ETIMEDOUT);
3605 
3606 	if (sc->asic_ver == 0x7601)
3607 		shift = MT7601_BANK_SHIFT;
3608 	else
3609 		shift = MT7610_BANK_SHIFT;
3610 
3611 	tmp = MTW_RF_CSR_WRITE | MTW_RF_CSR_KICK | (bank & 0xf) << shift |
3612 	    reg << 8 | val;
3613 	return (mtw_write(sc, MTW_RF_CSR, tmp));
3614 }
3615 
3616 void
mtw_select_chan_group(struct mtw_softc * sc,int group)3617 mtw_select_chan_group(struct mtw_softc *sc, int group)
3618 {
3619 	uint32_t tmp;
3620 	uint8_t bbp;
3621 
3622 	/* Tx band 20MHz 2G */
3623 	mtw_read(sc, MTW_TX_BAND_CFG, &tmp);
3624 	tmp &= ~(
3625 	    MTW_TX_BAND_SEL_2G | MTW_TX_BAND_SEL_5G | MTW_TX_BAND_UPPER_40M);
3626 	tmp |= (group == 0) ? MTW_TX_BAND_SEL_2G : MTW_TX_BAND_SEL_5G;
3627 	mtw_write(sc, MTW_TX_BAND_CFG, tmp);
3628 
3629 	/* select 20 MHz bandwidth */
3630 	mtw_bbp_read(sc, 4, &bbp);
3631 	bbp &= ~0x18;
3632 	bbp |= 0x40;
3633 	mtw_bbp_write(sc, 4, bbp);
3634 
3635 	/* calibrate BBP */
3636 	mtw_bbp_write(sc, 69, 0x12);
3637 	mtw_bbp_write(sc, 91, 0x07);
3638 	mtw_bbp_write(sc, 195, 0x23);
3639 	mtw_bbp_write(sc, 196, 0x17);
3640 	mtw_bbp_write(sc, 195, 0x24);
3641 	mtw_bbp_write(sc, 196, 0x06);
3642 	mtw_bbp_write(sc, 195, 0x81);
3643 	mtw_bbp_write(sc, 196, 0x12);
3644 	mtw_bbp_write(sc, 195, 0x83);
3645 	mtw_bbp_write(sc, 196, 0x17);
3646 	mtw_rf_write(sc, 5, 8, 0x00);
3647 	// mtw_mcu_calibrate(sc, 0x6, 0x10001);
3648 
3649 	/* set initial AGC value */
3650 	mt7601_set_agc(sc, 0x14);
3651 }
3652 
3653 static int
mtw_rf_read(struct mtw_softc * sc,uint8_t bank,uint8_t reg,uint8_t * val)3654 mtw_rf_read(struct mtw_softc *sc, uint8_t bank, uint8_t reg, uint8_t *val)
3655 {
3656 	uint32_t tmp;
3657 	int error, ntries, shift;
3658 
3659 	for (ntries = 0; ntries < 100; ntries++) {
3660 		if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
3661 			return (error);
3662 		if (!(tmp & MTW_RF_CSR_KICK))
3663 			break;
3664 	}
3665 	if (ntries == 100)
3666 		return (ETIMEDOUT);
3667 
3668 	if (sc->asic_ver == 0x7601)
3669 		shift = MT7601_BANK_SHIFT;
3670 	else
3671 		shift = MT7610_BANK_SHIFT;
3672 
3673 	tmp = MTW_RF_CSR_KICK | (bank & 0xf) << shift | reg << 8;
3674 	if ((error = mtw_write(sc, MTW_RF_CSR, tmp)) != 0)
3675 		return (error);
3676 
3677 	for (ntries = 0; ntries < 100; ntries++) {
3678 		if ((error = mtw_read(sc, MTW_RF_CSR, &tmp)) != 0)
3679 			return (error);
3680 		if (!(tmp & MTW_RF_CSR_KICK))
3681 			break;
3682 	}
3683 	if (ntries == 100)
3684 		return (ETIMEDOUT);
3685 
3686 	*val = tmp & 0xff;
3687 	return (0);
3688 }
3689 static void
mt7601_set_chan(struct mtw_softc * sc,u_int chan)3690 mt7601_set_chan(struct mtw_softc *sc, u_int chan)
3691 {
3692 	uint32_t tmp;
3693 	uint8_t bbp, rf, txpow1;
3694 	int i;
3695 	/* find the settings for this channel */
3696 	for (i = 0; mt7601_rf_chan[i].chan != chan; i++)
3697 		;
3698 
3699 	mtw_rf_write(sc, 0, 17, mt7601_rf_chan[i].r17);
3700 	mtw_rf_write(sc, 0, 18, mt7601_rf_chan[i].r18);
3701 	mtw_rf_write(sc, 0, 19, mt7601_rf_chan[i].r19);
3702 	mtw_rf_write(sc, 0, 20, mt7601_rf_chan[i].r20);
3703 
3704 	/* use Tx power values from EEPROM */
3705 	txpow1 = sc->txpow1[i];
3706 
3707 	/* Tx automatic level control */
3708 	mtw_read(sc, MTW_TX_ALC_CFG0, &tmp);
3709 	tmp &= ~0x3f3f;
3710 	tmp |= (txpow1 & 0x3f);
3711 	mtw_write(sc, MTW_TX_ALC_CFG0, tmp);
3712 
3713 	/* LNA */
3714 	mtw_bbp_write(sc, 62, 0x37 - sc->lna[0]);
3715 	mtw_bbp_write(sc, 63, 0x37 - sc->lna[0]);
3716 	mtw_bbp_write(sc, 64, 0x37 - sc->lna[0]);
3717 
3718 	/* VCO calibration */
3719 	mtw_rf_write(sc, 0, 4, 0x0a);
3720 	mtw_rf_write(sc, 0, 5, 0x20);
3721 	mtw_rf_read(sc, 0, 4, &rf);
3722 	mtw_rf_write(sc, 0, 4, rf | 0x80);
3723 
3724 	/* select 20 MHz bandwidth */
3725 	mtw_bbp_read(sc, 4, &bbp);
3726 	bbp &= ~0x18;
3727 	bbp |= 0x40;
3728 	mtw_bbp_write(sc, 4, bbp);
3729 	mtw_bbp_write(sc, 178, 0xff);
3730 }
3731 
3732 static int
mtw_set_chan(struct mtw_softc * sc,struct ieee80211_channel * c)3733 mtw_set_chan(struct mtw_softc *sc, struct ieee80211_channel *c)
3734 {
3735 	struct ieee80211com *ic = &sc->sc_ic;
3736 	u_int chan, group;
3737 
3738 	chan = ieee80211_chan2ieee(ic, c);
3739 	if (chan == 0 || chan == IEEE80211_CHAN_ANY)
3740 		return (EINVAL);
3741 
3742 	/* determine channel group */
3743 	if (chan <= 14)
3744 		group = 0;
3745 	else if (chan <= 64)
3746 		group = 1;
3747 	else if (chan <= 128)
3748 		group = 2;
3749 	else
3750 		group = 3;
3751 
3752 	if (group != sc->sc_chan_group || !sc->sc_bw_calibrated)
3753 		mtw_select_chan_group(sc, group);
3754 
3755 	sc->sc_chan_group = group;
3756 
3757 	/* chipset specific */
3758 	if (sc->asic_ver == 0x7601)
3759 		mt7601_set_chan(sc, chan);
3760 
3761 	DELAY(1000);
3762 	return (0);
3763 }
3764 
3765 static void
mtw_set_channel(struct ieee80211com * ic)3766 mtw_set_channel(struct ieee80211com *ic)
3767 {
3768 	struct mtw_softc *sc = ic->ic_softc;
3769 
3770 	MTW_LOCK(sc);
3771 	mtw_set_chan(sc, ic->ic_curchan);
3772 	MTW_UNLOCK(sc);
3773 
3774 	return;
3775 }
3776 
3777 static void
mtw_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])3778 mtw_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans,
3779     struct ieee80211_channel chans[])
3780 {
3781 	// struct mtw_softc *sc = ic->ic_softc;
3782 	uint8_t bands[IEEE80211_MODE_BYTES];
3783 
3784 	memset(bands, 0, sizeof(bands));
3785 	setbit(bands, IEEE80211_MODE_11B);
3786 	setbit(bands, IEEE80211_MODE_11G);
3787 	setbit(bands, IEEE80211_MODE_11NG);
3788 
3789 	/* Note: for now, only support HT20 channels */
3790 	ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
3791 }
3792 
3793 static void
mtw_scan_start(struct ieee80211com * ic)3794 mtw_scan_start(struct ieee80211com *ic)
3795 {
3796 	struct mtw_softc *sc = ic->ic_softc;
3797 	MTW_LOCK(sc);
3798 	/* abort TSF synchronization */
3799 	mtw_abort_tsf_sync(sc);
3800 	mtw_set_bssid(sc, ieee80211broadcastaddr);
3801 
3802 	MTW_UNLOCK(sc);
3803 
3804 	return;
3805 }
3806 
3807 static void
mtw_scan_end(struct ieee80211com * ic)3808 mtw_scan_end(struct ieee80211com *ic)
3809 {
3810 	struct mtw_softc *sc = ic->ic_softc;
3811 
3812 	MTW_LOCK(sc);
3813 
3814 	mtw_enable_tsf_sync(sc);
3815 	mtw_set_bssid(sc, sc->sc_bssid);
3816 
3817 	MTW_UNLOCK(sc);
3818 
3819 	return;
3820 }
3821 
3822 /*
3823  * Could be called from ieee80211_node_timeout()
3824  * (non-sleepable thread)
3825  */
3826 static void
mtw_update_beacon(struct ieee80211vap * vap,int item)3827 mtw_update_beacon(struct ieee80211vap *vap, int item)
3828 {
3829 	struct ieee80211com *ic = vap->iv_ic;
3830 	struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off;
3831 	struct ieee80211_node *ni = vap->iv_bss;
3832 	struct mtw_softc *sc = ic->ic_softc;
3833 	struct mtw_vap *rvp = MTW_VAP(vap);
3834 	int mcast = 0;
3835 	uint32_t i;
3836 
3837 	switch (item) {
3838 	case IEEE80211_BEACON_ERP:
3839 		mtw_updateslot(ic);
3840 		break;
3841 	case IEEE80211_BEACON_HTINFO:
3842 		mtw_updateprot(ic);
3843 		break;
3844 	case IEEE80211_BEACON_TIM:
3845 		mcast = 1; /*TODO*/
3846 		break;
3847 	default:
3848 		break;
3849 	}
3850 
3851 	setbit(bo->bo_flags, item);
3852 	if (rvp->beacon_mbuf == NULL) {
3853 		rvp->beacon_mbuf = ieee80211_beacon_alloc(ni);
3854 		if (rvp->beacon_mbuf == NULL)
3855 			return;
3856 	}
3857 	ieee80211_beacon_update(ni, rvp->beacon_mbuf, mcast);
3858 
3859 	i = MTW_CMDQ_GET(&sc->cmdq_store);
3860 	MTW_DPRINTF(sc, MTW_DEBUG_BEACON, "cmdq_store=%d\n", i);
3861 	sc->cmdq[i].func = mtw_update_beacon_cb;
3862 	sc->cmdq[i].arg0 = vap;
3863 	ieee80211_runtask(ic, &sc->cmdq_task);
3864 
3865 	return;
3866 }
3867 
3868 static void
mtw_update_beacon_cb(void * arg)3869 mtw_update_beacon_cb(void *arg)
3870 {
3871 
3872 	struct ieee80211vap *vap = arg;
3873 	struct ieee80211_node *ni = vap->iv_bss;
3874 	struct mtw_vap *rvp = MTW_VAP(vap);
3875 	struct ieee80211com *ic = vap->iv_ic;
3876 	struct mtw_softc *sc = ic->ic_softc;
3877 	struct mtw_txwi txwi;
3878 	struct mbuf *m;
3879 	uint16_t txwisize;
3880 	uint8_t ridx;
3881 	if (ni->ni_chan == IEEE80211_CHAN_ANYC)
3882 		return;
3883 	if (ic->ic_bsschan == IEEE80211_CHAN_ANYC)
3884 		return;
3885 
3886 	/*
3887 	 * No need to call ieee80211_beacon_update(), mtw_update_beacon()
3888 	 * is taking care of appropriate calls.
3889 	 */
3890 	if (rvp->beacon_mbuf == NULL) {
3891 		rvp->beacon_mbuf = ieee80211_beacon_alloc(ni);
3892 		if (rvp->beacon_mbuf == NULL)
3893 			return;
3894 	}
3895 	m = rvp->beacon_mbuf;
3896 
3897 	memset(&txwi, 0, sizeof(txwi));
3898 	txwi.wcid = 0xff;
3899 	txwi.len = htole16(m->m_pkthdr.len);
3900 
3901 	/* send beacons at the lowest available rate */
3902 	ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? MTW_RIDX_OFDM6 :
3903 							MTW_RIDX_CCK1;
3904 	txwi.phy = htole16(rt2860_rates[ridx].mcs);
3905 	if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
3906 		txwi.phy |= htole16(MTW_PHY_OFDM);
3907 	txwi.txop = MTW_TX_TXOP_HT;
3908 	txwi.flags = MTW_TX_TS;
3909 	txwi.xflags = MTW_TX_NSEQ;
3910 
3911 	txwisize =  sizeof(txwi);
3912 	mtw_write_region_1(sc, MTW_BCN_BASE, (uint8_t *)&txwi, txwisize);
3913 	mtw_write_region_1(sc, MTW_BCN_BASE + txwisize, mtod(m, uint8_t *),
3914 	    (m->m_pkthdr.len + 1) & ~1);
3915 }
3916 
3917 static void
mtw_updateprot(struct ieee80211com * ic)3918 mtw_updateprot(struct ieee80211com *ic)
3919 {
3920 	struct mtw_softc *sc = ic->ic_softc;
3921 	uint32_t i;
3922 
3923 	i = MTW_CMDQ_GET(&sc->cmdq_store);
3924 	MTW_DPRINTF(sc, MTW_DEBUG_BEACON, "test cmdq_store=%d\n", i);
3925 	sc->cmdq[i].func = mtw_updateprot_cb;
3926 	sc->cmdq[i].arg0 = ic;
3927 	ieee80211_runtask(ic, &sc->cmdq_task);
3928 }
3929 
3930 static void
mtw_updateprot_cb(void * arg)3931 mtw_updateprot_cb(void *arg)
3932 {
3933 
3934 	struct ieee80211com *ic = arg;
3935 	struct mtw_softc *sc = ic->ic_softc;
3936 	uint32_t tmp;
3937 
3938 	tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
3939 	/* setup protection frame rate (MCS code) */
3940 	tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ?
3941 	    rt2860_rates[MTW_RIDX_OFDM6].mcs | MTW_PHY_OFDM :
3942 	    rt2860_rates[MTW_RIDX_CCK11].mcs;
3943 
3944 	/* CCK frames don't require protection */
3945 	mtw_write(sc, MTW_CCK_PROT_CFG, tmp);
3946 	if (ic->ic_flags & IEEE80211_F_USEPROT) {
3947 		if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3948 			tmp |= RT2860_PROT_CTRL_RTS_CTS;
3949 		else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3950 			tmp |= RT2860_PROT_CTRL_CTS;
3951 	}
3952 	mtw_write(sc, MTW_OFDM_PROT_CFG, tmp);
3953 }
3954 
3955 static void
mtw_usb_timeout_cb(void * arg)3956 mtw_usb_timeout_cb(void *arg)
3957 {
3958 	struct ieee80211vap *vap = arg;
3959 	struct mtw_softc *sc = vap->iv_ic->ic_softc;
3960 
3961 	MTW_LOCK_ASSERT(sc, MA_OWNED);
3962 
3963 	if (vap->iv_state == IEEE80211_S_SCAN) {
3964 		MTW_DPRINTF(sc, MTW_DEBUG_USB | MTW_DEBUG_STATE,
3965 		    "timeout caused by scan\n");
3966 		/* cancel bgscan */
3967 		ieee80211_cancel_scan(vap);
3968 	} else {
3969 		MTW_DPRINTF(sc, MTW_DEBUG_USB | MTW_DEBUG_STATE,
3970 		    "timeout by unknown cause\n");
3971 	}
3972 }
mtw_reset(struct mtw_softc * sc)3973 static int mtw_reset(struct mtw_softc *sc)
3974 {
3975 
3976 	usb_device_request_t req;
3977 	uint16_t tmp;
3978 	uint16_t actlen;
3979 
3980 	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3981 	req.bRequest = MTW_RESET;
3982 	USETW(req.wValue, 1);
3983 	USETW(req.wIndex, 0);
3984 	USETW(req.wLength, 0);
3985 	return (usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
3986 				 &req, &tmp, 0, &actlen, 1000));
3987 
3988 }
3989 
3990 
3991 static void
mtw_update_promisc_locked(struct mtw_softc * sc)3992 mtw_update_promisc_locked(struct mtw_softc *sc)
3993 {
3994 
3995 	uint32_t tmp;
3996 
3997 	mtw_read(sc, MTW_RX_FILTR_CFG, &tmp);
3998 
3999 	tmp |= MTW_DROP_UC_NOME;
4000 	if (sc->sc_ic.ic_promisc > 0)
4001 		tmp &= ~MTW_DROP_UC_NOME;
4002 
4003 	mtw_write(sc, MTW_RX_FILTR_CFG, tmp);
4004 
4005 	MTW_DPRINTF(sc, MTW_DEBUG_RECV, "%s promiscuous mode\n",
4006 	    (sc->sc_ic.ic_promisc > 0) ? "entering" : "leaving");
4007 }
4008 
4009 static void
mtw_update_promisc(struct ieee80211com * ic)4010 mtw_update_promisc(struct ieee80211com *ic)
4011 {
4012 	struct mtw_softc *sc = ic->ic_softc;
4013 
4014 	if ((sc->sc_flags & MTW_RUNNING) == 0)
4015 		return;
4016 
4017 	MTW_LOCK(sc);
4018 	mtw_update_promisc_locked(sc);
4019 	MTW_UNLOCK(sc);
4020 }
4021 
4022 static void
mtw_enable_tsf_sync(struct mtw_softc * sc)4023 mtw_enable_tsf_sync(struct mtw_softc *sc)
4024 {
4025 	struct ieee80211com *ic = &sc->sc_ic;
4026 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4027 	uint32_t tmp;
4028 	int error;
4029 	mtw_read(sc, MTW_BCN_TIME_CFG, &tmp);
4030 	tmp &= ~0x1fffff;
4031 	tmp |= vap->iv_bss->ni_intval * 16;
4032 	tmp |= MTW_TSF_TIMER_EN | MTW_TBTT_TIMER_EN;
4033 
4034 	/* local TSF is always updated with remote TSF on beacon reception */
4035 	tmp |= 1 << MTW_TSF_SYNC_MODE_SHIFT;
4036 	error = mtw_write(sc, MTW_BCN_TIME_CFG, tmp);
4037 	if (error != 0) {
4038 		device_printf(sc->sc_dev, "enable_tsf_sync failed error:%d\n",
4039 		    error);
4040 	}
4041 	return;
4042 }
4043 
4044 static void
mtw_enable_mrr(struct mtw_softc * sc)4045 mtw_enable_mrr(struct mtw_softc *sc)
4046 {
4047 #define CCK(mcs) (mcs)
4048 
4049 #define OFDM(mcs) (1 << 3 | (mcs))
4050 	mtw_write(sc, MTW_LG_FBK_CFG0,
4051 	    OFDM(6) << 28 |	/* 54->48 */
4052 		OFDM(5) << 24 | /* 48->36 */
4053 		OFDM(4) << 20 | /* 36->24 */
4054 		OFDM(3) << 16 | /* 24->18 */
4055 		OFDM(2) << 12 | /* 18->12 */
4056 		OFDM(1) << 8 |	/* 12-> 9 */
4057 		OFDM(0) << 4 |	/*  9-> 6 */
4058 		OFDM(0));	/*  6-> 6 */
4059 
4060 	mtw_write(sc, MTW_LG_FBK_CFG1,
4061 	    CCK(2) << 12 |    /* 11->5.5 */
4062 		CCK(1) << 8 | /* 5.5-> 2 */
4063 		CCK(0) << 4 | /*   2-> 1 */
4064 		CCK(0));      /*   1-> 1 */
4065 #undef OFDM
4066 #undef CCK
4067 }
4068 
4069 static void
mtw_set_txpreamble(struct mtw_softc * sc)4070 mtw_set_txpreamble(struct mtw_softc *sc)
4071 {
4072 	struct ieee80211com *ic = &sc->sc_ic;
4073 	uint32_t tmp;
4074 
4075 	mtw_read(sc, MTW_AUTO_RSP_CFG, &tmp);
4076 	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4077 		tmp |= MTW_CCK_SHORT_EN;
4078 	else
4079 		tmp &= ~MTW_CCK_SHORT_EN;
4080 	mtw_write(sc, MTW_AUTO_RSP_CFG, tmp);
4081 }
4082 
4083 static void
mtw_set_basicrates(struct mtw_softc * sc)4084 mtw_set_basicrates(struct mtw_softc *sc)
4085 {
4086 	struct ieee80211com *ic = &sc->sc_ic;
4087 
4088 	/* set basic rates mask */
4089 	if (ic->ic_curmode == IEEE80211_MODE_11B)
4090 		mtw_write(sc, MTW_LEGACY_BASIC_RATE, 0x003);
4091 	else if (ic->ic_curmode == IEEE80211_MODE_11A)
4092 		mtw_write(sc, MTW_LEGACY_BASIC_RATE, 0x150);
4093 	else /* 11g */
4094 		mtw_write(sc, MTW_LEGACY_BASIC_RATE, 0x17f);
4095 }
4096 
4097 static void
mtw_set_bssid(struct mtw_softc * sc,const uint8_t * bssid)4098 mtw_set_bssid(struct mtw_softc *sc, const uint8_t *bssid)
4099 {
4100 	mtw_write(sc, MTW_MAC_BSSID_DW0,
4101 	    bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
4102 	mtw_write(sc, MTW_MAC_BSSID_DW1, bssid[4] | bssid[5] << 8);
4103 }
4104 
4105 static void
mtw_set_macaddr(struct mtw_softc * sc,const uint8_t * addr)4106 mtw_set_macaddr(struct mtw_softc *sc, const uint8_t *addr)
4107 {
4108 	mtw_write(sc, MTW_MAC_ADDR_DW0,
4109 	    addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4110 	mtw_write(sc, MTW_MAC_ADDR_DW1, addr[4] | addr[5] << 8 | 0xff << 16);
4111 }
4112 
4113 static void
mtw_updateslot(struct ieee80211com * ic)4114 mtw_updateslot(struct ieee80211com *ic)
4115 {
4116 
4117 	struct mtw_softc *sc = ic->ic_softc;
4118 	uint32_t i;
4119 
4120 	i = MTW_CMDQ_GET(&sc->cmdq_store);
4121 	MTW_DPRINTF(sc, MTW_DEBUG_BEACON, "cmdq_store=%d\n", i);
4122 	sc->cmdq[i].func = mtw_updateslot_cb;
4123 	sc->cmdq[i].arg0 = ic;
4124 	ieee80211_runtask(ic, &sc->cmdq_task);
4125 
4126 	return;
4127 }
4128 
4129 /* ARGSUSED */
4130 static void
mtw_updateslot_cb(void * arg)4131 mtw_updateslot_cb(void *arg)
4132 {
4133   struct ieee80211com *ic = arg;
4134 	struct mtw_softc *sc = ic->ic_softc;
4135 	uint32_t tmp;
4136 	mtw_read(sc, MTW_BKOFF_SLOT_CFG, &tmp);
4137 	tmp &= ~0xff;
4138 	tmp |= IEEE80211_GET_SLOTTIME(ic);
4139 	mtw_write(sc, MTW_BKOFF_SLOT_CFG, tmp);
4140 }
4141 
4142 static void
mtw_update_mcast(struct ieee80211com * ic)4143 mtw_update_mcast(struct ieee80211com *ic)
4144 {
4145 }
4146 
4147 static int8_t
mtw_rssi2dbm(struct mtw_softc * sc,uint8_t rssi,uint8_t rxchain)4148 mtw_rssi2dbm(struct mtw_softc *sc, uint8_t rssi, uint8_t rxchain)
4149 {
4150 	struct ieee80211com *ic = &sc->sc_ic;
4151 	struct ieee80211_channel *c = ic->ic_curchan;
4152 	int delta;
4153 
4154 	if (IEEE80211_IS_CHAN_5GHZ(c)) {
4155 		u_int chan = ieee80211_chan2ieee(ic, c);
4156 		delta = sc->rssi_5ghz[rxchain];
4157 
4158 		/* determine channel group */
4159 		if (chan <= 64)
4160 			delta -= sc->lna[1];
4161 		else if (chan <= 128)
4162 			delta -= sc->lna[2];
4163 		else
4164 			delta -= sc->lna[3];
4165 	} else
4166 		delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
4167 
4168 	return (-12 - delta - rssi);
4169 }
4170 static int
mt7601_bbp_init(struct mtw_softc * sc)4171 mt7601_bbp_init(struct mtw_softc *sc)
4172 {
4173 	uint8_t bbp;
4174 	int i, error, ntries;
4175 
4176 	/* wait for BBP to wake up */
4177 	for (ntries = 0; ntries < 20; ntries++) {
4178 		if ((error = mtw_bbp_read(sc, 0, &bbp)) != 0)
4179 			return (error);
4180 		if (bbp != 0 && bbp != 0xff)
4181 			break;
4182 	}
4183 
4184 	if (ntries == 20)
4185 		return (ETIMEDOUT);
4186 
4187 	mtw_bbp_read(sc, 3, &bbp);
4188 	mtw_bbp_write(sc, 3, 0);
4189 	mtw_bbp_read(sc, 105, &bbp);
4190 	mtw_bbp_write(sc, 105, 0);
4191 
4192 	/* initialize BBP registers to default values */
4193 	for (i = 0; i < nitems(mt7601_def_bbp); i++) {
4194 		if ((error = mtw_bbp_write(sc, mt7601_def_bbp[i].reg,
4195 			 mt7601_def_bbp[i].val)) != 0)
4196 			return (error);
4197 	}
4198 
4199 	sc->sc_bw_calibrated = 0;
4200 
4201 	return (0);
4202 }
4203 
4204 static int
mt7601_rf_init(struct mtw_softc * sc)4205 mt7601_rf_init(struct mtw_softc *sc)
4206 {
4207 	int i, error;
4208 
4209 	/* RF bank 0 */
4210 	for (i = 0; i < nitems(mt7601_rf_bank0); i++) {
4211 		error = mtw_rf_write(sc, 0, mt7601_rf_bank0[i].reg,
4212 		    mt7601_rf_bank0[i].val);
4213 		if (error != 0)
4214 			return (error);
4215 	}
4216 	/* RF bank 4 */
4217 	for (i = 0; i < nitems(mt7601_rf_bank4); i++) {
4218 		error = mtw_rf_write(sc, 4, mt7601_rf_bank4[i].reg,
4219 		    mt7601_rf_bank4[i].val);
4220 		if (error != 0)
4221 			return (error);
4222 	}
4223 	/* RF bank 5 */
4224 	for (i = 0; i < nitems(mt7601_rf_bank5); i++) {
4225 		error = mtw_rf_write(sc, 5, mt7601_rf_bank5[i].reg,
4226 		    mt7601_rf_bank5[i].val);
4227 		if (error != 0)
4228 			return (error);
4229 	}
4230 	return (0);
4231 }
4232 
4233 static int
mtw_txrx_enable(struct mtw_softc * sc)4234 mtw_txrx_enable(struct mtw_softc *sc)
4235 {
4236 	struct ieee80211com *ic = &sc->sc_ic;
4237 	uint32_t tmp;
4238 	int error, ntries;
4239 	mtw_write(sc, MTW_MAC_SYS_CTRL, MTW_MAC_TX_EN);
4240 	for (ntries = 0; ntries < 200; ntries++) {
4241 		if ((error = mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp)) != 0) {
4242 			return (error);
4243 		}
4244 		if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
4245 			break;
4246 		mtw_delay(sc, 50);
4247 	}
4248 	if (ntries == 200) {
4249 		return (ETIMEDOUT);
4250 	}
4251 
4252 	DELAY(50);
4253 
4254 	tmp |= MTW_RX_DMA_EN | MTW_TX_DMA_EN | MTW_TX_WB_DDONE;
4255 	mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
4256 
4257 	/* enable Rx bulk aggregation (set timeout and limit) */
4258 	tmp = MTW_USB_TX_EN | MTW_USB_RX_EN | MTW_USB_RX_AGG_EN |
4259 	    MTW_USB_RX_AGG_TO(128) | MTW_USB_RX_AGG_LMT(2);
4260 	mtw_write(sc, MTW_USB_DMA_CFG, tmp);
4261 
4262 	/* set Rx filter */
4263 	tmp = MTW_DROP_CRC_ERR | MTW_DROP_PHY_ERR;
4264 	if (ic->ic_opmode != IEEE80211_M_MONITOR) {
4265 		tmp |= MTW_DROP_UC_NOME | MTW_DROP_DUPL | MTW_DROP_CTS |
4266 		    MTW_DROP_BA | MTW_DROP_ACK | MTW_DROP_VER_ERR |
4267 		    MTW_DROP_CTRL_RSV | MTW_DROP_CFACK | MTW_DROP_CFEND;
4268 		if (ic->ic_opmode == IEEE80211_M_STA)
4269 			tmp |= MTW_DROP_RTS | MTW_DROP_PSPOLL;
4270 	}
4271 	mtw_write(sc, MTW_RX_FILTR_CFG, tmp);
4272 
4273 	mtw_write(sc, MTW_MAC_SYS_CTRL, MTW_MAC_RX_EN | MTW_MAC_TX_EN);
4274 	return (0);
4275 }
4276 static int
mt7601_rxdc_cal(struct mtw_softc * sc)4277 mt7601_rxdc_cal(struct mtw_softc *sc)
4278 {
4279 	uint32_t tmp;
4280 	uint8_t bbp;
4281 	int ntries;
4282 
4283 	mtw_read(sc, MTW_MAC_SYS_CTRL, &tmp);
4284 	mtw_write(sc, MTW_MAC_SYS_CTRL, MTW_MAC_RX_EN);
4285 	mtw_bbp_write(sc, 158, 0x8d);
4286 	mtw_bbp_write(sc, 159, 0xfc);
4287 	mtw_bbp_write(sc, 158, 0x8c);
4288 	mtw_bbp_write(sc, 159, 0x4c);
4289 
4290 	for (ntries = 0; ntries < 20; ntries++) {
4291 		DELAY(300);
4292 		mtw_bbp_write(sc, 158, 0x8c);
4293 		mtw_bbp_read(sc, 159, &bbp);
4294 		if (bbp == 0x0c)
4295 			break;
4296 	}
4297 
4298 	if (ntries == 20)
4299 		return (ETIMEDOUT);
4300 
4301 	mtw_write(sc, MTW_MAC_SYS_CTRL, 0);
4302 	mtw_bbp_write(sc, 158, 0x8d);
4303 	mtw_bbp_write(sc, 159, 0xe0);
4304 	mtw_write(sc, MTW_MAC_SYS_CTRL, tmp);
4305 	return (0);
4306 }
4307 
4308 static int
mt7601_r49_read(struct mtw_softc * sc,uint8_t flag,int8_t * val)4309 mt7601_r49_read(struct mtw_softc *sc, uint8_t flag, int8_t *val)
4310 {
4311 	uint8_t bbp;
4312 
4313 	mtw_bbp_read(sc, 47, &bbp);
4314 	bbp = 0x90;
4315 	mtw_bbp_write(sc, 47, bbp);
4316 	bbp &= ~0x0f;
4317 	bbp |= flag;
4318 	mtw_bbp_write(sc, 47, bbp);
4319 	return (mtw_bbp_read(sc, 49, val));
4320 }
4321 
4322 static int
mt7601_rf_temperature(struct mtw_softc * sc,int8_t * val)4323 mt7601_rf_temperature(struct mtw_softc *sc, int8_t *val)
4324 {
4325 	uint32_t rfb, rfs;
4326 	uint8_t bbp;
4327 	int ntries;
4328 
4329 	mtw_read(sc, MTW_RF_BYPASS0, &rfb);
4330 	mtw_read(sc, MTW_RF_SETTING0, &rfs);
4331 	mtw_write(sc, MTW_RF_BYPASS0, 0);
4332 	mtw_write(sc, MTW_RF_SETTING0, 0x10);
4333 	mtw_write(sc, MTW_RF_BYPASS0, 0x10);
4334 
4335 	mtw_bbp_read(sc, 47, &bbp);
4336 	bbp &= ~0x7f;
4337 	bbp |= 0x10;
4338 	mtw_bbp_write(sc, 47, bbp);
4339 
4340 	mtw_bbp_write(sc, 22, 0x40);
4341 
4342 	for (ntries = 0; ntries < 10; ntries++) {
4343 		mtw_bbp_read(sc, 47, &bbp);
4344 		if ((bbp & 0x10) == 0)
4345 			break;
4346 	}
4347 	if (ntries == 10)
4348 		return (ETIMEDOUT);
4349 
4350 	mt7601_r49_read(sc, MT7601_R47_TEMP, val);
4351 
4352 	mtw_bbp_write(sc, 22, 0);
4353 
4354 	mtw_bbp_read(sc, 21, &bbp);
4355 	bbp |= 0x02;
4356 	mtw_bbp_write(sc, 21, bbp);
4357 	bbp &= ~0x02;
4358 	mtw_bbp_write(sc, 21, bbp);
4359 
4360 	mtw_write(sc, MTW_RF_BYPASS0, 0);
4361 	mtw_write(sc, MTW_RF_SETTING0, rfs);
4362 	mtw_write(sc, MTW_RF_BYPASS0, rfb);
4363 	return (0);
4364 }
4365 
4366 static int
mt7601_rf_setup(struct mtw_softc * sc)4367 mt7601_rf_setup(struct mtw_softc *sc)
4368 {
4369 	uint32_t tmp;
4370 	uint8_t rf;
4371 	int error;
4372 
4373 	if (sc->sc_rf_calibrated)
4374 		return (0);
4375 
4376 	/* init RF registers */
4377 	if ((error = mt7601_rf_init(sc)) != 0)
4378 		return (error);
4379 
4380 	/* init frequency offset */
4381 	mtw_rf_write(sc, 0, 12, sc->rf_freq_offset);
4382 	mtw_rf_read(sc, 0, 12, &rf);
4383 
4384 	/* read temperature */
4385 	mt7601_rf_temperature(sc, &rf);
4386 	sc->bbp_temp = rf;
4387 	device_printf(sc->sc_dev, "BBP temp 0x%x\n", rf);
4388 
4389 	mtw_rf_read(sc, 0, 7, &rf);
4390 	if ((error = mtw_mcu_calibrate(sc, 0x1, 0)) != 0)
4391 		return (error);
4392 	mtw_delay(sc, 100);
4393 	mtw_rf_read(sc, 0, 7, &rf);
4394 
4395 	/* Calibrate VCO RF 0/4 */
4396 	mtw_rf_write(sc, 0, 4, 0x0a);
4397 	mtw_rf_write(sc, 0, 4, 0x20);
4398 	mtw_rf_read(sc, 0, 4, &rf);
4399 	mtw_rf_write(sc, 0, 4, rf | 0x80);
4400 
4401 	if ((error = mtw_mcu_calibrate(sc, 0x9, 0)) != 0)
4402 		return (error);
4403 	if ((error = mt7601_rxdc_cal(sc)) != 0)
4404 		return (error);
4405 	if ((error = mtw_mcu_calibrate(sc, 0x6, 1)) != 0)
4406 		return (error);
4407 	if ((error = mtw_mcu_calibrate(sc, 0x6, 0)) != 0)
4408 		return (error);
4409 	if ((error = mtw_mcu_calibrate(sc, 0x4, 0)) != 0)
4410 		return (error);
4411 	if ((error = mtw_mcu_calibrate(sc, 0x5, 0)) != 0)
4412 		return (error);
4413 
4414 	mtw_read(sc, MTW_LDO_CFG0, &tmp);
4415 	tmp &= ~(1 << 4);
4416 	tmp |= (1 << 2);
4417 	mtw_write(sc, MTW_LDO_CFG0, tmp);
4418 
4419 	if ((error = mtw_mcu_calibrate(sc, 0x8, 0)) != 0)
4420 		return (error);
4421 	if ((error = mt7601_rxdc_cal(sc)) != 0)
4422 		return (error);
4423 
4424 	sc->sc_rf_calibrated = 1;
4425 	return (0);
4426 }
4427 
4428 static void
mtw_set_txrts(struct mtw_softc * sc)4429 mtw_set_txrts(struct mtw_softc *sc)
4430 {
4431 	uint32_t tmp;
4432 
4433 	/* set RTS threshold */
4434 	mtw_read(sc, MTW_TX_RTS_CFG, &tmp);
4435 	tmp &= ~0xffff00;
4436 	tmp |= 0x1000 << MTW_RTS_THRES_SHIFT;
4437 	mtw_write(sc, MTW_TX_RTS_CFG, tmp);
4438 }
4439 static int
mtw_mcu_radio(struct mtw_softc * sc,int func,uint32_t val)4440 mtw_mcu_radio(struct mtw_softc *sc, int func, uint32_t val)
4441 {
4442 	struct mtw_mcu_cmd_16 cmd;
4443 
4444 	cmd.r1 = htole32(func);
4445 	cmd.r2 = htole32(val);
4446 	cmd.r3 = 0;
4447 	cmd.r4 = 0;
4448 	return (mtw_mcu_cmd(sc, 20, &cmd, sizeof(struct mtw_mcu_cmd_16)));
4449 }
4450 static void
mtw_init_locked(struct mtw_softc * sc)4451 mtw_init_locked(struct mtw_softc *sc)
4452 {
4453 
4454 	struct ieee80211com *ic = &sc->sc_ic;
4455 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4456 	uint32_t tmp;
4457 	int i, error, ridx, ntries;
4458 	if (ic->ic_nrunning > 1)
4459 		return;
4460 	mtw_stop(sc);
4461 
4462 	for (i = 0; i != MTW_EP_QUEUES; i++)
4463 		mtw_setup_tx_list(sc, &sc->sc_epq[i]);
4464 
4465 	for (ntries = 0; ntries < 100; ntries++) {
4466 		if ((error = mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp)) != 0)
4467 			goto fail;
4468 		if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
4469 			break;
4470 		DELAY(1000);
4471 	}
4472 	if (ntries == 100) {
4473 		device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
4474 		error = ETIMEDOUT;
4475 		goto fail;
4476 	}
4477 	tmp &= 0xff0;
4478 	tmp |= MTW_TX_WB_DDONE;
4479 	mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
4480 
4481 	mtw_set_leds(sc, MTW_LED_MODE_ON);
4482 	/* reset MAC and baseband */
4483 	mtw_write(sc, MTW_MAC_SYS_CTRL, MTW_BBP_HRST | MTW_MAC_SRST);
4484 	mtw_write(sc, MTW_USB_DMA_CFG, 0);
4485 	mtw_write(sc, MTW_MAC_SYS_CTRL, 0);
4486 
4487 	/* init MAC values */
4488 	if (sc->asic_ver == 0x7601) {
4489 		for (i = 0; i < nitems(mt7601_def_mac); i++)
4490 			mtw_write(sc, mt7601_def_mac[i].reg,
4491 			    mt7601_def_mac[i].val);
4492 	}
4493 
4494 	/* wait while MAC is busy */
4495 	for (ntries = 0; ntries < 100; ntries++) {
4496 		if ((error = mtw_read(sc, MTW_MAC_STATUS_REG, &tmp)) != 0)
4497 			goto fail;
4498 		if (!(tmp & (MTW_RX_STATUS_BUSY | MTW_TX_STATUS_BUSY)))
4499 			break;
4500 		DELAY(1000);
4501 	}
4502 	if (ntries == 100) {
4503 		error = ETIMEDOUT;
4504 		goto fail;
4505 	}
4506 
4507 	/* set MAC address */
4508 
4509 	mtw_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
4510 
4511 	/* clear WCID attribute table */
4512 	mtw_set_region_4(sc, MTW_WCID_ATTR(0), 1, 8 * 32);
4513 
4514 	mtw_write(sc, 0x1648, 0x00830083);
4515 	mtw_read(sc, MTW_FCE_L2_STUFF, &tmp);
4516 	tmp &= ~MTW_L2S_WR_MPDU_LEN_EN;
4517 	mtw_write(sc, MTW_FCE_L2_STUFF, tmp);
4518 
4519 	/* RTS config */
4520 	mtw_set_txrts(sc);
4521 
4522 	/* clear Host to MCU mailbox */
4523 	mtw_write(sc, MTW_BBP_CSR, 0);
4524 	mtw_write(sc, MTW_H2M_MAILBOX, 0);
4525 
4526 	/* clear RX WCID search table */
4527 	mtw_set_region_4(sc, MTW_WCID_ENTRY(0), 0xffffffff, 512);
4528 
4529 	/* abort TSF synchronization */
4530 	mtw_abort_tsf_sync(sc);
4531 
4532 	mtw_read(sc, MTW_US_CYC_CNT, &tmp);
4533 	tmp = (tmp & ~0xff);
4534 	if (sc->asic_ver == 0x7601)
4535 		tmp |= 0x1e;
4536 	mtw_write(sc, MTW_US_CYC_CNT, tmp);
4537 
4538 	/* clear shared key table */
4539 	mtw_set_region_4(sc, MTW_SKEY(0, 0), 0, 8 * 32);
4540 
4541 	/* clear IV/EIV table */
4542 	mtw_set_region_4(sc, MTW_IVEIV(0), 0, 8 * 32);
4543 
4544 	/* clear shared key mode */
4545 	mtw_write(sc, MTW_SKEY_MODE_0_7, 0);
4546 	mtw_write(sc, MTW_SKEY_MODE_8_15, 0);
4547 
4548 	/* txop truncation */
4549 	mtw_write(sc, MTW_TXOP_CTRL_CFG, 0x0000583f);
4550 
4551 	/* init Tx power for all Tx rates */
4552 	for (ridx = 0; ridx < 5; ridx++) {
4553 		if (sc->txpow20mhz[ridx] == 0xffffffff)
4554 			continue;
4555 		mtw_write(sc, MTW_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
4556 	}
4557 	mtw_write(sc, MTW_TX_PWR_CFG7, 0);
4558 	mtw_write(sc, MTW_TX_PWR_CFG9, 0);
4559 
4560 	mtw_read(sc, MTW_CMB_CTRL, &tmp);
4561 	tmp &= ~(1 << 18 | 1 << 14);
4562 	mtw_write(sc, MTW_CMB_CTRL, tmp);
4563 
4564 	/* clear USB DMA */
4565 	mtw_write(sc, MTW_USB_DMA_CFG,
4566 	    MTW_USB_TX_EN | MTW_USB_RX_EN | MTW_USB_RX_AGG_EN |
4567 		MTW_USB_TX_CLEAR | MTW_USB_TXOP_HALT | MTW_USB_RX_WL_DROP);
4568 	mtw_delay(sc, 50);
4569 	mtw_read(sc, MTW_USB_DMA_CFG, &tmp);
4570 	tmp &= ~(MTW_USB_TX_CLEAR | MTW_USB_TXOP_HALT | MTW_USB_RX_WL_DROP);
4571 	mtw_write(sc, MTW_USB_DMA_CFG, tmp);
4572 
4573 	/* enable radio */
4574 	mtw_mcu_radio(sc, 0x31, 0);
4575 
4576 	/* init RF registers */
4577 	if (sc->asic_ver == 0x7601)
4578 		mt7601_rf_init(sc);
4579 
4580 	/* init baseband registers */
4581 	if (sc->asic_ver == 0x7601)
4582 		error = mt7601_bbp_init(sc);
4583 
4584 	if (error != 0) {
4585 		device_printf(sc->sc_dev, "could not initialize BBP\n");
4586 		goto fail;
4587 	}
4588 
4589 	/* setup and calibrate RF */
4590 	error = mt7601_rf_setup(sc);
4591 
4592 	if (error != 0) {
4593 		device_printf(sc->sc_dev, "could not initialize RF\n");
4594 		goto fail;
4595 	}
4596 
4597 	/* select default channel */
4598 	mtw_set_chan(sc, ic->ic_curchan);
4599 
4600 	/* setup initial protection mode */
4601 	mtw_updateprot_cb(ic);
4602 
4603 	sc->sc_flags |= MTW_RUNNING;
4604 	sc->cmdq_run = MTW_CMDQ_GO;
4605 	for (i = 0; i != MTW_N_XFER; i++)
4606 		usbd_xfer_set_stall(sc->sc_xfer[i]);
4607 
4608 	usbd_transfer_start(sc->sc_xfer[MTW_BULK_RX]);
4609 
4610 	error = mtw_txrx_enable(sc);
4611 	if (error != 0) {
4612 		goto fail;
4613 	}
4614 
4615 	return;
4616 
4617 fail:
4618 
4619 	mtw_stop(sc);
4620 	return;
4621 }
4622 
4623 static void
mtw_stop(void * arg)4624 mtw_stop(void *arg)
4625 {
4626 	struct mtw_softc *sc = (struct mtw_softc *)arg;
4627 	uint32_t tmp;
4628 	int i, ntries, error;
4629 
4630 	MTW_LOCK_ASSERT(sc, MA_OWNED);
4631 
4632 	sc->sc_flags &= ~MTW_RUNNING;
4633 
4634 	sc->ratectl_run = MTW_RATECTL_OFF;
4635 	sc->cmdq_run = sc->cmdq_key_set;
4636 
4637 	MTW_UNLOCK(sc);
4638 
4639 	for (i = 0; i < MTW_N_XFER; i++)
4640 		usbd_transfer_drain(sc->sc_xfer[i]);
4641 
4642 	MTW_LOCK(sc);
4643 
4644 	mtw_drain_mbufq(sc);
4645 
4646 	if (sc->rx_m != NULL) {
4647 		m_free(sc->rx_m);
4648 		sc->rx_m = NULL;
4649 	}
4650 
4651 	/* Disable Tx/Rx DMA. */
4652 	mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp);
4653 	tmp &= ~(MTW_RX_DMA_EN | MTW_TX_DMA_EN);
4654 	mtw_write(sc, MTW_WPDMA_GLO_CFG, tmp);
4655 	// mtw_usb_dma_write(sc, 0);
4656 
4657 	for (ntries = 0; ntries < 100; ntries++) {
4658 		if (mtw_read(sc, MTW_WPDMA_GLO_CFG, &tmp) != 0)
4659 			break;
4660 		if ((tmp & (MTW_TX_DMA_BUSY | MTW_RX_DMA_BUSY)) == 0)
4661 			break;
4662 		DELAY(10);
4663 	}
4664 	if (ntries == 100) {
4665 		device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
4666 	}
4667 
4668 	/* stop MAC Tx/Rx */
4669 	mtw_read(sc, MTW_MAC_SYS_CTRL, &tmp);
4670 	tmp &= ~(MTW_MAC_RX_EN | MTW_MAC_TX_EN);
4671 	mtw_write(sc, MTW_MAC_SYS_CTRL, tmp);
4672 
4673 	/* disable RTS retry */
4674 	mtw_read(sc, MTW_TX_RTS_CFG, &tmp);
4675 	tmp &= ~0xff;
4676 	mtw_write(sc, MTW_TX_RTS_CFG, tmp);
4677 
4678 	/* US_CYC_CFG */
4679 	mtw_read(sc, MTW_US_CYC_CNT, &tmp);
4680 	tmp = (tmp & ~0xff);
4681 	mtw_write(sc, MTW_US_CYC_CNT, tmp);
4682 
4683 	/* stop PBF */
4684 	mtw_read(sc, MTW_PBF_CFG, &tmp);
4685 	tmp &= ~0x3;
4686 	mtw_write(sc, MTW_PBF_CFG, tmp);
4687 
4688 	/* wait for pending Tx to complete */
4689 	for (ntries = 0; ntries < 100; ntries++) {
4690 		if ((error = mtw_read(sc, MTW_TXRXQ_PCNT, &tmp)) != 0)
4691 			break;
4692 		if ((tmp & MTW_TX2Q_PCNT_MASK) == 0)
4693 			break;
4694 	}
4695 
4696 }
4697 
4698 static void
mtw_delay(struct mtw_softc * sc,u_int ms)4699 mtw_delay(struct mtw_softc *sc, u_int ms)
4700 {
4701 	usb_pause_mtx(mtx_owned(&sc->sc_mtx) ? &sc->sc_mtx : NULL,
4702 	    USB_MS_TO_TICKS(ms));
4703 }
4704 
4705 static void
mtw_update_chw(struct ieee80211com * ic)4706 mtw_update_chw(struct ieee80211com *ic)
4707 {
4708 
4709 	printf("%s: TODO\n", __func__);
4710 }
4711 
4712 static int
mtw_ampdu_enable(struct ieee80211_node * ni,struct ieee80211_tx_ampdu * tap)4713 mtw_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
4714 {
4715 
4716 	/* For now, no A-MPDU TX support in the driver */
4717 	return (0);
4718 }
4719 
4720 static device_method_t mtw_methods[] = {
4721 	/* Device interface */
4722 	DEVMETHOD(device_probe, mtw_match),
4723 	DEVMETHOD(device_attach, mtw_attach),
4724 	DEVMETHOD(device_detach, mtw_detach), DEVMETHOD_END
4725 };
4726 
4727 static driver_t mtw_driver = { .name = "mtw",
4728 	.methods = mtw_methods,
4729 	.size = sizeof(struct mtw_softc) };
4730 
4731 DRIVER_MODULE(mtw, uhub, mtw_driver, mtw_driver_loaded, NULL);
4732 MODULE_DEPEND(mtw, wlan, 1, 1, 1);
4733 MODULE_DEPEND(mtw, usb, 1, 1, 1);
4734 MODULE_DEPEND(mtw, firmware, 1, 1, 1);
4735 MODULE_VERSION(mtw, 1);
4736 USB_PNP_HOST_INFO(mtw_devs);
4737