1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7 #include <linux/component.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/dma-mapping.h>
14
15 #include <drm/clients/drm_client_setup.h>
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fbdev_dma.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_ioctl.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_vblank.h>
27
28 #include "mtk_crtc.h"
29 #include "mtk_ddp_comp.h"
30 #include "mtk_disp_drv.h"
31 #include "mtk_drm_drv.h"
32 #include "mtk_gem.h"
33
34 #define DRIVER_NAME "mediatek"
35 #define DRIVER_DESC "Mediatek SoC DRM"
36 #define DRIVER_MAJOR 1
37 #define DRIVER_MINOR 0
38
39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
41 };
42
43 static struct drm_framebuffer *
mtk_drm_mode_fb_create(struct drm_device * dev,struct drm_file * file,const struct drm_mode_fb_cmd2 * cmd)44 mtk_drm_mode_fb_create(struct drm_device *dev,
45 struct drm_file *file,
46 const struct drm_mode_fb_cmd2 *cmd)
47 {
48 const struct drm_format_info *info = drm_get_format_info(dev, cmd);
49
50 if (info->num_planes != 1)
51 return ERR_PTR(-EINVAL);
52
53 return drm_gem_fb_create(dev, file, cmd);
54 }
55
56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
57 .fb_create = mtk_drm_mode_fb_create,
58 .atomic_check = drm_atomic_helper_check,
59 .atomic_commit = drm_atomic_helper_commit,
60 };
61
62 static const unsigned int mt2701_mtk_ddp_main[] = {
63 DDP_COMPONENT_OVL0,
64 DDP_COMPONENT_RDMA0,
65 DDP_COMPONENT_COLOR0,
66 DDP_COMPONENT_BLS,
67 DDP_COMPONENT_DSI0,
68 };
69
70 static const unsigned int mt2701_mtk_ddp_ext[] = {
71 DDP_COMPONENT_RDMA1,
72 DDP_COMPONENT_DPI0,
73 };
74
75 static const unsigned int mt7623_mtk_ddp_main[] = {
76 DDP_COMPONENT_OVL0,
77 DDP_COMPONENT_RDMA0,
78 DDP_COMPONENT_COLOR0,
79 DDP_COMPONENT_BLS,
80 DDP_COMPONENT_DPI0,
81 };
82
83 static const unsigned int mt7623_mtk_ddp_ext[] = {
84 DDP_COMPONENT_RDMA1,
85 DDP_COMPONENT_DSI0,
86 };
87
88 static const unsigned int mt2712_mtk_ddp_main[] = {
89 DDP_COMPONENT_OVL0,
90 DDP_COMPONENT_COLOR0,
91 DDP_COMPONENT_AAL0,
92 DDP_COMPONENT_OD0,
93 DDP_COMPONENT_RDMA0,
94 DDP_COMPONENT_DPI0,
95 DDP_COMPONENT_PWM0,
96 };
97
98 static const unsigned int mt2712_mtk_ddp_ext[] = {
99 DDP_COMPONENT_OVL1,
100 DDP_COMPONENT_COLOR1,
101 DDP_COMPONENT_AAL1,
102 DDP_COMPONENT_OD1,
103 DDP_COMPONENT_RDMA1,
104 DDP_COMPONENT_DPI1,
105 DDP_COMPONENT_PWM1,
106 };
107
108 static const unsigned int mt2712_mtk_ddp_third[] = {
109 DDP_COMPONENT_RDMA2,
110 DDP_COMPONENT_DSI3,
111 DDP_COMPONENT_PWM2,
112 };
113
114 static unsigned int mt8167_mtk_ddp_main[] = {
115 DDP_COMPONENT_OVL0,
116 DDP_COMPONENT_COLOR0,
117 DDP_COMPONENT_CCORR,
118 DDP_COMPONENT_AAL0,
119 DDP_COMPONENT_GAMMA,
120 DDP_COMPONENT_DITHER0,
121 DDP_COMPONENT_RDMA0,
122 DDP_COMPONENT_DSI0,
123 };
124
125 static const unsigned int mt8173_mtk_ddp_main[] = {
126 DDP_COMPONENT_OVL0,
127 DDP_COMPONENT_COLOR0,
128 DDP_COMPONENT_AAL0,
129 DDP_COMPONENT_OD0,
130 DDP_COMPONENT_RDMA0,
131 DDP_COMPONENT_UFOE,
132 DDP_COMPONENT_DSI0,
133 DDP_COMPONENT_PWM0,
134 };
135
136 static const unsigned int mt8173_mtk_ddp_ext[] = {
137 DDP_COMPONENT_OVL1,
138 DDP_COMPONENT_COLOR1,
139 DDP_COMPONENT_GAMMA,
140 DDP_COMPONENT_RDMA1,
141 DDP_COMPONENT_DPI0,
142 };
143
144 static const unsigned int mt8183_mtk_ddp_main[] = {
145 DDP_COMPONENT_OVL0,
146 DDP_COMPONENT_OVL_2L0,
147 DDP_COMPONENT_RDMA0,
148 DDP_COMPONENT_COLOR0,
149 DDP_COMPONENT_CCORR,
150 DDP_COMPONENT_AAL0,
151 DDP_COMPONENT_GAMMA,
152 DDP_COMPONENT_DITHER0,
153 DDP_COMPONENT_DSI0,
154 };
155
156 static const unsigned int mt8183_mtk_ddp_ext[] = {
157 DDP_COMPONENT_OVL_2L1,
158 DDP_COMPONENT_RDMA1,
159 DDP_COMPONENT_DPI0,
160 };
161
162 static const unsigned int mt8186_mtk_ddp_main[] = {
163 DDP_COMPONENT_OVL0,
164 DDP_COMPONENT_RDMA0,
165 DDP_COMPONENT_COLOR0,
166 DDP_COMPONENT_CCORR,
167 DDP_COMPONENT_AAL0,
168 DDP_COMPONENT_GAMMA,
169 DDP_COMPONENT_POSTMASK0,
170 DDP_COMPONENT_DITHER0,
171 DDP_COMPONENT_DSI0,
172 };
173
174 static const unsigned int mt8186_mtk_ddp_ext[] = {
175 DDP_COMPONENT_OVL_2L0,
176 DDP_COMPONENT_RDMA1,
177 DDP_COMPONENT_DPI0,
178 };
179
180 static const unsigned int mt8188_mtk_ddp_main[] = {
181 DDP_COMPONENT_OVL0,
182 DDP_COMPONENT_RDMA0,
183 DDP_COMPONENT_COLOR0,
184 DDP_COMPONENT_CCORR,
185 DDP_COMPONENT_AAL0,
186 DDP_COMPONENT_GAMMA,
187 DDP_COMPONENT_POSTMASK0,
188 DDP_COMPONENT_DITHER0,
189 };
190
191 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
192 {0, DDP_COMPONENT_DP_INTF0},
193 {0, DDP_COMPONENT_DSI0},
194 };
195
196 static const unsigned int mt8192_mtk_ddp_main[] = {
197 DDP_COMPONENT_OVL0,
198 DDP_COMPONENT_OVL_2L0,
199 DDP_COMPONENT_RDMA0,
200 DDP_COMPONENT_COLOR0,
201 DDP_COMPONENT_CCORR,
202 DDP_COMPONENT_AAL0,
203 DDP_COMPONENT_GAMMA,
204 DDP_COMPONENT_POSTMASK0,
205 DDP_COMPONENT_DITHER0,
206 DDP_COMPONENT_DSI0,
207 };
208
209 static const unsigned int mt8192_mtk_ddp_ext[] = {
210 DDP_COMPONENT_OVL_2L2,
211 DDP_COMPONENT_RDMA4,
212 DDP_COMPONENT_DPI0,
213 };
214
215 static const unsigned int mt8195_mtk_ddp_main[] = {
216 DDP_COMPONENT_OVL0,
217 DDP_COMPONENT_RDMA0,
218 DDP_COMPONENT_COLOR0,
219 DDP_COMPONENT_CCORR,
220 DDP_COMPONENT_AAL0,
221 DDP_COMPONENT_GAMMA,
222 DDP_COMPONENT_DITHER0,
223 DDP_COMPONENT_DSC0,
224 DDP_COMPONENT_MERGE0,
225 DDP_COMPONENT_DP_INTF0,
226 };
227
228 static const unsigned int mt8195_mtk_ddp_ext[] = {
229 DDP_COMPONENT_DRM_OVL_ADAPTOR,
230 DDP_COMPONENT_MERGE5,
231 DDP_COMPONENT_DP_INTF1,
232 };
233
234 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
235 .main_path = mt2701_mtk_ddp_main,
236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
237 .ext_path = mt2701_mtk_ddp_ext,
238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
239 .shadow_register = true,
240 .mmsys_dev_num = 1,
241 };
242
243 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
244 .main_path = mt7623_mtk_ddp_main,
245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
246 .ext_path = mt7623_mtk_ddp_ext,
247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
248 .shadow_register = true,
249 .mmsys_dev_num = 1,
250 };
251
252 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
253 .main_path = mt2712_mtk_ddp_main,
254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
255 .ext_path = mt2712_mtk_ddp_ext,
256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
257 .third_path = mt2712_mtk_ddp_third,
258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
259 .mmsys_dev_num = 1,
260 };
261
262 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
263 .main_path = mt8167_mtk_ddp_main,
264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
265 .mmsys_dev_num = 1,
266 };
267
268 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
269 .main_path = mt8173_mtk_ddp_main,
270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
271 .ext_path = mt8173_mtk_ddp_ext,
272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
273 .mmsys_dev_num = 1,
274 };
275
276 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
277 .main_path = mt8183_mtk_ddp_main,
278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
279 .ext_path = mt8183_mtk_ddp_ext,
280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
281 .mmsys_dev_num = 1,
282 };
283
284 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
285 .main_path = mt8186_mtk_ddp_main,
286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
287 .ext_path = mt8186_mtk_ddp_ext,
288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
289 .mmsys_dev_num = 1,
290 };
291
292 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
293 .main_path = mt8188_mtk_ddp_main,
294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
295 .conn_routes = mt8188_mtk_ddp_main_routes,
296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
297 .mmsys_dev_num = 2,
298 .max_width = 8191,
299 .min_width = 1,
300 .min_height = 1,
301 };
302
303 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
304 .main_path = mt8192_mtk_ddp_main,
305 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
306 .ext_path = mt8192_mtk_ddp_ext,
307 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
308 .mmsys_dev_num = 1,
309 };
310
311 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
312 .main_path = mt8195_mtk_ddp_main,
313 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
314 .mmsys_dev_num = 2,
315 .max_width = 8191,
316 .min_width = 1,
317 .min_height = 1,
318 };
319
320 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
321 .ext_path = mt8195_mtk_ddp_ext,
322 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
323 .mmsys_id = 1,
324 .mmsys_dev_num = 2,
325 .max_width = 8191,
326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
327 .min_height = 1,
328 };
329
330 static const struct of_device_id mtk_drm_of_ids[] = {
331 { .compatible = "mediatek,mt2701-mmsys",
332 .data = &mt2701_mmsys_driver_data},
333 { .compatible = "mediatek,mt7623-mmsys",
334 .data = &mt7623_mmsys_driver_data},
335 { .compatible = "mediatek,mt2712-mmsys",
336 .data = &mt2712_mmsys_driver_data},
337 { .compatible = "mediatek,mt8167-mmsys",
338 .data = &mt8167_mmsys_driver_data},
339 { .compatible = "mediatek,mt8173-mmsys",
340 .data = &mt8173_mmsys_driver_data},
341 { .compatible = "mediatek,mt8183-mmsys",
342 .data = &mt8183_mmsys_driver_data},
343 { .compatible = "mediatek,mt8186-mmsys",
344 .data = &mt8186_mmsys_driver_data},
345 { .compatible = "mediatek,mt8188-vdosys0",
346 .data = &mt8188_vdosys0_driver_data},
347 { .compatible = "mediatek,mt8188-vdosys1",
348 .data = &mt8195_vdosys1_driver_data},
349 { .compatible = "mediatek,mt8192-mmsys",
350 .data = &mt8192_mmsys_driver_data},
351 { .compatible = "mediatek,mt8195-mmsys",
352 .data = &mt8195_vdosys0_driver_data},
353 { .compatible = "mediatek,mt8195-vdosys0",
354 .data = &mt8195_vdosys0_driver_data},
355 { .compatible = "mediatek,mt8195-vdosys1",
356 .data = &mt8195_vdosys1_driver_data},
357 { }
358 };
359 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
360
mtk_drm_match(struct device * dev,const void * data)361 static int mtk_drm_match(struct device *dev, const void *data)
362 {
363 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
364 return true;
365 return false;
366 }
367
mtk_drm_get_all_drm_priv(struct device * dev)368 static bool mtk_drm_get_all_drm_priv(struct device *dev)
369 {
370 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
371 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
372 struct mtk_drm_private *temp_drm_priv;
373 struct device_node *phandle = dev->parent->of_node;
374 const struct of_device_id *of_id;
375 struct device_node *node;
376 struct device *drm_dev;
377 unsigned int cnt = 0;
378 int i, j;
379
380 for_each_child_of_node(phandle->parent, node) {
381 struct platform_device *pdev;
382
383 of_id = of_match_node(mtk_drm_of_ids, node);
384 if (!of_id)
385 continue;
386
387 pdev = of_find_device_by_node(node);
388 if (!pdev)
389 continue;
390
391 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
392 if (!drm_dev)
393 continue;
394
395 temp_drm_priv = dev_get_drvdata(drm_dev);
396 if (!temp_drm_priv)
397 continue;
398
399 if (temp_drm_priv->data->main_len)
400 all_drm_priv[CRTC_MAIN] = temp_drm_priv;
401 else if (temp_drm_priv->data->ext_len)
402 all_drm_priv[CRTC_EXT] = temp_drm_priv;
403 else if (temp_drm_priv->data->third_len)
404 all_drm_priv[CRTC_THIRD] = temp_drm_priv;
405
406 if (temp_drm_priv->mtk_drm_bound)
407 cnt++;
408
409 if (cnt == MAX_CRTC) {
410 of_node_put(node);
411 break;
412 }
413 }
414
415 if (drm_priv->data->mmsys_dev_num == cnt) {
416 for (i = 0; i < cnt; i++)
417 for (j = 0; j < cnt; j++)
418 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
419
420 return true;
421 }
422
423 return false;
424 }
425
mtk_drm_find_mmsys_comp(struct mtk_drm_private * private,int comp_id)426 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
427 {
428 const struct mtk_mmsys_driver_data *drv_data = private->data;
429 int i;
430
431 if (drv_data->main_path)
432 for (i = 0; i < drv_data->main_len; i++)
433 if (drv_data->main_path[i] == comp_id)
434 return true;
435
436 if (drv_data->ext_path)
437 for (i = 0; i < drv_data->ext_len; i++)
438 if (drv_data->ext_path[i] == comp_id)
439 return true;
440
441 if (drv_data->third_path)
442 for (i = 0; i < drv_data->third_len; i++)
443 if (drv_data->third_path[i] == comp_id)
444 return true;
445
446 if (drv_data->num_conn_routes)
447 for (i = 0; i < drv_data->num_conn_routes; i++)
448 if (drv_data->conn_routes[i].route_ddp == comp_id)
449 return true;
450
451 return false;
452 }
453
mtk_drm_kms_init(struct drm_device * drm)454 static int mtk_drm_kms_init(struct drm_device *drm)
455 {
456 struct mtk_drm_private *private = drm->dev_private;
457 struct mtk_drm_private *priv_n;
458 struct device *dma_dev = NULL;
459 struct drm_crtc *crtc;
460 int ret, i, j;
461
462 if (drm_firmware_drivers_only())
463 return -ENODEV;
464
465 ret = drmm_mode_config_init(drm);
466 if (ret)
467 goto put_mutex_dev;
468
469 drm->mode_config.min_width = 64;
470 drm->mode_config.min_height = 64;
471
472 /*
473 * set max width and height as default value(4096x4096).
474 * this value would be used to check framebuffer size limitation
475 * at drm_mode_addfb().
476 */
477 drm->mode_config.max_width = 4096;
478 drm->mode_config.max_height = 4096;
479 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
480 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
481
482 for (i = 0; i < private->data->mmsys_dev_num; i++) {
483 drm->dev_private = private->all_drm_private[i];
484 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
485 if (ret)
486 goto put_mutex_dev;
487 }
488
489 /*
490 * Ensure internal panels are at the top of the connector list before
491 * crtc creation.
492 */
493 drm_helper_move_panel_connectors_to_head(drm);
494
495 /*
496 * 1. We currently support two fixed data streams, each optional,
497 * and each statically assigned to a crtc:
498 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
499 * 2. For multi mmsys architecture, crtc path data are located in
500 * different drm private data structures. Loop through crtc index to
501 * create crtc from the main path and then ext_path and finally the
502 * third path.
503 */
504 for (i = 0; i < MAX_CRTC; i++) {
505 for (j = 0; j < private->data->mmsys_dev_num; j++) {
506 priv_n = private->all_drm_private[j];
507
508 if (priv_n->data->max_width)
509 drm->mode_config.max_width = priv_n->data->max_width;
510
511 if (priv_n->data->min_width)
512 drm->mode_config.min_width = priv_n->data->min_width;
513
514 if (priv_n->data->min_height)
515 drm->mode_config.min_height = priv_n->data->min_height;
516
517 if (i == CRTC_MAIN && priv_n->data->main_len) {
518 ret = mtk_crtc_create(drm, priv_n->data->main_path,
519 priv_n->data->main_len, j,
520 priv_n->data->conn_routes,
521 priv_n->data->num_conn_routes);
522 if (ret)
523 goto err_component_unbind;
524
525 continue;
526 } else if (i == CRTC_EXT && priv_n->data->ext_len) {
527 ret = mtk_crtc_create(drm, priv_n->data->ext_path,
528 priv_n->data->ext_len, j, NULL, 0);
529 if (ret)
530 goto err_component_unbind;
531
532 continue;
533 } else if (i == CRTC_THIRD && priv_n->data->third_len) {
534 ret = mtk_crtc_create(drm, priv_n->data->third_path,
535 priv_n->data->third_len, j, NULL, 0);
536 if (ret)
537 goto err_component_unbind;
538
539 continue;
540 }
541 }
542 }
543
544 /* IGT will check if the cursor size is configured */
545 drm->mode_config.cursor_width = 512;
546 drm->mode_config.cursor_height = 512;
547
548 /* Use OVL device for all DMA memory allocations */
549 crtc = drm_crtc_from_index(drm, 0);
550 if (crtc)
551 dma_dev = mtk_crtc_dma_dev_get(crtc);
552 if (!dma_dev) {
553 ret = -ENODEV;
554 dev_err(drm->dev, "Need at least one OVL device\n");
555 goto err_component_unbind;
556 }
557
558 for (i = 0; i < private->data->mmsys_dev_num; i++)
559 private->all_drm_private[i]->dma_dev = dma_dev;
560
561 /*
562 * Configure the DMA segment size to make sure we get contiguous IOVA
563 * when importing PRIME buffers.
564 */
565 dma_set_max_seg_size(dma_dev, UINT_MAX);
566
567 ret = drm_vblank_init(drm, MAX_CRTC);
568 if (ret < 0)
569 goto err_component_unbind;
570
571 drm_kms_helper_poll_init(drm);
572 drm_mode_config_reset(drm);
573
574 return 0;
575
576 err_component_unbind:
577 for (i = 0; i < private->data->mmsys_dev_num; i++)
578 component_unbind_all(private->all_drm_private[i]->dev, drm);
579 put_mutex_dev:
580 for (i = 0; i < private->data->mmsys_dev_num; i++)
581 put_device(private->all_drm_private[i]->mutex_dev);
582
583 return ret;
584 }
585
mtk_drm_kms_deinit(struct drm_device * drm)586 static void mtk_drm_kms_deinit(struct drm_device *drm)
587 {
588 drm_kms_helper_poll_fini(drm);
589 drm_atomic_helper_shutdown(drm);
590
591 component_unbind_all(drm->dev, drm);
592 }
593
594 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
595
596 /*
597 * We need to override this because the device used to import the memory is
598 * not dev->dev, as drm_gem_prime_import() expects.
599 */
mtk_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)600 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev,
601 struct dma_buf *dma_buf)
602 {
603 struct mtk_drm_private *private = dev->dev_private;
604
605 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
606 }
607
608 static const struct drm_driver mtk_drm_driver = {
609 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
610
611 .dumb_create = mtk_gem_dumb_create,
612 DRM_FBDEV_DMA_DRIVER_OPS,
613
614 .gem_prime_import = mtk_gem_prime_import,
615 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
616 .fops = &mtk_drm_fops,
617
618 .name = DRIVER_NAME,
619 .desc = DRIVER_DESC,
620 .major = DRIVER_MAJOR,
621 .minor = DRIVER_MINOR,
622 };
623
compare_dev(struct device * dev,void * data)624 static int compare_dev(struct device *dev, void *data)
625 {
626 return dev == (struct device *)data;
627 }
628
mtk_drm_bind(struct device * dev)629 static int mtk_drm_bind(struct device *dev)
630 {
631 struct mtk_drm_private *private = dev_get_drvdata(dev);
632 struct platform_device *pdev;
633 struct drm_device *drm;
634 int ret, i;
635
636 pdev = of_find_device_by_node(private->mutex_node);
637 if (!pdev) {
638 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
639 private->mutex_node);
640 of_node_put(private->mutex_node);
641 return -EPROBE_DEFER;
642 }
643
644 private->mutex_dev = &pdev->dev;
645 private->mtk_drm_bound = true;
646 private->dev = dev;
647
648 if (!mtk_drm_get_all_drm_priv(dev))
649 return 0;
650
651 drm = drm_dev_alloc(&mtk_drm_driver, dev);
652 if (IS_ERR(drm))
653 return PTR_ERR(drm);
654
655 private->drm_master = true;
656 drm->dev_private = private;
657 for (i = 0; i < private->data->mmsys_dev_num; i++)
658 private->all_drm_private[i]->drm = drm;
659
660 ret = mtk_drm_kms_init(drm);
661 if (ret < 0)
662 goto err_free;
663
664 ret = drm_dev_register(drm, 0);
665 if (ret < 0)
666 goto err_deinit;
667
668 drm_client_setup(drm, NULL);
669
670 return 0;
671
672 err_deinit:
673 mtk_drm_kms_deinit(drm);
674 err_free:
675 private->drm = NULL;
676 drm_dev_put(drm);
677 for (i = 0; i < private->data->mmsys_dev_num; i++)
678 private->all_drm_private[i]->drm = NULL;
679 return ret;
680 }
681
mtk_drm_unbind(struct device * dev)682 static void mtk_drm_unbind(struct device *dev)
683 {
684 struct mtk_drm_private *private = dev_get_drvdata(dev);
685
686 /* for multi mmsys dev, unregister drm dev in mmsys master */
687 if (private->drm_master) {
688 drm_dev_unregister(private->drm);
689 mtk_drm_kms_deinit(private->drm);
690 drm_dev_put(private->drm);
691 }
692 private->mtk_drm_bound = false;
693 private->drm_master = false;
694 private->drm = NULL;
695 }
696
697 static const struct component_master_ops mtk_drm_ops = {
698 .bind = mtk_drm_bind,
699 .unbind = mtk_drm_unbind,
700 };
701
702 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
703 { .compatible = "mediatek,mt8167-disp-aal",
704 .data = (void *)MTK_DISP_AAL},
705 { .compatible = "mediatek,mt8173-disp-aal",
706 .data = (void *)MTK_DISP_AAL},
707 { .compatible = "mediatek,mt8183-disp-aal",
708 .data = (void *)MTK_DISP_AAL},
709 { .compatible = "mediatek,mt8192-disp-aal",
710 .data = (void *)MTK_DISP_AAL},
711 { .compatible = "mediatek,mt8167-disp-ccorr",
712 .data = (void *)MTK_DISP_CCORR },
713 { .compatible = "mediatek,mt8183-disp-ccorr",
714 .data = (void *)MTK_DISP_CCORR },
715 { .compatible = "mediatek,mt8192-disp-ccorr",
716 .data = (void *)MTK_DISP_CCORR },
717 { .compatible = "mediatek,mt2701-disp-color",
718 .data = (void *)MTK_DISP_COLOR },
719 { .compatible = "mediatek,mt8167-disp-color",
720 .data = (void *)MTK_DISP_COLOR },
721 { .compatible = "mediatek,mt8173-disp-color",
722 .data = (void *)MTK_DISP_COLOR },
723 { .compatible = "mediatek,mt8167-disp-dither",
724 .data = (void *)MTK_DISP_DITHER },
725 { .compatible = "mediatek,mt8183-disp-dither",
726 .data = (void *)MTK_DISP_DITHER },
727 { .compatible = "mediatek,mt8195-disp-dsc",
728 .data = (void *)MTK_DISP_DSC },
729 { .compatible = "mediatek,mt8167-disp-gamma",
730 .data = (void *)MTK_DISP_GAMMA, },
731 { .compatible = "mediatek,mt8173-disp-gamma",
732 .data = (void *)MTK_DISP_GAMMA, },
733 { .compatible = "mediatek,mt8183-disp-gamma",
734 .data = (void *)MTK_DISP_GAMMA, },
735 { .compatible = "mediatek,mt8195-disp-gamma",
736 .data = (void *)MTK_DISP_GAMMA, },
737 { .compatible = "mediatek,mt8195-disp-merge",
738 .data = (void *)MTK_DISP_MERGE },
739 { .compatible = "mediatek,mt2701-disp-mutex",
740 .data = (void *)MTK_DISP_MUTEX },
741 { .compatible = "mediatek,mt2712-disp-mutex",
742 .data = (void *)MTK_DISP_MUTEX },
743 { .compatible = "mediatek,mt8167-disp-mutex",
744 .data = (void *)MTK_DISP_MUTEX },
745 { .compatible = "mediatek,mt8173-disp-mutex",
746 .data = (void *)MTK_DISP_MUTEX },
747 { .compatible = "mediatek,mt8183-disp-mutex",
748 .data = (void *)MTK_DISP_MUTEX },
749 { .compatible = "mediatek,mt8186-disp-mutex",
750 .data = (void *)MTK_DISP_MUTEX },
751 { .compatible = "mediatek,mt8188-disp-mutex",
752 .data = (void *)MTK_DISP_MUTEX },
753 { .compatible = "mediatek,mt8192-disp-mutex",
754 .data = (void *)MTK_DISP_MUTEX },
755 { .compatible = "mediatek,mt8195-disp-mutex",
756 .data = (void *)MTK_DISP_MUTEX },
757 { .compatible = "mediatek,mt8173-disp-od",
758 .data = (void *)MTK_DISP_OD },
759 { .compatible = "mediatek,mt2701-disp-ovl",
760 .data = (void *)MTK_DISP_OVL },
761 { .compatible = "mediatek,mt8167-disp-ovl",
762 .data = (void *)MTK_DISP_OVL },
763 { .compatible = "mediatek,mt8173-disp-ovl",
764 .data = (void *)MTK_DISP_OVL },
765 { .compatible = "mediatek,mt8183-disp-ovl",
766 .data = (void *)MTK_DISP_OVL },
767 { .compatible = "mediatek,mt8192-disp-ovl",
768 .data = (void *)MTK_DISP_OVL },
769 { .compatible = "mediatek,mt8195-disp-ovl",
770 .data = (void *)MTK_DISP_OVL },
771 { .compatible = "mediatek,mt8183-disp-ovl-2l",
772 .data = (void *)MTK_DISP_OVL_2L },
773 { .compatible = "mediatek,mt8192-disp-ovl-2l",
774 .data = (void *)MTK_DISP_OVL_2L },
775 { .compatible = "mediatek,mt8192-disp-postmask",
776 .data = (void *)MTK_DISP_POSTMASK },
777 { .compatible = "mediatek,mt2701-disp-pwm",
778 .data = (void *)MTK_DISP_BLS },
779 { .compatible = "mediatek,mt8167-disp-pwm",
780 .data = (void *)MTK_DISP_PWM },
781 { .compatible = "mediatek,mt8173-disp-pwm",
782 .data = (void *)MTK_DISP_PWM },
783 { .compatible = "mediatek,mt2701-disp-rdma",
784 .data = (void *)MTK_DISP_RDMA },
785 { .compatible = "mediatek,mt8167-disp-rdma",
786 .data = (void *)MTK_DISP_RDMA },
787 { .compatible = "mediatek,mt8173-disp-rdma",
788 .data = (void *)MTK_DISP_RDMA },
789 { .compatible = "mediatek,mt8183-disp-rdma",
790 .data = (void *)MTK_DISP_RDMA },
791 { .compatible = "mediatek,mt8195-disp-rdma",
792 .data = (void *)MTK_DISP_RDMA },
793 { .compatible = "mediatek,mt8173-disp-ufoe",
794 .data = (void *)MTK_DISP_UFOE },
795 { .compatible = "mediatek,mt8173-disp-wdma",
796 .data = (void *)MTK_DISP_WDMA },
797 { .compatible = "mediatek,mt2701-dpi",
798 .data = (void *)MTK_DPI },
799 { .compatible = "mediatek,mt8167-dsi",
800 .data = (void *)MTK_DSI },
801 { .compatible = "mediatek,mt8173-dpi",
802 .data = (void *)MTK_DPI },
803 { .compatible = "mediatek,mt8183-dpi",
804 .data = (void *)MTK_DPI },
805 { .compatible = "mediatek,mt8186-dpi",
806 .data = (void *)MTK_DPI },
807 { .compatible = "mediatek,mt8188-dp-intf",
808 .data = (void *)MTK_DP_INTF },
809 { .compatible = "mediatek,mt8192-dpi",
810 .data = (void *)MTK_DPI },
811 { .compatible = "mediatek,mt8195-dp-intf",
812 .data = (void *)MTK_DP_INTF },
813 { .compatible = "mediatek,mt2701-dsi",
814 .data = (void *)MTK_DSI },
815 { .compatible = "mediatek,mt8173-dsi",
816 .data = (void *)MTK_DSI },
817 { .compatible = "mediatek,mt8183-dsi",
818 .data = (void *)MTK_DSI },
819 { .compatible = "mediatek,mt8186-dsi",
820 .data = (void *)MTK_DSI },
821 { .compatible = "mediatek,mt8188-dsi",
822 .data = (void *)MTK_DSI },
823 { }
824 };
825
mtk_drm_of_get_ddp_comp_type(struct device_node * node,enum mtk_ddp_comp_type * ctype)826 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype)
827 {
828 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
829
830 if (!of_id)
831 return -EINVAL;
832
833 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data);
834
835 return 0;
836 }
837
mtk_drm_of_get_ddp_ep_cid(struct device_node * node,int output_port,enum mtk_crtc_path crtc_path,struct device_node ** next,unsigned int * cid)838 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
839 int output_port, enum mtk_crtc_path crtc_path,
840 struct device_node **next, unsigned int *cid)
841 {
842 struct device_node *ep_dev_node, *ep_out;
843 enum mtk_ddp_comp_type comp_type;
844 int ret;
845
846 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path);
847 if (!ep_out)
848 return -ENOENT;
849
850 ep_dev_node = of_graph_get_remote_port_parent(ep_out);
851 of_node_put(ep_out);
852 if (!ep_dev_node)
853 return -EINVAL;
854
855 /*
856 * Pass the next node pointer regardless of failures in the later code
857 * so that if this function is called in a loop it will walk through all
858 * of the subsequent endpoints anyway.
859 */
860 *next = ep_dev_node;
861
862 if (!of_device_is_available(ep_dev_node))
863 return -ENODEV;
864
865 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type);
866 if (ret) {
867 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) {
868 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR;
869 return 0;
870 }
871 return ret;
872 }
873
874 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type);
875 if (ret < 0)
876 return ret;
877
878 /* All ok! Pass the Component ID to the caller. */
879 *cid = (unsigned int)ret;
880
881 return 0;
882 }
883
884 /**
885 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path
886 * @dev: The mediatek-drm device
887 * @cpath: CRTC Path relative to a VDO or MMSYS
888 * @out_path: Pointer to an array that will contain the new pipeline
889 * @out_path_len: Number of entries in the pipeline array
890 *
891 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending
892 * on the board-specific desired display configuration; this function walks
893 * through all of the output endpoints starting from a VDO or MMSYS hardware
894 * instance and builds the right pipeline as specified in device trees.
895 *
896 * Return:
897 * * %0 - Display HW Pipeline successfully built and validated
898 * * %-ENOENT - Display pipeline was not specified in device tree
899 * * %-EINVAL - Display pipeline built but validation failed
900 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller
901 */
mtk_drm_of_ddp_path_build_one(struct device * dev,enum mtk_crtc_path cpath,const unsigned int ** out_path,unsigned int * out_path_len)902 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath,
903 const unsigned int **out_path,
904 unsigned int *out_path_len)
905 {
906 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node;
907 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 };
908 unsigned int *final_ddp_path;
909 unsigned short int idx = 0;
910 bool ovl_adaptor_comp_added = false;
911 int ret;
912
913 /* Get the first entry for the temp_path array */
914 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]);
915 if (ret) {
916 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
917 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next);
918 ovl_adaptor_comp_added = true;
919 } else {
920 if (next)
921 dev_err(dev, "Invalid component %pOF\n", next);
922 else
923 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath);
924
925 return ret;
926 }
927 }
928 idx++;
929
930 /*
931 * Walk through port outputs until we reach the last valid mediatek-drm component.
932 * To be valid, this must end with an "invalid" component that is a display node.
933 */
934 do {
935 prev = next;
936 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]);
937 of_node_put(prev);
938 if (ret) {
939 of_node_put(next);
940 break;
941 }
942
943 /*
944 * If this is an OVL adaptor exclusive component and one of those
945 * was already added, don't add another instance of the generic
946 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether
947 * to probe that component master driver of which only one instance
948 * is needed and possible.
949 */
950 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
951 if (!ovl_adaptor_comp_added)
952 ovl_adaptor_comp_added = true;
953 else
954 idx--;
955 }
956 } while (++idx < DDP_COMPONENT_DRM_ID_MAX);
957
958 /*
959 * The device component might not be enabled: in that case, don't
960 * check the last entry and just report that the device is missing.
961 */
962 if (ret == -ENODEV)
963 return ret;
964
965 /* If the last entry is not a final display output, the configuration is wrong */
966 switch (temp_path[idx - 1]) {
967 case DDP_COMPONENT_DP_INTF0:
968 case DDP_COMPONENT_DP_INTF1:
969 case DDP_COMPONENT_DPI0:
970 case DDP_COMPONENT_DPI1:
971 case DDP_COMPONENT_DSI0:
972 case DDP_COMPONENT_DSI1:
973 case DDP_COMPONENT_DSI2:
974 case DDP_COMPONENT_DSI3:
975 break;
976 default:
977 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n",
978 temp_path[idx - 1], ret);
979 return -EINVAL;
980 }
981
982 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL);
983 if (!final_ddp_path)
984 return -ENOMEM;
985
986 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx);
987
988 /* Pipeline built! */
989 *out_path = final_ddp_path;
990 *out_path_len = idx;
991
992 return 0;
993 }
994
mtk_drm_of_ddp_path_build(struct device * dev,struct device_node * node,struct mtk_mmsys_driver_data * data)995 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node,
996 struct mtk_mmsys_driver_data *data)
997 {
998 struct device_node *ep_node;
999 struct of_endpoint of_ep;
1000 bool output_present[MAX_CRTC] = { false };
1001 int ret;
1002
1003 for_each_endpoint_of_node(node, ep_node) {
1004 ret = of_graph_parse_endpoint(ep_node, &of_ep);
1005 if (ret) {
1006 dev_err_probe(dev, ret, "Cannot parse endpoint\n");
1007 break;
1008 }
1009
1010 if (of_ep.id >= MAX_CRTC) {
1011 ret = dev_err_probe(dev, -EINVAL,
1012 "Invalid endpoint%u number\n", of_ep.port);
1013 break;
1014 }
1015
1016 output_present[of_ep.id] = true;
1017 }
1018
1019 if (ret) {
1020 of_node_put(ep_node);
1021 return ret;
1022 }
1023
1024 if (output_present[CRTC_MAIN]) {
1025 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN,
1026 &data->main_path, &data->main_len);
1027 if (ret && ret != -ENODEV)
1028 return ret;
1029 }
1030
1031 if (output_present[CRTC_EXT]) {
1032 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT,
1033 &data->ext_path, &data->ext_len);
1034 if (ret && ret != -ENODEV)
1035 return ret;
1036 }
1037
1038 if (output_present[CRTC_THIRD]) {
1039 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD,
1040 &data->third_path, &data->third_len);
1041 if (ret && ret != -ENODEV)
1042 return ret;
1043 }
1044
1045 return 0;
1046 }
1047
mtk_drm_probe(struct platform_device * pdev)1048 static int mtk_drm_probe(struct platform_device *pdev)
1049 {
1050 struct device *dev = &pdev->dev;
1051 struct device_node *phandle = dev->parent->of_node;
1052 const struct of_device_id *of_id;
1053 struct mtk_drm_private *private;
1054 struct mtk_mmsys_driver_data *mtk_drm_data;
1055 struct device_node *node;
1056 struct component_match *match = NULL;
1057 struct platform_device *ovl_adaptor;
1058 int ret;
1059 int i;
1060
1061 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
1062 if (!private)
1063 return -ENOMEM;
1064
1065 private->mmsys_dev = dev->parent;
1066 if (!private->mmsys_dev) {
1067 dev_err(dev, "Failed to get MMSYS device\n");
1068 return -ENODEV;
1069 }
1070
1071 of_id = of_match_node(mtk_drm_of_ids, phandle);
1072 if (!of_id)
1073 return -ENODEV;
1074
1075 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data;
1076 if (!mtk_drm_data)
1077 return -EINVAL;
1078
1079 /* Try to build the display pipeline from devicetree graphs */
1080 if (of_graph_is_present(phandle)) {
1081 dev_dbg(dev, "Building display pipeline for MMSYS %u\n",
1082 mtk_drm_data->mmsys_id);
1083 private->data = devm_kmemdup(dev, mtk_drm_data,
1084 sizeof(*mtk_drm_data), GFP_KERNEL);
1085 if (!private->data)
1086 return -ENOMEM;
1087
1088 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data);
1089 if (ret)
1090 return ret;
1091 } else {
1092 /* No devicetree graphs support: go with hardcoded paths if present */
1093 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id);
1094 private->data = mtk_drm_data;
1095 }
1096
1097 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
1098 sizeof(*private->all_drm_private),
1099 GFP_KERNEL);
1100 if (!private->all_drm_private)
1101 return -ENOMEM;
1102
1103 /* Bringup ovl_adaptor */
1104 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
1105 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
1106 PLATFORM_DEVID_AUTO,
1107 (void *)private->mmsys_dev,
1108 sizeof(*private->mmsys_dev));
1109 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
1110 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
1111 DDP_COMPONENT_DRM_OVL_ADAPTOR);
1112 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
1113 }
1114
1115 /* Iterate over sibling DISP function blocks */
1116 for_each_child_of_node(phandle->parent, node) {
1117 enum mtk_ddp_comp_type comp_type;
1118 int comp_id;
1119
1120 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type);
1121 if (ret)
1122 continue;
1123
1124 if (!of_device_is_available(node)) {
1125 dev_dbg(dev, "Skipping disabled component %pOF\n",
1126 node);
1127 continue;
1128 }
1129
1130 if (comp_type == MTK_DISP_MUTEX) {
1131 int id;
1132
1133 id = of_alias_get_id(node, "mutex");
1134 if (id < 0 || id == private->data->mmsys_id) {
1135 private->mutex_node = of_node_get(node);
1136 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
1137 }
1138 continue;
1139 }
1140
1141 comp_id = mtk_ddp_comp_get_id(node, comp_type);
1142 if (comp_id < 0) {
1143 dev_warn(dev, "Skipping unknown component %pOF\n",
1144 node);
1145 continue;
1146 }
1147
1148 if (!mtk_drm_find_mmsys_comp(private, comp_id))
1149 continue;
1150
1151 private->comp_node[comp_id] = of_node_get(node);
1152
1153 /*
1154 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
1155 * blocks have separate component platform drivers and initialize their own
1156 * DDP component structure. The others are initialized here.
1157 */
1158 if (comp_type == MTK_DISP_AAL ||
1159 comp_type == MTK_DISP_CCORR ||
1160 comp_type == MTK_DISP_COLOR ||
1161 comp_type == MTK_DISP_GAMMA ||
1162 comp_type == MTK_DISP_MERGE ||
1163 comp_type == MTK_DISP_OVL ||
1164 comp_type == MTK_DISP_OVL_2L ||
1165 comp_type == MTK_DISP_OVL_ADAPTOR ||
1166 comp_type == MTK_DISP_RDMA ||
1167 comp_type == MTK_DP_INTF ||
1168 comp_type == MTK_DPI ||
1169 comp_type == MTK_DSI) {
1170 dev_info(dev, "Adding component match for %pOF\n",
1171 node);
1172 drm_of_component_match_add(dev, &match, component_compare_of,
1173 node);
1174 }
1175
1176 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
1177 if (ret) {
1178 of_node_put(node);
1179 goto err_node;
1180 }
1181 }
1182
1183 if (!private->mutex_node) {
1184 dev_err(dev, "Failed to find disp-mutex node\n");
1185 ret = -ENODEV;
1186 goto err_node;
1187 }
1188
1189 pm_runtime_enable(dev);
1190
1191 platform_set_drvdata(pdev, private);
1192
1193 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
1194 if (ret)
1195 goto err_pm;
1196
1197 return 0;
1198
1199 err_pm:
1200 pm_runtime_disable(dev);
1201 err_node:
1202 of_node_put(private->mutex_node);
1203 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1204 of_node_put(private->comp_node[i]);
1205 return ret;
1206 }
1207
mtk_drm_remove(struct platform_device * pdev)1208 static void mtk_drm_remove(struct platform_device *pdev)
1209 {
1210 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1211 int i;
1212
1213 component_master_del(&pdev->dev, &mtk_drm_ops);
1214 pm_runtime_disable(&pdev->dev);
1215 of_node_put(private->mutex_node);
1216 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1217 of_node_put(private->comp_node[i]);
1218 }
1219
mtk_drm_shutdown(struct platform_device * pdev)1220 static void mtk_drm_shutdown(struct platform_device *pdev)
1221 {
1222 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1223
1224 drm_atomic_helper_shutdown(private->drm);
1225 }
1226
mtk_drm_sys_prepare(struct device * dev)1227 static int mtk_drm_sys_prepare(struct device *dev)
1228 {
1229 struct mtk_drm_private *private = dev_get_drvdata(dev);
1230 struct drm_device *drm = private->drm;
1231
1232 if (private->drm_master)
1233 return drm_mode_config_helper_suspend(drm);
1234 else
1235 return 0;
1236 }
1237
mtk_drm_sys_complete(struct device * dev)1238 static void mtk_drm_sys_complete(struct device *dev)
1239 {
1240 struct mtk_drm_private *private = dev_get_drvdata(dev);
1241 struct drm_device *drm = private->drm;
1242 int ret = 0;
1243
1244 if (private->drm_master)
1245 ret = drm_mode_config_helper_resume(drm);
1246 if (ret)
1247 dev_err(dev, "Failed to resume\n");
1248 }
1249
1250 static const struct dev_pm_ops mtk_drm_pm_ops = {
1251 .prepare = mtk_drm_sys_prepare,
1252 .complete = mtk_drm_sys_complete,
1253 };
1254
1255 static struct platform_driver mtk_drm_platform_driver = {
1256 .probe = mtk_drm_probe,
1257 .remove = mtk_drm_remove,
1258 .shutdown = mtk_drm_shutdown,
1259 .driver = {
1260 .name = "mediatek-drm",
1261 .pm = &mtk_drm_pm_ops,
1262 },
1263 };
1264
1265 static struct platform_driver * const mtk_drm_drivers[] = {
1266 &mtk_disp_aal_driver,
1267 &mtk_disp_ccorr_driver,
1268 &mtk_disp_color_driver,
1269 &mtk_disp_gamma_driver,
1270 &mtk_disp_merge_driver,
1271 &mtk_disp_ovl_adaptor_driver,
1272 &mtk_disp_ovl_driver,
1273 &mtk_disp_rdma_driver,
1274 &mtk_dpi_driver,
1275 &mtk_drm_platform_driver,
1276 &mtk_dsi_driver,
1277 &mtk_ethdr_driver,
1278 &mtk_mdp_rdma_driver,
1279 &mtk_padding_driver,
1280 };
1281
mtk_drm_init(void)1282 static int __init mtk_drm_init(void)
1283 {
1284 return platform_register_drivers(mtk_drm_drivers,
1285 ARRAY_SIZE(mtk_drm_drivers));
1286 }
1287
mtk_drm_exit(void)1288 static void __exit mtk_drm_exit(void)
1289 {
1290 platform_unregister_drivers(mtk_drm_drivers,
1291 ARRAY_SIZE(mtk_drm_drivers));
1292 }
1293
1294 module_init(mtk_drm_init);
1295 module_exit(mtk_drm_exit);
1296
1297 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1298 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1299 MODULE_LICENSE("GPL v2");
1300