1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #ifndef WITHOUT_CAPSICUM
31 #include <sys/capsicum.h>
32 #endif
33 #include <sys/types.h>
34 #include <sys/mman.h>
35 #include <sys/pciio.h>
36 #include <sys/ioctl.h>
37 #include <sys/stat.h>
38
39 #include <dev/io/iodev.h>
40 #include <dev/pci/pcireg.h>
41
42 #include <vm/vm.h>
43
44 #include <machine/iodev.h>
45 #include <machine/vm.h>
46
47 #ifndef WITHOUT_CAPSICUM
48 #include <capsicum_helpers.h>
49 #endif
50 #include <ctype.h>
51 #include <stdio.h>
52 #include <stdlib.h>
53 #include <string.h>
54 #include <err.h>
55 #include <errno.h>
56 #include <fcntl.h>
57 #include <sysexits.h>
58 #include <unistd.h>
59
60 #include <machine/vmm.h>
61
62 #include "debug.h"
63 #include "mem.h"
64 #include "pci_passthru.h"
65
66 #ifndef _PATH_DEVPCI
67 #define _PATH_DEVPCI "/dev/pci"
68 #endif
69
70 #define LEGACY_SUPPORT 1
71
72 #define MSIX_TABLE_COUNT(ctrl) (((ctrl) & PCIM_MSIXCTRL_TABLE_SIZE) + 1)
73 #define MSIX_CAPLEN 12
74
75 #define PASSTHRU_MMIO_MAX 2
76
77 static int pcifd = -1;
78
79 SET_DECLARE(passthru_dev_set, struct passthru_dev);
80
81 struct passthru_softc {
82 struct pci_devinst *psc_pi;
83 /* ROM is handled like a BAR */
84 struct pcibar psc_bar[PCI_BARMAX_WITH_ROM + 1];
85 struct {
86 int capoff;
87 int msgctrl;
88 int emulated;
89 } psc_msi;
90 struct {
91 int capoff;
92 } psc_msix;
93 struct pcisel psc_sel;
94
95 struct passthru_mmio_mapping psc_mmio_map[PASSTHRU_MMIO_MAX];
96 cfgread_handler psc_pcir_rhandler[PCI_REGMAX + 1];
97 cfgwrite_handler psc_pcir_whandler[PCI_REGMAX + 1];
98 };
99
100 static int
msi_caplen(int msgctrl)101 msi_caplen(int msgctrl)
102 {
103 int len;
104
105 len = 10; /* minimum length of msi capability */
106
107 if (msgctrl & PCIM_MSICTRL_64BIT)
108 len += 4;
109
110 #if 0
111 /*
112 * Ignore the 'mask' and 'pending' bits in the MSI capability.
113 * We'll let the guest manipulate them directly.
114 */
115 if (msgctrl & PCIM_MSICTRL_VECTOR)
116 len += 10;
117 #endif
118
119 return (len);
120 }
121
122 static int
pcifd_open(void)123 pcifd_open(void)
124 {
125 int fd;
126
127 fd = open(_PATH_DEVPCI, O_RDWR, 0);
128 if (fd < 0) {
129 warn("failed to open %s", _PATH_DEVPCI);
130 return (-1);
131 }
132 return (fd);
133 }
134
135 static int
pcifd_init(void)136 pcifd_init(void)
137 {
138 pcifd = pcifd_open();
139 if (pcifd < 0)
140 return (1);
141
142 #ifndef WITHOUT_CAPSICUM
143 cap_rights_t pcifd_rights;
144 cap_rights_init(&pcifd_rights, CAP_IOCTL, CAP_READ, CAP_WRITE);
145 if (caph_rights_limit(pcifd, &pcifd_rights) == -1)
146 errx(EX_OSERR, "Unable to apply rights for sandbox");
147
148 const cap_ioctl_t pcifd_ioctls[] = { PCIOCREAD, PCIOCWRITE, PCIOCGETBAR,
149 PCIOCBARIO, PCIOCBARMMAP, PCIOCGETCONF };
150 if (caph_ioctls_limit(pcifd, pcifd_ioctls, nitems(pcifd_ioctls)) == -1)
151 errx(EX_OSERR, "Unable to apply rights for sandbox");
152 #endif
153
154 return (0);
155 }
156
157 static uint32_t
host_read_config(int fd,const struct pcisel * sel,long reg,int width)158 host_read_config(int fd, const struct pcisel *sel, long reg, int width)
159 {
160 struct pci_io pi;
161
162 bzero(&pi, sizeof(pi));
163 pi.pi_sel = *sel;
164 pi.pi_reg = reg;
165 pi.pi_width = width;
166
167 if (ioctl(fd, PCIOCREAD, &pi) < 0)
168 return (0); /* XXX */
169 else
170 return (pi.pi_data);
171 }
172
173 static uint32_t
passthru_read_config(const struct pcisel * sel,long reg,int width)174 passthru_read_config(const struct pcisel *sel, long reg, int width)
175 {
176 return (host_read_config(pcifd, sel, reg, width));
177 }
178
179 uint32_t
pci_host_read_config(const struct pcisel * sel,long reg,int width)180 pci_host_read_config(const struct pcisel *sel, long reg, int width)
181 {
182 uint32_t ret;
183 int fd;
184
185 fd = pcifd_open();
186 if (fd < 0)
187 return (0);
188 ret = host_read_config(fd, sel, reg, width);
189 (void)close(fd);
190 return (ret);
191 }
192
193 static void
host_write_config(int fd,const struct pcisel * sel,long reg,int width,uint32_t data)194 host_write_config(int fd, const struct pcisel *sel, long reg, int width,
195 uint32_t data)
196 {
197 struct pci_io pi;
198
199 bzero(&pi, sizeof(pi));
200 pi.pi_sel = *sel;
201 pi.pi_reg = reg;
202 pi.pi_width = width;
203 pi.pi_data = data;
204
205 (void)ioctl(fd, PCIOCWRITE, &pi); /* XXX */
206 }
207
208 static void
passthru_write_config(const struct pcisel * sel,long reg,int width,uint32_t data)209 passthru_write_config(const struct pcisel *sel, long reg, int width,
210 uint32_t data)
211 {
212 host_write_config(pcifd, sel, reg, width, data);
213 }
214
215 void
pci_host_write_config(const struct pcisel * sel,long reg,int width,uint32_t data)216 pci_host_write_config(const struct pcisel *sel, long reg, int width,
217 uint32_t data)
218 {
219 int fd;
220
221 fd = pcifd_open();
222 if (fd < 0)
223 return;
224 host_write_config(fd, sel, reg, width, data);
225 (void)close(fd);
226 }
227
228 #ifdef LEGACY_SUPPORT
229 static int
passthru_add_msicap(struct pci_devinst * pi,int msgnum,int nextptr)230 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
231 {
232 int capoff;
233 struct msicap msicap;
234 u_char *capdata;
235
236 pci_populate_msicap(&msicap, msgnum, nextptr);
237
238 /*
239 * XXX
240 * Copy the msi capability structure in the last 16 bytes of the
241 * config space. This is wrong because it could shadow something
242 * useful to the device.
243 */
244 capoff = 256 - roundup(sizeof(msicap), 4);
245 capdata = (u_char *)&msicap;
246 for (size_t i = 0; i < sizeof(msicap); i++)
247 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
248
249 return (capoff);
250 }
251 #endif /* LEGACY_SUPPORT */
252
253 static int
cfginitmsi(struct passthru_softc * sc)254 cfginitmsi(struct passthru_softc *sc)
255 {
256 int i, ptr, capptr, cap, sts, caplen, table_size;
257 uint32_t u32;
258 struct pcisel sel;
259 struct pci_devinst *pi;
260 struct msixcap msixcap;
261 char *msixcap_ptr;
262
263 pi = sc->psc_pi;
264 sel = sc->psc_sel;
265
266 /*
267 * Parse the capabilities and cache the location of the MSI
268 * and MSI-X capabilities.
269 */
270 sts = passthru_read_config(&sel, PCIR_STATUS, 2);
271 if (sts & PCIM_STATUS_CAPPRESENT) {
272 ptr = passthru_read_config(&sel, PCIR_CAP_PTR, 1);
273 while (ptr != 0 && ptr != 0xff) {
274 cap = passthru_read_config(&sel, ptr + PCICAP_ID, 1);
275 if (cap == PCIY_MSI) {
276 /*
277 * Copy the MSI capability into the config
278 * space of the emulated pci device
279 */
280 sc->psc_msi.capoff = ptr;
281 sc->psc_msi.msgctrl =
282 passthru_read_config(&sel, ptr + 2, 2);
283 sc->psc_msi.emulated = 0;
284 caplen = msi_caplen(sc->psc_msi.msgctrl);
285 capptr = ptr;
286 while (caplen > 0) {
287 u32 = passthru_read_config(&sel, capptr,
288 4);
289 pci_set_cfgdata32(pi, capptr, u32);
290 caplen -= 4;
291 capptr += 4;
292 }
293 } else if (cap == PCIY_MSIX) {
294 /*
295 * Copy the MSI-X capability
296 */
297 sc->psc_msix.capoff = ptr;
298 caplen = 12;
299 msixcap_ptr = (char *)&msixcap;
300 capptr = ptr;
301 while (caplen > 0) {
302 u32 = passthru_read_config(&sel, capptr,
303 4);
304 memcpy(msixcap_ptr, &u32, 4);
305 pci_set_cfgdata32(pi, capptr, u32);
306 caplen -= 4;
307 capptr += 4;
308 msixcap_ptr += 4;
309 }
310 }
311 ptr = passthru_read_config(&sel, ptr + PCICAP_NEXTPTR,
312 1);
313 }
314 }
315
316 if (sc->psc_msix.capoff != 0) {
317 pi->pi_msix.pba_bar =
318 msixcap.pba_info & PCIM_MSIX_BIR_MASK;
319 pi->pi_msix.pba_offset =
320 msixcap.pba_info & ~PCIM_MSIX_BIR_MASK;
321 pi->pi_msix.table_bar =
322 msixcap.table_info & PCIM_MSIX_BIR_MASK;
323 pi->pi_msix.table_offset =
324 msixcap.table_info & ~PCIM_MSIX_BIR_MASK;
325 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
326 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
327
328 /* Allocate the emulated MSI-X table array */
329 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
330 pi->pi_msix.table = calloc(1, table_size);
331
332 /* Mask all table entries */
333 for (i = 0; i < pi->pi_msix.table_count; i++) {
334 pi->pi_msix.table[i].vector_control |=
335 PCIM_MSIX_VCTRL_MASK;
336 }
337 }
338
339 #ifdef LEGACY_SUPPORT
340 /*
341 * If the passthrough device does not support MSI then craft a
342 * MSI capability for it. We link the new MSI capability at the
343 * head of the list of capabilities.
344 */
345 if ((sts & PCIM_STATUS_CAPPRESENT) != 0 && sc->psc_msi.capoff == 0) {
346 int origptr, msiptr;
347 origptr = passthru_read_config(&sel, PCIR_CAP_PTR, 1);
348 msiptr = passthru_add_msicap(pi, 1, origptr);
349 sc->psc_msi.capoff = msiptr;
350 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
351 sc->psc_msi.emulated = 1;
352 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
353 }
354 #endif
355
356 /* Make sure one of the capabilities is present */
357 if (sc->psc_msi.capoff == 0 && sc->psc_msix.capoff == 0)
358 return (-1);
359 else
360 return (0);
361 }
362
363 static uint64_t
msix_table_read(struct passthru_softc * sc,uint64_t offset,int size)364 msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
365 {
366 struct pci_devinst *pi;
367 struct msix_table_entry *entry;
368 uint8_t *src8;
369 uint16_t *src16;
370 uint32_t *src32;
371 uint64_t *src64;
372 uint64_t data;
373 size_t entry_offset;
374 uint32_t table_offset;
375 int index, table_count;
376
377 pi = sc->psc_pi;
378
379 table_offset = pi->pi_msix.table_offset;
380 table_count = pi->pi_msix.table_count;
381 if (offset < table_offset ||
382 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
383 switch (size) {
384 case 1:
385 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
386 data = *src8;
387 break;
388 case 2:
389 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
390 data = *src16;
391 break;
392 case 4:
393 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
394 data = *src32;
395 break;
396 case 8:
397 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
398 data = *src64;
399 break;
400 default:
401 return (-1);
402 }
403 return (data);
404 }
405
406 offset -= table_offset;
407 index = offset / MSIX_TABLE_ENTRY_SIZE;
408 assert(index < table_count);
409
410 entry = &pi->pi_msix.table[index];
411 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
412
413 switch (size) {
414 case 1:
415 src8 = (uint8_t *)((uint8_t *)entry + entry_offset);
416 data = *src8;
417 break;
418 case 2:
419 src16 = (uint16_t *)((uint8_t *)entry + entry_offset);
420 data = *src16;
421 break;
422 case 4:
423 src32 = (uint32_t *)((uint8_t *)entry + entry_offset);
424 data = *src32;
425 break;
426 case 8:
427 src64 = (uint64_t *)((uint8_t *)entry + entry_offset);
428 data = *src64;
429 break;
430 default:
431 return (-1);
432 }
433
434 return (data);
435 }
436
437 static void
msix_table_write(struct passthru_softc * sc,uint64_t offset,int size,uint64_t data)438 msix_table_write(struct passthru_softc *sc, uint64_t offset, int size,
439 uint64_t data)
440 {
441 struct pci_devinst *pi;
442 struct msix_table_entry *entry;
443 uint8_t *dest8;
444 uint16_t *dest16;
445 uint32_t *dest32;
446 uint64_t *dest64;
447 size_t entry_offset;
448 uint32_t table_offset, vector_control;
449 int index, table_count;
450
451 pi = sc->psc_pi;
452
453 table_offset = pi->pi_msix.table_offset;
454 table_count = pi->pi_msix.table_count;
455 if (offset < table_offset ||
456 offset >= table_offset + table_count * MSIX_TABLE_ENTRY_SIZE) {
457 switch (size) {
458 case 1:
459 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
460 *dest8 = data;
461 break;
462 case 2:
463 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
464 *dest16 = data;
465 break;
466 case 4:
467 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
468 *dest32 = data;
469 break;
470 case 8:
471 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
472 *dest64 = data;
473 break;
474 }
475 return;
476 }
477
478 offset -= table_offset;
479 index = offset / MSIX_TABLE_ENTRY_SIZE;
480 assert(index < table_count);
481
482 entry = &pi->pi_msix.table[index];
483 entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
484
485 /* Only 4 byte naturally-aligned writes are supported */
486 assert(size == 4);
487 assert(entry_offset % 4 == 0);
488
489 vector_control = entry->vector_control;
490 dest32 = (uint32_t *)((uint8_t *)entry + entry_offset);
491 *dest32 = data;
492 /* If MSI-X hasn't been enabled, do nothing */
493 if (pi->pi_msix.enabled) {
494 /* If the entry is masked, don't set it up */
495 if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
496 (vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
497 (void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx,
498 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
499 sc->psc_sel.pc_func, index, entry->addr,
500 entry->msg_data, entry->vector_control);
501 }
502 }
503 }
504
505 static int
init_msix_table(struct passthru_softc * sc)506 init_msix_table(struct passthru_softc *sc)
507 {
508 struct pci_devinst *pi = sc->psc_pi;
509 struct pci_bar_mmap pbm;
510 int b, s, f;
511 uint32_t table_size, table_offset;
512
513 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
514
515 b = sc->psc_sel.pc_bus;
516 s = sc->psc_sel.pc_dev;
517 f = sc->psc_sel.pc_func;
518
519 /*
520 * Map the region of the BAR containing the MSI-X table. This is
521 * necessary for two reasons:
522 * 1. The PBA may reside in the first or last page containing the MSI-X
523 * table.
524 * 2. While PCI devices are not supposed to use the page(s) containing
525 * the MSI-X table for other purposes, some do in practice.
526 */
527 memset(&pbm, 0, sizeof(pbm));
528 pbm.pbm_sel = sc->psc_sel;
529 pbm.pbm_flags = PCIIO_BAR_MMAP_RW;
530 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar);
531 pbm.pbm_memattr = VM_MEMATTR_DEVICE;
532
533 if (ioctl(pcifd, PCIOCBARMMAP, &pbm) != 0) {
534 warn("Failed to map MSI-X table BAR on %d/%d/%d", b, s, f);
535 return (-1);
536 }
537 assert(pbm.pbm_bar_off == 0);
538 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base;
539 pi->pi_msix.mapped_size = pbm.pbm_map_length;
540
541 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
542
543 table_size = pi->pi_msix.table_offset - table_offset;
544 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
545 table_size = roundup2(table_size, 4096);
546
547 /*
548 * Unmap any pages not containing the table, we do not need to emulate
549 * accesses to them. Avoid releasing address space to help ensure that
550 * a buggy out-of-bounds access causes a crash.
551 */
552 if (table_offset != 0)
553 if (mprotect(pi->pi_msix.mapped_addr, table_offset,
554 PROT_NONE) != 0)
555 warn("Failed to unmap MSI-X table BAR region");
556 if (table_offset + table_size != pi->pi_msix.mapped_size)
557 if (mprotect(
558 pi->pi_msix.mapped_addr + table_offset + table_size,
559 pi->pi_msix.mapped_size - (table_offset + table_size),
560 PROT_NONE) != 0)
561 warn("Failed to unmap MSI-X table BAR region");
562
563 return (0);
564 }
565
566 static int
cfginitbar(struct passthru_softc * sc)567 cfginitbar(struct passthru_softc *sc)
568 {
569 int i, error;
570 struct pci_devinst *pi;
571 struct pci_bar_io bar;
572 enum pcibar_type bartype;
573 uint64_t base, size;
574
575 pi = sc->psc_pi;
576
577 /*
578 * Initialize BAR registers
579 */
580 for (i = 0; i <= PCI_BARMAX; i++) {
581 uint8_t lobits;
582
583 bzero(&bar, sizeof(bar));
584 bar.pbi_sel = sc->psc_sel;
585 bar.pbi_reg = PCIR_BAR(i);
586
587 if (ioctl(pcifd, PCIOCGETBAR, &bar) < 0)
588 continue;
589
590 if (PCI_BAR_IO(bar.pbi_base)) {
591 bartype = PCIBAR_IO;
592 base = bar.pbi_base & PCIM_BAR_IO_BASE;
593 } else {
594 switch (bar.pbi_base & PCIM_BAR_MEM_TYPE) {
595 case PCIM_BAR_MEM_64:
596 bartype = PCIBAR_MEM64;
597 break;
598 default:
599 bartype = PCIBAR_MEM32;
600 break;
601 }
602 base = bar.pbi_base & PCIM_BAR_MEM_BASE;
603 }
604 size = bar.pbi_length;
605
606 if (bartype != PCIBAR_IO) {
607 if (((base | size) & PAGE_MASK) != 0) {
608 warnx("passthru device %d/%d/%d BAR %d: "
609 "base %#lx or size %#lx not page aligned\n",
610 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
611 sc->psc_sel.pc_func, i, base, size);
612 return (-1);
613 }
614 }
615
616 /* Cache information about the "real" BAR */
617 sc->psc_bar[i].type = bartype;
618 sc->psc_bar[i].size = size;
619 sc->psc_bar[i].addr = base;
620 sc->psc_bar[i].lobits = 0;
621
622 /* Allocate the BAR in the guest I/O or MMIO space */
623 error = pci_emul_alloc_bar(pi, i, bartype, size);
624 if (error)
625 return (-1);
626
627 /* Use same lobits as physical bar */
628 lobits = (uint8_t)passthru_read_config(&sc->psc_sel,
629 PCIR_BAR(i), 0x01);
630 if (bartype == PCIBAR_MEM32 || bartype == PCIBAR_MEM64) {
631 lobits &= ~PCIM_BAR_MEM_BASE;
632 } else {
633 lobits &= ~PCIM_BAR_IO_BASE;
634 }
635 sc->psc_bar[i].lobits = lobits;
636 pi->pi_bar[i].lobits = lobits;
637
638 /*
639 * 64-bit BAR takes up two slots so skip the next one.
640 */
641 if (bartype == PCIBAR_MEM64) {
642 i++;
643 assert(i <= PCI_BARMAX);
644 sc->psc_bar[i].type = PCIBAR_MEMHI64;
645 }
646 }
647 return (0);
648 }
649
650 static int
cfginit(struct pci_devinst * pi,int bus,int slot,int func)651 cfginit(struct pci_devinst *pi, int bus, int slot, int func)
652 {
653 int error;
654 struct passthru_softc *sc;
655 uint16_t cmd;
656 uint8_t intline, intpin;
657
658 error = 1;
659 sc = pi->pi_arg;
660
661 bzero(&sc->psc_sel, sizeof(struct pcisel));
662 sc->psc_sel.pc_bus = bus;
663 sc->psc_sel.pc_dev = slot;
664 sc->psc_sel.pc_func = func;
665
666 /*
667 * Copy physical PCI header to virtual config space. COMMAND,
668 * INTLINE, and INTPIN shouldn't be aligned with their
669 * physical value and they are already set by pci_emul_init().
670 */
671 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
672 intline = pci_get_cfgdata8(pi, PCIR_INTLINE);
673 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN);
674 for (int i = 0; i <= PCIR_MAXLAT; i += 4) {
675 pci_set_cfgdata32(pi, i,
676 passthru_read_config(&sc->psc_sel, i, 4));
677 }
678 pci_set_cfgdata16(pi, PCIR_COMMAND, cmd);
679 pci_set_cfgdata8(pi, PCIR_INTLINE, intline);
680 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin);
681
682 if (cfginitmsi(sc) != 0) {
683 warnx("failed to initialize MSI for PCI %d/%d/%d",
684 bus, slot, func);
685 goto done;
686 }
687
688 if (cfginitbar(sc) != 0) {
689 warnx("failed to initialize BARs for PCI %d/%d/%d",
690 bus, slot, func);
691 goto done;
692 }
693
694 if (pci_msix_table_bar(pi) >= 0) {
695 error = init_msix_table(sc);
696 if (error != 0) {
697 warnx(
698 "failed to initialize MSI-X table for PCI %d/%d/%d: %d",
699 bus, slot, func, error);
700 goto done;
701 }
702 }
703
704 error = 0; /* success */
705 done:
706 return (error);
707 }
708
709 struct passthru_mmio_mapping *
passthru_get_mmio(struct passthru_softc * sc,int num)710 passthru_get_mmio(struct passthru_softc *sc, int num)
711 {
712 assert(sc != NULL);
713 assert(num < PASSTHRU_MMIO_MAX);
714
715 return (&sc->psc_mmio_map[num]);
716 }
717
718 struct pcisel *
passthru_get_sel(struct passthru_softc * sc)719 passthru_get_sel(struct passthru_softc *sc)
720 {
721 assert(sc != NULL);
722
723 return (&sc->psc_sel);
724 }
725
726 int
set_pcir_handler(struct passthru_softc * sc,int reg,int len,cfgread_handler rhandler,cfgwrite_handler whandler)727 set_pcir_handler(struct passthru_softc *sc, int reg, int len,
728 cfgread_handler rhandler, cfgwrite_handler whandler)
729 {
730 if (reg > PCI_REGMAX || reg + len > PCI_REGMAX + 1)
731 return (-1);
732
733 for (int i = reg; i < reg + len; ++i) {
734 assert(sc->psc_pcir_rhandler[i] == NULL || rhandler == NULL);
735 assert(sc->psc_pcir_whandler[i] == NULL || whandler == NULL);
736 sc->psc_pcir_rhandler[i] = rhandler;
737 sc->psc_pcir_whandler[i] = whandler;
738 }
739
740 return (0);
741 }
742
743 static int
passthru_legacy_config(nvlist_t * nvl,const char * opts)744 passthru_legacy_config(nvlist_t *nvl, const char *opts)
745 {
746 const char *cp;
747 char *tofree;
748 char value[16];
749 int bus, slot, func;
750
751 if (opts == NULL)
752 return (0);
753
754 cp = strchr(opts, ',');
755
756 if (strncmp(opts, "ppt", strlen("ppt")) == 0) {
757 tofree = strndup(opts, cp - opts);
758 set_config_value_node(nvl, "pptdev", tofree);
759 free(tofree);
760 } else if (sscanf(opts, "pci0:%d:%d:%d", &bus, &slot, &func) == 3 ||
761 sscanf(opts, "pci%d:%d:%d", &bus, &slot, &func) == 3 ||
762 sscanf(opts, "%d/%d/%d", &bus, &slot, &func) == 3) {
763 snprintf(value, sizeof(value), "%d", bus);
764 set_config_value_node(nvl, "bus", value);
765 snprintf(value, sizeof(value), "%d", slot);
766 set_config_value_node(nvl, "slot", value);
767 snprintf(value, sizeof(value), "%d", func);
768 set_config_value_node(nvl, "func", value);
769 } else {
770 EPRINTLN("passthru: invalid options \"%s\"", opts);
771 return (-1);
772 }
773
774 if (cp == NULL) {
775 return (0);
776 }
777
778 return (pci_parse_legacy_config(nvl, cp + 1));
779 }
780
781 static int
passthru_init_rom(struct passthru_softc * const sc,const char * const romfile)782 passthru_init_rom(struct passthru_softc *const sc, const char *const romfile)
783 {
784 if (romfile == NULL) {
785 return (0);
786 }
787
788 const int fd = open(romfile, O_RDONLY);
789 if (fd < 0) {
790 warnx("%s: can't open romfile \"%s\"", __func__, romfile);
791 return (-1);
792 }
793
794 struct stat sbuf;
795 if (fstat(fd, &sbuf) < 0) {
796 warnx("%s: can't fstat romfile \"%s\"", __func__, romfile);
797 close(fd);
798 return (-1);
799 }
800 const uint64_t rom_size = sbuf.st_size;
801
802 void *const rom_data = mmap(NULL, rom_size, PROT_READ, MAP_SHARED, fd,
803 0);
804 if (rom_data == MAP_FAILED) {
805 warnx("%s: unable to mmap romfile \"%s\" (%d)", __func__,
806 romfile, errno);
807 close(fd);
808 return (-1);
809 }
810
811 void *rom_addr;
812 int error = pci_emul_alloc_rom(sc->psc_pi, rom_size, &rom_addr);
813 if (error) {
814 warnx("%s: failed to alloc rom segment", __func__);
815 munmap(rom_data, rom_size);
816 close(fd);
817 return (error);
818 }
819 memcpy(rom_addr, rom_data, rom_size);
820
821 sc->psc_bar[PCI_ROM_IDX].type = PCIBAR_ROM;
822 sc->psc_bar[PCI_ROM_IDX].addr = (uint64_t)rom_addr;
823 sc->psc_bar[PCI_ROM_IDX].size = rom_size;
824
825 munmap(rom_data, rom_size);
826 close(fd);
827
828 return (0);
829 }
830
831 static bool
passthru_lookup_pptdev(const char * name,int * bus,int * slot,int * func)832 passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func)
833 {
834 struct pci_conf_io pc;
835 struct pci_conf conf[1];
836 struct pci_match_conf patterns[1];
837 char *cp;
838
839 bzero(&pc, sizeof(struct pci_conf_io));
840 pc.match_buf_len = sizeof(conf);
841 pc.matches = conf;
842
843 bzero(&patterns, sizeof(patterns));
844
845 /*
846 * The pattern structure requires the unit to be split out from
847 * the driver name. Walk backwards from the end of the name to
848 * find the start of the unit.
849 */
850 cp = strchr(name, '\0');
851 assert(cp != NULL);
852 while (cp != name && isdigit(cp[-1]))
853 cp--;
854 if (cp == name || !isdigit(*cp)) {
855 EPRINTLN("Invalid passthru device name %s", name);
856 return (false);
857 }
858 if ((size_t)(cp - name) + 1 > sizeof(patterns[0].pd_name)) {
859 EPRINTLN("Passthru device name %s is too long", name);
860 return (false);
861 }
862 memcpy(patterns[0].pd_name, name, cp - name);
863 patterns[0].pd_unit = strtol(cp, &cp, 10);
864 if (*cp != '\0') {
865 EPRINTLN("Invalid passthru device name %s", name);
866 return (false);
867 }
868 patterns[0].flags = PCI_GETCONF_MATCH_NAME | PCI_GETCONF_MATCH_UNIT;
869 pc.num_patterns = 1;
870 pc.pat_buf_len = sizeof(patterns);
871 pc.patterns = patterns;
872
873 if (ioctl(pcifd, PCIOCGETCONF, &pc) == -1) {
874 EPRINTLN("ioctl(PCIOCGETCONF): %s", strerror(errno));
875 return (false);
876 }
877 if (pc.status != PCI_GETCONF_LAST_DEVICE &&
878 pc.status != PCI_GETCONF_MORE_DEVS) {
879 EPRINTLN("error returned from PCIOCGETCONF ioctl");
880 return (false);
881 }
882 if (pc.num_matches == 0) {
883 EPRINTLN("Passthru device %s not found", name);
884 return (false);
885 }
886
887 if (conf[0].pc_sel.pc_domain != 0) {
888 EPRINTLN("Passthru device %s on unsupported domain", name);
889 return (false);
890 }
891 *bus = conf[0].pc_sel.pc_bus;
892 *slot = conf[0].pc_sel.pc_dev;
893 *func = conf[0].pc_sel.pc_func;
894 return (true);
895 }
896
897 static int
passthru_init(struct pci_devinst * pi,nvlist_t * nvl)898 passthru_init(struct pci_devinst *pi, nvlist_t *nvl)
899 {
900 int bus, slot, func, error, memflags;
901 struct passthru_softc *sc;
902 struct passthru_dev **devpp;
903 struct passthru_dev *devp, *dev = NULL;
904 const char *value;
905
906 sc = NULL;
907 error = 1;
908
909 memflags = vm_get_memflags(pi->pi_vmctx);
910 if (!(memflags & VM_MEM_F_WIRED)) {
911 warnx("passthru requires guest memory to be wired");
912 return (error);
913 }
914
915 if (pcifd < 0 && pcifd_init()) {
916 return (error);
917 }
918
919 #define GET_INT_CONFIG(var, name) do { \
920 value = get_config_value_node(nvl, name); \
921 if (value == NULL) { \
922 EPRINTLN("passthru: missing required %s setting", name); \
923 return (error); \
924 } \
925 var = atoi(value); \
926 } while (0)
927
928 value = get_config_value_node(nvl, "pptdev");
929 if (value != NULL) {
930 if (!passthru_lookup_pptdev(value, &bus, &slot, &func))
931 return (error);
932 } else {
933 GET_INT_CONFIG(bus, "bus");
934 GET_INT_CONFIG(slot, "slot");
935 GET_INT_CONFIG(func, "func");
936 }
937
938 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) {
939 warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
940 bus, slot, func);
941 goto done;
942 }
943
944 sc = calloc(1, sizeof(struct passthru_softc));
945
946 pi->pi_arg = sc;
947 sc->psc_pi = pi;
948
949 /* initialize config space */
950 if ((error = cfginit(pi, bus, slot, func)) != 0)
951 goto done;
952
953 /* initialize ROM */
954 if ((error = passthru_init_rom(sc,
955 get_config_value_node(nvl, "rom"))) != 0)
956 goto done;
957
958 /* Emulate most PCI header register. */
959 if ((error = set_pcir_handler(sc, 0, PCIR_MAXLAT + 1,
960 passthru_cfgread_emulate, passthru_cfgwrite_emulate)) != 0)
961 goto done;
962
963 /* Allow access to the physical status register. */
964 if ((error = set_pcir_handler(sc, PCIR_COMMAND, 0x04, NULL, NULL)) != 0)
965 goto done;
966
967 SET_FOREACH(devpp, passthru_dev_set) {
968 devp = *devpp;
969 assert(devp->probe != NULL);
970 if (devp->probe(pi) == 0) {
971 dev = devp;
972 break;
973 }
974 }
975
976 if (dev != NULL) {
977 error = dev->init(pi, nvl);
978 if (error != 0)
979 goto done;
980 }
981
982 error = 0; /* success */
983 done:
984 if (error) {
985 if (dev != NULL)
986 dev->deinit(pi);
987 free(sc);
988 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func);
989 }
990 return (error);
991 }
992
993 static int
msicap_access(struct passthru_softc * sc,int coff)994 msicap_access(struct passthru_softc *sc, int coff)
995 {
996 int caplen;
997
998 if (sc->psc_msi.capoff == 0)
999 return (0);
1000
1001 caplen = msi_caplen(sc->psc_msi.msgctrl);
1002
1003 if (coff >= sc->psc_msi.capoff && coff < sc->psc_msi.capoff + caplen)
1004 return (1);
1005 else
1006 return (0);
1007 }
1008
1009 static int
msixcap_access(struct passthru_softc * sc,int coff)1010 msixcap_access(struct passthru_softc *sc, int coff)
1011 {
1012 if (sc->psc_msix.capoff == 0)
1013 return (0);
1014
1015 return (coff >= sc->psc_msix.capoff &&
1016 coff < sc->psc_msix.capoff + MSIX_CAPLEN);
1017 }
1018
1019 static int
passthru_cfgread_default(struct passthru_softc * sc,struct pci_devinst * pi __unused,int coff,int bytes,uint32_t * rv)1020 passthru_cfgread_default(struct passthru_softc *sc,
1021 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv)
1022 {
1023 /*
1024 * MSI capability is emulated.
1025 */
1026 if (msicap_access(sc, coff) || msixcap_access(sc, coff))
1027 return (-1);
1028
1029 /*
1030 * Emulate the command register. If a single read reads both the
1031 * command and status registers, read the status register from the
1032 * device's config space.
1033 */
1034 if (coff == PCIR_COMMAND) {
1035 uint32_t st;
1036
1037 if (bytes <= 2)
1038 return (-1);
1039 st = passthru_read_config(&sc->psc_sel, PCIR_STATUS, 2);
1040 *rv = (st << 16) | pci_get_cfgdata16(pi, PCIR_COMMAND);
1041 return (0);
1042 }
1043
1044 /* Everything else just read from the device's config space */
1045 *rv = passthru_read_config(&sc->psc_sel, coff, bytes);
1046
1047 return (0);
1048 }
1049
1050 int
passthru_cfgread_emulate(struct passthru_softc * sc __unused,struct pci_devinst * pi __unused,int coff __unused,int bytes __unused,uint32_t * rv __unused)1051 passthru_cfgread_emulate(struct passthru_softc *sc __unused,
1052 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1053 uint32_t *rv __unused)
1054 {
1055 return (-1);
1056 }
1057
1058 static int
passthru_cfgread(struct pci_devinst * pi,int coff,int bytes,uint32_t * rv)1059 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv)
1060 {
1061 struct passthru_softc *sc;
1062
1063 sc = pi->pi_arg;
1064
1065 if (sc->psc_pcir_rhandler[coff] != NULL)
1066 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv));
1067
1068 return (passthru_cfgread_default(sc, pi, coff, bytes, rv));
1069 }
1070
1071 static int
passthru_cfgwrite_default(struct passthru_softc * sc,struct pci_devinst * pi,int coff,int bytes,uint32_t val)1072 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi,
1073 int coff, int bytes, uint32_t val)
1074 {
1075 int error, msix_table_entries, i;
1076 uint16_t cmd_old;
1077
1078 /*
1079 * MSI capability is emulated
1080 */
1081 if (msicap_access(sc, coff)) {
1082 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
1083 PCIY_MSI);
1084 error = vm_setup_pptdev_msi(pi->pi_vmctx, sc->psc_sel.pc_bus,
1085 sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
1086 pi->pi_msi.addr, pi->pi_msi.msg_data,
1087 pi->pi_msi.maxmsgnum);
1088 if (error != 0)
1089 err(1, "vm_setup_pptdev_msi");
1090 return (0);
1091 }
1092
1093 if (msixcap_access(sc, coff)) {
1094 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
1095 PCIY_MSIX);
1096 if (pi->pi_msix.enabled) {
1097 msix_table_entries = pi->pi_msix.table_count;
1098 for (i = 0; i < msix_table_entries; i++) {
1099 error = vm_setup_pptdev_msix(pi->pi_vmctx,
1100 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
1101 sc->psc_sel.pc_func, i,
1102 pi->pi_msix.table[i].addr,
1103 pi->pi_msix.table[i].msg_data,
1104 pi->pi_msix.table[i].vector_control);
1105
1106 if (error)
1107 err(1, "vm_setup_pptdev_msix");
1108 }
1109 } else {
1110 error = vm_disable_pptdev_msix(pi->pi_vmctx,
1111 sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
1112 sc->psc_sel.pc_func);
1113 if (error)
1114 err(1, "vm_disable_pptdev_msix");
1115 }
1116 return (0);
1117 }
1118
1119 /*
1120 * The command register is emulated, but the status register
1121 * is passed through.
1122 */
1123 if (coff == PCIR_COMMAND) {
1124 if (bytes <= 2)
1125 return (-1);
1126
1127 /* Update the physical status register. */
1128 passthru_write_config(&sc->psc_sel, PCIR_STATUS, val >> 16, 2);
1129
1130 /* Update the virtual command register. */
1131 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
1132 pci_set_cfgdata16(pi, PCIR_COMMAND, val & 0xffff);
1133 pci_emul_cmd_changed(pi, cmd_old);
1134 return (0);
1135 }
1136
1137 passthru_write_config(&sc->psc_sel, coff, bytes, val);
1138
1139 return (0);
1140 }
1141
1142 int
passthru_cfgwrite_emulate(struct passthru_softc * sc __unused,struct pci_devinst * pi __unused,int coff __unused,int bytes __unused,uint32_t val __unused)1143 passthru_cfgwrite_emulate(struct passthru_softc *sc __unused,
1144 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1145 uint32_t val __unused)
1146 {
1147 return (-1);
1148 }
1149
1150 static int
passthru_cfgwrite(struct pci_devinst * pi,int coff,int bytes,uint32_t val)1151 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)
1152 {
1153 struct passthru_softc *sc;
1154
1155 sc = pi->pi_arg;
1156
1157 if (sc->psc_pcir_whandler[coff] != NULL)
1158 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val));
1159
1160 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val));
1161 }
1162
1163 static void
passthru_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)1164 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
1165 uint64_t value)
1166 {
1167 struct passthru_softc *sc;
1168 struct pci_bar_ioreq pio;
1169
1170 sc = pi->pi_arg;
1171
1172 if (baridx == pci_msix_table_bar(pi)) {
1173 msix_table_write(sc, offset, size, value);
1174 } else {
1175 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1176 assert(size == 1 || size == 2 || size == 4);
1177 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1178
1179 bzero(&pio, sizeof(pio));
1180 pio.pbi_sel = sc->psc_sel;
1181 pio.pbi_op = PCIBARIO_WRITE;
1182 pio.pbi_bar = baridx;
1183 pio.pbi_offset = (uint32_t)offset;
1184 pio.pbi_width = size;
1185 pio.pbi_value = (uint32_t)value;
1186
1187 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1188 }
1189 }
1190
1191 static uint64_t
passthru_read(struct pci_devinst * pi,int baridx,uint64_t offset,int size)1192 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
1193 {
1194 struct passthru_softc *sc;
1195 struct pci_bar_ioreq pio;
1196 uint64_t val;
1197
1198 sc = pi->pi_arg;
1199
1200 if (baridx == pci_msix_table_bar(pi)) {
1201 val = msix_table_read(sc, offset, size);
1202 } else {
1203 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1204 assert(size == 1 || size == 2 || size == 4);
1205 assert(offset <= UINT32_MAX && offset + size <= UINT32_MAX);
1206
1207 bzero(&pio, sizeof(pio));
1208 pio.pbi_sel = sc->psc_sel;
1209 pio.pbi_op = PCIBARIO_READ;
1210 pio.pbi_bar = baridx;
1211 pio.pbi_offset = (uint32_t)offset;
1212 pio.pbi_width = size;
1213
1214 (void)ioctl(pcifd, PCIOCBARIO, &pio);
1215
1216 val = pio.pbi_value;
1217 }
1218
1219 return (val);
1220 }
1221
1222 static void
passthru_msix_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1223 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled,
1224 uint64_t address)
1225 {
1226 struct passthru_softc *sc;
1227 size_t remaining;
1228 uint32_t table_size, table_offset;
1229
1230 sc = pi->pi_arg;
1231 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
1232 if (table_offset > 0) {
1233 if (!enabled) {
1234 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1235 sc->psc_sel.pc_bus,
1236 sc->psc_sel.pc_dev,
1237 sc->psc_sel.pc_func, address,
1238 table_offset) != 0)
1239 warnx("pci_passthru: unmap_pptdev_mmio failed");
1240 } else {
1241 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1242 sc->psc_sel.pc_dev,
1243 sc->psc_sel.pc_func, address,
1244 table_offset,
1245 sc->psc_bar[baridx].addr) != 0)
1246 warnx("pci_passthru: map_pptdev_mmio failed");
1247 }
1248 }
1249 table_size = pi->pi_msix.table_offset - table_offset;
1250 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
1251 table_size = roundup2(table_size, 4096);
1252 remaining = pi->pi_bar[baridx].size - table_offset - table_size;
1253 if (remaining > 0) {
1254 address += table_offset + table_size;
1255 if (!enabled) {
1256 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1257 sc->psc_sel.pc_bus,
1258 sc->psc_sel.pc_dev,
1259 sc->psc_sel.pc_func, address,
1260 remaining) != 0)
1261 warnx("pci_passthru: unmap_pptdev_mmio failed");
1262 } else {
1263 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1264 sc->psc_sel.pc_dev,
1265 sc->psc_sel.pc_func, address,
1266 remaining,
1267 sc->psc_bar[baridx].addr +
1268 table_offset + table_size) != 0)
1269 warnx("pci_passthru: map_pptdev_mmio failed");
1270 }
1271 }
1272 }
1273
1274 static void
passthru_mmio_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1275 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
1276 uint64_t address)
1277 {
1278 struct passthru_softc *sc;
1279
1280 sc = pi->pi_arg;
1281 if (!enabled) {
1282 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1283 sc->psc_sel.pc_dev,
1284 sc->psc_sel.pc_func, address,
1285 sc->psc_bar[baridx].size) != 0)
1286 warnx("pci_passthru: unmap_pptdev_mmio failed");
1287 } else {
1288 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1289 sc->psc_sel.pc_dev,
1290 sc->psc_sel.pc_func, address,
1291 sc->psc_bar[baridx].size,
1292 sc->psc_bar[baridx].addr) != 0)
1293 warnx("pci_passthru: map_pptdev_mmio failed");
1294 }
1295 }
1296
1297 static void
passthru_addr_rom(struct pci_devinst * const pi,const int idx,const int enabled)1298 passthru_addr_rom(struct pci_devinst *const pi, const int idx,
1299 const int enabled)
1300 {
1301 const uint64_t addr = pi->pi_bar[idx].addr;
1302 const uint64_t size = pi->pi_bar[idx].size;
1303
1304 if (!enabled) {
1305 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) {
1306 errx(4, "%s: munmap_memseg @ [%016lx - %016lx] failed",
1307 __func__, addr, addr + size);
1308 }
1309
1310 } else {
1311 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM,
1312 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) {
1313 errx(4, "%s: mmap_memseg @ [%016lx - %016lx] failed",
1314 __func__, addr, addr + size);
1315 }
1316 }
1317 }
1318
1319 static void
passthru_addr(struct pci_devinst * pi,int baridx,int enabled,uint64_t address)1320 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address)
1321 {
1322 switch (pi->pi_bar[baridx].type) {
1323 case PCIBAR_IO:
1324 /* IO BARs are emulated */
1325 break;
1326 case PCIBAR_ROM:
1327 passthru_addr_rom(pi, baridx, enabled);
1328 break;
1329 case PCIBAR_MEM32:
1330 case PCIBAR_MEM64:
1331 if (baridx == pci_msix_table_bar(pi))
1332 passthru_msix_addr(pi, baridx, enabled, address);
1333 else
1334 passthru_mmio_addr(pi, baridx, enabled, address);
1335 break;
1336 default:
1337 errx(4, "%s: invalid BAR type %d", __func__,
1338 pi->pi_bar[baridx].type);
1339 }
1340 }
1341
1342 static const struct pci_devemu passthru = {
1343 .pe_emu = "passthru",
1344 .pe_init = passthru_init,
1345 .pe_legacy_config = passthru_legacy_config,
1346 .pe_cfgwrite = passthru_cfgwrite,
1347 .pe_cfgread = passthru_cfgread,
1348 .pe_barwrite = passthru_write,
1349 .pe_barread = passthru_read,
1350 .pe_baraddr = passthru_addr,
1351 };
1352 PCI_EMUL_SET(passthru);
1353