1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,dispcc-sm6125.h> 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-sm6125.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <19200000>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <32764>; 33 clock-output-names = "sleep_clk"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo260"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 next-level-cache = <&l2_0>; 48 l2_0: l2-cache { 49 compatible = "cache"; 50 cache-level = <2>; 51 cache-unified; 52 }; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "qcom,kryo260"; 58 reg = <0x0 0x1>; 59 enable-method = "psci"; 60 capacity-dmips-mhz = <1024>; 61 next-level-cache = <&l2_0>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo260"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 capacity-dmips-mhz = <1024>; 70 next-level-cache = <&l2_0>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo260"; 76 reg = <0x0 0x3>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 next-level-cache = <&l2_0>; 80 }; 81 82 cpu4: cpu@100 { 83 device_type = "cpu"; 84 compatible = "qcom,kryo260"; 85 reg = <0x0 0x100>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <1638>; 88 next-level-cache = <&l2_1>; 89 l2_1: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 cpu5: cpu@101 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo260"; 99 reg = <0x0 0x101>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <1638>; 102 next-level-cache = <&l2_1>; 103 }; 104 105 cpu6: cpu@102 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo260"; 108 reg = <0x0 0x102>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1638>; 111 next-level-cache = <&l2_1>; 112 }; 113 114 cpu7: cpu@103 { 115 device_type = "cpu"; 116 compatible = "qcom,kryo260"; 117 reg = <0x0 0x103>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <1638>; 120 next-level-cache = <&l2_1>; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&cpu0>; 127 }; 128 129 core1 { 130 cpu = <&cpu1>; 131 }; 132 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 137 core3 { 138 cpu = <&cpu3>; 139 }; 140 }; 141 142 cluster1 { 143 core0 { 144 cpu = <&cpu4>; 145 }; 146 147 core1 { 148 cpu = <&cpu5>; 149 }; 150 151 core2 { 152 cpu = <&cpu6>; 153 }; 154 155 core3 { 156 cpu = <&cpu7>; 157 }; 158 }; 159 }; 160 }; 161 162 firmware { 163 scm: scm { 164 compatible = "qcom,scm-sm6125", "qcom,scm"; 165 #reset-cells = <1>; 166 }; 167 }; 168 169 memory@40000000 { 170 /* We expect the bootloader to fill in the size */ 171 reg = <0x0 0x40000000 0x0 0x0>; 172 device_type = "memory"; 173 }; 174 175 pmu { 176 compatible = "arm,armv8-pmuv3"; 177 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 178 }; 179 180 psci { 181 compatible = "arm,psci-1.0"; 182 method = "smc"; 183 }; 184 185 rpm: remoteproc { 186 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc"; 187 188 glink-edge { 189 compatible = "qcom,glink-rpm"; 190 191 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 192 qcom,rpm-msg-ram = <&rpm_msg_ram>; 193 mboxes = <&apcs_glb 0>; 194 195 rpm_requests: rpm-requests { 196 compatible = "qcom,rpm-sm6125", "qcom,glink-smd-rpm"; 197 qcom,glink-channels = "rpm_requests"; 198 199 rpmcc: clock-controller { 200 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 201 #clock-cells = <1>; 202 clocks = <&xo_board>; 203 clock-names = "xo"; 204 }; 205 206 rpmpd: power-controller { 207 compatible = "qcom,sm6125-rpmpd"; 208 #power-domain-cells = <1>; 209 operating-points-v2 = <&rpmpd_opp_table>; 210 211 rpmpd_opp_table: opp-table { 212 compatible = "operating-points-v2"; 213 214 rpmpd_opp_ret: opp1 { 215 opp-level = <RPM_SMD_LEVEL_RETENTION>; 216 }; 217 218 rpmpd_opp_ret_plus: opp2 { 219 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 220 }; 221 222 rpmpd_opp_min_svs: opp3 { 223 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 224 }; 225 226 rpmpd_opp_low_svs: opp4 { 227 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 228 }; 229 230 rpmpd_opp_svs: opp5 { 231 opp-level = <RPM_SMD_LEVEL_SVS>; 232 }; 233 234 rpmpd_opp_svs_plus: opp6 { 235 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 236 }; 237 238 rpmpd_opp_nom: opp7 { 239 opp-level = <RPM_SMD_LEVEL_NOM>; 240 }; 241 242 rpmpd_opp_nom_plus: opp8 { 243 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 244 }; 245 246 rpmpd_opp_turbo: opp9 { 247 opp-level = <RPM_SMD_LEVEL_TURBO>; 248 }; 249 250 rpmpd_opp_turbo_no_cpr: opp10 { 251 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 252 }; 253 }; 254 }; 255 }; 256 }; 257 }; 258 259 reserved_memory: reserved-memory { 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 264 hyp_mem: memory@45700000 { 265 reg = <0x0 0x45700000 0x0 0x600000>; 266 no-map; 267 }; 268 269 xbl_aop_mem: memory@45e00000 { 270 reg = <0x0 0x45e00000 0x0 0x140000>; 271 no-map; 272 }; 273 274 sec_apps_mem: memory@45fff000 { 275 reg = <0x0 0x45fff000 0x0 0x1000>; 276 no-map; 277 }; 278 279 smem_mem: memory@46000000 { 280 reg = <0x0 0x46000000 0x0 0x200000>; 281 no-map; 282 }; 283 284 reserved_mem1: memory@46200000 { 285 reg = <0x0 0x46200000 0x0 0x2d00000>; 286 no-map; 287 }; 288 289 camera_mem: memory@4ab00000 { 290 reg = <0x0 0x4ab00000 0x0 0x500000>; 291 no-map; 292 }; 293 294 modem_mem: memory@4b000000 { 295 reg = <0x0 0x4b000000 0x0 0x7e00000>; 296 no-map; 297 }; 298 299 venus_mem: memory@52e00000 { 300 reg = <0x0 0x52e00000 0x0 0x500000>; 301 no-map; 302 }; 303 304 wlan_msa_mem: memory@53300000 { 305 reg = <0x0 0x53300000 0x0 0x200000>; 306 no-map; 307 }; 308 309 cdsp_mem: memory@53500000 { 310 reg = <0x0 0x53500000 0x0 0x1e00000>; 311 no-map; 312 }; 313 314 adsp_pil_mem: memory@55300000 { 315 reg = <0x0 0x55300000 0x0 0x1e00000>; 316 no-map; 317 }; 318 319 ipa_fw_mem: memory@57100000 { 320 reg = <0x0 0x57100000 0x0 0x10000>; 321 no-map; 322 }; 323 324 ipa_gsi_mem: memory@57110000 { 325 reg = <0x0 0x57110000 0x0 0x5000>; 326 no-map; 327 }; 328 329 gpu_mem: memory@57115000 { 330 reg = <0x0 0x57115000 0x0 0x2000>; 331 no-map; 332 }; 333 334 cont_splash_mem: memory@5c000000 { 335 reg = <0x0 0x5c000000 0x0 0x00f00000>; 336 no-map; 337 }; 338 339 dfps_data_mem: memory@5cf00000 { 340 reg = <0x0 0x5cf00000 0x0 0x0100000>; 341 no-map; 342 }; 343 344 cdsp_sec_mem: memory@5f800000 { 345 reg = <0x0 0x5f800000 0x0 0x1e00000>; 346 no-map; 347 }; 348 349 qseecom_mem: memory@5e400000 { 350 reg = <0x0 0x5e400000 0x0 0x1400000>; 351 no-map; 352 }; 353 354 sdsp_mem: memory@f3000000 { 355 reg = <0x0 0xf3000000 0x0 0x400000>; 356 no-map; 357 }; 358 359 adsp_mem: memory@f3400000 { 360 reg = <0x0 0xf3400000 0x0 0x800000>; 361 no-map; 362 }; 363 364 qseecom_ta_mem: memory@13fc00000 { 365 reg = <0x1 0x3fc00000 0x0 0x400000>; 366 no-map; 367 }; 368 }; 369 370 smem: smem { 371 compatible = "qcom,smem"; 372 memory-region = <&smem_mem>; 373 hwlocks = <&tcsr_mutex 3>; 374 }; 375 376 soc@0 { 377 #address-cells = <1>; 378 #size-cells = <1>; 379 ranges = <0x00 0x00 0x00 0xffffffff>; 380 compatible = "simple-bus"; 381 382 tcsr_mutex: hwlock@340000 { 383 compatible = "qcom,tcsr-mutex"; 384 reg = <0x00340000 0x20000>; 385 #hwlock-cells = <1>; 386 }; 387 388 tlmm: pinctrl@500000 { 389 compatible = "qcom,sm6125-tlmm"; 390 reg = <0x00500000 0x400000>, 391 <0x00900000 0x400000>, 392 <0x00d00000 0x400000>; 393 reg-names = "west", "south", "east"; 394 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 395 gpio-controller; 396 gpio-ranges = <&tlmm 0 0 134>; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 401 sdc2_off_state: sdc2-off-state { 402 clk-pins { 403 pins = "sdc2_clk"; 404 drive-strength = <2>; 405 bias-disable; 406 }; 407 408 cmd-pins { 409 pins = "sdc2_cmd"; 410 drive-strength = <2>; 411 bias-pull-up; 412 }; 413 414 data-pins { 415 pins = "sdc2_data"; 416 drive-strength = <2>; 417 bias-pull-up; 418 }; 419 }; 420 421 sdc2_on_state: sdc2-on-state { 422 clk-pins { 423 pins = "sdc2_clk"; 424 drive-strength = <16>; 425 bias-disable; 426 }; 427 428 cmd-pins { 429 pins = "sdc2_cmd"; 430 drive-strength = <10>; 431 bias-pull-up; 432 }; 433 434 data-pins { 435 pins = "sdc2_data"; 436 drive-strength = <10>; 437 bias-pull-up; 438 }; 439 }; 440 441 qup_i2c0_default: qup-i2c0-default-state { 442 pins = "gpio0", "gpio1"; 443 function = "qup00"; 444 drive-strength = <2>; 445 bias-disable; 446 }; 447 448 qup_i2c0_sleep: qup-i2c0-sleep-state { 449 pins = "gpio0", "gpio1"; 450 function = "gpio"; 451 drive-strength = <2>; 452 bias-pull-up; 453 }; 454 455 qup_i2c1_default: qup-i2c1-default-state { 456 pins = "gpio4", "gpio5"; 457 function = "qup01"; 458 drive-strength = <2>; 459 bias-disable; 460 }; 461 462 qup_i2c1_sleep: qup-i2c1-sleep-state { 463 pins = "gpio4", "gpio5"; 464 function = "gpio"; 465 drive-strength = <2>; 466 bias-pull-up; 467 }; 468 469 qup_i2c2_default: qup-i2c2-default-state { 470 pins = "gpio6", "gpio7"; 471 function = "qup02"; 472 drive-strength = <2>; 473 bias-disable; 474 }; 475 476 qup_i2c2_sleep: qup-i2c2-sleep-state { 477 pins = "gpio6", "gpio7"; 478 function = "gpio"; 479 drive-strength = <2>; 480 bias-pull-up; 481 }; 482 483 qup_i2c3_default: qup-i2c3-default-state { 484 pins = "gpio14", "gpio15"; 485 function = "qup03"; 486 drive-strength = <2>; 487 bias-disable; 488 }; 489 490 qup_i2c3_sleep: qup-i2c3-sleep-state { 491 pins = "gpio14", "gpio15"; 492 function = "gpio"; 493 drive-strength = <2>; 494 bias-pull-up; 495 }; 496 497 qup_i2c4_default: qup-i2c4-default-state { 498 pins = "gpio16", "gpio17"; 499 function = "qup04"; 500 drive-strength = <2>; 501 bias-disable; 502 }; 503 504 qup_i2c4_sleep: qup-i2c4-sleep-state { 505 pins = "gpio16", "gpio17"; 506 function = "gpio"; 507 drive-strength = <2>; 508 bias-pull-up; 509 }; 510 511 qup_i2c5_default: qup-i2c5-default-state { 512 pins = "gpio22", "gpio23"; 513 function = "qup10"; 514 drive-strength = <2>; 515 bias-disable; 516 }; 517 518 qup_i2c5_sleep: qup-i2c5-sleep-state { 519 pins = "gpio22", "gpio23"; 520 function = "gpio"; 521 drive-strength = <2>; 522 bias-pull-up; 523 }; 524 525 qup_i2c6_default: qup-i2c6-default-state { 526 pins = "gpio30", "gpio31"; 527 function = "qup11"; 528 drive-strength = <2>; 529 bias-disable; 530 }; 531 532 qup_i2c6_sleep: qup-i2c6-sleep-state { 533 pins = "gpio30", "gpio31"; 534 function = "gpio"; 535 drive-strength = <2>; 536 bias-pull-up; 537 }; 538 539 qup_i2c7_default: qup-i2c7-default-state { 540 pins = "gpio28", "gpio29"; 541 function = "qup12"; 542 drive-strength = <2>; 543 bias-disable; 544 }; 545 546 qup_i2c7_sleep: qup-i2c7-sleep-state { 547 pins = "gpio28", "gpio29"; 548 function = "gpio"; 549 drive-strength = <2>; 550 bias-pull-up; 551 }; 552 553 qup_i2c8_default: qup-i2c8-default-state { 554 pins = "gpio18", "gpio19"; 555 function = "qup13"; 556 drive-strength = <2>; 557 bias-disable; 558 }; 559 560 qup_i2c8_sleep: qup-i2c8-sleep-state { 561 pins = "gpio18", "gpio19"; 562 function = "gpio"; 563 drive-strength = <2>; 564 bias-pull-up; 565 }; 566 567 qup_i2c9_default: qup-i2c9-default-state { 568 pins = "gpio10", "gpio11"; 569 function = "qup14"; 570 drive-strength = <2>; 571 bias-disable; 572 }; 573 574 qup_i2c9_sleep: qup-i2c9-sleep-state { 575 pins = "gpio10", "gpio11"; 576 function = "gpio"; 577 drive-strength = <2>; 578 bias-pull-up; 579 }; 580 581 qup_spi0_default: qup-spi0-default-state { 582 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 583 function = "qup00"; 584 drive-strength = <6>; 585 bias-disable; 586 }; 587 588 qup_spi0_sleep: qup-spi0-sleep-state { 589 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 590 function = "gpio"; 591 drive-strength = <6>; 592 bias-disable; 593 }; 594 595 qup_spi2_default: qup-spi2-default-state { 596 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 597 function = "qup02"; 598 drive-strength = <6>; 599 bias-disable; 600 }; 601 602 qup_spi2_sleep: qup-spi2-sleep-state { 603 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 604 function = "gpio"; 605 drive-strength = <6>; 606 bias-disable; 607 }; 608 609 qup_spi5_default: qup-spi5-default-state { 610 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 611 function = "qup10"; 612 drive-strength = <6>; 613 bias-disable; 614 }; 615 616 qup_spi5_sleep: qup-spi5-sleep-state { 617 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 618 function = "gpio"; 619 drive-strength = <6>; 620 bias-disable; 621 }; 622 623 qup_spi6_default: qup-spi6-default-state { 624 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 625 function = "qup11"; 626 drive-strength = <6>; 627 bias-disable; 628 }; 629 630 qup_spi6_sleep: qup-spi6-sleep-state { 631 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 632 function = "gpio"; 633 drive-strength = <6>; 634 bias-disable; 635 }; 636 637 qup_spi8_default: qup-spi8-default-state { 638 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 639 function = "qup13"; 640 drive-strength = <6>; 641 bias-disable; 642 }; 643 644 qup_spi8_sleep: qup-spi8-sleep-state { 645 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 646 function = "gpio"; 647 drive-strength = <6>; 648 bias-disable; 649 }; 650 651 qup_spi9_default: qup-spi9-default-state { 652 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 653 function = "qup14"; 654 drive-strength = <6>; 655 bias-disable; 656 }; 657 658 qup_spi9_sleep: qup-spi9-sleep-state { 659 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 660 function = "gpio"; 661 drive-strength = <6>; 662 bias-disable; 663 }; 664 665 qup_uart4_default: qup-uart4-default-state { 666 pins = "gpio16", "gpio17"; 667 function = "qup04"; 668 drive-strength = <2>; 669 bias-disable; 670 }; 671 }; 672 673 gcc: clock-controller@1400000 { 674 compatible = "qcom,gcc-sm6125"; 675 reg = <0x01400000 0x1f0000>; 676 #clock-cells = <1>; 677 #reset-cells = <1>; 678 #power-domain-cells = <1>; 679 clock-names = "bi_tcxo", "sleep_clk"; 680 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 681 }; 682 683 hsusb_phy1: phy@1613000 { 684 compatible = "qcom,msm8996-qusb2-phy"; 685 reg = <0x01613000 0x180>; 686 #phy-cells = <0>; 687 688 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 689 <&rpmcc RPM_SMD_XO_CLK_SRC>; 690 clock-names = "cfg_ahb", "ref"; 691 692 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 693 status = "disabled"; 694 }; 695 696 rng: rng@1b53000 { 697 compatible = "qcom,prng-ee"; 698 reg = <0x01b53000 0x1000>; 699 clocks = <&gcc GCC_PRNG_AHB_CLK>; 700 clock-names = "core"; 701 }; 702 703 spmi_bus: spmi@1c40000 { 704 compatible = "qcom,spmi-pmic-arb"; 705 reg = <0x01c40000 0x1100>, 706 <0x01e00000 0x2000000>, 707 <0x03e00000 0x100000>, 708 <0x03f00000 0xa0000>, 709 <0x01c0a000 0x26000>; 710 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 711 interrupt-names = "periph_irq"; 712 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 713 qcom,ee = <0>; 714 qcom,channel = <0>; 715 #address-cells = <2>; 716 #size-cells = <0>; 717 interrupt-controller; 718 #interrupt-cells = <4>; 719 }; 720 721 rpm_msg_ram: sram@45f0000 { 722 compatible = "qcom,rpm-msg-ram"; 723 reg = <0x045f0000 0x7000>; 724 }; 725 726 sdhc_1: mmc@4744000 { 727 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 728 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 729 reg-names = "hc", "cqhci"; 730 731 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "hc_irq", "pwr_irq"; 734 735 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 736 <&gcc GCC_SDCC1_APPS_CLK>, 737 <&rpmcc RPM_SMD_XO_CLK_SRC>; 738 clock-names = "iface", "core", "xo"; 739 iommus = <&apps_smmu 0x160 0x0>; 740 741 power-domains = <&rpmpd RPMPD_VDDCX>; 742 743 qcom,dll-config = <0x000f642c>; 744 qcom,ddr-config = <0x80040873>; 745 746 bus-width = <8>; 747 non-removable; 748 supports-cqe; 749 750 status = "disabled"; 751 }; 752 753 sdhc_2: mmc@4784000 { 754 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 755 reg = <0x04784000 0x1000>; 756 reg-names = "hc"; 757 758 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "hc_irq", "pwr_irq"; 761 762 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 763 <&gcc GCC_SDCC2_APPS_CLK>, 764 <&rpmcc RPM_SMD_XO_CLK_SRC>; 765 clock-names = "iface", "core", "xo"; 766 iommus = <&apps_smmu 0x180 0x0>; 767 768 pinctrl-0 = <&sdc2_on_state>; 769 pinctrl-1 = <&sdc2_off_state>; 770 pinctrl-names = "default", "sleep"; 771 772 power-domains = <&rpmpd RPMPD_VDDCX>; 773 774 qcom,dll-config = <0x0007642c>; 775 qcom,ddr-config = <0x80040873>; 776 777 bus-width = <4>; 778 status = "disabled"; 779 }; 780 781 ufs_mem_hc: ufshc@4804000 { 782 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 783 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 784 reg-names = "std", "ice"; 785 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 786 787 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 788 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 789 <&gcc GCC_UFS_PHY_AHB_CLK>, 790 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 791 <&rpmcc RPM_SMD_XO_CLK_SRC>, 792 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 793 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 794 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 795 clock-names = "core_clk", 796 "bus_aggr_clk", 797 "iface_clk", 798 "core_clk_unipro", 799 "ref_clk", 800 "tx_lane0_sync_clk", 801 "rx_lane0_sync_clk", 802 "ice_core_clk"; 803 freq-table-hz = <50000000 240000000>, 804 <0 0>, 805 <0 0>, 806 <37500000 150000000>, 807 <0 0>, 808 <0 0>, 809 <0 0>, 810 <75000000 300000000>; 811 812 resets = <&gcc GCC_UFS_PHY_BCR>; 813 reset-names = "rst"; 814 #reset-cells = <1>; 815 816 phys = <&ufs_mem_phy>; 817 phy-names = "ufsphy"; 818 819 lanes-per-direction = <1>; 820 821 iommus = <&apps_smmu 0x200 0x0>; 822 823 status = "disabled"; 824 }; 825 826 ufs_mem_phy: phy@4807000 { 827 compatible = "qcom,sm6125-qmp-ufs-phy"; 828 reg = <0x04807000 0xdb8>; 829 830 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 831 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 832 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 833 clock-names = "ref", 834 "ref_aux", 835 "qref"; 836 837 resets = <&ufs_mem_hc 0>; 838 reset-names = "ufsphy"; 839 840 power-domains = <&gcc UFS_PHY_GDSC>; 841 842 #phy-cells = <0>; 843 844 status = "disabled"; 845 }; 846 847 gpi_dma0: dma-controller@4a00000 { 848 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 849 reg = <0x04a00000 0x60000>; 850 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 858 dma-channels = <8>; 859 dma-channel-mask = <0x1f>; 860 iommus = <&apps_smmu 0x136 0x0>; 861 #dma-cells = <3>; 862 status = "disabled"; 863 }; 864 865 qupv3_id_0: geniqup@4ac0000 { 866 compatible = "qcom,geni-se-qup"; 867 reg = <0x04ac0000 0x2000>; 868 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 869 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 870 clock-names = "m-ahb", "s-ahb"; 871 iommus = <&apps_smmu 0x123 0x0>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 ranges; 875 status = "disabled"; 876 877 i2c0: i2c@4a80000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0x04a80000 0x4000>; 880 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 881 clock-names = "se"; 882 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 883 pinctrl-0 = <&qup_i2c0_default>; 884 pinctrl-1 = <&qup_i2c0_sleep>; 885 pinctrl-names = "default", "sleep"; 886 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 887 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 888 dma-names = "tx", "rx"; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 894 spi0: spi@4a80000 { 895 compatible = "qcom,geni-spi"; 896 reg = <0x04a80000 0x4000>; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 898 clock-names = "se"; 899 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 900 pinctrl-0 = <&qup_spi0_default>; 901 pinctrl-1 = <&qup_spi0_sleep>; 902 pinctrl-names = "default", "sleep"; 903 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 904 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 905 dma-names = "tx", "rx"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 status = "disabled"; 909 }; 910 911 i2c1: i2c@4a84000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0x04a84000 0x4000>; 914 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 915 clock-names = "se"; 916 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 917 pinctrl-0 = <&qup_i2c1_default>; 918 pinctrl-1 = <&qup_i2c1_sleep>; 919 pinctrl-names = "default", "sleep"; 920 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 921 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 922 dma-names = "tx", "rx"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 status = "disabled"; 926 }; 927 928 i2c2: i2c@4a88000 { 929 compatible = "qcom,geni-i2c"; 930 reg = <0x04a88000 0x4000>; 931 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 932 clock-names = "se"; 933 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 934 pinctrl-0 = <&qup_i2c2_default>; 935 pinctrl-1 = <&qup_i2c2_sleep>; 936 pinctrl-names = "default", "sleep"; 937 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 938 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 939 dma-names = "tx", "rx"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 945 spi2: spi@4a88000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0x04a88000 0x4000>; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 949 clock-names = "se"; 950 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 951 pinctrl-0 = <&qup_spi2_default>; 952 pinctrl-1 = <&qup_spi2_sleep>; 953 pinctrl-names = "default", "sleep"; 954 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 955 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 956 dma-names = "tx", "rx"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 962 i2c3: i2c@4a8c000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0x04a8c000 0x4000>; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 966 clock-names = "se"; 967 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 968 pinctrl-0 = <&qup_i2c3_default>; 969 pinctrl-1 = <&qup_i2c3_sleep>; 970 pinctrl-names = "default", "sleep"; 971 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 972 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 973 dma-names = "tx", "rx"; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 i2c4: i2c@4a90000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0x04a90000 0x4000>; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 983 clock-names = "se"; 984 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 985 pinctrl-0 = <&qup_i2c4_default>; 986 pinctrl-1 = <&qup_i2c4_sleep>; 987 pinctrl-names = "default", "sleep"; 988 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 989 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 990 dma-names = "tx", "rx"; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 }; 995 996 uart4: serial@4a90000 { 997 compatible = "qcom,geni-debug-uart"; 998 reg = <0x04a90000 0x4000>; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1000 clock-names = "se"; 1001 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1002 pinctrl-0 = <&qup_uart4_default>; 1003 pinctrl-names = "default"; 1004 status = "disabled"; 1005 }; 1006 }; 1007 1008 gpi_dma1: dma-controller@4c00000 { 1009 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 1010 reg = <0x04c00000 0x60000>; 1011 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1019 dma-channels = <8>; 1020 dma-channel-mask = <0x0f>; 1021 iommus = <&apps_smmu 0x156 0x0>; 1022 #dma-cells = <3>; 1023 status = "disabled"; 1024 }; 1025 1026 qupv3_id_1: geniqup@4cc0000 { 1027 compatible = "qcom,geni-se-qup"; 1028 reg = <0x04cc0000 0x2000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1030 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1031 clock-names = "m-ahb", "s-ahb"; 1032 iommus = <&apps_smmu 0x143 0x0>; 1033 #address-cells = <1>; 1034 #size-cells = <1>; 1035 ranges; 1036 status = "disabled"; 1037 1038 i2c5: i2c@4c80000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0x04c80000 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1042 clock-names = "se"; 1043 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1044 pinctrl-0 = <&qup_i2c5_default>; 1045 pinctrl-1 = <&qup_i2c5_sleep>; 1046 pinctrl-names = "default", "sleep"; 1047 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1048 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1049 dma-names = "tx", "rx"; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 spi5: spi@4c80000 { 1056 compatible = "qcom,geni-spi"; 1057 reg = <0x04c80000 0x4000>; 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1059 clock-names = "se"; 1060 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1061 pinctrl-0 = <&qup_spi5_default>; 1062 pinctrl-1 = <&qup_spi5_sleep>; 1063 pinctrl-names = "default", "sleep"; 1064 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1065 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 i2c6: i2c@4c84000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0x04c84000 0x4000>; 1075 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1076 clock-names = "se"; 1077 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1078 pinctrl-0 = <&qup_i2c6_default>; 1079 pinctrl-1 = <&qup_i2c6_sleep>; 1080 pinctrl-names = "default", "sleep"; 1081 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1082 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1083 dma-names = "tx", "rx"; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 status = "disabled"; 1087 }; 1088 1089 spi6: spi@4c84000 { 1090 compatible = "qcom,geni-spi"; 1091 reg = <0x04c84000 0x4000>; 1092 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1093 clock-names = "se"; 1094 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1095 pinctrl-0 = <&qup_spi6_default>; 1096 pinctrl-1 = <&qup_spi6_sleep>; 1097 pinctrl-names = "default", "sleep"; 1098 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1099 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1100 dma-names = "tx", "rx"; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 i2c7: i2c@4c88000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0x04c88000 0x4000>; 1109 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1110 clock-names = "se"; 1111 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1112 pinctrl-0 = <&qup_i2c7_default>; 1113 pinctrl-1 = <&qup_i2c7_sleep>; 1114 pinctrl-names = "default", "sleep"; 1115 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1116 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1117 dma-names = "tx", "rx"; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 status = "disabled"; 1121 }; 1122 1123 i2c8: i2c@4c8c000 { 1124 compatible = "qcom,geni-i2c"; 1125 reg = <0x04c8c000 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1127 clock-names = "se"; 1128 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1129 pinctrl-0 = <&qup_i2c8_default>; 1130 pinctrl-1 = <&qup_i2c8_sleep>; 1131 pinctrl-names = "default", "sleep"; 1132 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1133 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi8: spi@4c8c000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0x04c8c000 0x4000>; 1143 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1144 clock-names = "se"; 1145 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1146 pinctrl-0 = <&qup_spi8_default>; 1147 pinctrl-1 = <&qup_spi8_sleep>; 1148 pinctrl-names = "default", "sleep"; 1149 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1150 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1151 dma-names = "tx", "rx"; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c9: i2c@4c90000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0x04c90000 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1161 clock-names = "se"; 1162 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1163 pinctrl-0 = <&qup_i2c9_default>; 1164 pinctrl-1 = <&qup_i2c9_sleep>; 1165 pinctrl-names = "default", "sleep"; 1166 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1167 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1168 dma-names = "tx", "rx"; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 spi9: spi@4c90000 { 1175 compatible = "qcom,geni-spi"; 1176 reg = <0x04c90000 0x4000>; 1177 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1178 clock-names = "se"; 1179 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1180 pinctrl-0 = <&qup_spi9_default>; 1181 pinctrl-1 = <&qup_spi9_sleep>; 1182 pinctrl-names = "default", "sleep"; 1183 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1184 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 }; 1191 1192 usb3: usb@4ef8800 { 1193 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 1194 reg = <0x04ef8800 0x400>; 1195 #address-cells = <1>; 1196 #size-cells = <1>; 1197 ranges; 1198 1199 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1200 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1201 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1202 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1203 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1204 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1205 clock-names = "cfg_noc", 1206 "core", 1207 "iface", 1208 "sleep", 1209 "mock_utmi", 1210 "xo"; 1211 1212 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1213 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1214 assigned-clock-rates = <19200000>, <66666667>; 1215 1216 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1220 interrupt-names = "pwr_event", 1221 "qusb2_phy", 1222 "hs_phy_irq", 1223 "ss_phy_irq"; 1224 1225 power-domains = <&gcc USB30_PRIM_GDSC>; 1226 qcom,select-utmi-as-pipe-clk; 1227 status = "disabled"; 1228 1229 usb3_dwc3: usb@4e00000 { 1230 compatible = "snps,dwc3"; 1231 reg = <0x04e00000 0xcd00>; 1232 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1233 iommus = <&apps_smmu 0x100 0x0>; 1234 phys = <&hsusb_phy1>; 1235 phy-names = "usb2-phy"; 1236 snps,dis_u2_susphy_quirk; 1237 snps,dis_enblslpm_quirk; 1238 snps,dis-u1-entry-quirk; 1239 snps,dis-u2-entry-quirk; 1240 maximum-speed = "high-speed"; 1241 dr_mode = "peripheral"; 1242 }; 1243 }; 1244 1245 sram@4690000 { 1246 compatible = "qcom,rpm-stats"; 1247 reg = <0x04690000 0x10000>; 1248 }; 1249 1250 mdss: display-subsystem@5e00000 { 1251 compatible = "qcom,sm6125-mdss"; 1252 reg = <0x05e00000 0x1000>; 1253 reg-names = "mdss"; 1254 1255 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1256 interrupt-controller; 1257 #interrupt-cells = <1>; 1258 1259 clocks = <&gcc GCC_DISP_AHB_CLK>, 1260 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1261 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1262 clock-names = "iface", 1263 "ahb", 1264 "core"; 1265 1266 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1267 1268 power-domains = <&dispcc MDSS_GDSC>; 1269 1270 iommus = <&apps_smmu 0x400 0x0>; 1271 1272 #address-cells = <1>; 1273 #size-cells = <1>; 1274 ranges; 1275 1276 status = "disabled"; 1277 1278 mdss_mdp: display-controller@5e01000 { 1279 compatible = "qcom,sm6125-dpu"; 1280 reg = <0x05e01000 0x83208>, 1281 <0x05eb0000 0x3000>; 1282 reg-names = "mdp", "vbif"; 1283 1284 interrupt-parent = <&mdss>; 1285 interrupts = <0>; 1286 1287 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1288 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1289 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1290 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1291 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1292 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 1293 <&gcc GCC_DISP_THROTTLE_CORE_CLK>; 1294 clock-names = "bus", 1295 "iface", 1296 "rot", 1297 "lut", 1298 "core", 1299 "vsync", 1300 "throttle"; 1301 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1302 assigned-clock-rates = <19200000>; 1303 1304 operating-points-v2 = <&mdp_opp_table>; 1305 power-domains = <&rpmpd RPMPD_VDDCX>; 1306 1307 ports { 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 1311 port@0 { 1312 reg = <0>; 1313 dpu_intf1_out: endpoint { 1314 remote-endpoint = <&mdss_dsi0_in>; 1315 }; 1316 }; 1317 }; 1318 1319 mdp_opp_table: opp-table { 1320 compatible = "operating-points-v2"; 1321 1322 opp-192000000 { 1323 opp-hz = /bits/ 64 <192000000>; 1324 required-opps = <&rpmpd_opp_low_svs>; 1325 }; 1326 1327 opp-256000000 { 1328 opp-hz = /bits/ 64 <256000000>; 1329 required-opps = <&rpmpd_opp_svs>; 1330 }; 1331 1332 opp-307200000 { 1333 opp-hz = /bits/ 64 <307200000>; 1334 required-opps = <&rpmpd_opp_svs_plus>; 1335 }; 1336 1337 opp-384000000 { 1338 opp-hz = /bits/ 64 <384000000>; 1339 required-opps = <&rpmpd_opp_nom>; 1340 }; 1341 1342 opp-400000000 { 1343 opp-hz = /bits/ 64 <400000000>; 1344 required-opps = <&rpmpd_opp_turbo>; 1345 }; 1346 }; 1347 }; 1348 1349 mdss_dsi0: dsi@5e94000 { 1350 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1351 reg = <0x05e94000 0x400>; 1352 reg-names = "dsi_ctrl"; 1353 1354 interrupt-parent = <&mdss>; 1355 interrupts = <4>; 1356 1357 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1358 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1359 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1360 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1361 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1362 <&gcc GCC_DISP_HF_AXI_CLK>; 1363 clock-names = "byte", 1364 "byte_intf", 1365 "pixel", 1366 "core", 1367 "iface", 1368 "bus"; 1369 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1370 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1371 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1372 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1373 1374 operating-points-v2 = <&dsi_opp_table>; 1375 power-domains = <&rpmpd RPMPD_VDDCX>; 1376 1377 phys = <&mdss_dsi0_phy>; 1378 phy-names = "dsi"; 1379 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 1383 status = "disabled"; 1384 1385 ports { 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 1389 port@0 { 1390 reg = <0>; 1391 mdss_dsi0_in: endpoint { 1392 remote-endpoint = <&dpu_intf1_out>; 1393 }; 1394 }; 1395 1396 port@1 { 1397 reg = <1>; 1398 mdss_dsi0_out: endpoint { 1399 }; 1400 }; 1401 }; 1402 1403 dsi_opp_table: opp-table { 1404 compatible = "operating-points-v2"; 1405 1406 opp-164000000 { 1407 opp-hz = /bits/ 64 <164000000>; 1408 required-opps = <&rpmpd_opp_low_svs>; 1409 }; 1410 1411 opp-187500000 { 1412 opp-hz = /bits/ 64 <187500000>; 1413 required-opps = <&rpmpd_opp_svs>; 1414 }; 1415 }; 1416 }; 1417 1418 mdss_dsi0_phy: phy@5e94400 { 1419 compatible = "qcom,sm6125-dsi-phy-14nm"; 1420 reg = <0x05e94400 0x100>, 1421 <0x05e94500 0x300>, 1422 <0x05e94800 0x188>; 1423 reg-names = "dsi_phy", 1424 "dsi_phy_lane", 1425 "dsi_pll"; 1426 1427 #clock-cells = <1>; 1428 #phy-cells = <0>; 1429 1430 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1431 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1432 clock-names = "iface", 1433 "ref"; 1434 1435 required-opps = <&rpmpd_opp_nom>; 1436 power-domains = <&rpmpd RPMPD_VDDMX>; 1437 1438 status = "disabled"; 1439 }; 1440 }; 1441 1442 dispcc: clock-controller@5f00000 { 1443 compatible = "qcom,sm6125-dispcc"; 1444 reg = <0x05f00000 0x20000>; 1445 1446 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1447 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1448 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1449 <0>, 1450 <0>, 1451 <0>, 1452 <&gcc GCC_DISP_AHB_CLK>, 1453 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1454 clock-names = "bi_tcxo", 1455 "dsi0_phy_pll_out_byteclk", 1456 "dsi0_phy_pll_out_dsiclk", 1457 "dsi1_phy_pll_out_dsiclk", 1458 "dp_phy_pll_link_clk", 1459 "dp_phy_pll_vco_div_clk", 1460 "cfg_ahb_clk", 1461 "gcc_disp_gpll0_div_clk_src"; 1462 1463 required-opps = <&rpmpd_opp_ret>; 1464 power-domains = <&rpmpd RPMPD_VDDCX>; 1465 1466 #clock-cells = <1>; 1467 #reset-cells = <1>; 1468 #power-domain-cells = <1>; 1469 }; 1470 1471 apps_smmu: iommu@c600000 { 1472 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1473 reg = <0x0c600000 0x80000>; 1474 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1539 1540 #global-interrupts = <1>; 1541 #iommu-cells = <2>; 1542 }; 1543 1544 apcs_glb: mailbox@f111000 { 1545 compatible = "qcom,sm6125-apcs-hmss-global", 1546 "qcom,msm8994-apcs-kpss-global"; 1547 reg = <0x0f111000 0x1000>; 1548 1549 #mbox-cells = <1>; 1550 }; 1551 1552 timer@f120000 { 1553 compatible = "arm,armv7-timer-mem"; 1554 #address-cells = <1>; 1555 #size-cells = <1>; 1556 ranges; 1557 reg = <0x0f120000 0x1000>; 1558 clock-frequency = <19200000>; 1559 1560 frame@f121000 { 1561 frame-number = <0>; 1562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1564 reg = <0x0f121000 0x1000>, 1565 <0x0f122000 0x1000>; 1566 }; 1567 1568 frame@f123000 { 1569 frame-number = <1>; 1570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1571 reg = <0x0f123000 0x1000>; 1572 status = "disabled"; 1573 }; 1574 1575 frame@f124000 { 1576 frame-number = <2>; 1577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1578 reg = <0x0f124000 0x1000>; 1579 status = "disabled"; 1580 }; 1581 1582 frame@f125000 { 1583 frame-number = <3>; 1584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1585 reg = <0x0f125000 0x1000>; 1586 status = "disabled"; 1587 }; 1588 1589 frame@f126000 { 1590 frame-number = <4>; 1591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1592 reg = <0x0f126000 0x1000>; 1593 status = "disabled"; 1594 }; 1595 1596 frame@f127000 { 1597 frame-number = <5>; 1598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1599 reg = <0x0f127000 0x1000>; 1600 status = "disabled"; 1601 }; 1602 1603 frame@f128000 { 1604 frame-number = <6>; 1605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1606 reg = <0x0f128000 0x1000>; 1607 status = "disabled"; 1608 }; 1609 }; 1610 1611 intc: interrupt-controller@f200000 { 1612 compatible = "arm,gic-v3"; 1613 reg = <0x0f200000 0x20000>, 1614 <0x0f300000 0x100000>; 1615 #interrupt-cells = <3>; 1616 interrupt-controller; 1617 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1618 }; 1619 }; 1620 1621 timer { 1622 compatible = "arm,armv8-timer"; 1623 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 1624 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 1625 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 1626 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 1627 clock-frequency = <19200000>; 1628 }; 1629}; 1630