1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/cputypes.h>
68 #include <x86/isa/icu.h>
69 #include <x86/vmware.h>
70
71 #ifdef XENHVM
72 #include <xen/xen-os.h>
73 #endif
74
75 #ifdef __i386__
76 #define IDENTBLUE_CYRIX486 0
77 #define IDENTBLUE_IBMCPU 1
78 #define IDENTBLUE_CYRIXM2 2
79
80 static void identifycyrix(void);
81 static void print_transmeta_info(void);
82 #endif
83 static u_int find_cpu_vendor_id(void);
84 static void print_AMD_info(void);
85 static void print_INTEL_info(void);
86 static void print_INTEL_TLB(u_int data);
87 static void print_hypervisor_info(void);
88 static void print_svm_info(void);
89 static void print_via_padlock_info(void);
90 static void print_vmx_info(void);
91
92 #ifdef __i386__
93 int cpu; /* Are we 386, 386sx, 486, etc? */
94 int cpu_class;
95 #endif
96 u_int cpu_feature; /* Feature flags */
97 u_int cpu_feature2; /* Feature flags */
98 u_int amd_feature; /* AMD feature flags */
99 u_int amd_feature2; /* AMD feature flags */
100 u_int amd_rascap; /* AMD RAS capabilities */
101 u_int amd_pminfo; /* AMD advanced power management info */
102 u_int amd_extended_feature_extensions;
103 u_int via_feature_rng; /* VIA RNG features */
104 u_int via_feature_xcrypt; /* VIA ACE features */
105 u_int cpu_high; /* Highest arg to CPUID */
106 u_int cpu_exthigh; /* Highest arg to extended CPUID */
107 u_int cpu_id; /* Stepping ID */
108 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
109 u_int cpu_procinfo2; /* Multicore info */
110 u_int cpu_procinfo3;
111 char cpu_vendor[20]; /* CPU Origin code */
112 u_int cpu_vendor_id; /* CPU vendor ID */
113 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
114 u_int cpu_clflush_line_size = 32;
115 /* leaf 7 %ecx = 0 */
116 u_int cpu_stdext_feature; /* %ebx */
117 u_int cpu_stdext_feature2; /* %ecx */
118 u_int cpu_stdext_feature3; /* %edx */
119 /* leaf 7 %ecx = 1 */
120 u_int cpu_stdext_feature4; /* %eax */
121 uint64_t cpu_ia32_arch_caps;
122 u_int cpu_max_ext_state_size;
123 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
124 u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */
125 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
126 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
127 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
128 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
129 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
130 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
131 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
132 const char machine[] = MACHINE;
133
134 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
135 &via_feature_rng, 0,
136 "VIA RNG feature available in CPU");
137 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
138 &via_feature_xcrypt, 0,
139 "VIA xcrypt feature available in CPU");
140
141 #ifdef __amd64__
142 #ifdef SCTL_MASK32
143 extern int adaptive_machine_arch;
144 #endif
145
146 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)147 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
148 {
149 #ifdef SCTL_MASK32
150 static const char machine32[] = "i386";
151 #endif
152 int error;
153
154 #ifdef SCTL_MASK32
155 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
156 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
157 else
158 #endif
159 error = SYSCTL_OUT(req, machine, sizeof(machine));
160 return (error);
161
162 }
163 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
164 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
165 #else
166 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
167 machine, "Machine class");
168 #endif
169
170 char cpu_model[128];
171 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
172 cpu_model, 0, "Machine model");
173
174 static int hw_clockrate;
175 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
176 &hw_clockrate, 0, "CPU instruction clock rate");
177
178 u_int hv_base;
179 u_int hv_high;
180 char hv_vendor[16];
181 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
182 0, "Hypervisor vendor");
183
184 static eventhandler_tag tsc_post_tag;
185
186 static char cpu_brand[48];
187
188 #ifdef __i386__
189 #define MAX_BRAND_INDEX 8
190
191 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
192 NULL, /* No brand */
193 "Intel Celeron",
194 "Intel Pentium III",
195 "Intel Pentium III Xeon",
196 NULL,
197 NULL,
198 NULL,
199 NULL,
200 "Intel Pentium 4"
201 };
202
203 static struct {
204 char *cpu_name;
205 int cpu_class;
206 } cpus[] = {
207 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
208 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
209 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
210 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
211 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
212 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
213 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
214 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
215 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
216 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
217 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
218 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
219 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
220 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
221 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
222 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
223 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
224 };
225 #endif
226
227 static struct {
228 char *vendor;
229 u_int vendor_id;
230 } cpu_vendors[] = {
231 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
232 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
233 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
234 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
235 #ifdef __i386__
236 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
237 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
238 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
239 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
240 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
241 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
242 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
243 #if 0
244 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
245 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
246 #endif
247 #endif
248 };
249
250 void
printcpuinfo(void)251 printcpuinfo(void)
252 {
253 u_int regs[4], i;
254 char *brand;
255
256 printf("CPU: ");
257 #ifdef __i386__
258 cpu_class = cpus[cpu].cpu_class;
259 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
260 #else
261 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
262 #endif
263
264 /* Check for extended CPUID information and a processor name. */
265 if (cpu_exthigh >= 0x80000004) {
266 brand = cpu_brand;
267 for (i = 0x80000002; i < 0x80000005; i++) {
268 do_cpuid(i, regs);
269 memcpy(brand, regs, sizeof(regs));
270 brand += sizeof(regs);
271 }
272 }
273
274 switch (cpu_vendor_id) {
275 case CPU_VENDOR_INTEL:
276 #ifdef __i386__
277 if ((cpu_id & 0xf00) > 0x300) {
278 u_int brand_index;
279
280 cpu_model[0] = '\0';
281
282 switch (cpu_id & 0x3000) {
283 case 0x1000:
284 strcpy(cpu_model, "Overdrive ");
285 break;
286 case 0x2000:
287 strcpy(cpu_model, "Dual ");
288 break;
289 }
290
291 switch (cpu_id & 0xf00) {
292 case 0x400:
293 strcat(cpu_model, "i486 ");
294 /* Check the particular flavor of 486 */
295 switch (cpu_id & 0xf0) {
296 case 0x00:
297 case 0x10:
298 strcat(cpu_model, "DX");
299 break;
300 case 0x20:
301 strcat(cpu_model, "SX");
302 break;
303 case 0x30:
304 strcat(cpu_model, "DX2");
305 break;
306 case 0x40:
307 strcat(cpu_model, "SL");
308 break;
309 case 0x50:
310 strcat(cpu_model, "SX2");
311 break;
312 case 0x70:
313 strcat(cpu_model,
314 "DX2 Write-Back Enhanced");
315 break;
316 case 0x80:
317 strcat(cpu_model, "DX4");
318 break;
319 }
320 break;
321 case 0x500:
322 /* Check the particular flavor of 586 */
323 strcat(cpu_model, "Pentium");
324 switch (cpu_id & 0xf0) {
325 case 0x00:
326 strcat(cpu_model, " A-step");
327 break;
328 case 0x10:
329 strcat(cpu_model, "/P5");
330 break;
331 case 0x20:
332 strcat(cpu_model, "/P54C");
333 break;
334 case 0x30:
335 strcat(cpu_model, "/P24T");
336 break;
337 case 0x40:
338 strcat(cpu_model, "/P55C");
339 break;
340 case 0x70:
341 strcat(cpu_model, "/P54C");
342 break;
343 case 0x80:
344 strcat(cpu_model, "/P55C (quarter-micron)");
345 break;
346 default:
347 /* nothing */
348 break;
349 }
350 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
351 /*
352 * XXX - If/when Intel fixes the bug, this
353 * should also check the version of the
354 * CPU, not just that it's a Pentium.
355 */
356 has_f00f_bug = 1;
357 #endif
358 break;
359 case 0x600:
360 /* Check the particular flavor of 686 */
361 switch (cpu_id & 0xf0) {
362 case 0x00:
363 strcat(cpu_model, "Pentium Pro A-step");
364 break;
365 case 0x10:
366 strcat(cpu_model, "Pentium Pro");
367 break;
368 case 0x30:
369 case 0x50:
370 case 0x60:
371 strcat(cpu_model,
372 "Pentium II/Pentium II Xeon/Celeron");
373 cpu = CPU_PII;
374 break;
375 case 0x70:
376 case 0x80:
377 case 0xa0:
378 case 0xb0:
379 strcat(cpu_model,
380 "Pentium III/Pentium III Xeon/Celeron");
381 cpu = CPU_PIII;
382 break;
383 default:
384 strcat(cpu_model, "Unknown 80686");
385 break;
386 }
387 break;
388 case 0xf00:
389 strcat(cpu_model, "Pentium 4");
390 cpu = CPU_P4;
391 break;
392 default:
393 strcat(cpu_model, "unknown");
394 break;
395 }
396
397 /*
398 * If we didn't get a brand name from the extended
399 * CPUID, try to look it up in the brand table.
400 */
401 if (cpu_high > 0 && *cpu_brand == '\0') {
402 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
403 if (brand_index <= MAX_BRAND_INDEX &&
404 cpu_brandtable[brand_index] != NULL)
405 strcpy(cpu_brand,
406 cpu_brandtable[brand_index]);
407 }
408 }
409 #else
410 /* Please make up your mind folks! */
411 strcat(cpu_model, "EM64T");
412 #endif
413 break;
414 case CPU_VENDOR_AMD:
415 /*
416 * Values taken from AMD Processor Recognition
417 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
418 * (also describes ``Features'' encodings.
419 */
420 strcpy(cpu_model, "AMD ");
421 #ifdef __i386__
422 switch (cpu_id & 0xFF0) {
423 case 0x410:
424 strcat(cpu_model, "Standard Am486DX");
425 break;
426 case 0x430:
427 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
428 break;
429 case 0x470:
430 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
431 break;
432 case 0x480:
433 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
434 break;
435 case 0x490:
436 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
437 break;
438 case 0x4E0:
439 strcat(cpu_model, "Am5x86 Write-Through");
440 break;
441 case 0x4F0:
442 strcat(cpu_model, "Am5x86 Write-Back");
443 break;
444 case 0x500:
445 strcat(cpu_model, "K5 model 0");
446 break;
447 case 0x510:
448 strcat(cpu_model, "K5 model 1");
449 break;
450 case 0x520:
451 strcat(cpu_model, "K5 PR166 (model 2)");
452 break;
453 case 0x530:
454 strcat(cpu_model, "K5 PR200 (model 3)");
455 break;
456 case 0x560:
457 strcat(cpu_model, "K6");
458 break;
459 case 0x570:
460 strcat(cpu_model, "K6 266 (model 1)");
461 break;
462 case 0x580:
463 strcat(cpu_model, "K6-2");
464 break;
465 case 0x590:
466 strcat(cpu_model, "K6-III");
467 break;
468 case 0x5a0:
469 strcat(cpu_model, "Geode LX");
470 break;
471 default:
472 strcat(cpu_model, "Unknown");
473 break;
474 }
475 #else
476 if ((cpu_id & 0xf00) == 0xf00)
477 strcat(cpu_model, "AMD64 Processor");
478 else
479 strcat(cpu_model, "Unknown");
480 #endif
481 break;
482 #ifdef __i386__
483 case CPU_VENDOR_CYRIX:
484 strcpy(cpu_model, "Cyrix ");
485 switch (cpu_id & 0xff0) {
486 case 0x440:
487 strcat(cpu_model, "MediaGX");
488 break;
489 case 0x520:
490 strcat(cpu_model, "6x86");
491 break;
492 case 0x540:
493 cpu_class = CPUCLASS_586;
494 strcat(cpu_model, "GXm");
495 break;
496 case 0x600:
497 strcat(cpu_model, "6x86MX");
498 break;
499 default:
500 /*
501 * Even though CPU supports the cpuid
502 * instruction, it can be disabled.
503 * Therefore, this routine supports all Cyrix
504 * CPUs.
505 */
506 switch (cyrix_did & 0xf0) {
507 case 0x00:
508 switch (cyrix_did & 0x0f) {
509 case 0x00:
510 strcat(cpu_model, "486SLC");
511 break;
512 case 0x01:
513 strcat(cpu_model, "486DLC");
514 break;
515 case 0x02:
516 strcat(cpu_model, "486SLC2");
517 break;
518 case 0x03:
519 strcat(cpu_model, "486DLC2");
520 break;
521 case 0x04:
522 strcat(cpu_model, "486SRx");
523 break;
524 case 0x05:
525 strcat(cpu_model, "486DRx");
526 break;
527 case 0x06:
528 strcat(cpu_model, "486SRx2");
529 break;
530 case 0x07:
531 strcat(cpu_model, "486DRx2");
532 break;
533 case 0x08:
534 strcat(cpu_model, "486SRu");
535 break;
536 case 0x09:
537 strcat(cpu_model, "486DRu");
538 break;
539 case 0x0a:
540 strcat(cpu_model, "486SRu2");
541 break;
542 case 0x0b:
543 strcat(cpu_model, "486DRu2");
544 break;
545 default:
546 strcat(cpu_model, "Unknown");
547 break;
548 }
549 break;
550 case 0x10:
551 switch (cyrix_did & 0x0f) {
552 case 0x00:
553 strcat(cpu_model, "486S");
554 break;
555 case 0x01:
556 strcat(cpu_model, "486S2");
557 break;
558 case 0x02:
559 strcat(cpu_model, "486Se");
560 break;
561 case 0x03:
562 strcat(cpu_model, "486S2e");
563 break;
564 case 0x0a:
565 strcat(cpu_model, "486DX");
566 break;
567 case 0x0b:
568 strcat(cpu_model, "486DX2");
569 break;
570 case 0x0f:
571 strcat(cpu_model, "486DX4");
572 break;
573 default:
574 strcat(cpu_model, "Unknown");
575 break;
576 }
577 break;
578 case 0x20:
579 if ((cyrix_did & 0x0f) < 8)
580 strcat(cpu_model, "6x86"); /* Where did you get it? */
581 else
582 strcat(cpu_model, "5x86");
583 break;
584 case 0x30:
585 strcat(cpu_model, "6x86");
586 break;
587 case 0x40:
588 if ((cyrix_did & 0xf000) == 0x3000) {
589 cpu_class = CPUCLASS_586;
590 strcat(cpu_model, "GXm");
591 } else
592 strcat(cpu_model, "MediaGX");
593 break;
594 case 0x50:
595 strcat(cpu_model, "6x86MX");
596 break;
597 case 0xf0:
598 switch (cyrix_did & 0x0f) {
599 case 0x0d:
600 strcat(cpu_model, "Overdrive CPU");
601 break;
602 case 0x0e:
603 strcpy(cpu_model, "Texas Instruments 486SXL");
604 break;
605 case 0x0f:
606 strcat(cpu_model, "486SLC/DLC");
607 break;
608 default:
609 strcat(cpu_model, "Unknown");
610 break;
611 }
612 break;
613 default:
614 strcat(cpu_model, "Unknown");
615 break;
616 }
617 break;
618 }
619 break;
620 case CPU_VENDOR_RISE:
621 strcpy(cpu_model, "Rise ");
622 switch (cpu_id & 0xff0) {
623 case 0x500: /* 6401 and 6441 (Kirin) */
624 case 0x520: /* 6510 (Lynx) */
625 strcat(cpu_model, "mP6");
626 break;
627 default:
628 strcat(cpu_model, "Unknown");
629 }
630 break;
631 #endif
632 case CPU_VENDOR_CENTAUR:
633 #ifdef __i386__
634 switch (cpu_id & 0xff0) {
635 case 0x540:
636 strcpy(cpu_model, "IDT WinChip C6");
637 break;
638 case 0x580:
639 strcpy(cpu_model, "IDT WinChip 2");
640 break;
641 case 0x590:
642 strcpy(cpu_model, "IDT WinChip 3");
643 break;
644 case 0x660:
645 strcpy(cpu_model, "VIA C3 Samuel");
646 break;
647 case 0x670:
648 if (cpu_id & 0x8)
649 strcpy(cpu_model, "VIA C3 Ezra");
650 else
651 strcpy(cpu_model, "VIA C3 Samuel 2");
652 break;
653 case 0x680:
654 strcpy(cpu_model, "VIA C3 Ezra-T");
655 break;
656 case 0x690:
657 strcpy(cpu_model, "VIA C3 Nehemiah");
658 break;
659 case 0x6a0:
660 case 0x6d0:
661 strcpy(cpu_model, "VIA C7 Esther");
662 break;
663 case 0x6f0:
664 strcpy(cpu_model, "VIA Nano");
665 break;
666 default:
667 strcpy(cpu_model, "VIA/IDT Unknown");
668 }
669 #else
670 strcpy(cpu_model, "VIA ");
671 if ((cpu_id & 0xff0) == 0x6f0)
672 strcat(cpu_model, "Nano Processor");
673 else
674 strcat(cpu_model, "Unknown");
675 #endif
676 break;
677 #ifdef __i386__
678 case CPU_VENDOR_IBM:
679 strcpy(cpu_model, "Blue Lightning CPU");
680 break;
681 case CPU_VENDOR_NSC:
682 switch (cpu_id & 0xff0) {
683 case 0x540:
684 strcpy(cpu_model, "Geode SC1100");
685 cpu = CPU_GEODE1100;
686 break;
687 default:
688 strcpy(cpu_model, "Geode/NSC unknown");
689 break;
690 }
691 break;
692 #endif
693 case CPU_VENDOR_HYGON:
694 strcpy(cpu_model, "Hygon ");
695 #ifdef __i386__
696 strcat(cpu_model, "Unknown");
697 #else
698 if ((cpu_id & 0xf00) == 0xf00)
699 strcat(cpu_model, "AMD64 Processor");
700 else
701 strcat(cpu_model, "Unknown");
702 #endif
703 break;
704
705 default:
706 strcat(cpu_model, "Unknown");
707 break;
708 }
709
710 /*
711 * Replace cpu_model with cpu_brand minus leading spaces if
712 * we have one.
713 */
714 brand = cpu_brand;
715 while (*brand == ' ')
716 ++brand;
717 if (*brand != '\0')
718 strcpy(cpu_model, brand);
719
720 printf("%s (", cpu_model);
721 if (tsc_freq != 0) {
722 hw_clockrate = (tsc_freq + 5000) / 1000000;
723 printf("%jd.%02d-MHz ",
724 (intmax_t)(tsc_freq + 4999) / 1000000,
725 (u_int)((tsc_freq + 4999) / 10000) % 100);
726 }
727 #ifdef __i386__
728 switch(cpu_class) {
729 case CPUCLASS_286:
730 printf("286");
731 break;
732 case CPUCLASS_386:
733 printf("386");
734 break;
735 #if defined(I486_CPU)
736 case CPUCLASS_486:
737 printf("486");
738 break;
739 #endif
740 #if defined(I586_CPU)
741 case CPUCLASS_586:
742 printf("586");
743 break;
744 #endif
745 #if defined(I686_CPU)
746 case CPUCLASS_686:
747 printf("686");
748 break;
749 #endif
750 default:
751 printf("Unknown"); /* will panic below... */
752 }
753 #else
754 printf("K8");
755 #endif
756 printf("-class CPU)\n");
757 if (*cpu_vendor)
758 printf(" Origin=\"%s\"", cpu_vendor);
759 if (cpu_id)
760 printf(" Id=0x%x", cpu_id);
761
762 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
763 cpu_vendor_id == CPU_VENDOR_AMD ||
764 cpu_vendor_id == CPU_VENDOR_HYGON ||
765 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
766 #ifdef __i386__
767 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
768 cpu_vendor_id == CPU_VENDOR_RISE ||
769 cpu_vendor_id == CPU_VENDOR_NSC ||
770 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
771 #endif
772 0) {
773 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
774 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
775 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
776 #ifdef __i386__
777 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
778 printf("\n DIR=0x%04x", cyrix_did);
779 #endif
780
781 /*
782 * AMD CPUID Specification
783 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
784 *
785 * Intel Processor Identification and CPUID Instruction
786 * http://www.intel.com/assets/pdf/appnote/241618.pdf
787 */
788 if (cpu_high > 0) {
789 /*
790 * Here we should probably set up flags indicating
791 * whether or not various features are available.
792 * The interesting ones are probably VME, PSE, PAE,
793 * and PGE. The code already assumes without bothering
794 * to check that all CPUs >= Pentium have a TSC and
795 * MSRs.
796 */
797 printf("\n Features=0x%b", cpu_feature,
798 "\020"
799 "\001FPU" /* Integral FPU */
800 "\002VME" /* Extended VM86 mode support */
801 "\003DE" /* Debugging Extensions (CR4.DE) */
802 "\004PSE" /* 4MByte page tables */
803 "\005TSC" /* Timestamp counter */
804 "\006MSR" /* Machine specific registers */
805 "\007PAE" /* Physical address extension */
806 "\010MCE" /* Machine Check support */
807 "\011CX8" /* CMPEXCH8 instruction */
808 "\012APIC" /* SMP local APIC */
809 "\013oldMTRR" /* Previous implementation of MTRR */
810 "\014SEP" /* Fast System Call */
811 "\015MTRR" /* Memory Type Range Registers */
812 "\016PGE" /* PG_G (global bit) support */
813 "\017MCA" /* Machine Check Architecture */
814 "\020CMOV" /* CMOV instruction */
815 "\021PAT" /* Page attributes table */
816 "\022PSE36" /* 36 bit address space support */
817 "\023PN" /* Processor Serial number */
818 "\024CLFLUSH" /* Has the CLFLUSH instruction */
819 "\025<b20>"
820 "\026DTS" /* Debug Trace Store */
821 "\027ACPI" /* ACPI support */
822 "\030MMX" /* MMX instructions */
823 "\031FXSR" /* FXSAVE/FXRSTOR */
824 "\032SSE" /* Streaming SIMD Extensions */
825 "\033SSE2" /* Streaming SIMD Extensions #2 */
826 "\034SS" /* Self snoop */
827 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
828 "\036TM" /* Thermal Monitor clock slowdown */
829 "\037IA64" /* CPU can execute IA64 instructions */
830 "\040PBE" /* Pending Break Enable */
831 );
832
833 if (cpu_feature2 != 0) {
834 printf("\n Features2=0x%b", cpu_feature2,
835 "\020"
836 "\001SSE3" /* SSE3 */
837 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
838 "\003DTES64" /* 64-bit Debug Trace */
839 "\004MON" /* MONITOR/MWAIT Instructions */
840 "\005DS_CPL" /* CPL Qualified Debug Store */
841 "\006VMX" /* Virtual Machine Extensions */
842 "\007SMX" /* Safer Mode Extensions */
843 "\010EST" /* Enhanced SpeedStep */
844 "\011TM2" /* Thermal Monitor 2 */
845 "\012SSSE3" /* SSSE3 */
846 "\013CNXT-ID" /* L1 context ID available */
847 "\014SDBG" /* IA32 silicon debug */
848 "\015FMA" /* Fused Multiply Add */
849 "\016CX16" /* CMPXCHG16B Instruction */
850 "\017xTPR" /* Send Task Priority Messages*/
851 "\020PDCM" /* Perf/Debug Capability MSR */
852 "\021<b16>"
853 "\022PCID" /* Process-context Identifiers*/
854 "\023DCA" /* Direct Cache Access */
855 "\024SSE4.1" /* SSE 4.1 */
856 "\025SSE4.2" /* SSE 4.2 */
857 "\026x2APIC" /* xAPIC Extensions */
858 "\027MOVBE" /* MOVBE Instruction */
859 "\030POPCNT" /* POPCNT Instruction */
860 "\031TSCDLT" /* TSC-Deadline Timer */
861 "\032AESNI" /* AES Crypto */
862 "\033XSAVE" /* XSAVE/XRSTOR States */
863 "\034OSXSAVE" /* OS-Enabled State Management*/
864 "\035AVX" /* Advanced Vector Extensions */
865 "\036F16C" /* Half-precision conversions */
866 "\037RDRAND" /* RDRAND Instruction */
867 "\040HV" /* Hypervisor */
868 );
869 }
870
871 if (amd_feature != 0) {
872 printf("\n AMD Features=0x%b", amd_feature,
873 "\020" /* in hex */
874 "\001<s0>" /* Same */
875 "\002<s1>" /* Same */
876 "\003<s2>" /* Same */
877 "\004<s3>" /* Same */
878 "\005<s4>" /* Same */
879 "\006<s5>" /* Same */
880 "\007<s6>" /* Same */
881 "\010<s7>" /* Same */
882 "\011<s8>" /* Same */
883 "\012<s9>" /* Same */
884 "\013<b10>" /* Undefined */
885 "\014SYSCALL" /* Have SYSCALL/SYSRET */
886 "\015<s12>" /* Same */
887 "\016<s13>" /* Same */
888 "\017<s14>" /* Same */
889 "\020<s15>" /* Same */
890 "\021<s16>" /* Same */
891 "\022<s17>" /* Same */
892 "\023<b18>" /* Reserved, unknown */
893 "\024MP" /* Multiprocessor Capable */
894 "\025NX" /* Has EFER.NXE, NX */
895 "\026<b21>" /* Undefined */
896 "\027MMX+" /* AMD MMX Extensions */
897 "\030<s23>" /* Same */
898 "\031<s24>" /* Same */
899 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
900 "\033Page1GB" /* 1-GB large page support */
901 "\034RDTSCP" /* RDTSCP */
902 "\035<b28>" /* Undefined */
903 "\036LM" /* 64 bit long mode */
904 "\0373DNow!+" /* AMD 3DNow! Extensions */
905 "\0403DNow!" /* AMD 3DNow! */
906 );
907 }
908
909 if (amd_feature2 != 0) {
910 printf("\n AMD Features2=0x%b", amd_feature2,
911 "\020"
912 "\001LAHF" /* LAHF/SAHF in long mode */
913 "\002CMP" /* CMP legacy */
914 "\003SVM" /* Secure Virtual Mode */
915 "\004ExtAPIC" /* Extended APIC register */
916 "\005CR8" /* CR8 in legacy mode */
917 "\006ABM" /* LZCNT instruction */
918 "\007SSE4A" /* SSE4A */
919 "\010MAS" /* Misaligned SSE mode */
920 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
921 "\012OSVW" /* OS visible workaround */
922 "\013IBS" /* Instruction based sampling */
923 "\014XOP" /* XOP extended instructions */
924 "\015SKINIT" /* SKINIT/STGI */
925 "\016WDT" /* Watchdog timer */
926 "\017<b14>"
927 "\020LWP" /* Lightweight Profiling */
928 "\021FMA4" /* 4-operand FMA instructions */
929 "\022TCE" /* Translation Cache Extension */
930 "\023<b18>"
931 "\024NodeId" /* NodeId MSR support */
932 "\025<b20>"
933 "\026TBM" /* Trailing Bit Manipulation */
934 "\027Topology" /* Topology Extensions */
935 "\030PCXC" /* Core perf count */
936 "\031PNXC" /* NB perf count */
937 "\032<b25>"
938 "\033DBE" /* Data Breakpoint extension */
939 "\034PTSC" /* Performance TSC */
940 "\035PL2I" /* L2I perf count */
941 "\036MWAITX" /* MONITORX/MWAITX instructions */
942 "\037ADMSKX" /* Address mask extension */
943 "\040<b31>"
944 );
945 }
946
947 if (cpu_stdext_feature != 0) {
948 printf("\n Structured Extended Features=0x%b",
949 cpu_stdext_feature,
950 "\020"
951 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
952 "\001FSGSBASE"
953 "\002TSCADJ"
954 "\003SGX"
955 /* Bit Manipulation Instructions */
956 "\004BMI1"
957 /* Hardware Lock Elision */
958 "\005HLE"
959 /* Advanced Vector Instructions 2 */
960 "\006AVX2"
961 /* FDP_EXCPTN_ONLY */
962 "\007FDPEXC"
963 /* Supervisor Mode Execution Prot. */
964 "\010SMEP"
965 /* Bit Manipulation Instructions */
966 "\011BMI2"
967 "\012ERMS"
968 /* Invalidate Processor Context ID */
969 "\013INVPCID"
970 /* Restricted Transactional Memory */
971 "\014RTM"
972 "\015PQM"
973 "\016NFPUSG"
974 /* Intel Memory Protection Extensions */
975 "\017MPX"
976 "\020PQE"
977 /* AVX512 Foundation */
978 "\021AVX512F"
979 "\022AVX512DQ"
980 /* Enhanced NRBG */
981 "\023RDSEED"
982 /* ADCX + ADOX */
983 "\024ADX"
984 /* Supervisor Mode Access Prevention */
985 "\025SMAP"
986 "\026AVX512IFMA"
987 /* Formerly PCOMMIT */
988 "\027<b22>"
989 "\030CLFLUSHOPT"
990 "\031CLWB"
991 "\032PROCTRACE"
992 "\033AVX512PF"
993 "\034AVX512ER"
994 "\035AVX512CD"
995 "\036SHA"
996 "\037AVX512BW"
997 "\040AVX512VL"
998 );
999 }
1000
1001 if (cpu_stdext_feature2 != 0) {
1002 printf("\n Structured Extended Features2=0x%b",
1003 cpu_stdext_feature2,
1004 "\020"
1005 "\001PREFETCHWT1"
1006 "\002AVX512VBMI"
1007 "\003UMIP"
1008 "\004PKU"
1009 "\005OSPKE"
1010 "\006WAITPKG"
1011 "\007AVX512VBMI2"
1012 "\011GFNI"
1013 "\012VAES"
1014 "\013VPCLMULQDQ"
1015 "\014AVX512VNNI"
1016 "\015AVX512BITALG"
1017 "\016TME"
1018 "\017AVX512VPOPCNTDQ"
1019 "\021LA57"
1020 "\027RDPID"
1021 "\032CLDEMOTE"
1022 "\034MOVDIRI"
1023 "\035MOVDIR64B"
1024 "\036ENQCMD"
1025 "\037SGXLC"
1026 );
1027 }
1028
1029 if (cpu_stdext_feature3 != 0) {
1030 printf("\n Structured Extended Features3=0x%b",
1031 cpu_stdext_feature3,
1032 "\020"
1033 "\003AVX512_4VNNIW"
1034 "\004AVX512_4FMAPS"
1035 "\005FSRM"
1036 "\011AVX512VP2INTERSECT"
1037 "\012MCUOPT"
1038 "\013MD_CLEAR"
1039 "\016TSXFA"
1040 "\023PCONFIG"
1041 "\025IBT"
1042 "\033IBPB"
1043 "\034STIBP"
1044 "\035L1DFL"
1045 "\036ARCH_CAP"
1046 "\037CORE_CAP"
1047 "\040SSBD"
1048 );
1049 }
1050
1051 if (cpu_stdext_feature4 != 0) {
1052 printf("\n Structured Extended Features4=0x%b",
1053 cpu_stdext_feature4,
1054 "\020"
1055 "\007LASS"
1056 "\022FRED"
1057 "\023LKGS"
1058 "\024WRMSRNS"
1059 "\025NMISRC"
1060 "\033LAM"
1061 );
1062 }
1063
1064 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1065 cpuid_count(0xd, 0x1, regs);
1066 if (regs[0] != 0) {
1067 printf("\n XSAVE Features=0x%b",
1068 regs[0],
1069 "\020"
1070 "\001XSAVEOPT"
1071 "\002XSAVEC"
1072 "\003XINUSE"
1073 "\004XSAVES");
1074 }
1075 }
1076
1077 if (cpu_ia32_arch_caps != 0) {
1078 printf("\n IA32_ARCH_CAPS=0x%b",
1079 (u_int)cpu_ia32_arch_caps,
1080 "\020"
1081 "\001RDCL_NO"
1082 "\002IBRS_ALL"
1083 "\003RSBA"
1084 "\004SKIP_L1DFL_VME"
1085 "\005SSB_NO"
1086 "\006MDS_NO"
1087 "\010TSX_CTRL"
1088 "\011TAA_NO"
1089 );
1090 }
1091
1092 if (amd_extended_feature_extensions != 0) {
1093 u_int amd_fe_masked;
1094
1095 amd_fe_masked = amd_extended_feature_extensions;
1096 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1097 amd_fe_masked &=
1098 ~(AMDFEID_IBRS_ALWAYSON |
1099 AMDFEID_PREFER_IBRS);
1100 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1101 amd_fe_masked &=
1102 ~AMDFEID_STIBP_ALWAYSON;
1103
1104 printf("\n "
1105 "AMD Extended Feature Extensions ID EBX="
1106 "0x%b", amd_fe_masked,
1107 "\020"
1108 "\001CLZERO"
1109 "\002IRPerf"
1110 "\003XSaveErPtr"
1111 "\004INVLPGB"
1112 "\005RDPRU"
1113 "\007BE"
1114 "\011MCOMMIT"
1115 "\012WBNOINVD"
1116 "\015IBPB"
1117 "\016INT_WBINVD"
1118 "\017IBRS"
1119 "\020STIBP"
1120 "\021IBRS_ALWAYSON"
1121 "\022STIBP_ALWAYSON"
1122 "\023PREFER_IBRS"
1123 "\024SAMEMODE_IBRS"
1124 "\025NOLMSLE"
1125 "\026INVLPGBNEST"
1126 "\030PPIN"
1127 "\031SSBD"
1128 "\032VIRT_SSBD"
1129 "\033SSB_NO"
1130 "\034CPPC"
1131 "\035PSFD"
1132 "\036BTC_NO"
1133 "\037IBPB_RET"
1134 );
1135 }
1136
1137 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1138 print_via_padlock_info();
1139
1140 if (cpu_feature2 & CPUID2_VMX)
1141 print_vmx_info();
1142
1143 if (amd_feature2 & AMDID2_SVM)
1144 print_svm_info();
1145
1146 if ((cpu_feature & CPUID_HTT) &&
1147 (cpu_vendor_id == CPU_VENDOR_AMD ||
1148 cpu_vendor_id == CPU_VENDOR_HYGON))
1149 cpu_feature &= ~CPUID_HTT;
1150
1151 /*
1152 * If this CPU supports P-state invariant TSC then
1153 * mention the capability.
1154 */
1155 if (tsc_is_invariant) {
1156 printf("\n TSC: P-state invariant");
1157 if (tsc_perf_stat)
1158 printf(", performance statistics");
1159 }
1160 }
1161 #ifdef __i386__
1162 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1163 printf(" DIR=0x%04x", cyrix_did);
1164 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1165 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1166 #ifndef CYRIX_CACHE_REALLY_WORKS
1167 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1168 printf("\n CPU cache: write-through mode");
1169 #endif
1170 #endif
1171 }
1172
1173 /* Avoid ugly blank lines: only print newline when we have to. */
1174 if (*cpu_vendor || cpu_id)
1175 printf("\n");
1176
1177 if (bootverbose) {
1178 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1179 cpu_vendor_id == CPU_VENDOR_HYGON)
1180 print_AMD_info();
1181 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1182 print_INTEL_info();
1183 #ifdef __i386__
1184 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1185 print_transmeta_info();
1186 #endif
1187 }
1188
1189 print_hypervisor_info();
1190 }
1191
1192 #ifdef __i386__
1193 void
panicifcpuunsupported(void)1194 panicifcpuunsupported(void)
1195 {
1196
1197 #if !defined(lint)
1198 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1199 #error This kernel is not configured for one of the supported CPUs
1200 #endif
1201 #else /* lint */
1202 #endif /* lint */
1203 /*
1204 * Now that we have told the user what they have,
1205 * let them know if that machine type isn't configured.
1206 */
1207 switch (cpu_class) {
1208 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1209 case CPUCLASS_386:
1210 #if !defined(I486_CPU)
1211 case CPUCLASS_486:
1212 #endif
1213 #if !defined(I586_CPU)
1214 case CPUCLASS_586:
1215 #endif
1216 #if !defined(I686_CPU)
1217 case CPUCLASS_686:
1218 #endif
1219 panic("CPU class not configured");
1220 default:
1221 break;
1222 }
1223 }
1224
1225 static volatile u_int trap_by_rdmsr;
1226
1227 /*
1228 * Special exception 6 handler.
1229 * The rdmsr instruction generates invalid opcodes fault on 486-class
1230 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1231 * function identblue() when this handler is called. Stacked eip should
1232 * be advanced.
1233 */
1234 inthand_t bluetrap6;
1235 __asm
1236 (" \n\
1237 .text \n\
1238 .p2align 2,0x90 \n\
1239 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1240 " __XSTRING(CNAME(bluetrap6)) ": \n\
1241 ss \n\
1242 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1243 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1244 iret \n\
1245 ");
1246
1247 /*
1248 * Special exception 13 handler.
1249 * Accessing non-existent MSR generates general protection fault.
1250 */
1251 inthand_t bluetrap13;
1252 __asm
1253 (" \n\
1254 .text \n\
1255 .p2align 2,0x90 \n\
1256 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1257 " __XSTRING(CNAME(bluetrap13)) ": \n\
1258 ss \n\
1259 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1260 popl %eax /* discard error code */ \n\
1261 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1262 iret \n\
1263 ");
1264
1265 /*
1266 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1267 * support cpuid instruction. This function should be called after
1268 * loading interrupt descriptor table register.
1269 *
1270 * I don't like this method that handles fault, but I couldn't get
1271 * information for any other methods. Does blue giant know?
1272 */
1273 static int
identblue(void)1274 identblue(void)
1275 {
1276
1277 trap_by_rdmsr = 0;
1278
1279 /*
1280 * Cyrix 486-class CPU does not support rdmsr instruction.
1281 * The rdmsr instruction generates invalid opcode fault, and exception
1282 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1283 * bluetrap6() set the magic number to trap_by_rdmsr.
1284 */
1285 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1286 GSEL(GCODE_SEL, SEL_KPL));
1287
1288 /*
1289 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1290 * In this case, rdmsr generates general protection fault, and
1291 * exception will be trapped by bluetrap13().
1292 */
1293 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1294 GSEL(GCODE_SEL, SEL_KPL));
1295
1296 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1297
1298 if (trap_by_rdmsr == 0xa8c1d)
1299 return IDENTBLUE_CYRIX486;
1300 else if (trap_by_rdmsr == 0xa89c4)
1301 return IDENTBLUE_CYRIXM2;
1302 return IDENTBLUE_IBMCPU;
1303 }
1304
1305 /*
1306 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1307 *
1308 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1309 * +-------+-------+---------------+
1310 * | SID | RID | Device ID |
1311 * | (DIR 1) | (DIR 0) |
1312 * +-------+-------+---------------+
1313 */
1314 static void
identifycyrix(void)1315 identifycyrix(void)
1316 {
1317 register_t saveintr;
1318 int ccr2_test = 0, dir_test = 0;
1319 u_char ccr2, ccr3;
1320
1321 saveintr = intr_disable();
1322
1323 ccr2 = read_cyrix_reg(CCR2);
1324 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1325 read_cyrix_reg(CCR2);
1326 if (read_cyrix_reg(CCR2) != ccr2)
1327 ccr2_test = 1;
1328 write_cyrix_reg(CCR2, ccr2);
1329
1330 ccr3 = read_cyrix_reg(CCR3);
1331 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1332 read_cyrix_reg(CCR3);
1333 if (read_cyrix_reg(CCR3) != ccr3)
1334 dir_test = 1; /* CPU supports DIRs. */
1335 write_cyrix_reg(CCR3, ccr3);
1336
1337 if (dir_test) {
1338 /* Device ID registers are available. */
1339 cyrix_did = read_cyrix_reg(DIR1) << 8;
1340 cyrix_did += read_cyrix_reg(DIR0);
1341 } else if (ccr2_test)
1342 cyrix_did = 0x0010; /* 486S A-step */
1343 else
1344 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1345
1346 intr_restore(saveintr);
1347 }
1348 #endif
1349
1350 /* Update TSC freq with the value indicated by the caller. */
1351 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1352 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1353 {
1354
1355 /* If there was an error during the transition, don't do anything. */
1356 if (status != 0)
1357 return;
1358
1359 /* Total setting for this level gives the new frequency in MHz. */
1360 hw_clockrate = level->total_set.freq;
1361 }
1362
1363 static void
hook_tsc_freq(void * arg __unused)1364 hook_tsc_freq(void *arg __unused)
1365 {
1366
1367 if (tsc_is_invariant)
1368 return;
1369
1370 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1371 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1372 }
1373
1374 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1375
1376 static struct {
1377 const char *vm_cpuid;
1378 int vm_guest;
1379 void (*init)(void);
1380 } vm_cpuids[] = {
1381 { "XenVMMXenVMM", VM_GUEST_XEN,
1382 #ifdef XENHVM
1383 &xen_early_init,
1384 #endif
1385 }, /* XEN */
1386 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1387 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1388 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1389 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1390 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1391 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1392 };
1393
1394 static void
identify_hypervisor_cpuid_base(void)1395 identify_hypervisor_cpuid_base(void)
1396 {
1397 void (*init_fn)(void) = NULL;
1398 u_int leaf, regs[4];
1399 int i;
1400
1401 /*
1402 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1403 * http://lkml.org/lkml/2008/10/1/246
1404 *
1405 * KB1009458: Mechanisms to determine if software is running in
1406 * a VMware virtual machine
1407 * http://kb.vmware.com/kb/1009458
1408 *
1409 * Search for a hypervisor that we recognize. If we cannot find
1410 * a specific hypervisor, return the first information about the
1411 * hypervisor that we found, as others may be able to use.
1412 */
1413 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1414 do_cpuid(leaf, regs);
1415
1416 /*
1417 * KVM from Linux kernels prior to commit
1418 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1419 * to 0 rather than a valid hv_high value. Check for
1420 * the KVM signature bytes and fixup %eax to the
1421 * highest supported leaf in that case.
1422 */
1423 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1424 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1425 regs[0] = leaf + 1;
1426
1427 if (regs[0] >= leaf) {
1428 enum VM_GUEST prev_vm_guest = vm_guest;
1429
1430 for (i = 0; i < nitems(vm_cpuids); i++)
1431 if (strncmp((const char *)®s[1],
1432 vm_cpuids[i].vm_cpuid, 12) == 0) {
1433 vm_guest = vm_cpuids[i].vm_guest;
1434 init_fn = vm_cpuids[i].init;
1435 break;
1436 }
1437
1438 /*
1439 * If this is the first entry or we found a
1440 * specific hypervisor, record the base, high value,
1441 * and vendor identifier.
1442 */
1443 if (vm_guest != prev_vm_guest || leaf == 0x40000000) {
1444 hv_base = leaf;
1445 hv_high = regs[0];
1446 ((u_int *)&hv_vendor)[0] = regs[1];
1447 ((u_int *)&hv_vendor)[1] = regs[2];
1448 ((u_int *)&hv_vendor)[2] = regs[3];
1449 hv_vendor[12] = '\0';
1450
1451 /*
1452 * If we found a specific hypervisor, then
1453 * we are finished.
1454 */
1455 if (vm_guest != VM_GUEST_VM &&
1456 /*
1457 * Xen and other hypervisors can expose the
1458 * HyperV signature in addition to the
1459 * native one in order to support Viridian
1460 * extensions for Windows guests.
1461 *
1462 * Do the full cpuid scan if HyperV is
1463 * detected, as the native hypervisor is
1464 * preferred.
1465 */
1466 vm_guest != VM_GUEST_HV)
1467 break;
1468 }
1469 }
1470 }
1471
1472 if (init_fn != NULL)
1473 init_fn();
1474 }
1475
1476 void
identify_hypervisor(void)1477 identify_hypervisor(void)
1478 {
1479 u_int regs[4];
1480 char *p;
1481
1482 TSENTER();
1483 /*
1484 * If CPUID2_HV is set, we are running in a hypervisor environment.
1485 */
1486 if (cpu_feature2 & CPUID2_HV) {
1487 vm_guest = VM_GUEST_VM;
1488 identify_hypervisor_cpuid_base();
1489
1490 /* If we have a definitive vendor, we can return now. */
1491 if (*hv_vendor != '\0') {
1492 TSEXIT();
1493 return;
1494 }
1495 }
1496
1497 /*
1498 * Examine SMBIOS strings for older hypervisors.
1499 */
1500 p = kern_getenv("smbios.system.serial");
1501 if (p != NULL) {
1502 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1503 vmware_hvcall(0, VMW_HVCMD_GETVERSION,
1504 VMW_HVCMD_DEFAULT_PARAM, regs);
1505 if (regs[1] == VMW_HVMAGIC) {
1506 vm_guest = VM_GUEST_VMWARE;
1507 freeenv(p);
1508 TSEXIT();
1509 return;
1510 }
1511 }
1512 freeenv(p);
1513 }
1514 TSEXIT();
1515 }
1516
1517 bool
fix_cpuid(void)1518 fix_cpuid(void)
1519 {
1520 uint64_t msr;
1521
1522 /*
1523 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1524 * get the largest standard CPUID function number again if it is set
1525 * from BIOS. It is necessary for probing correct CPU topology later
1526 * and for the correct operation of the AVX-aware userspace.
1527 */
1528 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1529 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1530 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1531 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1532 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1533 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1534 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1535 msr &= ~IA32_MISC_EN_LIMCPUID;
1536 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1537 return (true);
1538 }
1539 }
1540
1541 /*
1542 * Re-enable AMD Topology Extension that could be disabled by BIOS
1543 * on some notebook processors. Without the extension it's really
1544 * hard to determine the correct CPU cache topology.
1545 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1546 * Models 60h-6Fh Processors, Publication # 50742.
1547 */
1548 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1549 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1550 msr = rdmsr(MSR_EXTFEATURES);
1551 if ((msr & ((uint64_t)1 << 54)) == 0) {
1552 msr |= (uint64_t)1 << 54;
1553 wrmsr(MSR_EXTFEATURES, msr);
1554 return (true);
1555 }
1556 }
1557 return (false);
1558 }
1559
1560 void
identify_cpu1(void)1561 identify_cpu1(void)
1562 {
1563 u_int regs[4];
1564
1565 do_cpuid(0, regs);
1566 cpu_high = regs[0];
1567 ((u_int *)&cpu_vendor)[0] = regs[1];
1568 ((u_int *)&cpu_vendor)[1] = regs[3];
1569 ((u_int *)&cpu_vendor)[2] = regs[2];
1570 cpu_vendor[12] = '\0';
1571
1572 do_cpuid(1, regs);
1573 cpu_id = regs[0];
1574 cpu_procinfo = regs[1];
1575 cpu_feature = regs[3];
1576 cpu_feature2 = regs[2];
1577 }
1578
1579 void
identify_cpu2(void)1580 identify_cpu2(void)
1581 {
1582 u_int regs[4], cpu_stdext_disable, max_eax_l7;
1583
1584 if (cpu_high >= 6) {
1585 cpuid_count(6, 0, regs);
1586 cpu_power_eax = regs[0];
1587 cpu_power_ebx = regs[1];
1588 cpu_power_ecx = regs[2];
1589 cpu_power_edx = regs[3];
1590 }
1591
1592 if (cpu_high >= 7) {
1593 cpuid_count(7, 0, regs);
1594 cpu_stdext_feature = regs[1];
1595 max_eax_l7 = regs[0];
1596
1597 /*
1598 * Some hypervisors failed to filter out unsupported
1599 * extended features. Allow to disable the
1600 * extensions, activation of which requires setting a
1601 * bit in CR4, and which VM monitors do not support.
1602 */
1603 cpu_stdext_disable = 0;
1604 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1605 cpu_stdext_feature &= ~cpu_stdext_disable;
1606
1607 cpu_stdext_feature2 = regs[2];
1608 cpu_stdext_feature3 = regs[3];
1609
1610 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1611 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1612
1613 if (max_eax_l7 >= 1) {
1614 cpuid_count(7, 1, regs);
1615 cpu_stdext_feature4 = regs[0];
1616 }
1617 }
1618 }
1619
1620 void
identify_cpu_ext_features(void)1621 identify_cpu_ext_features(void)
1622 {
1623 u_int regs[4];
1624
1625 if (cpu_high >= 7) {
1626 cpuid_count(7, 0, regs);
1627 cpu_stdext_feature2 = regs[2];
1628 cpu_stdext_feature3 = regs[3];
1629 }
1630 }
1631
1632 void
identify_cpu_fixup_bsp(void)1633 identify_cpu_fixup_bsp(void)
1634 {
1635 u_int regs[4];
1636
1637 cpu_vendor_id = find_cpu_vendor_id();
1638
1639 if (fix_cpuid()) {
1640 do_cpuid(0, regs);
1641 cpu_high = regs[0];
1642 }
1643 }
1644
1645 /*
1646 * Final stage of CPU identification.
1647 */
1648 void
finishidentcpu(void)1649 finishidentcpu(void)
1650 {
1651 u_int regs[4];
1652 #ifdef __i386__
1653 u_char ccr3;
1654 #endif
1655
1656 identify_cpu_fixup_bsp();
1657
1658 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1659 do_cpuid(5, regs);
1660 cpu_mon_mwait_flags = regs[2];
1661 cpu_mon_mwait_edx = regs[3];
1662 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1663 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1664 }
1665
1666 identify_cpu2();
1667
1668 #ifdef __i386__
1669 if (cpu_high > 0 &&
1670 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1671 cpu_vendor_id == CPU_VENDOR_AMD ||
1672 cpu_vendor_id == CPU_VENDOR_HYGON ||
1673 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1674 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1675 cpu_vendor_id == CPU_VENDOR_NSC)) {
1676 do_cpuid(0x80000000, regs);
1677 if (regs[0] >= 0x80000000)
1678 cpu_exthigh = regs[0];
1679 }
1680 #else
1681 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1682 cpu_vendor_id == CPU_VENDOR_AMD ||
1683 cpu_vendor_id == CPU_VENDOR_HYGON ||
1684 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1685 do_cpuid(0x80000000, regs);
1686 cpu_exthigh = regs[0];
1687 }
1688 #endif
1689 if (cpu_exthigh >= 0x80000001) {
1690 do_cpuid(0x80000001, regs);
1691 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1692 amd_feature2 = regs[2];
1693 }
1694 if (cpu_exthigh >= 0x80000007) {
1695 do_cpuid(0x80000007, regs);
1696 amd_rascap = regs[1];
1697 amd_pminfo = regs[3];
1698 }
1699 if (cpu_exthigh >= 0x80000008) {
1700 do_cpuid(0x80000008, regs);
1701 cpu_maxphyaddr = regs[0] & 0xff;
1702 amd_extended_feature_extensions = regs[1];
1703 cpu_procinfo2 = regs[2];
1704 cpu_procinfo3 = regs[3];
1705 } else {
1706 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1707 }
1708
1709 #ifdef __i386__
1710 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1711 if (cpu == CPU_486) {
1712 /*
1713 * These conditions are equivalent to:
1714 * - CPU does not support cpuid instruction.
1715 * - Cyrix/IBM CPU is detected.
1716 */
1717 if (identblue() == IDENTBLUE_IBMCPU) {
1718 strcpy(cpu_vendor, "IBM");
1719 cpu_vendor_id = CPU_VENDOR_IBM;
1720 cpu = CPU_BLUE;
1721 return;
1722 }
1723 }
1724 switch (cpu_id & 0xf00) {
1725 case 0x600:
1726 /*
1727 * Cyrix's datasheet does not describe DIRs.
1728 * Therefor, I assume it does not have them
1729 * and use the result of the cpuid instruction.
1730 * XXX they seem to have it for now at least. -Peter
1731 */
1732 identifycyrix();
1733 cpu = CPU_M2;
1734 break;
1735 default:
1736 identifycyrix();
1737 /*
1738 * This routine contains a trick.
1739 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1740 */
1741 switch (cyrix_did & 0x00f0) {
1742 case 0x00:
1743 case 0xf0:
1744 cpu = CPU_486DLC;
1745 break;
1746 case 0x10:
1747 cpu = CPU_CY486DX;
1748 break;
1749 case 0x20:
1750 if ((cyrix_did & 0x000f) < 8)
1751 cpu = CPU_M1;
1752 else
1753 cpu = CPU_M1SC;
1754 break;
1755 case 0x30:
1756 cpu = CPU_M1;
1757 break;
1758 case 0x40:
1759 /* MediaGX CPU */
1760 cpu = CPU_M1SC;
1761 break;
1762 default:
1763 /* M2 and later CPUs are treated as M2. */
1764 cpu = CPU_M2;
1765
1766 /*
1767 * enable cpuid instruction.
1768 */
1769 ccr3 = read_cyrix_reg(CCR3);
1770 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1771 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1772 write_cyrix_reg(CCR3, ccr3);
1773
1774 do_cpuid(0, regs);
1775 cpu_high = regs[0]; /* eax */
1776 do_cpuid(1, regs);
1777 cpu_id = regs[0]; /* eax */
1778 cpu_feature = regs[3]; /* edx */
1779 break;
1780 }
1781 }
1782 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1783 /*
1784 * There are BlueLightning CPUs that do not change
1785 * undefined flags by dividing 5 by 2. In this case,
1786 * the CPU identification routine in locore.s leaves
1787 * cpu_vendor null string and puts CPU_486 into the
1788 * cpu.
1789 */
1790 if (identblue() == IDENTBLUE_IBMCPU) {
1791 strcpy(cpu_vendor, "IBM");
1792 cpu_vendor_id = CPU_VENDOR_IBM;
1793 cpu = CPU_BLUE;
1794 return;
1795 }
1796 }
1797 #endif
1798 }
1799
1800 int
pti_get_default(void)1801 pti_get_default(void)
1802 {
1803
1804 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1805 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1806 return (0);
1807 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1808 return (0);
1809 return (1);
1810 }
1811
1812 static u_int
find_cpu_vendor_id(void)1813 find_cpu_vendor_id(void)
1814 {
1815 int i;
1816
1817 for (i = 0; i < nitems(cpu_vendors); i++)
1818 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1819 return (cpu_vendors[i].vendor_id);
1820 return (0);
1821 }
1822
1823 static void
print_AMD_assoc(int i)1824 print_AMD_assoc(int i)
1825 {
1826 if (i == 255)
1827 printf(", fully associative\n");
1828 else
1829 printf(", %d-way associative\n", i);
1830 }
1831
1832 static void
print_AMD_l2_assoc(int i)1833 print_AMD_l2_assoc(int i)
1834 {
1835 switch (i & 0x0f) {
1836 case 0: printf(", disabled/not present\n"); break;
1837 case 1: printf(", direct mapped\n"); break;
1838 case 2: printf(", 2-way associative\n"); break;
1839 case 4: printf(", 4-way associative\n"); break;
1840 case 6: printf(", 8-way associative\n"); break;
1841 case 8: printf(", 16-way associative\n"); break;
1842 case 15: printf(", fully associative\n"); break;
1843 default: printf(", reserved configuration\n"); break;
1844 }
1845 }
1846
1847 static void
print_AMD_info(void)1848 print_AMD_info(void)
1849 {
1850 #ifdef __i386__
1851 uint64_t amd_whcr;
1852 #endif
1853 u_int regs[4];
1854
1855 if (cpu_exthigh >= 0x80000005) {
1856 do_cpuid(0x80000005, regs);
1857 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1858 print_AMD_assoc(regs[0] >> 24);
1859
1860 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1861 print_AMD_assoc((regs[0] >> 8) & 0xff);
1862
1863 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1864 print_AMD_assoc(regs[1] >> 24);
1865
1866 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1867 print_AMD_assoc((regs[1] >> 8) & 0xff);
1868
1869 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1870 printf(", %d bytes/line", regs[2] & 0xff);
1871 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1872 print_AMD_assoc((regs[2] >> 16) & 0xff);
1873
1874 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1875 printf(", %d bytes/line", regs[3] & 0xff);
1876 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1877 print_AMD_assoc((regs[3] >> 16) & 0xff);
1878 }
1879
1880 if (cpu_exthigh >= 0x80000006) {
1881 do_cpuid(0x80000006, regs);
1882 if ((regs[0] >> 16) != 0) {
1883 printf("L2 2MB data TLB: %d entries",
1884 (regs[0] >> 16) & 0xfff);
1885 print_AMD_l2_assoc(regs[0] >> 28);
1886 printf("L2 2MB instruction TLB: %d entries",
1887 regs[0] & 0xfff);
1888 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1889 } else {
1890 printf("L2 2MB unified TLB: %d entries",
1891 regs[0] & 0xfff);
1892 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1893 }
1894 if ((regs[1] >> 16) != 0) {
1895 printf("L2 4KB data TLB: %d entries",
1896 (regs[1] >> 16) & 0xfff);
1897 print_AMD_l2_assoc(regs[1] >> 28);
1898
1899 printf("L2 4KB instruction TLB: %d entries",
1900 (regs[1] >> 16) & 0xfff);
1901 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1902 } else {
1903 printf("L2 4KB unified TLB: %d entries",
1904 (regs[1] >> 16) & 0xfff);
1905 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1906 }
1907 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1908 printf(", %d bytes/line", regs[2] & 0xff);
1909 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1910 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1911 }
1912
1913 #ifdef __i386__
1914 if (((cpu_id & 0xf00) == 0x500)
1915 && (((cpu_id & 0x0f0) > 0x80)
1916 || (((cpu_id & 0x0f0) == 0x80)
1917 && (cpu_id & 0x00f) > 0x07))) {
1918 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1919 amd_whcr = rdmsr(0xc0000082);
1920 if (!(amd_whcr & (0x3ff << 22))) {
1921 printf("Write Allocate Disable\n");
1922 } else {
1923 printf("Write Allocate Enable Limit: %dM bytes\n",
1924 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1925 printf("Write Allocate 15-16M bytes: %s\n",
1926 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1927 }
1928 } else if (((cpu_id & 0xf00) == 0x500)
1929 && ((cpu_id & 0x0f0) > 0x50)) {
1930 /* K6, K6-2(old core) */
1931 amd_whcr = rdmsr(0xc0000082);
1932 if (!(amd_whcr & (0x7f << 1))) {
1933 printf("Write Allocate Disable\n");
1934 } else {
1935 printf("Write Allocate Enable Limit: %dM bytes\n",
1936 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1937 printf("Write Allocate 15-16M bytes: %s\n",
1938 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1939 printf("Hardware Write Allocate Control: %s\n",
1940 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1941 }
1942 }
1943 #endif
1944 /*
1945 * Opteron Rev E shows a bug as in very rare occasions a read memory
1946 * barrier is not performed as expected if it is followed by a
1947 * non-atomic read-modify-write instruction.
1948 * As long as that bug pops up very rarely (intensive machine usage
1949 * on other operating systems generally generates one unexplainable
1950 * crash any 2 months) and as long as a model specific fix would be
1951 * impractical at this stage, print out a warning string if the broken
1952 * model and family are identified.
1953 */
1954 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1955 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1956 printf("WARNING: This architecture revision has known SMP "
1957 "hardware bugs which may cause random instability\n");
1958 }
1959
1960 static void
print_INTEL_info(void)1961 print_INTEL_info(void)
1962 {
1963 u_int regs[4];
1964 u_int rounds, regnum;
1965 u_int nwaycode, nway;
1966
1967 if (cpu_high >= 2) {
1968 rounds = 0;
1969 do {
1970 do_cpuid(0x2, regs);
1971 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1972 break; /* we have a buggy CPU */
1973
1974 for (regnum = 0; regnum <= 3; ++regnum) {
1975 if (regs[regnum] & (1<<31))
1976 continue;
1977 if (regnum != 0)
1978 print_INTEL_TLB(regs[regnum] & 0xff);
1979 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1980 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1981 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1982 }
1983 } while (--rounds > 0);
1984 }
1985
1986 if (cpu_exthigh >= 0x80000006) {
1987 do_cpuid(0x80000006, regs);
1988 nwaycode = (regs[2] >> 12) & 0x0f;
1989 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1990 nway = 1 << (nwaycode / 2);
1991 else
1992 nway = 0;
1993 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1994 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1995 }
1996 }
1997
1998 static void
print_INTEL_TLB(u_int data)1999 print_INTEL_TLB(u_int data)
2000 {
2001 switch (data) {
2002 case 0x0:
2003 case 0x40:
2004 default:
2005 break;
2006 case 0x1:
2007 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
2008 break;
2009 case 0x2:
2010 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
2011 break;
2012 case 0x3:
2013 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
2014 break;
2015 case 0x4:
2016 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
2017 break;
2018 case 0x6:
2019 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
2020 break;
2021 case 0x8:
2022 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2023 break;
2024 case 0x9:
2025 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2026 break;
2027 case 0xa:
2028 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2029 break;
2030 case 0xb:
2031 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2032 break;
2033 case 0xc:
2034 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2035 break;
2036 case 0xd:
2037 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2038 break;
2039 case 0xe:
2040 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2041 break;
2042 case 0x1d:
2043 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2044 break;
2045 case 0x21:
2046 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2047 break;
2048 case 0x22:
2049 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2050 break;
2051 case 0x23:
2052 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2053 break;
2054 case 0x24:
2055 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2056 break;
2057 case 0x25:
2058 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2059 break;
2060 case 0x29:
2061 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2062 break;
2063 case 0x2c:
2064 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2065 break;
2066 case 0x30:
2067 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2068 break;
2069 case 0x39: /* De-listed in SDM rev. 54 */
2070 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2071 break;
2072 case 0x3b: /* De-listed in SDM rev. 54 */
2073 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2074 break;
2075 case 0x3c: /* De-listed in SDM rev. 54 */
2076 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2077 break;
2078 case 0x41:
2079 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2080 break;
2081 case 0x42:
2082 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2083 break;
2084 case 0x43:
2085 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2086 break;
2087 case 0x44:
2088 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2089 break;
2090 case 0x45:
2091 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2092 break;
2093 case 0x46:
2094 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2095 break;
2096 case 0x47:
2097 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2098 break;
2099 case 0x48:
2100 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2101 break;
2102 case 0x49:
2103 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2104 CPUID_TO_MODEL(cpu_id) == 0x6)
2105 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2106 else
2107 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2108 break;
2109 case 0x4a:
2110 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2111 break;
2112 case 0x4b:
2113 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2114 break;
2115 case 0x4c:
2116 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2117 break;
2118 case 0x4d:
2119 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2120 break;
2121 case 0x4e:
2122 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2123 break;
2124 case 0x4f:
2125 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2126 break;
2127 case 0x50:
2128 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2129 break;
2130 case 0x51:
2131 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2132 break;
2133 case 0x52:
2134 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2135 break;
2136 case 0x55:
2137 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2138 break;
2139 case 0x56:
2140 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2141 break;
2142 case 0x57:
2143 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2144 break;
2145 case 0x59:
2146 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2147 break;
2148 case 0x5a:
2149 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2150 break;
2151 case 0x5b:
2152 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2153 break;
2154 case 0x5c:
2155 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2156 break;
2157 case 0x5d:
2158 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2159 break;
2160 case 0x60:
2161 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2162 break;
2163 case 0x61:
2164 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2165 break;
2166 case 0x63:
2167 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2168 break;
2169 case 0x64:
2170 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2171 break;
2172 case 0x66:
2173 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2174 break;
2175 case 0x67:
2176 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2177 break;
2178 case 0x68:
2179 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2180 break;
2181 case 0x6a:
2182 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2183 break;
2184 case 0x6b:
2185 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2186 break;
2187 case 0x6c:
2188 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2189 break;
2190 case 0x6d:
2191 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2192 break;
2193 case 0x70:
2194 printf("Trace cache: 12K-uops, 8-way set associative\n");
2195 break;
2196 case 0x71:
2197 printf("Trace cache: 16K-uops, 8-way set associative\n");
2198 break;
2199 case 0x72:
2200 printf("Trace cache: 32K-uops, 8-way set associative\n");
2201 break;
2202 case 0x76:
2203 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2204 break;
2205 case 0x78:
2206 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2207 break;
2208 case 0x79:
2209 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2210 break;
2211 case 0x7a:
2212 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2213 break;
2214 case 0x7b:
2215 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2216 break;
2217 case 0x7c:
2218 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2219 break;
2220 case 0x7d:
2221 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2222 break;
2223 case 0x7f:
2224 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2225 break;
2226 case 0x80:
2227 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2228 break;
2229 case 0x82:
2230 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2231 break;
2232 case 0x83:
2233 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2234 break;
2235 case 0x84:
2236 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2237 break;
2238 case 0x85:
2239 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2240 break;
2241 case 0x86:
2242 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2243 break;
2244 case 0x87:
2245 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2246 break;
2247 case 0xa0:
2248 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2249 break;
2250 case 0xb0:
2251 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2252 break;
2253 case 0xb1:
2254 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2255 break;
2256 case 0xb2:
2257 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2258 break;
2259 case 0xb3:
2260 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2261 break;
2262 case 0xb4:
2263 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2264 break;
2265 case 0xb5:
2266 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2267 break;
2268 case 0xb6:
2269 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2270 break;
2271 case 0xba:
2272 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2273 break;
2274 case 0xc0:
2275 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2276 break;
2277 case 0xc1:
2278 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2279 break;
2280 case 0xc2:
2281 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2282 break;
2283 case 0xc3:
2284 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2285 break;
2286 case 0xc4:
2287 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2288 break;
2289 case 0xca:
2290 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2291 break;
2292 case 0xd0:
2293 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2294 break;
2295 case 0xd1:
2296 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2297 break;
2298 case 0xd2:
2299 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2300 break;
2301 case 0xd6:
2302 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2303 break;
2304 case 0xd7:
2305 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2306 break;
2307 case 0xd8:
2308 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2309 break;
2310 case 0xdc:
2311 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2312 break;
2313 case 0xdd:
2314 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2315 break;
2316 case 0xde:
2317 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2318 break;
2319 case 0xe2:
2320 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2321 break;
2322 case 0xe3:
2323 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2324 break;
2325 case 0xe4:
2326 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2327 break;
2328 case 0xea:
2329 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2330 break;
2331 case 0xeb:
2332 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2333 break;
2334 case 0xec:
2335 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2336 break;
2337 case 0xf0:
2338 printf("64-Byte prefetching\n");
2339 break;
2340 case 0xf1:
2341 printf("128-Byte prefetching\n");
2342 break;
2343 }
2344 }
2345
2346 static void
print_svm_info(void)2347 print_svm_info(void)
2348 {
2349 u_int features, regs[4];
2350 uint64_t msr;
2351 int comma;
2352
2353 printf("\n SVM: ");
2354 do_cpuid(0x8000000A, regs);
2355 features = regs[3];
2356
2357 msr = rdmsr(MSR_VM_CR);
2358 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2359 printf("(disabled in BIOS) ");
2360
2361 if (!bootverbose) {
2362 comma = 0;
2363 if (features & (1 << 0)) {
2364 printf("%sNP", comma ? "," : "");
2365 comma = 1;
2366 }
2367 if (features & (1 << 3)) {
2368 printf("%sNRIP", comma ? "," : "");
2369 comma = 1;
2370 }
2371 if (features & (1 << 5)) {
2372 printf("%sVClean", comma ? "," : "");
2373 comma = 1;
2374 }
2375 if (features & (1 << 6)) {
2376 printf("%sAFlush", comma ? "," : "");
2377 comma = 1;
2378 }
2379 if (features & (1 << 7)) {
2380 printf("%sDAssist", comma ? "," : "");
2381 comma = 1;
2382 }
2383 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2384 return;
2385 }
2386
2387 printf("Features=0x%b", features,
2388 "\020"
2389 "\001NP" /* Nested paging */
2390 "\002LbrVirt" /* LBR virtualization */
2391 "\003SVML" /* SVM lock */
2392 "\004NRIPS" /* NRIP save */
2393 "\005TscRateMsr" /* MSR based TSC rate control */
2394 "\006VmcbClean" /* VMCB clean bits */
2395 "\007FlushByAsid" /* Flush by ASID */
2396 "\010DecodeAssist" /* Decode assist */
2397 "\011<b8>"
2398 "\012<b9>"
2399 "\013PauseFilter" /* PAUSE intercept filter */
2400 "\014EncryptedMcodePatch"
2401 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2402 "\016AVIC" /* virtual interrupt controller */
2403 "\017<b14>"
2404 "\020V_VMSAVE_VMLOAD"
2405 "\021vGIF"
2406 "\022GMET" /* Guest Mode Execute Trap */
2407 "\023<b18>"
2408 "\024<b19>"
2409 "\025GuesSpecCtl" /* Guest Spec_ctl */
2410 "\026<b21>"
2411 "\027<b22>"
2412 "\030<b23>"
2413 "\031<b24>"
2414 "\032<b25>"
2415 "\033<b26>"
2416 "\034<b27>"
2417 "\035<b28>"
2418 "\036<b29>"
2419 "\037<b30>"
2420 "\040<b31>"
2421 );
2422 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2423 }
2424
2425 #ifdef __i386__
2426 static void
print_transmeta_info(void)2427 print_transmeta_info(void)
2428 {
2429 u_int regs[4], nreg = 0;
2430
2431 do_cpuid(0x80860000, regs);
2432 nreg = regs[0];
2433 if (nreg >= 0x80860001) {
2434 do_cpuid(0x80860001, regs);
2435 printf(" Processor revision %u.%u.%u.%u\n",
2436 (regs[1] >> 24) & 0xff,
2437 (regs[1] >> 16) & 0xff,
2438 (regs[1] >> 8) & 0xff,
2439 regs[1] & 0xff);
2440 }
2441 if (nreg >= 0x80860002) {
2442 do_cpuid(0x80860002, regs);
2443 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2444 (regs[1] >> 24) & 0xff,
2445 (regs[1] >> 16) & 0xff,
2446 (regs[1] >> 8) & 0xff,
2447 regs[1] & 0xff,
2448 regs[2]);
2449 }
2450 if (nreg >= 0x80860006) {
2451 char info[65];
2452 do_cpuid(0x80860003, (u_int*) &info[0]);
2453 do_cpuid(0x80860004, (u_int*) &info[16]);
2454 do_cpuid(0x80860005, (u_int*) &info[32]);
2455 do_cpuid(0x80860006, (u_int*) &info[48]);
2456 info[64] = 0;
2457 printf(" %s\n", info);
2458 }
2459 }
2460 #endif
2461
2462 static void
print_via_padlock_info(void)2463 print_via_padlock_info(void)
2464 {
2465 u_int regs[4];
2466
2467 do_cpuid(0xc0000001, regs);
2468 printf("\n VIA Padlock Features=0x%b", regs[3],
2469 "\020"
2470 "\003RNG" /* RNG */
2471 "\007AES" /* ACE */
2472 "\011AES-CTR" /* ACE2 */
2473 "\013SHA1,SHA256" /* PHE */
2474 "\015RSA" /* PMM */
2475 );
2476 }
2477
2478 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2479 vmx_settable(uint64_t basic, int msr, int true_msr)
2480 {
2481 uint64_t val;
2482
2483 if (basic & (1ULL << 55))
2484 val = rdmsr(true_msr);
2485 else
2486 val = rdmsr(msr);
2487
2488 /* Just report the controls that can be set to 1. */
2489 return (val >> 32);
2490 }
2491
2492 static void
print_vmx_info(void)2493 print_vmx_info(void)
2494 {
2495 uint64_t basic, msr;
2496 uint32_t entry, exit, mask, pin, proc, proc2;
2497 int comma;
2498
2499 printf("\n VT-x: ");
2500 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2501 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2502 printf("(disabled in BIOS) ");
2503 basic = rdmsr(MSR_VMX_BASIC);
2504 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2505 MSR_VMX_TRUE_PINBASED_CTLS);
2506 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2507 MSR_VMX_TRUE_PROCBASED_CTLS);
2508 if (proc & PROCBASED_SECONDARY_CONTROLS)
2509 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2510 MSR_VMX_PROCBASED_CTLS2);
2511 else
2512 proc2 = 0;
2513 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2514 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2515
2516 if (!bootverbose) {
2517 comma = 0;
2518 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2519 entry & VM_ENTRY_LOAD_PAT) {
2520 printf("%sPAT", comma ? "," : "");
2521 comma = 1;
2522 }
2523 if (proc & PROCBASED_HLT_EXITING) {
2524 printf("%sHLT", comma ? "," : "");
2525 comma = 1;
2526 }
2527 if (proc & PROCBASED_MTF) {
2528 printf("%sMTF", comma ? "," : "");
2529 comma = 1;
2530 }
2531 if (proc & PROCBASED_PAUSE_EXITING) {
2532 printf("%sPAUSE", comma ? "," : "");
2533 comma = 1;
2534 }
2535 if (proc2 & PROCBASED2_ENABLE_EPT) {
2536 printf("%sEPT", comma ? "," : "");
2537 comma = 1;
2538 }
2539 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2540 printf("%sUG", comma ? "," : "");
2541 comma = 1;
2542 }
2543 if (proc2 & PROCBASED2_ENABLE_VPID) {
2544 printf("%sVPID", comma ? "," : "");
2545 comma = 1;
2546 }
2547 if (proc & PROCBASED_USE_TPR_SHADOW &&
2548 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2549 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2550 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2551 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2552 printf("%sVID", comma ? "," : "");
2553 comma = 1;
2554 if (pin & PINBASED_POSTED_INTERRUPT)
2555 printf(",PostIntr");
2556 }
2557 return;
2558 }
2559
2560 mask = basic >> 32;
2561 printf("Basic Features=0x%b", mask,
2562 "\020"
2563 "\02132PA" /* 32-bit physical addresses */
2564 "\022SMM" /* SMM dual-monitor */
2565 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2566 "\030TRUE" /* TRUE_CTLS MSRs */
2567 );
2568 printf("\n Pin-Based Controls=0x%b", pin,
2569 "\020"
2570 "\001ExtINT" /* External-interrupt exiting */
2571 "\004NMI" /* NMI exiting */
2572 "\006VNMI" /* Virtual NMIs */
2573 "\007PreTmr" /* Activate VMX-preemption timer */
2574 "\010PostIntr" /* Process posted interrupts */
2575 );
2576 printf("\n Primary Processor Controls=0x%b", proc,
2577 "\020"
2578 "\003INTWIN" /* Interrupt-window exiting */
2579 "\004TSCOff" /* Use TSC offsetting */
2580 "\010HLT" /* HLT exiting */
2581 "\012INVLPG" /* INVLPG exiting */
2582 "\013MWAIT" /* MWAIT exiting */
2583 "\014RDPMC" /* RDPMC exiting */
2584 "\015RDTSC" /* RDTSC exiting */
2585 "\020CR3-LD" /* CR3-load exiting */
2586 "\021CR3-ST" /* CR3-store exiting */
2587 "\024CR8-LD" /* CR8-load exiting */
2588 "\025CR8-ST" /* CR8-store exiting */
2589 "\026TPR" /* Use TPR shadow */
2590 "\027NMIWIN" /* NMI-window exiting */
2591 "\030MOV-DR" /* MOV-DR exiting */
2592 "\031IO" /* Unconditional I/O exiting */
2593 "\032IOmap" /* Use I/O bitmaps */
2594 "\034MTF" /* Monitor trap flag */
2595 "\035MSRmap" /* Use MSR bitmaps */
2596 "\036MONITOR" /* MONITOR exiting */
2597 "\037PAUSE" /* PAUSE exiting */
2598 );
2599 if (proc & PROCBASED_SECONDARY_CONTROLS)
2600 printf("\n Secondary Processor Controls=0x%b", proc2,
2601 "\020"
2602 "\001APIC" /* Virtualize APIC accesses */
2603 "\002EPT" /* Enable EPT */
2604 "\003DT" /* Descriptor-table exiting */
2605 "\004RDTSCP" /* Enable RDTSCP */
2606 "\005x2APIC" /* Virtualize x2APIC mode */
2607 "\006VPID" /* Enable VPID */
2608 "\007WBINVD" /* WBINVD exiting */
2609 "\010UG" /* Unrestricted guest */
2610 "\011APIC-reg" /* APIC-register virtualization */
2611 "\012VID" /* Virtual-interrupt delivery */
2612 "\013PAUSE-loop" /* PAUSE-loop exiting */
2613 "\014RDRAND" /* RDRAND exiting */
2614 "\015INVPCID" /* Enable INVPCID */
2615 "\016VMFUNC" /* Enable VM functions */
2616 "\017VMCS" /* VMCS shadowing */
2617 "\020EPT#VE" /* EPT-violation #VE */
2618 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2619 );
2620 printf("\n Exit Controls=0x%b", exit,
2621 "\020"
2622 "\003DR" /* Save debug controls */
2623 /* Ignore Host address-space size */
2624 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2625 "\020AckInt" /* Acknowledge interrupt on exit */
2626 "\023PAT-SV" /* Save MSR_PAT */
2627 "\024PAT-LD" /* Load MSR_PAT */
2628 "\025EFER-SV" /* Save MSR_EFER */
2629 "\026EFER-LD" /* Load MSR_EFER */
2630 "\027PTMR-SV" /* Save VMX-preemption timer value */
2631 );
2632 printf("\n Entry Controls=0x%b", entry,
2633 "\020"
2634 "\003DR" /* Save debug controls */
2635 /* Ignore IA-32e mode guest */
2636 /* Ignore Entry to SMM */
2637 /* Ignore Deactivate dual-monitor treatment */
2638 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2639 "\017PAT" /* Load MSR_PAT */
2640 "\020EFER" /* Load MSR_EFER */
2641 );
2642 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2643 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2644 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2645 mask = msr;
2646 printf("\n EPT Features=0x%b", mask,
2647 "\020"
2648 "\001XO" /* Execute-only translations */
2649 "\007PW4" /* Page-walk length of 4 */
2650 "\011UC" /* EPT paging-structure mem can be UC */
2651 "\017WB" /* EPT paging-structure mem can be WB */
2652 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2653 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2654 "\025INVEPT" /* INVEPT is supported */
2655 "\026AD" /* Accessed and dirty flags for EPT */
2656 "\032single" /* INVEPT single-context type */
2657 "\033all" /* INVEPT all-context type */
2658 );
2659 mask = msr >> 32;
2660 printf("\n VPID Features=0x%b", mask,
2661 "\020"
2662 "\001INVVPID" /* INVVPID is supported */
2663 "\011individual" /* INVVPID individual-address type */
2664 "\012single" /* INVVPID single-context type */
2665 "\013all" /* INVVPID all-context type */
2666 /* INVVPID single-context-retaining-globals type */
2667 "\014single-globals"
2668 );
2669 }
2670 }
2671
2672 static void
print_hypervisor_info(void)2673 print_hypervisor_info(void)
2674 {
2675
2676 if (*hv_vendor != '\0')
2677 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2678 }
2679
2680 /*
2681 * Returns the maximum physical address that can be used with the
2682 * current system.
2683 */
2684 vm_paddr_t
cpu_getmaxphyaddr(void)2685 cpu_getmaxphyaddr(void)
2686 {
2687
2688 #if defined(__i386__)
2689 if (!pae_mode)
2690 return (0xffffffff);
2691 #endif
2692 return ((1ULL << cpu_maxphyaddr) - 1);
2693 }
2694
2695 const static struct {
2696 u_int family;
2697 u_int model_min;
2698 u_int model_max;
2699 u_int generation;
2700 } zen_idents[] = {
2701 { .family = 0x17, .model_min = 0x00, .model_max = 0x2f, .generation = CPU_AMD_ZEN1 },
2702 { .family = 0x17, .model_min = 0x50, .model_max = 0x5f, .generation = CPU_AMD_ZEN1 },
2703 { .family = 0x17, .model_min = 0x30, .model_max = 0x4f, .generation = CPU_AMD_ZEN2 },
2704 { .family = 0x17, .model_min = 0x60, .model_max = 0x7f, .generation = CPU_AMD_ZEN2 },
2705 { .family = 0x17, .model_min = 0x90, .model_max = 0x91, .generation = CPU_AMD_ZEN2 },
2706 { .family = 0x17, .model_min = 0xa0, .model_max = 0xaf, .generation = CPU_AMD_ZEN2 },
2707 { .family = 0x19, .model_min = 0x00, .model_max = 0x0f, .generation = CPU_AMD_ZEN3 },
2708 { .family = 0x19, .model_min = 0x20, .model_max = 0x5f, .generation = CPU_AMD_ZEN3 },
2709 { .family = 0x19, .model_min = 0x10, .model_max = 0x1f, .generation = CPU_AMD_ZEN4 },
2710 { .family = 0x19, .model_min = 0x60, .model_max = 0xaf, .generation = CPU_AMD_ZEN4 },
2711 { .family = 0x1a, .model_min = 0x00, .model_max = 0x2f, .generation = CPU_AMD_ZEN5 },
2712 { .family = 0x1a, .model_min = 0x40, .model_max = 0x4f, .generation = CPU_AMD_ZEN5 },
2713 { .family = 0x1a, .model_min = 0x60, .model_max = 0x7f, .generation = CPU_AMD_ZEN5 },
2714 { .family = 0x1a, .model_min = 0x50, .model_max = 0x5f, .generation = CPU_AMD_ZEN6 },
2715 { .family = 0x1a, .model_min = 0x80, .model_max = 0xaf, .generation = CPU_AMD_ZEN6 },
2716 { .family = 0x1a, .model_min = 0xc0, .model_max = 0xcf, .generation = CPU_AMD_ZEN6 },
2717 };
2718
2719 u_int
ident_zen_cpu(void)2720 ident_zen_cpu(void)
2721 {
2722 u_int family = CPUID_TO_FAMILY(cpu_id);
2723 u_int model = CPUID_TO_MODEL(cpu_id);
2724 int i;
2725
2726 if (cpu_vendor_id != CPU_VENDOR_AMD)
2727 return (CPU_AMD_UNKNOWN);
2728
2729 for (i = 0; i < nitems(zen_idents); i++) {
2730 if (family != zen_idents[i].family)
2731 continue;
2732 if (model < zen_idents[i].model_min ||
2733 model > zen_idents[i].model_max)
2734 continue;
2735 return (zen_idents[i].generation);
2736 }
2737
2738 return (CPU_AMD_UNKNOWN);
2739 }
2740