1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
50 * into the driver.
51 *
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
54 *
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
58 *
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
61 *
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
66 * ring.
67 */
68
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
71 #endif
72
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
77 #include <sys/mbuf.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
84
85 #include <net/debugnet.h>
86 #include <net/if.h>
87 #include <net/if_var.h>
88 #include <net/if_arp.h>
89 #include <net/ethernet.h>
90 #include <net/if_dl.h>
91 #include <net/if_media.h>
92
93 #include <net/bpf.h>
94
95 #include <net/if_types.h>
96 #include <net/if_vlan_var.h>
97
98 #include <netinet/in_systm.h>
99 #include <netinet/in.h>
100 #include <netinet/ip.h>
101 #include <netinet/tcp.h>
102
103 #include <machine/bus.h>
104 #include <machine/resource.h>
105 #include <sys/bus.h>
106 #include <sys/rman.h>
107
108 #include <dev/mii/mii.h>
109 #include <dev/mii/miivar.h>
110 #include "miidevs.h"
111 #include <dev/mii/brgphyreg.h>
112
113 #include <dev/pci/pcireg.h>
114 #include <dev/pci/pcivar.h>
115
116 #include <dev/bge/if_bgereg.h>
117
118 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
119 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
120
121 MODULE_DEPEND(bge, pci, 1, 1, 1);
122 MODULE_DEPEND(bge, ether, 1, 1, 1);
123 MODULE_DEPEND(bge, miibus, 1, 1, 1);
124
125 /* "device miibus" required. See GENERIC if you get errors here. */
126 #include "miibus_if.h"
127
128 /*
129 * Various supported device vendors/types and their names. Note: the
130 * spec seems to indicate that the hardware still has Alteon's vendor
131 * ID burned into it, though it will always be overridden by the vendor
132 * ID in the EEPROM. Just to be safe, we cover all possibilities.
133 */
134 static const struct bge_type {
135 uint16_t bge_vid;
136 uint16_t bge_did;
137 } bge_devs[] = {
138 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
139 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
140
141 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
142 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
143 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
144
145 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
146
147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
233
234 { SK_VENDORID, SK_DEVICEID_ALTIMA },
235
236 { TC_VENDORID, TC_DEVICEID_3C996 },
237
238 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
239 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
240 { 0, 0 }
241 };
242
243 static const struct bge_vendor {
244 uint16_t v_id;
245 const char *v_name;
246 } bge_vendors[] = {
247 { ALTEON_VENDORID, "Alteon" },
248 { ALTIMA_VENDORID, "Altima" },
249 { APPLE_VENDORID, "Apple" },
250 { BCOM_VENDORID, "Broadcom" },
251 { SK_VENDORID, "SysKonnect" },
252 { TC_VENDORID, "3Com" },
253 { FJTSU_VENDORID, "Fujitsu" },
254 { 0, NULL }
255 };
256
257 static const struct bge_revision {
258 uint32_t br_chipid;
259 const char *br_name;
260 } bge_revisions[] = {
261 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
262 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
263 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
264 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
265 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
266 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
267 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
268 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
269 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
270 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
271 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
272 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
273 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
274 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
275 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
276 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
277 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
278 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
279 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
280 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
281 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
282 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
283 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
284 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
285 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
286 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
287 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
288 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
289 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
290 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
291 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
292 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
293 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
294 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
295 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
296 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
297 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
298 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
299 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
300 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
301 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
302 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
303 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
304 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
305 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
306 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" },
307 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
308 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
309 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
310 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
311 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
312 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
313 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
314 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
315 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
316 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
317 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
318 /* 5754 and 5787 share the same ASIC ID */
319 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
320 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
321 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
322 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
323 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
324 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
325 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
326 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
327 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
328 { 0, NULL }
329 };
330
331 /*
332 * Some defaults for major revisions, so that newer steppings
333 * that we don't know about have a shot at working.
334 */
335 static const struct bge_revision bge_majorrevs[] = {
336 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
337 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
338 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
339 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
340 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
341 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
342 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
343 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
344 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
345 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
346 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
347 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
348 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
349 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
350 /* 5754 and 5787 share the same ASIC ID */
351 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
352 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
353 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
354 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
355 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
356 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
357 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
358 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
359 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
360 { 0, NULL }
361 };
362
363 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
364 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
365 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
366 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
367 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
368 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
369 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
370 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
371
372 static uint32_t bge_chipid(device_t);
373 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
374 static const struct bge_revision * bge_lookup_rev(uint32_t);
375
376 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
377
378 static int bge_probe(device_t);
379 static int bge_attach(device_t);
380 static int bge_detach(device_t);
381 static int bge_suspend(device_t);
382 static int bge_resume(device_t);
383 static void bge_release_resources(struct bge_softc *);
384 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
385 static int bge_dma_alloc(struct bge_softc *);
386 static void bge_dma_free(struct bge_softc *);
387 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
388 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
389
390 static void bge_devinfo(struct bge_softc *);
391 static int bge_mbox_reorder(struct bge_softc *);
392
393 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
394 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
395 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
396 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
397 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
398
399 static void bge_txeof(struct bge_softc *, uint16_t);
400 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
401 static int bge_rxeof(struct bge_softc *, uint16_t, int);
402
403 static void bge_asf_driver_up (struct bge_softc *);
404 static void bge_tick(void *);
405 static void bge_stats_clear_regs(struct bge_softc *);
406 static void bge_stats_update(struct bge_softc *);
407 static void bge_stats_update_regs(struct bge_softc *);
408 static struct mbuf *bge_check_short_dma(struct mbuf *);
409 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
410 uint16_t *, uint16_t *);
411 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
412
413 static void bge_intr(void *);
414 static int bge_msi_intr(void *);
415 static void bge_intr_task(void *, int);
416 static void bge_start(if_t);
417 static void bge_start_locked(if_t);
418 static void bge_start_tx(struct bge_softc *, uint32_t);
419 static int bge_ioctl(if_t, u_long, caddr_t);
420 static void bge_init_locked(struct bge_softc *);
421 static void bge_init(void *);
422 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
423 static void bge_stop(struct bge_softc *);
424 static void bge_watchdog(struct bge_softc *);
425 static int bge_shutdown(device_t);
426 static int bge_ifmedia_upd_locked(if_t);
427 static int bge_ifmedia_upd(if_t);
428 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
429 static uint64_t bge_get_counter(if_t, ift_counter);
430
431 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
432 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
433
434 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
435 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
436
437 static void bge_setpromisc(struct bge_softc *);
438 static void bge_setmulti(struct bge_softc *);
439 static void bge_setvlan(struct bge_softc *);
440
441 static __inline void bge_rxreuse_std(struct bge_softc *, int);
442 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
443 static int bge_newbuf_std(struct bge_softc *, int);
444 static int bge_newbuf_jumbo(struct bge_softc *, int);
445 static int bge_init_rx_ring_std(struct bge_softc *);
446 static void bge_free_rx_ring_std(struct bge_softc *);
447 static int bge_init_rx_ring_jumbo(struct bge_softc *);
448 static void bge_free_rx_ring_jumbo(struct bge_softc *);
449 static void bge_free_tx_ring(struct bge_softc *);
450 static int bge_init_tx_ring(struct bge_softc *);
451
452 static int bge_chipinit(struct bge_softc *);
453 static int bge_blockinit(struct bge_softc *);
454 static uint32_t bge_dma_swap_options(struct bge_softc *);
455
456 static int bge_has_eaddr(struct bge_softc *);
457 static uint32_t bge_readmem_ind(struct bge_softc *, int);
458 static void bge_writemem_ind(struct bge_softc *, int, int);
459 static void bge_writembx(struct bge_softc *, int, int);
460 #ifdef notdef
461 static uint32_t bge_readreg_ind(struct bge_softc *, int);
462 #endif
463 static void bge_writemem_direct(struct bge_softc *, int, int);
464 static void bge_writereg_ind(struct bge_softc *, int, int);
465
466 static int bge_miibus_readreg(device_t, int, int);
467 static int bge_miibus_writereg(device_t, int, int, int);
468 static void bge_miibus_statchg(device_t);
469 #ifdef DEVICE_POLLING
470 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
471 #endif
472
473 #define BGE_RESET_SHUTDOWN 0
474 #define BGE_RESET_START 1
475 #define BGE_RESET_SUSPEND 2
476 static void bge_sig_post_reset(struct bge_softc *, int);
477 static void bge_sig_legacy(struct bge_softc *, int);
478 static void bge_sig_pre_reset(struct bge_softc *, int);
479 static void bge_stop_fw(struct bge_softc *);
480 static int bge_reset(struct bge_softc *);
481 static void bge_link_upd(struct bge_softc *);
482
483 static void bge_ape_lock_init(struct bge_softc *);
484 static void bge_ape_read_fw_ver(struct bge_softc *);
485 static int bge_ape_lock(struct bge_softc *, int);
486 static void bge_ape_unlock(struct bge_softc *, int);
487 static void bge_ape_send_event(struct bge_softc *, uint32_t);
488 static void bge_ape_driver_state_change(struct bge_softc *, int);
489
490 /*
491 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
492 * leak information to untrusted users. It is also known to cause alignment
493 * traps on certain architectures.
494 */
495 #ifdef BGE_REGISTER_DEBUG
496 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
497 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
498 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
499 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
500 #endif
501 static void bge_add_sysctls(struct bge_softc *);
502 static void bge_add_sysctl_stats_regs(struct bge_softc *,
503 struct sysctl_ctx_list *, struct sysctl_oid_list *);
504 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
505 struct sysctl_oid_list *);
506 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
507
508 DEBUGNET_DEFINE(bge);
509
510 static device_method_t bge_methods[] = {
511 /* Device interface */
512 DEVMETHOD(device_probe, bge_probe),
513 DEVMETHOD(device_attach, bge_attach),
514 DEVMETHOD(device_detach, bge_detach),
515 DEVMETHOD(device_shutdown, bge_shutdown),
516 DEVMETHOD(device_suspend, bge_suspend),
517 DEVMETHOD(device_resume, bge_resume),
518
519 /* MII interface */
520 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
521 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
522 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
523
524 DEVMETHOD_END
525 };
526
527 static driver_t bge_driver = {
528 "bge",
529 bge_methods,
530 sizeof(struct bge_softc)
531 };
532
533 DRIVER_MODULE(bge, pci, bge_driver, 0, 0);
534 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
535 nitems(bge_devs) - 1);
536 DRIVER_MODULE(miibus, bge, miibus_driver, 0, 0);
537
538 static int bge_allow_asf = 1;
539
540 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
541 "BGE driver parameters");
542 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
543 "Allow ASF mode if available");
544
545 static int
bge_has_eaddr(struct bge_softc * sc)546 bge_has_eaddr(struct bge_softc *sc)
547 {
548 return (1);
549 }
550
551 static uint32_t
bge_readmem_ind(struct bge_softc * sc,int off)552 bge_readmem_ind(struct bge_softc *sc, int off)
553 {
554 device_t dev;
555 uint32_t val;
556
557 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
558 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
559 return (0);
560
561 dev = sc->bge_dev;
562
563 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
564 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
565 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
566 return (val);
567 }
568
569 static void
bge_writemem_ind(struct bge_softc * sc,int off,int val)570 bge_writemem_ind(struct bge_softc *sc, int off, int val)
571 {
572 device_t dev;
573
574 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
575 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
576 return;
577
578 dev = sc->bge_dev;
579
580 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
581 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
582 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
583 }
584
585 #ifdef notdef
586 static uint32_t
bge_readreg_ind(struct bge_softc * sc,int off)587 bge_readreg_ind(struct bge_softc *sc, int off)
588 {
589 device_t dev;
590
591 dev = sc->bge_dev;
592
593 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
594 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
595 }
596 #endif
597
598 static void
bge_writereg_ind(struct bge_softc * sc,int off,int val)599 bge_writereg_ind(struct bge_softc *sc, int off, int val)
600 {
601 device_t dev;
602
603 dev = sc->bge_dev;
604
605 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
606 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
607 }
608
609 static void
bge_writemem_direct(struct bge_softc * sc,int off,int val)610 bge_writemem_direct(struct bge_softc *sc, int off, int val)
611 {
612 CSR_WRITE_4(sc, off, val);
613 }
614
615 static void
bge_writembx(struct bge_softc * sc,int off,int val)616 bge_writembx(struct bge_softc *sc, int off, int val)
617 {
618 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
619 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
620
621 CSR_WRITE_4(sc, off, val);
622 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
623 CSR_READ_4(sc, off);
624 }
625
626 /*
627 * Clear all stale locks and select the lock for this driver instance.
628 */
629 static void
bge_ape_lock_init(struct bge_softc * sc)630 bge_ape_lock_init(struct bge_softc *sc)
631 {
632 uint32_t bit, regbase;
633 int i;
634
635 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
636 regbase = BGE_APE_LOCK_GRANT;
637 else
638 regbase = BGE_APE_PER_LOCK_GRANT;
639
640 /* Clear any stale locks. */
641 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
642 switch (i) {
643 case BGE_APE_LOCK_PHY0:
644 case BGE_APE_LOCK_PHY1:
645 case BGE_APE_LOCK_PHY2:
646 case BGE_APE_LOCK_PHY3:
647 bit = BGE_APE_LOCK_GRANT_DRIVER0;
648 break;
649 default:
650 if (sc->bge_func_addr == 0)
651 bit = BGE_APE_LOCK_GRANT_DRIVER0;
652 else
653 bit = (1 << sc->bge_func_addr);
654 }
655 APE_WRITE_4(sc, regbase + 4 * i, bit);
656 }
657
658 /* Select the PHY lock based on the device's function number. */
659 switch (sc->bge_func_addr) {
660 case 0:
661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
662 break;
663 case 1:
664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
665 break;
666 case 2:
667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
668 break;
669 case 3:
670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
671 break;
672 default:
673 device_printf(sc->bge_dev,
674 "PHY lock not supported on this function\n");
675 }
676 }
677
678 /*
679 * Check for APE firmware, set flags, and print version info.
680 */
681 static void
bge_ape_read_fw_ver(struct bge_softc * sc)682 bge_ape_read_fw_ver(struct bge_softc *sc)
683 {
684 const char *fwtype;
685 uint32_t apedata, features;
686
687 /* Check for a valid APE signature in shared memory. */
688 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
689 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
690 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
691 return;
692 }
693
694 /* Check if APE firmware is running. */
695 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
696 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
697 device_printf(sc->bge_dev, "APE signature found "
698 "but FW status not ready! 0x%08x\n", apedata);
699 return;
700 }
701
702 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
703
704 /* Fetch the APE firmware type and version. */
705 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
706 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
707 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
708 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
709 fwtype = "NCSI";
710 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
711 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
712 fwtype = "DASH";
713 } else
714 fwtype = "UNKN";
715
716 /* Print the APE firmware version. */
717 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
718 fwtype,
719 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
720 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
721 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
722 (apedata & BGE_APE_FW_VERSION_BLDMSK));
723 }
724
725 static int
bge_ape_lock(struct bge_softc * sc,int locknum)726 bge_ape_lock(struct bge_softc *sc, int locknum)
727 {
728 uint32_t bit, gnt, req, status;
729 int i, off;
730
731 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
732 return (0);
733
734 /* Lock request/grant registers have different bases. */
735 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
736 req = BGE_APE_LOCK_REQ;
737 gnt = BGE_APE_LOCK_GRANT;
738 } else {
739 req = BGE_APE_PER_LOCK_REQ;
740 gnt = BGE_APE_PER_LOCK_GRANT;
741 }
742
743 off = 4 * locknum;
744
745 switch (locknum) {
746 case BGE_APE_LOCK_GPIO:
747 /* Lock required when using GPIO. */
748 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
749 return (0);
750 if (sc->bge_func_addr == 0)
751 bit = BGE_APE_LOCK_REQ_DRIVER0;
752 else
753 bit = (1 << sc->bge_func_addr);
754 break;
755 case BGE_APE_LOCK_GRC:
756 /* Lock required to reset the device. */
757 if (sc->bge_func_addr == 0)
758 bit = BGE_APE_LOCK_REQ_DRIVER0;
759 else
760 bit = (1 << sc->bge_func_addr);
761 break;
762 case BGE_APE_LOCK_MEM:
763 /* Lock required when accessing certain APE memory. */
764 if (sc->bge_func_addr == 0)
765 bit = BGE_APE_LOCK_REQ_DRIVER0;
766 else
767 bit = (1 << sc->bge_func_addr);
768 break;
769 case BGE_APE_LOCK_PHY0:
770 case BGE_APE_LOCK_PHY1:
771 case BGE_APE_LOCK_PHY2:
772 case BGE_APE_LOCK_PHY3:
773 /* Lock required when accessing PHYs. */
774 bit = BGE_APE_LOCK_REQ_DRIVER0;
775 break;
776 default:
777 return (EINVAL);
778 }
779
780 /* Request a lock. */
781 APE_WRITE_4(sc, req + off, bit);
782
783 /* Wait up to 1 second to acquire lock. */
784 for (i = 0; i < 20000; i++) {
785 status = APE_READ_4(sc, gnt + off);
786 if (status == bit)
787 break;
788 DELAY(50);
789 }
790
791 /* Handle any errors. */
792 if (status != bit) {
793 device_printf(sc->bge_dev, "APE lock %d request failed! "
794 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
795 locknum, req + off, bit & 0xFFFF, gnt + off,
796 status & 0xFFFF);
797 /* Revoke the lock request. */
798 APE_WRITE_4(sc, gnt + off, bit);
799 return (EBUSY);
800 }
801
802 return (0);
803 }
804
805 static void
bge_ape_unlock(struct bge_softc * sc,int locknum)806 bge_ape_unlock(struct bge_softc *sc, int locknum)
807 {
808 uint32_t bit, gnt;
809 int off;
810
811 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
812 return;
813
814 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
815 gnt = BGE_APE_LOCK_GRANT;
816 else
817 gnt = BGE_APE_PER_LOCK_GRANT;
818
819 off = 4 * locknum;
820
821 switch (locknum) {
822 case BGE_APE_LOCK_GPIO:
823 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
824 return;
825 if (sc->bge_func_addr == 0)
826 bit = BGE_APE_LOCK_GRANT_DRIVER0;
827 else
828 bit = (1 << sc->bge_func_addr);
829 break;
830 case BGE_APE_LOCK_GRC:
831 if (sc->bge_func_addr == 0)
832 bit = BGE_APE_LOCK_GRANT_DRIVER0;
833 else
834 bit = (1 << sc->bge_func_addr);
835 break;
836 case BGE_APE_LOCK_MEM:
837 if (sc->bge_func_addr == 0)
838 bit = BGE_APE_LOCK_GRANT_DRIVER0;
839 else
840 bit = (1 << sc->bge_func_addr);
841 break;
842 case BGE_APE_LOCK_PHY0:
843 case BGE_APE_LOCK_PHY1:
844 case BGE_APE_LOCK_PHY2:
845 case BGE_APE_LOCK_PHY3:
846 bit = BGE_APE_LOCK_GRANT_DRIVER0;
847 break;
848 default:
849 return;
850 }
851
852 APE_WRITE_4(sc, gnt + off, bit);
853 }
854
855 /*
856 * Send an event to the APE firmware.
857 */
858 static void
bge_ape_send_event(struct bge_softc * sc,uint32_t event)859 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
860 {
861 uint32_t apedata;
862 int i;
863
864 /* NCSI does not support APE events. */
865 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
866 return;
867
868 /* Wait up to 1ms for APE to service previous event. */
869 for (i = 10; i > 0; i--) {
870 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
871 break;
872 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
873 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
874 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
875 BGE_APE_EVENT_STATUS_EVENT_PENDING);
876 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
877 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
878 break;
879 }
880 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
881 DELAY(100);
882 }
883 if (i == 0)
884 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
885 event);
886 }
887
888 static void
bge_ape_driver_state_change(struct bge_softc * sc,int kind)889 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
890 {
891 uint32_t apedata, event;
892
893 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
894 return;
895
896 switch (kind) {
897 case BGE_RESET_START:
898 /* If this is the first load, clear the load counter. */
899 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
900 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
901 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
902 else {
903 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
904 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
905 }
906 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
907 BGE_APE_HOST_SEG_SIG_MAGIC);
908 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
909 BGE_APE_HOST_SEG_LEN_MAGIC);
910
911 /* Add some version info if bge(4) supports it. */
912 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
913 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
914 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
915 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
916 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
917 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
918 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
919 BGE_APE_HOST_DRVR_STATE_START);
920 event = BGE_APE_EVENT_STATUS_STATE_START;
921 break;
922 case BGE_RESET_SHUTDOWN:
923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
924 BGE_APE_HOST_DRVR_STATE_UNLOAD);
925 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
926 break;
927 case BGE_RESET_SUSPEND:
928 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
929 break;
930 default:
931 return;
932 }
933
934 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
935 BGE_APE_EVENT_STATUS_STATE_CHNGE);
936 }
937
938 /*
939 * Map a single buffer address.
940 */
941
942 static void
bge_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)943 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
944 {
945 struct bge_dmamap_arg *ctx;
946
947 if (error)
948 return;
949
950 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
951
952 ctx = arg;
953 ctx->bge_busaddr = segs->ds_addr;
954 }
955
956 static uint8_t
bge_nvram_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)957 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
958 {
959 uint32_t access, byte = 0;
960 int i;
961
962 /* Lock. */
963 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
964 for (i = 0; i < 8000; i++) {
965 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
966 break;
967 DELAY(20);
968 }
969 if (i == 8000)
970 return (1);
971
972 /* Enable access. */
973 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
974 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
975
976 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
977 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
978 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
979 DELAY(10);
980 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
981 DELAY(10);
982 break;
983 }
984 }
985
986 if (i == BGE_TIMEOUT * 10) {
987 if_printf(sc->bge_ifp, "nvram read timed out\n");
988 return (1);
989 }
990
991 /* Get result. */
992 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
993
994 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
995
996 /* Disable access. */
997 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
998
999 /* Unlock. */
1000 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1001 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1002
1003 return (0);
1004 }
1005
1006 /*
1007 * Read a sequence of bytes from NVRAM.
1008 */
1009 static int
bge_read_nvram(struct bge_softc * sc,caddr_t dest,int off,int cnt)1010 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1011 {
1012 int err = 0, i;
1013 uint8_t byte = 0;
1014
1015 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1016 return (1);
1017
1018 for (i = 0; i < cnt; i++) {
1019 err = bge_nvram_getbyte(sc, off + i, &byte);
1020 if (err)
1021 break;
1022 *(dest + i) = byte;
1023 }
1024
1025 return (err ? 1 : 0);
1026 }
1027
1028 /*
1029 * Read a byte of data stored in the EEPROM at address 'addr.' The
1030 * BCM570x supports both the traditional bitbang interface and an
1031 * auto access interface for reading the EEPROM. We use the auto
1032 * access method.
1033 */
1034 static uint8_t
bge_eeprom_getbyte(struct bge_softc * sc,int addr,uint8_t * dest)1035 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1036 {
1037 int i;
1038 uint32_t byte = 0;
1039
1040 /*
1041 * Enable use of auto EEPROM access so we can avoid
1042 * having to use the bitbang method.
1043 */
1044 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1045
1046 /* Reset the EEPROM, load the clock period. */
1047 CSR_WRITE_4(sc, BGE_EE_ADDR,
1048 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1049 DELAY(20);
1050
1051 /* Issue the read EEPROM command. */
1052 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1053
1054 /* Wait for completion */
1055 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1056 DELAY(10);
1057 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1058 break;
1059 }
1060
1061 if (i == BGE_TIMEOUT * 10) {
1062 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1063 return (1);
1064 }
1065
1066 /* Get result. */
1067 byte = CSR_READ_4(sc, BGE_EE_DATA);
1068
1069 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1070
1071 return (0);
1072 }
1073
1074 /*
1075 * Read a sequence of bytes from the EEPROM.
1076 */
1077 static int
bge_read_eeprom(struct bge_softc * sc,caddr_t dest,int off,int cnt)1078 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1079 {
1080 int i, error = 0;
1081 uint8_t byte = 0;
1082
1083 for (i = 0; i < cnt; i++) {
1084 error = bge_eeprom_getbyte(sc, off + i, &byte);
1085 if (error)
1086 break;
1087 *(dest + i) = byte;
1088 }
1089
1090 return (error ? 1 : 0);
1091 }
1092
1093 static int
bge_miibus_readreg(device_t dev,int phy,int reg)1094 bge_miibus_readreg(device_t dev, int phy, int reg)
1095 {
1096 struct bge_softc *sc;
1097 uint32_t val;
1098 int i;
1099
1100 sc = device_get_softc(dev);
1101
1102 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1103 return (0);
1104
1105 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1106 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1107 CSR_WRITE_4(sc, BGE_MI_MODE,
1108 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1109 DELAY(80);
1110 }
1111
1112 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1113 BGE_MIPHY(phy) | BGE_MIREG(reg));
1114
1115 /* Poll for the PHY register access to complete. */
1116 for (i = 0; i < BGE_TIMEOUT; i++) {
1117 DELAY(10);
1118 val = CSR_READ_4(sc, BGE_MI_COMM);
1119 if ((val & BGE_MICOMM_BUSY) == 0) {
1120 DELAY(5);
1121 val = CSR_READ_4(sc, BGE_MI_COMM);
1122 break;
1123 }
1124 }
1125
1126 if (i == BGE_TIMEOUT) {
1127 device_printf(sc->bge_dev,
1128 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1129 phy, reg, val);
1130 val = 0;
1131 }
1132
1133 /* Restore the autopoll bit if necessary. */
1134 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1135 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1136 DELAY(80);
1137 }
1138
1139 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1140
1141 if (val & BGE_MICOMM_READFAIL)
1142 return (0);
1143
1144 return (val & 0xFFFF);
1145 }
1146
1147 static int
bge_miibus_writereg(device_t dev,int phy,int reg,int val)1148 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1149 {
1150 struct bge_softc *sc;
1151 int i;
1152
1153 sc = device_get_softc(dev);
1154
1155 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1156 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1157 return (0);
1158
1159 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1160 return (0);
1161
1162 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1163 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1164 CSR_WRITE_4(sc, BGE_MI_MODE,
1165 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1166 DELAY(80);
1167 }
1168
1169 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1170 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1171
1172 for (i = 0; i < BGE_TIMEOUT; i++) {
1173 DELAY(10);
1174 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1175 DELAY(5);
1176 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1177 break;
1178 }
1179 }
1180
1181 /* Restore the autopoll bit if necessary. */
1182 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1183 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1184 DELAY(80);
1185 }
1186
1187 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1188
1189 if (i == BGE_TIMEOUT)
1190 device_printf(sc->bge_dev,
1191 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1192 phy, reg, val);
1193
1194 return (0);
1195 }
1196
1197 static void
bge_miibus_statchg(device_t dev)1198 bge_miibus_statchg(device_t dev)
1199 {
1200 struct bge_softc *sc;
1201 struct mii_data *mii;
1202 uint32_t mac_mode, rx_mode, tx_mode;
1203
1204 sc = device_get_softc(dev);
1205 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1206 return;
1207 mii = device_get_softc(sc->bge_miibus);
1208
1209 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1210 (IFM_ACTIVE | IFM_AVALID)) {
1211 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1212 case IFM_10_T:
1213 case IFM_100_TX:
1214 sc->bge_link = 1;
1215 break;
1216 case IFM_1000_T:
1217 case IFM_1000_SX:
1218 case IFM_2500_SX:
1219 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1220 sc->bge_link = 1;
1221 else
1222 sc->bge_link = 0;
1223 break;
1224 default:
1225 sc->bge_link = 0;
1226 break;
1227 }
1228 } else
1229 sc->bge_link = 0;
1230 if (sc->bge_link == 0)
1231 return;
1232
1233 /*
1234 * APE firmware touches these registers to keep the MAC
1235 * connected to the outside world. Try to keep the
1236 * accesses atomic.
1237 */
1238
1239 /* Set the port mode (MII/GMII) to match the link speed. */
1240 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1241 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1242 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1243 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1244
1245 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1246 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1247 mac_mode |= BGE_PORTMODE_GMII;
1248 else
1249 mac_mode |= BGE_PORTMODE_MII;
1250
1251 /* Set MAC flow control behavior to match link flow control settings. */
1252 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1253 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1254 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1255 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1256 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1257 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1258 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1259 } else
1260 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1261
1262 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1263 DELAY(40);
1264 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1265 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1266 }
1267
1268 /*
1269 * Intialize a standard receive ring descriptor.
1270 */
1271 static int
bge_newbuf_std(struct bge_softc * sc,int i)1272 bge_newbuf_std(struct bge_softc *sc, int i)
1273 {
1274 struct mbuf *m;
1275 struct bge_rx_bd *r;
1276 bus_dma_segment_t segs[1];
1277 bus_dmamap_t map;
1278 int error, nsegs;
1279
1280 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1281 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1282 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1283 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1284 if (m == NULL)
1285 return (ENOBUFS);
1286 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1287 } else {
1288 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1289 if (m == NULL)
1290 return (ENOBUFS);
1291 m->m_len = m->m_pkthdr.len = MCLBYTES;
1292 }
1293 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1294 m_adj(m, ETHER_ALIGN);
1295
1296 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1297 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1298 if (error != 0) {
1299 m_freem(m);
1300 return (error);
1301 }
1302 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1303 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1304 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1305 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1306 sc->bge_cdata.bge_rx_std_dmamap[i]);
1307 }
1308 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1309 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1310 sc->bge_cdata.bge_rx_std_sparemap = map;
1311 sc->bge_cdata.bge_rx_std_chain[i] = m;
1312 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1313 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1314 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1315 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1316 r->bge_flags = BGE_RXBDFLAG_END;
1317 r->bge_len = segs[0].ds_len;
1318 r->bge_idx = i;
1319
1320 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1321 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1322
1323 return (0);
1324 }
1325
1326 /*
1327 * Initialize a jumbo receive ring descriptor. This allocates
1328 * a jumbo buffer from the pool managed internally by the driver.
1329 */
1330 static int
bge_newbuf_jumbo(struct bge_softc * sc,int i)1331 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1332 {
1333 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1334 bus_dmamap_t map;
1335 struct bge_extrx_bd *r;
1336 struct mbuf *m;
1337 int error, nsegs;
1338
1339 MGETHDR(m, M_NOWAIT, MT_DATA);
1340 if (m == NULL)
1341 return (ENOBUFS);
1342
1343 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1344 m_freem(m);
1345 return (ENOBUFS);
1346 }
1347 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1348 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1349 m_adj(m, ETHER_ALIGN);
1350
1351 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1352 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1353 if (error != 0) {
1354 m_freem(m);
1355 return (error);
1356 }
1357
1358 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1359 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1360 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1361 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1362 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1363 }
1364 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1365 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1366 sc->bge_cdata.bge_rx_jumbo_sparemap;
1367 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1368 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1369 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1370 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1371 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1372 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1373
1374 /*
1375 * Fill in the extended RX buffer descriptor.
1376 */
1377 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1378 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1379 r->bge_idx = i;
1380 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1381 switch (nsegs) {
1382 case 4:
1383 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1384 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1385 r->bge_len3 = segs[3].ds_len;
1386 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1387 case 3:
1388 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1389 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1390 r->bge_len2 = segs[2].ds_len;
1391 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1392 case 2:
1393 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1394 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1395 r->bge_len1 = segs[1].ds_len;
1396 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1397 case 1:
1398 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1399 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1400 r->bge_len0 = segs[0].ds_len;
1401 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1402 break;
1403 default:
1404 panic("%s: %d segments\n", __func__, nsegs);
1405 }
1406
1407 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1408 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1409
1410 return (0);
1411 }
1412
1413 static int
bge_init_rx_ring_std(struct bge_softc * sc)1414 bge_init_rx_ring_std(struct bge_softc *sc)
1415 {
1416 int error, i;
1417
1418 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1419 sc->bge_std = 0;
1420 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1421 if ((error = bge_newbuf_std(sc, i)) != 0)
1422 return (error);
1423 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1424 }
1425
1426 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1427 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1428
1429 sc->bge_std = 0;
1430 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1431
1432 return (0);
1433 }
1434
1435 static void
bge_free_rx_ring_std(struct bge_softc * sc)1436 bge_free_rx_ring_std(struct bge_softc *sc)
1437 {
1438 int i;
1439
1440 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1441 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1442 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1443 sc->bge_cdata.bge_rx_std_dmamap[i],
1444 BUS_DMASYNC_POSTREAD);
1445 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1446 sc->bge_cdata.bge_rx_std_dmamap[i]);
1447 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1448 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1449 }
1450 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1451 sizeof(struct bge_rx_bd));
1452 }
1453 }
1454
1455 static int
bge_init_rx_ring_jumbo(struct bge_softc * sc)1456 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1457 {
1458 struct bge_rcb *rcb;
1459 int error, i;
1460
1461 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1462 sc->bge_jumbo = 0;
1463 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1464 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1465 return (error);
1466 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1467 }
1468
1469 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1470 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1471
1472 sc->bge_jumbo = 0;
1473
1474 /* Enable the jumbo receive producer ring. */
1475 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1476 rcb->bge_maxlen_flags =
1477 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1478 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1479
1480 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1481
1482 return (0);
1483 }
1484
1485 static void
bge_free_rx_ring_jumbo(struct bge_softc * sc)1486 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1487 {
1488 int i;
1489
1490 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1491 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1492 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1493 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1494 BUS_DMASYNC_POSTREAD);
1495 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1496 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1497 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1498 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1499 }
1500 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1501 sizeof(struct bge_extrx_bd));
1502 }
1503 }
1504
1505 static void
bge_free_tx_ring(struct bge_softc * sc)1506 bge_free_tx_ring(struct bge_softc *sc)
1507 {
1508 int i;
1509
1510 if (sc->bge_ldata.bge_tx_ring == NULL)
1511 return;
1512
1513 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1514 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1515 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1516 sc->bge_cdata.bge_tx_dmamap[i],
1517 BUS_DMASYNC_POSTWRITE);
1518 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1519 sc->bge_cdata.bge_tx_dmamap[i]);
1520 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1521 sc->bge_cdata.bge_tx_chain[i] = NULL;
1522 }
1523 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1524 sizeof(struct bge_tx_bd));
1525 }
1526 }
1527
1528 static int
bge_init_tx_ring(struct bge_softc * sc)1529 bge_init_tx_ring(struct bge_softc *sc)
1530 {
1531 sc->bge_txcnt = 0;
1532 sc->bge_tx_saved_considx = 0;
1533
1534 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1535 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1536 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1537
1538 /* Initialize transmit producer index for host-memory send ring. */
1539 sc->bge_tx_prodidx = 0;
1540 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1541
1542 /* 5700 b2 errata */
1543 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1544 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1545
1546 /* NIC-memory send ring not used; initialize to zero. */
1547 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1548 /* 5700 b2 errata */
1549 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1550 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1551
1552 return (0);
1553 }
1554
1555 static void
bge_setpromisc(struct bge_softc * sc)1556 bge_setpromisc(struct bge_softc *sc)
1557 {
1558 if_t ifp;
1559
1560 BGE_LOCK_ASSERT(sc);
1561
1562 ifp = sc->bge_ifp;
1563
1564 /* Enable or disable promiscuous mode as needed. */
1565 if (if_getflags(ifp) & IFF_PROMISC)
1566 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1567 else
1568 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1569 }
1570
1571 static u_int
bge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1572 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1573 {
1574 uint32_t *hashes = arg;
1575 int h;
1576
1577 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F;
1578 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1579
1580 return (1);
1581 }
1582
1583 static void
bge_setmulti(struct bge_softc * sc)1584 bge_setmulti(struct bge_softc *sc)
1585 {
1586 if_t ifp;
1587 uint32_t hashes[4] = { 0, 0, 0, 0 };
1588 int i;
1589
1590 BGE_LOCK_ASSERT(sc);
1591
1592 ifp = sc->bge_ifp;
1593
1594 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1595 for (i = 0; i < 4; i++)
1596 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1597 return;
1598 }
1599
1600 /* First, zot all the existing filters. */
1601 for (i = 0; i < 4; i++)
1602 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1603
1604 if_foreach_llmaddr(ifp, bge_hash_maddr, hashes);
1605
1606 for (i = 0; i < 4; i++)
1607 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1608 }
1609
1610 static void
bge_setvlan(struct bge_softc * sc)1611 bge_setvlan(struct bge_softc *sc)
1612 {
1613 if_t ifp;
1614
1615 BGE_LOCK_ASSERT(sc);
1616
1617 ifp = sc->bge_ifp;
1618
1619 /* Enable or disable VLAN tag stripping as needed. */
1620 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1621 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1622 else
1623 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1624 }
1625
1626 static void
bge_sig_pre_reset(struct bge_softc * sc,int type)1627 bge_sig_pre_reset(struct bge_softc *sc, int type)
1628 {
1629
1630 /*
1631 * Some chips don't like this so only do this if ASF is enabled
1632 */
1633 if (sc->bge_asf_mode)
1634 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1635
1636 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1637 switch (type) {
1638 case BGE_RESET_START:
1639 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1640 BGE_FW_DRV_STATE_START);
1641 break;
1642 case BGE_RESET_SHUTDOWN:
1643 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1644 BGE_FW_DRV_STATE_UNLOAD);
1645 break;
1646 case BGE_RESET_SUSPEND:
1647 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1648 BGE_FW_DRV_STATE_SUSPEND);
1649 break;
1650 }
1651 }
1652
1653 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1654 bge_ape_driver_state_change(sc, type);
1655 }
1656
1657 static void
bge_sig_post_reset(struct bge_softc * sc,int type)1658 bge_sig_post_reset(struct bge_softc *sc, int type)
1659 {
1660
1661 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1662 switch (type) {
1663 case BGE_RESET_START:
1664 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1665 BGE_FW_DRV_STATE_START_DONE);
1666 /* START DONE */
1667 break;
1668 case BGE_RESET_SHUTDOWN:
1669 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1670 BGE_FW_DRV_STATE_UNLOAD_DONE);
1671 break;
1672 }
1673 }
1674 if (type == BGE_RESET_SHUTDOWN)
1675 bge_ape_driver_state_change(sc, type);
1676 }
1677
1678 static void
bge_sig_legacy(struct bge_softc * sc,int type)1679 bge_sig_legacy(struct bge_softc *sc, int type)
1680 {
1681
1682 if (sc->bge_asf_mode) {
1683 switch (type) {
1684 case BGE_RESET_START:
1685 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1686 BGE_FW_DRV_STATE_START);
1687 break;
1688 case BGE_RESET_SHUTDOWN:
1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1690 BGE_FW_DRV_STATE_UNLOAD);
1691 break;
1692 }
1693 }
1694 }
1695
1696 static void
bge_stop_fw(struct bge_softc * sc)1697 bge_stop_fw(struct bge_softc *sc)
1698 {
1699 int i;
1700
1701 if (sc->bge_asf_mode) {
1702 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1703 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1704 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1705
1706 for (i = 0; i < 100; i++ ) {
1707 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1708 BGE_RX_CPU_DRV_EVENT))
1709 break;
1710 DELAY(10);
1711 }
1712 }
1713 }
1714
1715 static uint32_t
bge_dma_swap_options(struct bge_softc * sc)1716 bge_dma_swap_options(struct bge_softc *sc)
1717 {
1718 uint32_t dma_options;
1719
1720 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1721 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1722 #if BYTE_ORDER == BIG_ENDIAN
1723 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1724 #endif
1725 return (dma_options);
1726 }
1727
1728 /*
1729 * Do endian, PCI and DMA initialization.
1730 */
1731 static int
bge_chipinit(struct bge_softc * sc)1732 bge_chipinit(struct bge_softc *sc)
1733 {
1734 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1735 uint16_t val;
1736 int i;
1737
1738 /* Set endianness before we access any non-PCI registers. */
1739 misc_ctl = BGE_INIT;
1740 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1741 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1742 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1743
1744 /*
1745 * Clear the MAC statistics block in the NIC's
1746 * internal memory.
1747 */
1748 for (i = BGE_STATS_BLOCK;
1749 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1750 BGE_MEMWIN_WRITE(sc, i, 0);
1751
1752 for (i = BGE_STATUS_BLOCK;
1753 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1754 BGE_MEMWIN_WRITE(sc, i, 0);
1755
1756 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1757 /*
1758 * Fix data corruption caused by non-qword write with WB.
1759 * Fix master abort in PCI mode.
1760 * Fix PCI latency timer.
1761 */
1762 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1763 val |= (1 << 10) | (1 << 12) | (1 << 13);
1764 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1765 }
1766
1767 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1768 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1769 /*
1770 * For the 57766 and non Ax versions of 57765, bootcode
1771 * needs to setup the PCIE Fast Training Sequence (FTS)
1772 * value to prevent transmit hangs.
1773 */
1774 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1775 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1776 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1777 BGE_CPMU_PADRNG_CTL_RDIV2);
1778 }
1779 }
1780
1781 /*
1782 * Set up the PCI DMA control register.
1783 */
1784 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1785 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1786 if (sc->bge_flags & BGE_FLAG_PCIE) {
1787 if (sc->bge_mps >= 256)
1788 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1789 else
1790 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1791 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1792 if (BGE_IS_5714_FAMILY(sc)) {
1793 /* 256 bytes for read and write. */
1794 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1795 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1796 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1797 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1798 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1799 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1800 /*
1801 * In the BCM5703, the DMA read watermark should
1802 * be set to less than or equal to the maximum
1803 * memory read byte count of the PCI-X command
1804 * register.
1805 */
1806 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1807 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1808 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1809 /* 1536 bytes for read, 384 bytes for write. */
1810 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1811 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1812 } else {
1813 /* 384 bytes for read and write. */
1814 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1815 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1816 0x0F;
1817 }
1818 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1819 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1820 uint32_t tmp;
1821
1822 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1823 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1824 if (tmp == 6 || tmp == 7)
1825 dma_rw_ctl |=
1826 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1827
1828 /* Set PCI-X DMA write workaround. */
1829 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1830 }
1831 } else {
1832 /* Conventional PCI bus: 256 bytes for read and write. */
1833 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1834 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1835
1836 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1837 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1838 dma_rw_ctl |= 0x0F;
1839 }
1840 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1841 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1842 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1843 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1844 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1845 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1846 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1847 if (BGE_IS_5717_PLUS(sc)) {
1848 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1849 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1850 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1851 /*
1852 * Enable HW workaround for controllers that misinterpret
1853 * a status tag update and leave interrupts permanently
1854 * disabled.
1855 */
1856 if (!BGE_IS_57765_PLUS(sc) &&
1857 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1858 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1859 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1860 }
1861 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1862
1863 /*
1864 * Set up general mode register.
1865 */
1866 mode_ctl = bge_dma_swap_options(sc);
1867 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1868 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1869 /* Retain Host-2-BMC settings written by APE firmware. */
1870 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1871 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1872 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1873 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1874 }
1875 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1876 BGE_MODECTL_TX_NO_PHDR_CSUM;
1877
1878 /*
1879 * BCM5701 B5 have a bug causing data corruption when using
1880 * 64-bit DMA reads, which can be terminated early and then
1881 * completed later as 32-bit accesses, in combination with
1882 * certain bridges.
1883 */
1884 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1885 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1886 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1887
1888 /*
1889 * Tell the firmware the driver is running
1890 */
1891 if (sc->bge_asf_mode & ASF_STACKUP)
1892 mode_ctl |= BGE_MODECTL_STACKUP;
1893
1894 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1895
1896 /*
1897 * Disable memory write invalidate. Apparently it is not supported
1898 * properly by these devices.
1899 */
1900 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1901
1902 /* Set the timer prescaler (always 66 MHz). */
1903 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1904
1905 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1906 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1907 DELAY(40); /* XXX */
1908
1909 /* Put PHY into ready state */
1910 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1911 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1912 DELAY(40);
1913 }
1914
1915 return (0);
1916 }
1917
1918 static int
bge_blockinit(struct bge_softc * sc)1919 bge_blockinit(struct bge_softc *sc)
1920 {
1921 struct bge_rcb *rcb;
1922 bus_size_t vrcb;
1923 caddr_t lladdr;
1924 bge_hostaddr taddr;
1925 uint32_t dmactl, rdmareg, val;
1926 int i, limit;
1927
1928 /*
1929 * Initialize the memory window pointer register so that
1930 * we can access the first 32K of internal NIC RAM. This will
1931 * allow us to set up the TX send ring RCBs and the RX return
1932 * ring RCBs, plus other things which live in NIC memory.
1933 */
1934 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1935
1936 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1937
1938 if (!(BGE_IS_5705_PLUS(sc))) {
1939 /* Configure mbuf memory pool */
1940 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1941 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1942 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1943 else
1944 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1945
1946 /* Configure DMA resource pool */
1947 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1948 BGE_DMA_DESCRIPTORS);
1949 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1950 }
1951
1952 /* Configure mbuf pool watermarks */
1953 if (BGE_IS_5717_PLUS(sc)) {
1954 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1955 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
1956 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1958 } else {
1959 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1961 }
1962 } else if (!BGE_IS_5705_PLUS(sc)) {
1963 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1964 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1965 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1966 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1967 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1969 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1970 } else {
1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1974 }
1975
1976 /* Configure DMA resource watermarks */
1977 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1978 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1979
1980 /* Enable buffer manager */
1981 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1982 /*
1983 * Change the arbitration algorithm of TXMBUF read request to
1984 * round-robin instead of priority based for BCM5719. When
1985 * TXFIFO is almost empty, RDMA will hold its request until
1986 * TXFIFO is not almost empty.
1987 */
1988 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1989 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1990 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1991
1992 /* Poll for buffer manager start indication */
1993 for (i = 0; i < BGE_TIMEOUT; i++) {
1994 DELAY(10);
1995 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1996 break;
1997 }
1998
1999 if (i == BGE_TIMEOUT) {
2000 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2001 return (ENXIO);
2002 }
2003
2004 /* Enable flow-through queues */
2005 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2006 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2007
2008 /* Wait until queue initialization is complete */
2009 for (i = 0; i < BGE_TIMEOUT; i++) {
2010 DELAY(10);
2011 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2012 break;
2013 }
2014
2015 if (i == BGE_TIMEOUT) {
2016 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2017 return (ENXIO);
2018 }
2019
2020 /*
2021 * Summary of rings supported by the controller:
2022 *
2023 * Standard Receive Producer Ring
2024 * - This ring is used to feed receive buffers for "standard"
2025 * sized frames (typically 1536 bytes) to the controller.
2026 *
2027 * Jumbo Receive Producer Ring
2028 * - This ring is used to feed receive buffers for jumbo sized
2029 * frames (i.e. anything bigger than the "standard" frames)
2030 * to the controller.
2031 *
2032 * Mini Receive Producer Ring
2033 * - This ring is used to feed receive buffers for "mini"
2034 * sized frames to the controller.
2035 * - This feature required external memory for the controller
2036 * but was never used in a production system. Should always
2037 * be disabled.
2038 *
2039 * Receive Return Ring
2040 * - After the controller has placed an incoming frame into a
2041 * receive buffer that buffer is moved into a receive return
2042 * ring. The driver is then responsible to passing the
2043 * buffer up to the stack. Many versions of the controller
2044 * support multiple RR rings.
2045 *
2046 * Send Ring
2047 * - This ring is used for outgoing frames. Many versions of
2048 * the controller support multiple send rings.
2049 */
2050
2051 /* Initialize the standard receive producer ring control block. */
2052 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2053 rcb->bge_hostaddr.bge_addr_lo =
2054 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2055 rcb->bge_hostaddr.bge_addr_hi =
2056 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2057 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2058 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2059 if (BGE_IS_5717_PLUS(sc)) {
2060 /*
2061 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2062 * Bits 15-2 : Maximum RX frame size
2063 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2064 * Bit 0 : Reserved
2065 */
2066 rcb->bge_maxlen_flags =
2067 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2068 } else if (BGE_IS_5705_PLUS(sc)) {
2069 /*
2070 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2071 * Bits 15-2 : Reserved (should be 0)
2072 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2073 * Bit 0 : Reserved
2074 */
2075 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2076 } else {
2077 /*
2078 * Ring size is always XXX entries
2079 * Bits 31-16: Maximum RX frame size
2080 * Bits 15-2 : Reserved (should be 0)
2081 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2082 * Bit 0 : Reserved
2083 */
2084 rcb->bge_maxlen_flags =
2085 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2086 }
2087 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2088 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2089 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2090 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2091 else
2092 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2093 /* Write the standard receive producer ring control block. */
2094 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2095 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2096 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2097 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2098
2099 /* Reset the standard receive producer ring producer index. */
2100 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2101
2102 /*
2103 * Initialize the jumbo RX producer ring control
2104 * block. We set the 'ring disabled' bit in the
2105 * flags field until we're actually ready to start
2106 * using this ring (i.e. once we set the MTU
2107 * high enough to require it).
2108 */
2109 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2110 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2111 /* Get the jumbo receive producer ring RCB parameters. */
2112 rcb->bge_hostaddr.bge_addr_lo =
2113 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2114 rcb->bge_hostaddr.bge_addr_hi =
2115 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2116 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2117 sc->bge_cdata.bge_rx_jumbo_ring_map,
2118 BUS_DMASYNC_PREREAD);
2119 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2120 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2121 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2122 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2123 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2124 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2125 else
2126 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2127 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2128 rcb->bge_hostaddr.bge_addr_hi);
2129 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2130 rcb->bge_hostaddr.bge_addr_lo);
2131 /* Program the jumbo receive producer ring RCB parameters. */
2132 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2133 rcb->bge_maxlen_flags);
2134 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2135 /* Reset the jumbo receive producer ring producer index. */
2136 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2137 }
2138
2139 /* Disable the mini receive producer ring RCB. */
2140 if (BGE_IS_5700_FAMILY(sc)) {
2141 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2142 rcb->bge_maxlen_flags =
2143 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2144 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2145 rcb->bge_maxlen_flags);
2146 /* Reset the mini receive producer ring producer index. */
2147 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2148 }
2149
2150 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2151 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2152 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2153 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2154 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2155 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2156 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2157 }
2158 /*
2159 * The BD ring replenish thresholds control how often the
2160 * hardware fetches new BD's from the producer rings in host
2161 * memory. Setting the value too low on a busy system can
2162 * starve the hardware and reduce the throughput.
2163 *
2164 * Set the BD ring replentish thresholds. The recommended
2165 * values are 1/8th the number of descriptors allocated to
2166 * each ring.
2167 * XXX The 5754 requires a lower threshold, so it might be a
2168 * requirement of all 575x family chips. The Linux driver sets
2169 * the lower threshold for all 5705 family chips as well, but there
2170 * are reports that it might not need to be so strict.
2171 *
2172 * XXX Linux does some extra fiddling here for the 5906 parts as
2173 * well.
2174 */
2175 if (BGE_IS_5705_PLUS(sc))
2176 val = 8;
2177 else
2178 val = BGE_STD_RX_RING_CNT / 8;
2179 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2180 if (BGE_IS_JUMBO_CAPABLE(sc))
2181 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2182 BGE_JUMBO_RX_RING_CNT/8);
2183 if (BGE_IS_5717_PLUS(sc)) {
2184 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2185 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2186 }
2187
2188 /*
2189 * Disable all send rings by setting the 'ring disabled' bit
2190 * in the flags field of all the TX send ring control blocks,
2191 * located in NIC memory.
2192 */
2193 if (!BGE_IS_5705_PLUS(sc))
2194 /* 5700 to 5704 had 16 send rings. */
2195 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2196 else if (BGE_IS_57765_PLUS(sc) ||
2197 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2198 limit = 2;
2199 else if (BGE_IS_5717_PLUS(sc))
2200 limit = 4;
2201 else
2202 limit = 1;
2203 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2204 for (i = 0; i < limit; i++) {
2205 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2206 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2207 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2208 vrcb += sizeof(struct bge_rcb);
2209 }
2210
2211 /* Configure send ring RCB 0 (we use only the first ring) */
2212 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2213 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2214 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2215 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2216 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2217 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2218 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2219 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2220 else
2221 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2222 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2223 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2224 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2225
2226 /*
2227 * Disable all receive return rings by setting the
2228 * 'ring diabled' bit in the flags field of all the receive
2229 * return ring control blocks, located in NIC memory.
2230 */
2231 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2232 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2233 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2234 /* Should be 17, use 16 until we get an SRAM map. */
2235 limit = 16;
2236 } else if (!BGE_IS_5705_PLUS(sc))
2237 limit = BGE_RX_RINGS_MAX;
2238 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2239 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2240 BGE_IS_57765_PLUS(sc))
2241 limit = 4;
2242 else
2243 limit = 1;
2244 /* Disable all receive return rings. */
2245 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2246 for (i = 0; i < limit; i++) {
2247 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2248 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2249 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2250 BGE_RCB_FLAG_RING_DISABLED);
2251 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2252 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2253 (i * (sizeof(uint64_t))), 0);
2254 vrcb += sizeof(struct bge_rcb);
2255 }
2256
2257 /*
2258 * Set up receive return ring 0. Note that the NIC address
2259 * for RX return rings is 0x0. The return rings live entirely
2260 * within the host, so the nicaddr field in the RCB isn't used.
2261 */
2262 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2263 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2264 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2265 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2266 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2267 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2268 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2269
2270 lladdr = if_getlladdr(sc->bge_ifp);
2271 /* Set random backoff seed for TX */
2272 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2273 (lladdr[0] + lladdr[1] +
2274 lladdr[2] + lladdr[3] +
2275 lladdr[4] + lladdr[5]) &
2276 BGE_TX_BACKOFF_SEED_MASK);
2277
2278 /* Set inter-packet gap */
2279 val = 0x2620;
2280 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2281 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2282 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2283 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2284 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2285
2286 /*
2287 * Specify which ring to use for packets that don't match
2288 * any RX rules.
2289 */
2290 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2291
2292 /*
2293 * Configure number of RX lists. One interrupt distribution
2294 * list, sixteen active lists, one bad frames class.
2295 */
2296 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2297
2298 /* Initialize RX list placement stats mask. */
2299 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2300 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2301
2302 /* Disable host coalescing until we get it set up */
2303 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2304
2305 /* Poll to make sure it's shut down. */
2306 for (i = 0; i < BGE_TIMEOUT; i++) {
2307 DELAY(10);
2308 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2309 break;
2310 }
2311
2312 if (i == BGE_TIMEOUT) {
2313 device_printf(sc->bge_dev,
2314 "host coalescing engine failed to idle\n");
2315 return (ENXIO);
2316 }
2317
2318 /* Set up host coalescing defaults */
2319 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2320 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2321 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2322 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2323 if (!(BGE_IS_5705_PLUS(sc))) {
2324 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2325 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2326 }
2327 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2328 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2329
2330 /* Set up address of statistics block */
2331 if (!(BGE_IS_5705_PLUS(sc))) {
2332 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2333 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2334 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2335 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2336 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2337 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2338 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2339 }
2340
2341 /* Set up address of status block */
2342 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2343 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2344 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2345 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2346
2347 /* Set up status block size. */
2348 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2349 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2350 val = BGE_STATBLKSZ_FULL;
2351 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2352 } else {
2353 val = BGE_STATBLKSZ_32BYTE;
2354 bzero(sc->bge_ldata.bge_status_block, 32);
2355 }
2356 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2357 sc->bge_cdata.bge_status_map,
2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2359
2360 /* Turn on host coalescing state machine */
2361 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2362
2363 /* Turn on RX BD completion state machine and enable attentions */
2364 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2365 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2366
2367 /* Turn on RX list placement state machine */
2368 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2369
2370 /* Turn on RX list selector state machine. */
2371 if (!(BGE_IS_5705_PLUS(sc)))
2372 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2373
2374 /* Turn on DMA, clear stats. */
2375 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2376 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2377 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2378 BGE_MACMODE_FRMHDR_DMA_ENB;
2379
2380 if (sc->bge_flags & BGE_FLAG_TBI)
2381 val |= BGE_PORTMODE_TBI;
2382 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2383 val |= BGE_PORTMODE_GMII;
2384 else
2385 val |= BGE_PORTMODE_MII;
2386
2387 /* Allow APE to send/receive frames. */
2388 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2389 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2390
2391 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2392 DELAY(40);
2393
2394 /* Set misc. local control, enable interrupts on attentions */
2395 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2396
2397 #ifdef notdef
2398 /* Assert GPIO pins for PHY reset */
2399 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2400 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2401 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2402 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2403 #endif
2404
2405 /* Turn on DMA completion state machine */
2406 if (!(BGE_IS_5705_PLUS(sc)))
2407 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2408
2409 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2410
2411 /* Enable host coalescing bug fix. */
2412 if (BGE_IS_5755_PLUS(sc))
2413 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2414
2415 /* Request larger DMA burst size to get better performance. */
2416 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2417 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2418
2419 /* Turn on write DMA state machine */
2420 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2421 DELAY(40);
2422
2423 /* Turn on read DMA state machine */
2424 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2425
2426 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2427 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2428
2429 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2430 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2431 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2432 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2433 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2434 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2435 if (sc->bge_flags & BGE_FLAG_PCIE)
2436 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2437 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2438 val |= BGE_RDMAMODE_TSO4_ENABLE;
2439 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2440 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2441 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2442 val |= BGE_RDMAMODE_TSO6_ENABLE;
2443 }
2444
2445 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2446 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2447 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2448 BGE_RDMAMODE_H2BNC_VLAN_DET;
2449 /*
2450 * Allow multiple outstanding read requests from
2451 * non-LSO read DMA engine.
2452 */
2453 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2454 }
2455
2456 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2457 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2458 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2459 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2460 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2461 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2462 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2463 else
2464 rdmareg = BGE_RDMA_RSRVCTRL;
2465 dmactl = CSR_READ_4(sc, rdmareg);
2466 /*
2467 * Adjust tx margin to prevent TX data corruption and
2468 * fix internal FIFO overflow.
2469 */
2470 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2471 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2472 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2473 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2474 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2475 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2476 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2477 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2478 }
2479 /*
2480 * Enable fix for read DMA FIFO overruns.
2481 * The fix is to limit the number of RX BDs
2482 * the hardware would fetch at a fime.
2483 */
2484 CSR_WRITE_4(sc, rdmareg, dmactl |
2485 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2486 }
2487
2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2489 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2490 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2491 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2492 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2493 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2494 /*
2495 * Allow 4KB burst length reads for non-LSO frames.
2496 * Enable 512B burst length reads for buffer descriptors.
2497 */
2498 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2499 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2500 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2501 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2502 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2503 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2504 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2505 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2506 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2507 }
2508
2509 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2510 DELAY(40);
2511
2512 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2513 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2514 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2515 if ((val & 0xFFFF) > BGE_FRAMELEN)
2516 break;
2517 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2518 break;
2519 }
2520 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2521 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2522 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2523 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2524 else
2525 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2526 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2527 }
2528 }
2529
2530 /* Turn on RX data completion state machine */
2531 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2532
2533 /* Turn on RX BD initiator state machine */
2534 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2535
2536 /* Turn on RX data and RX BD initiator state machine */
2537 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2538
2539 /* Turn on Mbuf cluster free state machine */
2540 if (!(BGE_IS_5705_PLUS(sc)))
2541 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2542
2543 /* Turn on send BD completion state machine */
2544 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2545
2546 /* Turn on send data completion state machine */
2547 val = BGE_SDCMODE_ENABLE;
2548 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2549 val |= BGE_SDCMODE_CDELAY;
2550 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2551
2552 /* Turn on send data initiator state machine */
2553 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2554 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2555 BGE_SDIMODE_HW_LSO_PRE_DMA);
2556 else
2557 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2558
2559 /* Turn on send BD initiator state machine */
2560 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2561
2562 /* Turn on send BD selector state machine */
2563 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2564
2565 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2566 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2567 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2568
2569 /* ack/clear link change events */
2570 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2571 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2572 BGE_MACSTAT_LINK_CHANGED);
2573 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2574
2575 /*
2576 * Enable attention when the link has changed state for
2577 * devices that use auto polling.
2578 */
2579 if (sc->bge_flags & BGE_FLAG_TBI) {
2580 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2581 } else {
2582 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2583 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2584 DELAY(80);
2585 }
2586 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2587 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2588 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2589 BGE_EVTENB_MI_INTERRUPT);
2590 }
2591
2592 /*
2593 * Clear any pending link state attention.
2594 * Otherwise some link state change events may be lost until attention
2595 * is cleared by bge_intr() -> bge_link_upd() sequence.
2596 * It's not necessary on newer BCM chips - perhaps enabling link
2597 * state change attentions implies clearing pending attention.
2598 */
2599 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2600 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2601 BGE_MACSTAT_LINK_CHANGED);
2602
2603 /* Enable link state change attentions. */
2604 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2605
2606 return (0);
2607 }
2608
2609 static const struct bge_revision *
bge_lookup_rev(uint32_t chipid)2610 bge_lookup_rev(uint32_t chipid)
2611 {
2612 const struct bge_revision *br;
2613
2614 for (br = bge_revisions; br->br_name != NULL; br++) {
2615 if (br->br_chipid == chipid)
2616 return (br);
2617 }
2618
2619 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2620 if (br->br_chipid == BGE_ASICREV(chipid))
2621 return (br);
2622 }
2623
2624 return (NULL);
2625 }
2626
2627 static const struct bge_vendor *
bge_lookup_vendor(uint16_t vid)2628 bge_lookup_vendor(uint16_t vid)
2629 {
2630 const struct bge_vendor *v;
2631
2632 for (v = bge_vendors; v->v_name != NULL; v++)
2633 if (v->v_id == vid)
2634 return (v);
2635
2636 return (NULL);
2637 }
2638
2639 static uint32_t
bge_chipid(device_t dev)2640 bge_chipid(device_t dev)
2641 {
2642 uint32_t id;
2643
2644 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2645 BGE_PCIMISCCTL_ASICREV_SHIFT;
2646 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2647 /*
2648 * Find the ASCI revision. Different chips use different
2649 * registers.
2650 */
2651 switch (pci_get_device(dev)) {
2652 case BCOM_DEVICEID_BCM5717C:
2653 /* 5717 C0 seems to belong to 5720 line. */
2654 id = BGE_CHIPID_BCM5720_A0;
2655 break;
2656 case BCOM_DEVICEID_BCM5717:
2657 case BCOM_DEVICEID_BCM5718:
2658 case BCOM_DEVICEID_BCM5719:
2659 case BCOM_DEVICEID_BCM5720:
2660 case BCOM_DEVICEID_BCM5725:
2661 case BCOM_DEVICEID_BCM5727:
2662 case BCOM_DEVICEID_BCM5762:
2663 case BCOM_DEVICEID_BCM57764:
2664 case BCOM_DEVICEID_BCM57767:
2665 case BCOM_DEVICEID_BCM57787:
2666 id = pci_read_config(dev,
2667 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2668 break;
2669 case BCOM_DEVICEID_BCM57761:
2670 case BCOM_DEVICEID_BCM57762:
2671 case BCOM_DEVICEID_BCM57765:
2672 case BCOM_DEVICEID_BCM57766:
2673 case BCOM_DEVICEID_BCM57781:
2674 case BCOM_DEVICEID_BCM57782:
2675 case BCOM_DEVICEID_BCM57785:
2676 case BCOM_DEVICEID_BCM57786:
2677 case BCOM_DEVICEID_BCM57791:
2678 case BCOM_DEVICEID_BCM57795:
2679 id = pci_read_config(dev,
2680 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2681 break;
2682 default:
2683 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2684 }
2685 }
2686 return (id);
2687 }
2688
2689 /*
2690 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2691 * against our list and return its name if we find a match.
2692 *
2693 * Note that since the Broadcom controller contains VPD support, we
2694 * try to get the device name string from the controller itself instead
2695 * of the compiled-in string. It guarantees we'll always announce the
2696 * right product name. We fall back to the compiled-in string when
2697 * VPD is unavailable or corrupt.
2698 */
2699 static int
bge_probe(device_t dev)2700 bge_probe(device_t dev)
2701 {
2702 char model[64];
2703 const struct bge_revision *br;
2704 const char *pname;
2705 struct bge_softc *sc;
2706 const struct bge_type *t = bge_devs;
2707 const struct bge_vendor *v;
2708 uint32_t id;
2709 uint16_t did, vid;
2710
2711 sc = device_get_softc(dev);
2712 sc->bge_dev = dev;
2713 vid = pci_get_vendor(dev);
2714 did = pci_get_device(dev);
2715 while(t->bge_vid != 0) {
2716 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2717 id = bge_chipid(dev);
2718 br = bge_lookup_rev(id);
2719 if (bge_has_eaddr(sc) &&
2720 pci_get_vpd_ident(dev, &pname) == 0)
2721 snprintf(model, sizeof(model), "%s", pname);
2722 else {
2723 v = bge_lookup_vendor(vid);
2724 snprintf(model, sizeof(model), "%s %s",
2725 v != NULL ? v->v_name : "Unknown",
2726 br != NULL ? br->br_name :
2727 "NetXtreme/NetLink Ethernet Controller");
2728 }
2729 device_set_descf(dev, "%s, %sASIC rev. %#08x",
2730 model, br != NULL ? "" : "unknown ", id);
2731 return (BUS_PROBE_DEFAULT);
2732 }
2733 t++;
2734 }
2735
2736 return (ENXIO);
2737 }
2738
2739 static void
bge_dma_free(struct bge_softc * sc)2740 bge_dma_free(struct bge_softc *sc)
2741 {
2742 int i;
2743
2744 /* Destroy DMA maps for RX buffers. */
2745 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2746 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2747 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2748 sc->bge_cdata.bge_rx_std_dmamap[i]);
2749 }
2750 if (sc->bge_cdata.bge_rx_std_sparemap)
2751 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2752 sc->bge_cdata.bge_rx_std_sparemap);
2753
2754 /* Destroy DMA maps for jumbo RX buffers. */
2755 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2756 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2757 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2758 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2759 }
2760 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2761 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2762 sc->bge_cdata.bge_rx_jumbo_sparemap);
2763
2764 /* Destroy DMA maps for TX buffers. */
2765 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2766 if (sc->bge_cdata.bge_tx_dmamap[i])
2767 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2768 sc->bge_cdata.bge_tx_dmamap[i]);
2769 }
2770
2771 if (sc->bge_cdata.bge_rx_mtag)
2772 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2773 if (sc->bge_cdata.bge_mtag_jumbo)
2774 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2775 if (sc->bge_cdata.bge_tx_mtag)
2776 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2777
2778 /* Destroy standard RX ring. */
2779 if (sc->bge_ldata.bge_rx_std_ring_paddr)
2780 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2781 sc->bge_cdata.bge_rx_std_ring_map);
2782 if (sc->bge_ldata.bge_rx_std_ring)
2783 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2784 sc->bge_ldata.bge_rx_std_ring,
2785 sc->bge_cdata.bge_rx_std_ring_map);
2786
2787 if (sc->bge_cdata.bge_rx_std_ring_tag)
2788 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2789
2790 /* Destroy jumbo RX ring. */
2791 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2792 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2793 sc->bge_cdata.bge_rx_jumbo_ring_map);
2794
2795 if (sc->bge_ldata.bge_rx_jumbo_ring)
2796 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2797 sc->bge_ldata.bge_rx_jumbo_ring,
2798 sc->bge_cdata.bge_rx_jumbo_ring_map);
2799
2800 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2801 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2802
2803 /* Destroy RX return ring. */
2804 if (sc->bge_ldata.bge_rx_return_ring_paddr)
2805 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2806 sc->bge_cdata.bge_rx_return_ring_map);
2807
2808 if (sc->bge_ldata.bge_rx_return_ring)
2809 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2810 sc->bge_ldata.bge_rx_return_ring,
2811 sc->bge_cdata.bge_rx_return_ring_map);
2812
2813 if (sc->bge_cdata.bge_rx_return_ring_tag)
2814 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2815
2816 /* Destroy TX ring. */
2817 if (sc->bge_ldata.bge_tx_ring_paddr)
2818 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2819 sc->bge_cdata.bge_tx_ring_map);
2820
2821 if (sc->bge_ldata.bge_tx_ring)
2822 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2823 sc->bge_ldata.bge_tx_ring,
2824 sc->bge_cdata.bge_tx_ring_map);
2825
2826 if (sc->bge_cdata.bge_tx_ring_tag)
2827 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2828
2829 /* Destroy status block. */
2830 if (sc->bge_ldata.bge_status_block_paddr)
2831 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2832 sc->bge_cdata.bge_status_map);
2833
2834 if (sc->bge_ldata.bge_status_block)
2835 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2836 sc->bge_ldata.bge_status_block,
2837 sc->bge_cdata.bge_status_map);
2838
2839 if (sc->bge_cdata.bge_status_tag)
2840 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2841
2842 /* Destroy statistics block. */
2843 if (sc->bge_ldata.bge_stats_paddr)
2844 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2845 sc->bge_cdata.bge_stats_map);
2846
2847 if (sc->bge_ldata.bge_stats)
2848 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2849 sc->bge_ldata.bge_stats,
2850 sc->bge_cdata.bge_stats_map);
2851
2852 if (sc->bge_cdata.bge_stats_tag)
2853 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2854
2855 if (sc->bge_cdata.bge_buffer_tag)
2856 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2857
2858 /* Destroy the parent tag. */
2859 if (sc->bge_cdata.bge_parent_tag)
2860 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2861 }
2862
2863 static int
bge_dma_ring_alloc(struct bge_softc * sc,bus_size_t alignment,bus_size_t maxsize,bus_dma_tag_t * tag,uint8_t ** ring,bus_dmamap_t * map,bus_addr_t * paddr,const char * msg)2864 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2865 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2866 bus_addr_t *paddr, const char *msg)
2867 {
2868 struct bge_dmamap_arg ctx;
2869 bus_addr_t lowaddr;
2870 bus_size_t ring_end;
2871 int error;
2872
2873 lowaddr = BUS_SPACE_MAXADDR;
2874 again:
2875 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2876 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2877 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2878 if (error != 0) {
2879 device_printf(sc->bge_dev,
2880 "could not create %s dma tag\n", msg);
2881 return (ENOMEM);
2882 }
2883 /* Allocate DMA'able memory for ring. */
2884 error = bus_dmamem_alloc(*tag, (void **)ring,
2885 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2886 if (error != 0) {
2887 device_printf(sc->bge_dev,
2888 "could not allocate DMA'able memory for %s\n", msg);
2889 return (ENOMEM);
2890 }
2891 /* Load the address of the ring. */
2892 ctx.bge_busaddr = 0;
2893 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2894 &ctx, BUS_DMA_NOWAIT);
2895 if (error != 0) {
2896 device_printf(sc->bge_dev,
2897 "could not load DMA'able memory for %s\n", msg);
2898 return (ENOMEM);
2899 }
2900 *paddr = ctx.bge_busaddr;
2901 ring_end = *paddr + maxsize;
2902 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2903 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2904 /*
2905 * 4GB boundary crossed. Limit maximum allowable DMA
2906 * address space to 32bit and try again.
2907 */
2908 bus_dmamap_unload(*tag, *map);
2909 bus_dmamem_free(*tag, *ring, *map);
2910 bus_dma_tag_destroy(*tag);
2911 if (bootverbose)
2912 device_printf(sc->bge_dev, "4GB boundary crossed, "
2913 "limit DMA address space to 32bit for %s\n", msg);
2914 *ring = NULL;
2915 *tag = NULL;
2916 *map = NULL;
2917 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2918 goto again;
2919 }
2920 return (0);
2921 }
2922
2923 static int
bge_dma_alloc(struct bge_softc * sc)2924 bge_dma_alloc(struct bge_softc *sc)
2925 {
2926 bus_addr_t lowaddr;
2927 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2928 int i, error;
2929
2930 lowaddr = BUS_SPACE_MAXADDR;
2931 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2932 lowaddr = BGE_DMA_MAXADDR;
2933 /*
2934 * Allocate the parent bus DMA tag appropriate for PCI.
2935 */
2936 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2937 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2938 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2939 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2940 if (error != 0) {
2941 device_printf(sc->bge_dev,
2942 "could not allocate parent dma tag\n");
2943 return (ENOMEM);
2944 }
2945
2946 /* Create tag for standard RX ring. */
2947 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2948 &sc->bge_cdata.bge_rx_std_ring_tag,
2949 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2950 &sc->bge_cdata.bge_rx_std_ring_map,
2951 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2952 if (error)
2953 return (error);
2954
2955 /* Create tag for RX return ring. */
2956 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2957 &sc->bge_cdata.bge_rx_return_ring_tag,
2958 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2959 &sc->bge_cdata.bge_rx_return_ring_map,
2960 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2961 if (error)
2962 return (error);
2963
2964 /* Create tag for TX ring. */
2965 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2966 &sc->bge_cdata.bge_tx_ring_tag,
2967 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2968 &sc->bge_cdata.bge_tx_ring_map,
2969 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2970 if (error)
2971 return (error);
2972
2973 /*
2974 * Create tag for status block.
2975 * Because we only use single Tx/Rx/Rx return ring, use
2976 * minimum status block size except BCM5700 AX/BX which
2977 * seems to want to see full status block size regardless
2978 * of configured number of ring.
2979 */
2980 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2981 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2982 sbsz = BGE_STATUS_BLK_SZ;
2983 else
2984 sbsz = 32;
2985 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2986 &sc->bge_cdata.bge_status_tag,
2987 (uint8_t **)&sc->bge_ldata.bge_status_block,
2988 &sc->bge_cdata.bge_status_map,
2989 &sc->bge_ldata.bge_status_block_paddr, "status block");
2990 if (error)
2991 return (error);
2992
2993 /* Create tag for statistics block. */
2994 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2995 &sc->bge_cdata.bge_stats_tag,
2996 (uint8_t **)&sc->bge_ldata.bge_stats,
2997 &sc->bge_cdata.bge_stats_map,
2998 &sc->bge_ldata.bge_stats_paddr, "statistics block");
2999 if (error)
3000 return (error);
3001
3002 /* Create tag for jumbo RX ring. */
3003 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3004 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3005 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3006 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3007 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3008 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3009 if (error)
3010 return (error);
3011 }
3012
3013 /* Create parent tag for buffers. */
3014 boundary = 0;
3015 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3016 boundary = BGE_DMA_BNDRY;
3017 /*
3018 * XXX
3019 * watchdog timeout issue was observed on BCM5704 which
3020 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3021 * Both limiting DMA address space to 32bits and flushing
3022 * mailbox write seem to address the issue.
3023 */
3024 if (sc->bge_pcixcap != 0)
3025 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3026 }
3027 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3028 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
3029 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3030 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3031 if (error != 0) {
3032 device_printf(sc->bge_dev,
3033 "could not allocate buffer dma tag\n");
3034 return (ENOMEM);
3035 }
3036 /* Create tag for Tx mbufs. */
3037 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3038 txsegsz = BGE_TSOSEG_SZ;
3039 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3040 } else {
3041 txsegsz = MCLBYTES;
3042 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3043 }
3044 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3045 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3046 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3047 &sc->bge_cdata.bge_tx_mtag);
3048
3049 if (error) {
3050 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3051 return (ENOMEM);
3052 }
3053
3054 /* Create tag for Rx mbufs. */
3055 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3056 rxmaxsegsz = MJUM9BYTES;
3057 else
3058 rxmaxsegsz = MCLBYTES;
3059 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3060 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3061 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3062
3063 if (error) {
3064 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3065 return (ENOMEM);
3066 }
3067
3068 /* Create DMA maps for RX buffers. */
3069 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3070 &sc->bge_cdata.bge_rx_std_sparemap);
3071 if (error) {
3072 device_printf(sc->bge_dev,
3073 "can't create spare DMA map for RX\n");
3074 return (ENOMEM);
3075 }
3076 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3077 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3078 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3079 if (error) {
3080 device_printf(sc->bge_dev,
3081 "can't create DMA map for RX\n");
3082 return (ENOMEM);
3083 }
3084 }
3085
3086 /* Create DMA maps for TX buffers. */
3087 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3088 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3089 &sc->bge_cdata.bge_tx_dmamap[i]);
3090 if (error) {
3091 device_printf(sc->bge_dev,
3092 "can't create DMA map for TX\n");
3093 return (ENOMEM);
3094 }
3095 }
3096
3097 /* Create tags for jumbo RX buffers. */
3098 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3099 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3100 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3101 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3102 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3103 if (error) {
3104 device_printf(sc->bge_dev,
3105 "could not allocate jumbo dma tag\n");
3106 return (ENOMEM);
3107 }
3108 /* Create DMA maps for jumbo RX buffers. */
3109 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3110 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3111 if (error) {
3112 device_printf(sc->bge_dev,
3113 "can't create spare DMA map for jumbo RX\n");
3114 return (ENOMEM);
3115 }
3116 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3117 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3118 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3119 if (error) {
3120 device_printf(sc->bge_dev,
3121 "can't create DMA map for jumbo RX\n");
3122 return (ENOMEM);
3123 }
3124 }
3125 }
3126
3127 return (0);
3128 }
3129
3130 /*
3131 * Return true if this device has more than one port.
3132 */
3133 static int
bge_has_multiple_ports(struct bge_softc * sc)3134 bge_has_multiple_ports(struct bge_softc *sc)
3135 {
3136 device_t dev = sc->bge_dev;
3137 u_int b, d, f, fscan, s;
3138
3139 d = pci_get_domain(dev);
3140 b = pci_get_bus(dev);
3141 s = pci_get_slot(dev);
3142 f = pci_get_function(dev);
3143 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3144 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3145 return (1);
3146 return (0);
3147 }
3148
3149 /*
3150 * Return true if MSI can be used with this device.
3151 */
3152 static int
bge_can_use_msi(struct bge_softc * sc)3153 bge_can_use_msi(struct bge_softc *sc)
3154 {
3155 int can_use_msi = 0;
3156
3157 if (sc->bge_msi == 0)
3158 return (0);
3159
3160 /* Disable MSI for polling(4). */
3161 #ifdef DEVICE_POLLING
3162 return (0);
3163 #endif
3164 switch (sc->bge_asicrev) {
3165 case BGE_ASICREV_BCM5714_A0:
3166 case BGE_ASICREV_BCM5714:
3167 /*
3168 * Apparently, MSI doesn't work when these chips are
3169 * configured in single-port mode.
3170 */
3171 if (bge_has_multiple_ports(sc))
3172 can_use_msi = 1;
3173 break;
3174 case BGE_ASICREV_BCM5750:
3175 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3176 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3177 can_use_msi = 1;
3178 break;
3179 case BGE_ASICREV_BCM5784:
3180 /*
3181 * Prevent infinite "watchdog timeout" errors
3182 * in some MacBook Pro and make it work out-of-the-box.
3183 */
3184 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3185 break;
3186 /* FALLTHROUGH */
3187 default:
3188 if (BGE_IS_575X_PLUS(sc))
3189 can_use_msi = 1;
3190 }
3191 return (can_use_msi);
3192 }
3193
3194 static int
bge_mbox_reorder(struct bge_softc * sc)3195 bge_mbox_reorder(struct bge_softc *sc)
3196 {
3197 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3198 static const struct mbox_reorder {
3199 const uint16_t vendor;
3200 const uint16_t device;
3201 const char *desc;
3202 } mbox_reorder_lists[] = {
3203 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3204 };
3205 device_t dev;
3206 int i;
3207
3208 dev = sc->bge_dev;
3209 for (;;) {
3210 dev = device_get_parent(device_get_parent(dev));
3211 if (!is_pci_device(dev))
3212 break;
3213 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3214 if (pci_get_vendor(dev) ==
3215 mbox_reorder_lists[i].vendor &&
3216 pci_get_device(dev) ==
3217 mbox_reorder_lists[i].device) {
3218 device_printf(sc->bge_dev,
3219 "enabling MBOX workaround for %s\n",
3220 mbox_reorder_lists[i].desc);
3221 return (1);
3222 }
3223 }
3224 }
3225 return (0);
3226 }
3227
3228 static void
bge_devinfo(struct bge_softc * sc)3229 bge_devinfo(struct bge_softc *sc)
3230 {
3231 uint32_t cfg, clk;
3232
3233 device_printf(sc->bge_dev,
3234 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3235 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3236 if (sc->bge_flags & BGE_FLAG_PCIE)
3237 printf("PCI-E\n");
3238 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3239 printf("PCI-X ");
3240 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3241 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3242 clk = 133;
3243 else {
3244 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3245 switch (clk) {
3246 case 0:
3247 clk = 33;
3248 break;
3249 case 2:
3250 clk = 50;
3251 break;
3252 case 4:
3253 clk = 66;
3254 break;
3255 case 6:
3256 clk = 100;
3257 break;
3258 case 7:
3259 clk = 133;
3260 break;
3261 }
3262 }
3263 printf("%u MHz\n", clk);
3264 } else {
3265 if (sc->bge_pcixcap != 0)
3266 printf("PCI on PCI-X ");
3267 else
3268 printf("PCI ");
3269 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3270 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3271 clk = 66;
3272 else
3273 clk = 33;
3274 if (cfg & BGE_PCISTATE_32BIT_BUS)
3275 printf("%u MHz; 32bit\n", clk);
3276 else
3277 printf("%u MHz; 64bit\n", clk);
3278 }
3279 }
3280
3281 static int
bge_attach(device_t dev)3282 bge_attach(device_t dev)
3283 {
3284 if_t ifp;
3285 struct bge_softc *sc;
3286 uint32_t hwcfg = 0, misccfg, pcistate;
3287 u_char eaddr[ETHER_ADDR_LEN];
3288 int capmask, error, reg, rid, trys;
3289
3290 sc = device_get_softc(dev);
3291 sc->bge_dev = dev;
3292
3293 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3294 NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3295 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3296
3297 pci_enable_busmaster(dev);
3298
3299 /*
3300 * Allocate control/status registers.
3301 */
3302 rid = PCIR_BAR(0);
3303 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3304 RF_ACTIVE);
3305
3306 if (sc->bge_res == NULL) {
3307 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3308 error = ENXIO;
3309 goto fail;
3310 }
3311
3312 /* Save various chip information. */
3313 sc->bge_func_addr = pci_get_function(dev);
3314 sc->bge_chipid = bge_chipid(dev);
3315 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3316 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3317
3318 /* Set default PHY address. */
3319 sc->bge_phy_addr = 1;
3320 /*
3321 * PHY address mapping for various devices.
3322 *
3323 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3324 * ---------+-------+-------+-------+-------+
3325 * BCM57XX | 1 | X | X | X |
3326 * BCM5704 | 1 | X | 1 | X |
3327 * BCM5717 | 1 | 8 | 2 | 9 |
3328 * BCM5719 | 1 | 8 | 2 | 9 |
3329 * BCM5720 | 1 | 8 | 2 | 9 |
3330 *
3331 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3332 * ---------+-------+-------+-------+-------+
3333 * BCM57XX | X | X | X | X |
3334 * BCM5704 | X | X | X | X |
3335 * BCM5717 | X | X | X | X |
3336 * BCM5719 | 3 | 10 | 4 | 11 |
3337 * BCM5720 | X | X | X | X |
3338 *
3339 * Other addresses may respond but they are not
3340 * IEEE compliant PHYs and should be ignored.
3341 */
3342 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3343 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3344 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3345 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3346 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3347 BGE_SGDIGSTS_IS_SERDES)
3348 sc->bge_phy_addr = sc->bge_func_addr + 8;
3349 else
3350 sc->bge_phy_addr = sc->bge_func_addr + 1;
3351 } else {
3352 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3353 BGE_CPMU_PHY_STRAP_IS_SERDES)
3354 sc->bge_phy_addr = sc->bge_func_addr + 8;
3355 else
3356 sc->bge_phy_addr = sc->bge_func_addr + 1;
3357 }
3358 }
3359
3360 if (bge_has_eaddr(sc))
3361 sc->bge_flags |= BGE_FLAG_EADDR;
3362
3363 /* Save chipset family. */
3364 switch (sc->bge_asicrev) {
3365 case BGE_ASICREV_BCM5762:
3366 case BGE_ASICREV_BCM57765:
3367 case BGE_ASICREV_BCM57766:
3368 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3369 /* FALLTHROUGH */
3370 case BGE_ASICREV_BCM5717:
3371 case BGE_ASICREV_BCM5719:
3372 case BGE_ASICREV_BCM5720:
3373 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3374 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3375 BGE_FLAG_JUMBO_FRAME;
3376 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3377 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3378 /*
3379 * Enable work around for DMA engine miscalculation
3380 * of TXMBUF available space.
3381 */
3382 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3383 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3384 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3385 /* Jumbo frame on BCM5719 A0 does not work. */
3386 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3387 }
3388 }
3389 break;
3390 case BGE_ASICREV_BCM5755:
3391 case BGE_ASICREV_BCM5761:
3392 case BGE_ASICREV_BCM5784:
3393 case BGE_ASICREV_BCM5785:
3394 case BGE_ASICREV_BCM5787:
3395 case BGE_ASICREV_BCM57780:
3396 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3397 BGE_FLAG_5705_PLUS;
3398 break;
3399 case BGE_ASICREV_BCM5700:
3400 case BGE_ASICREV_BCM5701:
3401 case BGE_ASICREV_BCM5703:
3402 case BGE_ASICREV_BCM5704:
3403 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3404 break;
3405 case BGE_ASICREV_BCM5714_A0:
3406 case BGE_ASICREV_BCM5780:
3407 case BGE_ASICREV_BCM5714:
3408 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3409 /* FALLTHROUGH */
3410 case BGE_ASICREV_BCM5750:
3411 case BGE_ASICREV_BCM5752:
3412 case BGE_ASICREV_BCM5906:
3413 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3414 /* FALLTHROUGH */
3415 case BGE_ASICREV_BCM5705:
3416 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3417 break;
3418 }
3419
3420 /* Identify chips with APE processor. */
3421 switch (sc->bge_asicrev) {
3422 case BGE_ASICREV_BCM5717:
3423 case BGE_ASICREV_BCM5719:
3424 case BGE_ASICREV_BCM5720:
3425 case BGE_ASICREV_BCM5761:
3426 case BGE_ASICREV_BCM5762:
3427 sc->bge_flags |= BGE_FLAG_APE;
3428 break;
3429 }
3430
3431 /* Chips with APE need BAR2 access for APE registers/memory. */
3432 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3433 rid = PCIR_BAR(2);
3434 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3435 RF_ACTIVE);
3436 if (sc->bge_res2 == NULL) {
3437 device_printf (sc->bge_dev,
3438 "couldn't map BAR2 memory\n");
3439 error = ENXIO;
3440 goto fail;
3441 }
3442
3443 /* Enable APE register/memory access by host driver. */
3444 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3445 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3446 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3447 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3448 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3449
3450 bge_ape_lock_init(sc);
3451 bge_ape_read_fw_ver(sc);
3452 }
3453
3454 /* Add SYSCTLs, requires the chipset family to be set. */
3455 bge_add_sysctls(sc);
3456
3457 /* Identify the chips that use an CPMU. */
3458 if (BGE_IS_5717_PLUS(sc) ||
3459 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3460 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3461 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3462 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3463 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3464 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3465 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3466 else
3467 sc->bge_mi_mode = BGE_MIMODE_BASE;
3468 /* Enable auto polling for BCM570[0-5]. */
3469 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3470 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3471
3472 /*
3473 * All Broadcom controllers have 4GB boundary DMA bug.
3474 * Whenever an address crosses a multiple of the 4GB boundary
3475 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3476 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3477 * state machine will lockup and cause the device to hang.
3478 */
3479 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3480
3481 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3482 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3483 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3484
3485 /*
3486 * BCM5719 cannot handle DMA requests for DMA segments that
3487 * have larger than 4KB in size. However the maximum DMA
3488 * segment size created in DMA tag is 4KB for TSO, so we
3489 * wouldn't encounter the issue here.
3490 */
3491 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3492 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3493
3494 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3495 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3496 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3497 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3498 sc->bge_flags |= BGE_FLAG_5788;
3499 }
3500
3501 capmask = BMSR_DEFCAPMASK;
3502 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3503 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3504 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3505 pci_get_vendor(dev) == BCOM_VENDORID &&
3506 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3507 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3508 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3509 (pci_get_vendor(dev) == BCOM_VENDORID &&
3510 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3511 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3512 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3513 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3514 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3515 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3516 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3517 /* These chips are 10/100 only. */
3518 capmask &= ~BMSR_EXTSTAT;
3519 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3520 }
3521
3522 /*
3523 * Some controllers seem to require a special firmware to use
3524 * TSO. But the firmware is not available to FreeBSD and Linux
3525 * claims that the TSO performed by the firmware is slower than
3526 * hardware based TSO. Moreover the firmware based TSO has one
3527 * known bug which can't handle TSO if Ethernet header + IP/TCP
3528 * header is greater than 80 bytes. A workaround for the TSO
3529 * bug exist but it seems it's too expensive than not using
3530 * TSO at all. Some hardware also have the TSO bug so limit
3531 * the TSO to the controllers that are not affected TSO issues
3532 * (e.g. 5755 or higher).
3533 */
3534 if (BGE_IS_5717_PLUS(sc)) {
3535 /* BCM5717 requires different TSO configuration. */
3536 sc->bge_flags |= BGE_FLAG_TSO3;
3537 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3538 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3539 /* TSO on BCM5719 A0 does not work. */
3540 sc->bge_flags &= ~BGE_FLAG_TSO3;
3541 }
3542 } else if (BGE_IS_5755_PLUS(sc)) {
3543 /*
3544 * BCM5754 and BCM5787 shares the same ASIC id so
3545 * explicit device id check is required.
3546 * Due to unknown reason TSO does not work on BCM5755M.
3547 */
3548 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3549 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3550 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3551 sc->bge_flags |= BGE_FLAG_TSO;
3552 }
3553
3554 /*
3555 * Check if this is a PCI-X or PCI Express device.
3556 */
3557 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3558 /*
3559 * Found a PCI Express capabilities register, this
3560 * must be a PCI Express device.
3561 */
3562 sc->bge_flags |= BGE_FLAG_PCIE;
3563 sc->bge_expcap = reg;
3564 /* Extract supported maximum payload size. */
3565 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3566 PCIER_DEVICE_CAP, 2);
3567 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3568 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3569 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3570 sc->bge_expmrq = 2048;
3571 else
3572 sc->bge_expmrq = 4096;
3573 pci_set_max_read_req(dev, sc->bge_expmrq);
3574 } else {
3575 /*
3576 * Check if the device is in PCI-X Mode.
3577 * (This bit is not valid on PCI Express controllers.)
3578 */
3579 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3580 sc->bge_pcixcap = reg;
3581 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3582 BGE_PCISTATE_PCI_BUSMODE) == 0)
3583 sc->bge_flags |= BGE_FLAG_PCIX;
3584 }
3585
3586 /*
3587 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3588 * not actually a MAC controller bug but an issue with the embedded
3589 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3590 */
3591 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3592 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3593 /*
3594 * Some PCI-X bridges are known to trigger write reordering to
3595 * the mailbox registers. Typical phenomena is watchdog timeouts
3596 * caused by out-of-order TX completions. Enable workaround for
3597 * PCI-X devices that live behind these bridges.
3598 * Note, PCI-X controllers can run in PCI mode so we can't use
3599 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3600 */
3601 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3602 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3603 /*
3604 * Allocate the interrupt, using MSI if possible. These devices
3605 * support 8 MSI messages, but only the first one is used in
3606 * normal operation.
3607 */
3608 rid = 0;
3609 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3610 sc->bge_msicap = reg;
3611 reg = 1;
3612 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3613 rid = 1;
3614 sc->bge_flags |= BGE_FLAG_MSI;
3615 }
3616 }
3617
3618 /*
3619 * All controllers except BCM5700 supports tagged status but
3620 * we use tagged status only for MSI case on BCM5717. Otherwise
3621 * MSI on BCM5717 does not work.
3622 */
3623 #ifndef DEVICE_POLLING
3624 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3625 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3626 #endif
3627
3628 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3629 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3630
3631 if (sc->bge_irq == NULL) {
3632 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3633 error = ENXIO;
3634 goto fail;
3635 }
3636
3637 bge_devinfo(sc);
3638
3639 sc->bge_asf_mode = 0;
3640 /* No ASF if APE present. */
3641 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3642 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3643 BGE_SRAM_DATA_SIG_MAGIC)) {
3644 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3645 BGE_HWCFG_ASF) {
3646 sc->bge_asf_mode |= ASF_ENABLE;
3647 sc->bge_asf_mode |= ASF_STACKUP;
3648 if (BGE_IS_575X_PLUS(sc))
3649 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3650 }
3651 }
3652 }
3653
3654 bge_stop_fw(sc);
3655 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3656 if (bge_reset(sc)) {
3657 device_printf(sc->bge_dev, "chip reset failed\n");
3658 error = ENXIO;
3659 goto fail;
3660 }
3661
3662 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3663 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3664
3665 if (bge_chipinit(sc)) {
3666 device_printf(sc->bge_dev, "chip initialization failed\n");
3667 error = ENXIO;
3668 goto fail;
3669 }
3670
3671 error = bge_get_eaddr(sc, eaddr);
3672 if (error) {
3673 device_printf(sc->bge_dev,
3674 "failed to read station address\n");
3675 error = ENXIO;
3676 goto fail;
3677 }
3678
3679 /* 5705 limits RX return ring to 512 entries. */
3680 if (BGE_IS_5717_PLUS(sc))
3681 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3682 else if (BGE_IS_5705_PLUS(sc))
3683 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3684 else
3685 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3686
3687 if (bge_dma_alloc(sc)) {
3688 device_printf(sc->bge_dev,
3689 "failed to allocate DMA resources\n");
3690 error = ENXIO;
3691 goto fail;
3692 }
3693
3694 /* Set default tuneable values. */
3695 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3696 sc->bge_rx_coal_ticks = 150;
3697 sc->bge_tx_coal_ticks = 150;
3698 sc->bge_rx_max_coal_bds = 10;
3699 sc->bge_tx_max_coal_bds = 10;
3700
3701 /* Initialize checksum features to use. */
3702 sc->bge_csum_features = BGE_CSUM_FEATURES;
3703 if (sc->bge_forced_udpcsum != 0)
3704 sc->bge_csum_features |= CSUM_UDP;
3705
3706 /* Set up ifnet structure */
3707 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3708 if_setsoftc(ifp, sc);
3709 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3710 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3711 if_setioctlfn(ifp, bge_ioctl);
3712 if_setstartfn(ifp, bge_start);
3713 if_setinitfn(ifp, bge_init);
3714 if_setgetcounterfn(ifp, bge_get_counter);
3715 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3716 if_setsendqready(ifp);
3717 /* Initially enable checksum offloading either for all of IPv4, TCP/IPv4
3718 * and UDP/IPv4, or for none. This avoids problems when the interface
3719 * is added to a bridge.
3720 */
3721 if (sc->bge_csum_features & CSUM_UDP)
3722 if_sethwassist(ifp, sc->bge_csum_features);
3723 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3724 IFCAP_VLAN_MTU);
3725 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3726 if_sethwassistbits(ifp, CSUM_TSO, 0);
3727 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3728 }
3729 #ifdef IFCAP_VLAN_HWCSUM
3730 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3731 #endif
3732 if_setcapenable(ifp, if_getcapabilities(ifp));
3733 /*
3734 * Disable TXCSUM capability initially, if UDP checksum offloading is
3735 * not enabled. This avoids problems when the interface is added to a
3736 * bridge.
3737 */
3738 if ((sc->bge_csum_features & CSUM_UDP) == 0)
3739 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
3740 #ifdef DEVICE_POLLING
3741 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3742 #endif
3743
3744 /*
3745 * 5700 B0 chips do not support checksumming correctly due
3746 * to hardware bugs.
3747 */
3748 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3749 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3750 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3751 if_sethwassist(ifp, 0);
3752 }
3753
3754 /*
3755 * Figure out what sort of media we have by checking the
3756 * hardware config word in the first 32k of NIC internal memory,
3757 * or fall back to examining the EEPROM if necessary.
3758 * Note: on some BCM5700 cards, this value appears to be unset.
3759 * If that's the case, we have to rely on identifying the NIC
3760 * by its PCI subsystem ID, as we do below for the SysKonnect
3761 * SK-9D41.
3762 */
3763 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3764 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3765 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3766 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3767 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3768 sizeof(hwcfg))) {
3769 /*
3770 * BCM57766 on Apple T2 Macs has no dedicated EEPROM;
3771 * the chip is copper-only so hwcfg=0 is correct.
3772 */
3773 if (sc->bge_asicrev != BGE_ASICREV_BCM57766) {
3774 device_printf(sc->bge_dev,
3775 "failed to read EEPROM\n");
3776 error = ENXIO;
3777 goto fail;
3778 }
3779 hwcfg = 0;
3780 } else
3781 hwcfg = ntohl(hwcfg);
3782 }
3783
3784 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3785 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3786 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3787 if (BGE_IS_5705_PLUS(sc)) {
3788 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3789 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3790 } else
3791 sc->bge_flags |= BGE_FLAG_TBI;
3792 }
3793
3794 /* Set various PHY bug flags. */
3795 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3796 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3797 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3798 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3799 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3800 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3801 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3802 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3803 if (pci_get_subvendor(dev) == DELL_VENDORID)
3804 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3805 if ((BGE_IS_5705_PLUS(sc)) &&
3806 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3807 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3808 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3809 !BGE_IS_5717_PLUS(sc)) {
3810 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3811 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3812 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3813 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3814 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3815 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3816 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3817 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3818 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3819 } else
3820 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3821 }
3822
3823 /*
3824 * Don't enable Ethernet@WireSpeed for the 5700 or the
3825 * 5705 A0 and A1 chips.
3826 */
3827 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3828 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3829 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3830 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3831 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3832
3833 if (sc->bge_flags & BGE_FLAG_TBI) {
3834 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3835 bge_ifmedia_sts);
3836 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3837 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3838 0, NULL);
3839 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3840 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3841 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3842 } else {
3843 /*
3844 * Do transceiver setup and tell the firmware the
3845 * driver is down so we can try to get access the
3846 * probe if ASF is running. Retry a couple of times
3847 * if we get a conflict with the ASF firmware accessing
3848 * the PHY.
3849 */
3850 trys = 0;
3851 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3852 again:
3853 bge_asf_driver_up(sc);
3854
3855 error = mii_attach(dev, &sc->bge_miibus, ifp,
3856 (ifm_change_cb_t)bge_ifmedia_upd,
3857 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3858 MII_OFFSET_ANY, MIIF_DOPAUSE);
3859 if (error != 0) {
3860 if (trys++ < 4) {
3861 device_printf(sc->bge_dev, "Try again\n");
3862 bge_miibus_writereg(sc->bge_dev,
3863 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3864 goto again;
3865 }
3866 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3867 goto fail;
3868 }
3869
3870 /*
3871 * Now tell the firmware we are going up after probing the PHY
3872 */
3873 if (sc->bge_asf_mode & ASF_STACKUP)
3874 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3875 }
3876
3877 /*
3878 * When using the BCM5701 in PCI-X mode, data corruption has
3879 * been observed in the first few bytes of some received packets.
3880 * Aligning the packet buffer in memory eliminates the corruption.
3881 * Unfortunately, this misaligns the packet payloads. On platforms
3882 * which do not support unaligned accesses, we will realign the
3883 * payloads by copying the received packets.
3884 */
3885 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3886 sc->bge_flags & BGE_FLAG_PCIX)
3887 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3888
3889 /*
3890 * Call MI attach routine.
3891 */
3892 ether_ifattach(ifp, eaddr);
3893
3894 /* Tell upper layer we support long frames. */
3895 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3896
3897 /*
3898 * Hookup IRQ last.
3899 */
3900 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3901 /* Take advantage of single-shot MSI. */
3902 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3903 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3904 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3905 taskqueue_thread_enqueue, &sc->bge_tq);
3906 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3907 "%s taskq", device_get_nameunit(sc->bge_dev));
3908 if (error != 0) {
3909 device_printf(dev, "could not start threads.\n");
3910 ether_ifdetach(ifp);
3911 goto fail;
3912 }
3913 error = bus_setup_intr(dev, sc->bge_irq,
3914 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3915 &sc->bge_intrhand);
3916 } else
3917 error = bus_setup_intr(dev, sc->bge_irq,
3918 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3919 &sc->bge_intrhand);
3920
3921 if (error) {
3922 ether_ifdetach(ifp);
3923 device_printf(sc->bge_dev, "couldn't set up irq\n");
3924 goto fail;
3925 }
3926
3927 /* Attach driver debugnet methods. */
3928 DEBUGNET_SET(ifp, bge);
3929
3930 fail:
3931 if (error)
3932 bge_detach(dev);
3933 return (error);
3934 }
3935
3936 static int
bge_detach(device_t dev)3937 bge_detach(device_t dev)
3938 {
3939 struct bge_softc *sc;
3940 if_t ifp;
3941
3942 sc = device_get_softc(dev);
3943 ifp = sc->bge_ifp;
3944
3945 #ifdef DEVICE_POLLING
3946 if (if_getcapenable(ifp) & IFCAP_POLLING)
3947 ether_poll_deregister(ifp);
3948 #endif
3949
3950 if (device_is_attached(dev)) {
3951 ether_ifdetach(ifp);
3952 BGE_LOCK(sc);
3953 bge_stop(sc);
3954 BGE_UNLOCK(sc);
3955 callout_drain(&sc->bge_stat_ch);
3956 }
3957
3958 if (sc->bge_tq)
3959 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3960
3961 if (sc->bge_flags & BGE_FLAG_TBI)
3962 ifmedia_removeall(&sc->bge_ifmedia);
3963 else if (sc->bge_miibus != NULL) {
3964 bus_generic_detach(dev);
3965 }
3966
3967 bge_release_resources(sc);
3968
3969 return (0);
3970 }
3971
3972 static void
bge_release_resources(struct bge_softc * sc)3973 bge_release_resources(struct bge_softc *sc)
3974 {
3975 device_t dev;
3976
3977 dev = sc->bge_dev;
3978
3979 if (sc->bge_tq != NULL)
3980 taskqueue_free(sc->bge_tq);
3981
3982 if (sc->bge_intrhand != NULL)
3983 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3984
3985 if (sc->bge_irq != NULL) {
3986 bus_release_resource(dev, SYS_RES_IRQ,
3987 rman_get_rid(sc->bge_irq), sc->bge_irq);
3988 pci_release_msi(dev);
3989 }
3990
3991 if (sc->bge_res != NULL)
3992 bus_release_resource(dev, SYS_RES_MEMORY,
3993 rman_get_rid(sc->bge_res), sc->bge_res);
3994
3995 if (sc->bge_res2 != NULL)
3996 bus_release_resource(dev, SYS_RES_MEMORY,
3997 rman_get_rid(sc->bge_res2), sc->bge_res2);
3998
3999 if (sc->bge_ifp != NULL)
4000 if_free(sc->bge_ifp);
4001
4002 bge_dma_free(sc);
4003
4004 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
4005 BGE_LOCK_DESTROY(sc);
4006 }
4007
4008 static int
bge_reset(struct bge_softc * sc)4009 bge_reset(struct bge_softc *sc)
4010 {
4011 device_t dev;
4012 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4013 void (*write_op)(struct bge_softc *, int, int);
4014 uint16_t devctl;
4015 int i;
4016
4017 dev = sc->bge_dev;
4018
4019 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4020 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4021 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4022 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4023
4024 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4025 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4026 if (sc->bge_flags & BGE_FLAG_PCIE)
4027 write_op = bge_writemem_direct;
4028 else
4029 write_op = bge_writemem_ind;
4030 } else
4031 write_op = bge_writereg_ind;
4032
4033 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4034 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4035 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4036 for (i = 0; i < 8000; i++) {
4037 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4038 BGE_NVRAMSWARB_GNT1)
4039 break;
4040 DELAY(20);
4041 }
4042 if (i == 8000) {
4043 if (bootverbose)
4044 device_printf(dev, "NVRAM lock timedout!\n");
4045 }
4046 }
4047 /* Take APE lock when performing reset. */
4048 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4049
4050 /* Save some important PCI state. */
4051 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4052 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4053
4054 pci_write_config(dev, BGE_PCI_MISC_CTL,
4055 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4056 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4057
4058 /* Disable fastboot on controllers that support it. */
4059 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4060 BGE_IS_5755_PLUS(sc)) {
4061 if (bootverbose)
4062 device_printf(dev, "Disabling fastboot\n");
4063 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4064 }
4065
4066 /*
4067 * Write the magic number to SRAM at offset 0xB50.
4068 * When firmware finishes its initialization it will
4069 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4070 */
4071 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4072
4073 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4074
4075 /* XXX: Broadcom Linux driver. */
4076 if (sc->bge_flags & BGE_FLAG_PCIE) {
4077 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4078 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4079 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4080 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4081 }
4082 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4083 /* Prevent PCIE link training during global reset */
4084 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4085 reset |= 1 << 29;
4086 }
4087 }
4088
4089 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4090 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4091 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4092 val | BGE_VCPU_STATUS_DRV_RESET);
4093 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4094 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4095 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4096 }
4097
4098 /*
4099 * Set GPHY Power Down Override to leave GPHY
4100 * powered up in D0 uninitialized.
4101 */
4102 if (BGE_IS_5705_PLUS(sc) &&
4103 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4104 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4105
4106 /* Issue global reset */
4107 write_op(sc, BGE_MISC_CFG, reset);
4108
4109 if (sc->bge_flags & BGE_FLAG_PCIE)
4110 DELAY(100 * 1000);
4111 else
4112 DELAY(1000);
4113
4114 /* XXX: Broadcom Linux driver. */
4115 if (sc->bge_flags & BGE_FLAG_PCIE) {
4116 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4117 DELAY(500000); /* wait for link training to complete */
4118 val = pci_read_config(dev, 0xC4, 4);
4119 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4120 }
4121 devctl = pci_read_config(dev,
4122 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4123 /* Clear enable no snoop and disable relaxed ordering. */
4124 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4125 PCIEM_CTL_NOSNOOP_ENABLE);
4126 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4127 devctl, 2);
4128 pci_set_max_read_req(dev, sc->bge_expmrq);
4129 /* Clear error status. */
4130 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4131 PCIEM_STA_CORRECTABLE_ERROR |
4132 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4133 PCIEM_STA_UNSUPPORTED_REQ, 2);
4134 }
4135
4136 /* Reset some of the PCI state that got zapped by reset. */
4137 pci_write_config(dev, BGE_PCI_MISC_CTL,
4138 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4139 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4140 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4141 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4142 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4143 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4144 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4145 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4146 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4147 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4148 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4149 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4150 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4151 /*
4152 * Disable PCI-X relaxed ordering to ensure status block update
4153 * comes first then packet buffer DMA. Otherwise driver may
4154 * read stale status block.
4155 */
4156 if (sc->bge_flags & BGE_FLAG_PCIX) {
4157 devctl = pci_read_config(dev,
4158 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4159 devctl &= ~PCIXM_COMMAND_ERO;
4160 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4161 devctl &= ~PCIXM_COMMAND_MAX_READ;
4162 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4163 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4164 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4165 PCIXM_COMMAND_MAX_READ);
4166 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4167 }
4168 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4169 devctl, 2);
4170 }
4171 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4172 if (BGE_IS_5714_FAMILY(sc)) {
4173 /* This chip disables MSI on reset. */
4174 if (sc->bge_flags & BGE_FLAG_MSI) {
4175 val = pci_read_config(dev,
4176 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4177 pci_write_config(dev,
4178 sc->bge_msicap + PCIR_MSI_CTRL,
4179 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4180 val = CSR_READ_4(sc, BGE_MSI_MODE);
4181 CSR_WRITE_4(sc, BGE_MSI_MODE,
4182 val | BGE_MSIMODE_ENABLE);
4183 }
4184 val = CSR_READ_4(sc, BGE_MARB_MODE);
4185 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4186 } else
4187 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4188
4189 /* Fix up byte swapping. */
4190 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4191
4192 val = CSR_READ_4(sc, BGE_MAC_MODE);
4193 val = (val & ~mac_mode_mask) | mac_mode;
4194 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4195 DELAY(40);
4196
4197 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4198
4199 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4200 for (i = 0; i < BGE_TIMEOUT; i++) {
4201 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4202 if (val & BGE_VCPU_STATUS_INIT_DONE)
4203 break;
4204 DELAY(100);
4205 }
4206 if (i == BGE_TIMEOUT) {
4207 device_printf(dev, "reset timed out\n");
4208 return (1);
4209 }
4210 } else {
4211 /*
4212 * Poll until we see the 1's complement of the magic number.
4213 * This indicates that the firmware initialization is complete.
4214 * We expect this to fail if no chip containing the Ethernet
4215 * address is fitted though.
4216 */
4217 for (i = 0; i < BGE_TIMEOUT; i++) {
4218 DELAY(10);
4219 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4220 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4221 break;
4222 }
4223
4224 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4225 device_printf(dev,
4226 "firmware handshake timed out, found 0x%08x\n",
4227 val);
4228 /* BCM57765 A0 needs additional time before accessing. */
4229 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4230 DELAY(10 * 1000); /* XXX */
4231 }
4232
4233 /*
4234 * The 5704 in TBI mode apparently needs some special
4235 * adjustment to insure the SERDES drive level is set
4236 * to 1.2V.
4237 */
4238 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4239 sc->bge_flags & BGE_FLAG_TBI) {
4240 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4241 val = (val & ~0xFFF) | 0x880;
4242 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4243 }
4244
4245 /* XXX: Broadcom Linux driver. */
4246 if (sc->bge_flags & BGE_FLAG_PCIE &&
4247 !BGE_IS_5717_PLUS(sc) &&
4248 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4249 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4250 /* Enable Data FIFO protection. */
4251 val = CSR_READ_4(sc, 0x7C00);
4252 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4253 }
4254
4255 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4256 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4257 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4258
4259 return (0);
4260 }
4261
4262 static __inline void
bge_rxreuse_std(struct bge_softc * sc,int i)4263 bge_rxreuse_std(struct bge_softc *sc, int i)
4264 {
4265 struct bge_rx_bd *r;
4266
4267 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4268 r->bge_flags = BGE_RXBDFLAG_END;
4269 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4270 r->bge_idx = i;
4271 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4272 }
4273
4274 static __inline void
bge_rxreuse_jumbo(struct bge_softc * sc,int i)4275 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4276 {
4277 struct bge_extrx_bd *r;
4278
4279 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4280 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4281 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4282 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4283 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4284 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4285 r->bge_idx = i;
4286 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4287 }
4288
4289 /*
4290 * Frame reception handling. This is called if there's a frame
4291 * on the receive return list.
4292 *
4293 * Note: we have to be able to handle two possibilities here:
4294 * 1) the frame is from the jumbo receive ring
4295 * 2) the frame is from the standard receive ring
4296 */
4297
4298 static int
bge_rxeof(struct bge_softc * sc,uint16_t rx_prod,int holdlck)4299 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4300 {
4301 if_t ifp;
4302 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4303 uint16_t rx_cons;
4304
4305 rx_cons = sc->bge_rx_saved_considx;
4306
4307 /* Nothing to do. */
4308 if (rx_cons == rx_prod)
4309 return (rx_npkts);
4310
4311 ifp = sc->bge_ifp;
4312
4313 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4314 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4315 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4316 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4317 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4318 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4319 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4320 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4321 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4322
4323 while (rx_cons != rx_prod) {
4324 struct bge_rx_bd *cur_rx;
4325 uint32_t rxidx;
4326 struct mbuf *m = NULL;
4327 uint16_t vlan_tag = 0;
4328 int have_tag = 0;
4329
4330 #ifdef DEVICE_POLLING
4331 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4332 if (sc->rxcycles <= 0)
4333 break;
4334 sc->rxcycles--;
4335 }
4336 #endif
4337
4338 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4339
4340 rxidx = cur_rx->bge_idx;
4341 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4342
4343 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4344 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4345 have_tag = 1;
4346 vlan_tag = cur_rx->bge_vlan_tag;
4347 }
4348
4349 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4350 jumbocnt++;
4351 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4352 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4353 bge_rxreuse_jumbo(sc, rxidx);
4354 continue;
4355 }
4356 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4357 bge_rxreuse_jumbo(sc, rxidx);
4358 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4359 continue;
4360 }
4361 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4362 } else {
4363 stdcnt++;
4364 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4365 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4366 bge_rxreuse_std(sc, rxidx);
4367 continue;
4368 }
4369 if (bge_newbuf_std(sc, rxidx) != 0) {
4370 bge_rxreuse_std(sc, rxidx);
4371 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4372 continue;
4373 }
4374 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4375 }
4376
4377 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4378 #ifndef __NO_STRICT_ALIGNMENT
4379 /*
4380 * For architectures with strict alignment we must make sure
4381 * the payload is aligned.
4382 */
4383 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4384 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4385 cur_rx->bge_len);
4386 m->m_data += ETHER_ALIGN;
4387 }
4388 #endif
4389 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4390 m->m_pkthdr.rcvif = ifp;
4391
4392 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4393 bge_rxcsum(sc, cur_rx, m);
4394
4395 /*
4396 * If we received a packet with a vlan tag,
4397 * attach that information to the packet.
4398 */
4399 if (have_tag) {
4400 m->m_pkthdr.ether_vtag = vlan_tag;
4401 m->m_flags |= M_VLANTAG;
4402 }
4403
4404 if (holdlck != 0) {
4405 BGE_UNLOCK(sc);
4406 if_input(ifp, m);
4407 BGE_LOCK(sc);
4408 } else
4409 if_input(ifp, m);
4410 rx_npkts++;
4411
4412 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4413 return (rx_npkts);
4414 }
4415
4416 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4417 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4418 if (stdcnt > 0)
4419 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4420 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4421
4422 if (jumbocnt > 0)
4423 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4424 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4425
4426 sc->bge_rx_saved_considx = rx_cons;
4427 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4428 if (stdcnt)
4429 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4430 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4431 if (jumbocnt)
4432 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4433 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4434 #ifdef notyet
4435 /*
4436 * This register wraps very quickly under heavy packet drops.
4437 * If you need correct statistics, you can enable this check.
4438 */
4439 if (BGE_IS_5705_PLUS(sc))
4440 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4441 #endif
4442 return (rx_npkts);
4443 }
4444
4445 static void
bge_rxcsum(struct bge_softc * sc,struct bge_rx_bd * cur_rx,struct mbuf * m)4446 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4447 {
4448
4449 if (BGE_IS_5717_PLUS(sc)) {
4450 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4451 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4452 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4453 if ((cur_rx->bge_error_flag &
4454 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4455 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4456 }
4457 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4458 m->m_pkthdr.csum_data =
4459 cur_rx->bge_tcp_udp_csum;
4460 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4461 CSUM_PSEUDO_HDR;
4462 }
4463 }
4464 } else {
4465 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4466 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4467 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4468 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4469 }
4470 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4471 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4472 m->m_pkthdr.csum_data =
4473 cur_rx->bge_tcp_udp_csum;
4474 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4475 CSUM_PSEUDO_HDR;
4476 }
4477 }
4478 }
4479
4480 static void
bge_txeof(struct bge_softc * sc,uint16_t tx_cons)4481 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4482 {
4483 struct bge_tx_bd *cur_tx;
4484 if_t ifp;
4485
4486 BGE_LOCK_ASSERT(sc);
4487
4488 /* Nothing to do. */
4489 if (sc->bge_tx_saved_considx == tx_cons)
4490 return;
4491
4492 ifp = sc->bge_ifp;
4493
4494 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4495 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4496 /*
4497 * Go through our tx ring and free mbufs for those
4498 * frames that have been sent.
4499 */
4500 while (sc->bge_tx_saved_considx != tx_cons) {
4501 uint32_t idx;
4502
4503 idx = sc->bge_tx_saved_considx;
4504 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4505 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4506 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4507 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4508 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4509 sc->bge_cdata.bge_tx_dmamap[idx],
4510 BUS_DMASYNC_POSTWRITE);
4511 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4512 sc->bge_cdata.bge_tx_dmamap[idx]);
4513 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4514 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4515 }
4516 sc->bge_txcnt--;
4517 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4518 }
4519
4520 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4521 if (sc->bge_txcnt == 0)
4522 sc->bge_timer = 0;
4523 }
4524
4525 #ifdef DEVICE_POLLING
4526 static int
bge_poll(if_t ifp,enum poll_cmd cmd,int count)4527 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4528 {
4529 struct bge_softc *sc = if_getsoftc(ifp);
4530 uint16_t rx_prod, tx_cons;
4531 uint32_t statusword;
4532 int rx_npkts = 0;
4533
4534 BGE_LOCK(sc);
4535 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4536 BGE_UNLOCK(sc);
4537 return (rx_npkts);
4538 }
4539
4540 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4541 sc->bge_cdata.bge_status_map,
4542 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4543 /* Fetch updates from the status block. */
4544 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4545 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4546
4547 statusword = sc->bge_ldata.bge_status_block->bge_status;
4548 /* Clear the status so the next pass only sees the changes. */
4549 sc->bge_ldata.bge_status_block->bge_status = 0;
4550
4551 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4552 sc->bge_cdata.bge_status_map,
4553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4554
4555 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4556 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4557 sc->bge_link_evt++;
4558
4559 if (cmd == POLL_AND_CHECK_STATUS)
4560 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4561 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4562 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4563 bge_link_upd(sc);
4564
4565 sc->rxcycles = count;
4566 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4567 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4568 BGE_UNLOCK(sc);
4569 return (rx_npkts);
4570 }
4571 bge_txeof(sc, tx_cons);
4572 if (!if_sendq_empty(ifp))
4573 bge_start_locked(ifp);
4574
4575 BGE_UNLOCK(sc);
4576 return (rx_npkts);
4577 }
4578 #endif /* DEVICE_POLLING */
4579
4580 static int
bge_msi_intr(void * arg)4581 bge_msi_intr(void *arg)
4582 {
4583 struct bge_softc *sc;
4584
4585 sc = (struct bge_softc *)arg;
4586 /*
4587 * This interrupt is not shared and controller already
4588 * disabled further interrupt.
4589 */
4590 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4591 return (FILTER_HANDLED);
4592 }
4593
4594 static void
bge_intr_task(void * arg,int pending)4595 bge_intr_task(void *arg, int pending)
4596 {
4597 struct bge_softc *sc;
4598 if_t ifp;
4599 uint32_t status, status_tag;
4600 uint16_t rx_prod, tx_cons;
4601
4602 sc = (struct bge_softc *)arg;
4603 ifp = sc->bge_ifp;
4604
4605 BGE_LOCK(sc);
4606 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4607 BGE_UNLOCK(sc);
4608 return;
4609 }
4610
4611 /* Get updated status block. */
4612 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4613 sc->bge_cdata.bge_status_map,
4614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4615
4616 /* Save producer/consumer indices. */
4617 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4618 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4619 status = sc->bge_ldata.bge_status_block->bge_status;
4620 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4621 /* Dirty the status flag. */
4622 sc->bge_ldata.bge_status_block->bge_status = 0;
4623 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4624 sc->bge_cdata.bge_status_map,
4625 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4626 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4627 status_tag = 0;
4628
4629 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4630 bge_link_upd(sc);
4631
4632 /* Let controller work. */
4633 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4634
4635 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4636 sc->bge_rx_saved_considx != rx_prod) {
4637 /* Check RX return ring producer/consumer. */
4638 BGE_UNLOCK(sc);
4639 bge_rxeof(sc, rx_prod, 0);
4640 BGE_LOCK(sc);
4641 }
4642 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4643 /* Check TX ring producer/consumer. */
4644 bge_txeof(sc, tx_cons);
4645 if (!if_sendq_empty(ifp))
4646 bge_start_locked(ifp);
4647 }
4648 BGE_UNLOCK(sc);
4649 }
4650
4651 static void
bge_intr(void * xsc)4652 bge_intr(void *xsc)
4653 {
4654 struct bge_softc *sc;
4655 if_t ifp;
4656 uint32_t statusword;
4657 uint16_t rx_prod, tx_cons;
4658
4659 sc = xsc;
4660
4661 BGE_LOCK(sc);
4662
4663 ifp = sc->bge_ifp;
4664
4665 #ifdef DEVICE_POLLING
4666 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4667 BGE_UNLOCK(sc);
4668 return;
4669 }
4670 #endif
4671
4672 /*
4673 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4674 * disable interrupts by writing nonzero like we used to, since with
4675 * our current organization this just gives complications and
4676 * pessimizations for re-enabling interrupts. We used to have races
4677 * instead of the necessary complications. Disabling interrupts
4678 * would just reduce the chance of a status update while we are
4679 * running (by switching to the interrupt-mode coalescence
4680 * parameters), but this chance is already very low so it is more
4681 * efficient to get another interrupt than prevent it.
4682 *
4683 * We do the ack first to ensure another interrupt if there is a
4684 * status update after the ack. We don't check for the status
4685 * changing later because it is more efficient to get another
4686 * interrupt than prevent it, not quite as above (not checking is
4687 * a smaller optimization than not toggling the interrupt enable,
4688 * since checking doesn't involve PCI accesses and toggling require
4689 * the status check). So toggling would probably be a pessimization
4690 * even with MSI. It would only be needed for using a task queue.
4691 */
4692 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4693
4694 /*
4695 * Do the mandatory PCI flush as well as get the link status.
4696 */
4697 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4698
4699 /* Make sure the descriptor ring indexes are coherent. */
4700 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4701 sc->bge_cdata.bge_status_map,
4702 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4703 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4704 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4705 sc->bge_ldata.bge_status_block->bge_status = 0;
4706 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4707 sc->bge_cdata.bge_status_map,
4708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4709
4710 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4711 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4712 statusword || sc->bge_link_evt)
4713 bge_link_upd(sc);
4714
4715 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4716 /* Check RX return ring producer/consumer. */
4717 bge_rxeof(sc, rx_prod, 1);
4718 }
4719
4720 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4721 /* Check TX ring producer/consumer. */
4722 bge_txeof(sc, tx_cons);
4723 }
4724
4725 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4726 !if_sendq_empty(ifp))
4727 bge_start_locked(ifp);
4728
4729 BGE_UNLOCK(sc);
4730 }
4731
4732 static void
bge_asf_driver_up(struct bge_softc * sc)4733 bge_asf_driver_up(struct bge_softc *sc)
4734 {
4735 if (sc->bge_asf_mode & ASF_STACKUP) {
4736 /* Send ASF heartbeat aprox. every 2s */
4737 if (sc->bge_asf_count)
4738 sc->bge_asf_count --;
4739 else {
4740 sc->bge_asf_count = 2;
4741 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4742 BGE_FW_CMD_DRV_ALIVE);
4743 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4744 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4745 BGE_FW_HB_TIMEOUT_SEC);
4746 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4747 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4748 BGE_RX_CPU_DRV_EVENT);
4749 }
4750 }
4751 }
4752
4753 static void
bge_tick(void * xsc)4754 bge_tick(void *xsc)
4755 {
4756 struct bge_softc *sc = xsc;
4757 struct mii_data *mii = NULL;
4758
4759 BGE_LOCK_ASSERT(sc);
4760
4761 /* Synchronize with possible callout reset/stop. */
4762 if (callout_pending(&sc->bge_stat_ch) ||
4763 !callout_active(&sc->bge_stat_ch))
4764 return;
4765
4766 if (BGE_IS_5705_PLUS(sc))
4767 bge_stats_update_regs(sc);
4768 else
4769 bge_stats_update(sc);
4770
4771 /* XXX Add APE heartbeat check here? */
4772
4773 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4774 mii = device_get_softc(sc->bge_miibus);
4775 /*
4776 * Do not touch PHY if we have link up. This could break
4777 * IPMI/ASF mode or produce extra input errors
4778 * (extra errors was reported for bcm5701 & bcm5704).
4779 */
4780 if (!sc->bge_link)
4781 mii_tick(mii);
4782 } else {
4783 /*
4784 * Since in TBI mode auto-polling can't be used we should poll
4785 * link status manually. Here we register pending link event
4786 * and trigger interrupt.
4787 */
4788 #ifdef DEVICE_POLLING
4789 /* In polling mode we poll link state in bge_poll(). */
4790 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4791 #endif
4792 {
4793 sc->bge_link_evt++;
4794 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4795 sc->bge_flags & BGE_FLAG_5788)
4796 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4797 else
4798 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4799 }
4800 }
4801
4802 bge_asf_driver_up(sc);
4803 bge_watchdog(sc);
4804
4805 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4806 }
4807
4808 static void
bge_stats_update_regs(struct bge_softc * sc)4809 bge_stats_update_regs(struct bge_softc *sc)
4810 {
4811 struct bge_mac_stats *stats;
4812 uint32_t val;
4813
4814 stats = &sc->bge_mac_stats;
4815
4816 stats->ifHCOutOctets +=
4817 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4818 stats->etherStatsCollisions +=
4819 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4820 stats->outXonSent +=
4821 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4822 stats->outXoffSent +=
4823 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4824 stats->dot3StatsInternalMacTransmitErrors +=
4825 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4826 stats->dot3StatsSingleCollisionFrames +=
4827 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4828 stats->dot3StatsMultipleCollisionFrames +=
4829 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4830 stats->dot3StatsDeferredTransmissions +=
4831 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4832 stats->dot3StatsExcessiveCollisions +=
4833 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4834 stats->dot3StatsLateCollisions +=
4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4836 stats->ifHCOutUcastPkts +=
4837 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4838 stats->ifHCOutMulticastPkts +=
4839 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4840 stats->ifHCOutBroadcastPkts +=
4841 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4842
4843 stats->ifHCInOctets +=
4844 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4845 stats->etherStatsFragments +=
4846 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4847 stats->ifHCInUcastPkts +=
4848 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4849 stats->ifHCInMulticastPkts +=
4850 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4851 stats->ifHCInBroadcastPkts +=
4852 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4853 stats->dot3StatsFCSErrors +=
4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4855 stats->dot3StatsAlignmentErrors +=
4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4857 stats->xonPauseFramesReceived +=
4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4859 stats->xoffPauseFramesReceived +=
4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4861 stats->macControlFramesReceived +=
4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4863 stats->xoffStateEntered +=
4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4865 stats->dot3StatsFramesTooLong +=
4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4867 stats->etherStatsJabbers +=
4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4869 stats->etherStatsUndersizePkts +=
4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4871
4872 stats->FramesDroppedDueToFilters +=
4873 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4874 stats->DmaWriteQueueFull +=
4875 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4876 stats->DmaWriteHighPriQueueFull +=
4877 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4878 stats->NoMoreRxBDs +=
4879 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4880 /*
4881 * XXX
4882 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4883 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4884 * includes number of unwanted multicast frames. This comes
4885 * from silicon bug and known workaround to get rough(not
4886 * exact) counter is to enable interrupt on MBUF low water
4887 * attention. This can be accomplished by setting
4888 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4889 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4890 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4891 * However that change would generate more interrupts and
4892 * there are still possibilities of losing multiple frames
4893 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4894 * Given that the workaround still would not get correct
4895 * counter I don't think it's worth to implement it. So
4896 * ignore reading the counter on controllers that have the
4897 * silicon bug.
4898 */
4899 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4900 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4901 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4902 stats->InputDiscards +=
4903 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4904 stats->InputErrors +=
4905 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4906 stats->RecvThresholdHit +=
4907 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4908
4909 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4910 /*
4911 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4912 * frames, it's safe to disable workaround for DMA engine's
4913 * miscalculation of TXMBUF space.
4914 */
4915 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4916 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4917 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4918 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4919 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4920 else
4921 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4922 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4923 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4924 }
4925 }
4926 }
4927
4928 static void
bge_stats_clear_regs(struct bge_softc * sc)4929 bge_stats_clear_regs(struct bge_softc *sc)
4930 {
4931
4932 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4933 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4934 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4935 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4936 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4937 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4938 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4939 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4940 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4945
4946 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4947 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4948 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4949 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4950 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4951 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4952 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4953 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4954 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4960
4961 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4962 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4963 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4964 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4965 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4966 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4967 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4968 }
4969
4970 static void
bge_stats_update(struct bge_softc * sc)4971 bge_stats_update(struct bge_softc *sc)
4972 {
4973 if_t ifp;
4974 bus_size_t stats;
4975 uint32_t cnt; /* current register value */
4976
4977 ifp = sc->bge_ifp;
4978
4979 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4980
4981 #define READ_STAT(sc, stats, stat) \
4982 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4983
4984 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4985 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4986 sc->bge_tx_collisions = cnt;
4987
4988 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4989 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
4990 sc->bge_rx_nobds = cnt;
4991 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4992 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
4993 sc->bge_rx_inerrs = cnt;
4994 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4995 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
4996 sc->bge_rx_discards = cnt;
4997
4998 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4999 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5000 sc->bge_tx_discards = cnt;
5001
5002 #undef READ_STAT
5003 }
5004
5005 /*
5006 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5007 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5008 * but when such padded frames employ the bge IP/TCP checksum offload,
5009 * the hardware checksum assist gives incorrect results (possibly
5010 * from incorporating its own padding into the UDP/TCP checksum; who knows).
5011 * If we pad such runts with zeros, the onboard checksum comes out correct.
5012 */
5013 static __inline int
bge_cksum_pad(struct mbuf * m)5014 bge_cksum_pad(struct mbuf *m)
5015 {
5016 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5017 struct mbuf *last;
5018
5019 /* If there's only the packet-header and we can pad there, use it. */
5020 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5021 M_TRAILINGSPACE(m) >= padlen) {
5022 last = m;
5023 } else {
5024 /*
5025 * Walk packet chain to find last mbuf. We will either
5026 * pad there, or append a new mbuf and pad it.
5027 */
5028 for (last = m; last->m_next != NULL; last = last->m_next);
5029 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5030 /* Allocate new empty mbuf, pad it. Compact later. */
5031 struct mbuf *n;
5032
5033 MGET(n, M_NOWAIT, MT_DATA);
5034 if (n == NULL)
5035 return (ENOBUFS);
5036 n->m_len = 0;
5037 last->m_next = n;
5038 last = n;
5039 }
5040 }
5041
5042 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5043 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5044 last->m_len += padlen;
5045 m->m_pkthdr.len += padlen;
5046
5047 return (0);
5048 }
5049
5050 static struct mbuf *
bge_check_short_dma(struct mbuf * m)5051 bge_check_short_dma(struct mbuf *m)
5052 {
5053 struct mbuf *n;
5054 int found;
5055
5056 /*
5057 * If device receive two back-to-back send BDs with less than
5058 * or equal to 8 total bytes then the device may hang. The two
5059 * back-to-back send BDs must in the same frame for this failure
5060 * to occur. Scan mbuf chains and see whether two back-to-back
5061 * send BDs are there. If this is the case, allocate new mbuf
5062 * and copy the frame to workaround the silicon bug.
5063 */
5064 for (n = m, found = 0; n != NULL; n = n->m_next) {
5065 if (n->m_len < 8) {
5066 found++;
5067 if (found > 1)
5068 break;
5069 continue;
5070 }
5071 found = 0;
5072 }
5073
5074 if (found > 1) {
5075 n = m_defrag(m, M_NOWAIT);
5076 if (n == NULL)
5077 m_freem(m);
5078 } else
5079 n = m;
5080 return (n);
5081 }
5082
5083 static struct mbuf *
bge_setup_tso(struct bge_softc * sc,struct mbuf * m,uint16_t * mss,uint16_t * flags)5084 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5085 uint16_t *flags)
5086 {
5087 struct ip *ip;
5088 struct tcphdr *tcp;
5089 struct mbuf *n;
5090 uint16_t hlen;
5091 uint32_t poff;
5092
5093 if (M_WRITABLE(m) == 0) {
5094 /* Get a writable copy. */
5095 n = m_dup(m, M_NOWAIT);
5096 m_freem(m);
5097 if (n == NULL)
5098 return (NULL);
5099 m = n;
5100 }
5101 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5102 if (m == NULL)
5103 return (NULL);
5104 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5105 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5106 m = m_pullup(m, poff + sizeof(struct tcphdr));
5107 if (m == NULL)
5108 return (NULL);
5109 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5110 m = m_pullup(m, poff + (tcp->th_off << 2));
5111 if (m == NULL)
5112 return (NULL);
5113 /*
5114 * It seems controller doesn't modify IP length and TCP pseudo
5115 * checksum. These checksum computed by upper stack should be 0.
5116 */
5117 *mss = m->m_pkthdr.tso_segsz;
5118 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5119 ip->ip_sum = 0;
5120 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5121 /* Clear pseudo checksum computed by TCP stack. */
5122 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5123 tcp->th_sum = 0;
5124 /*
5125 * Broadcom controllers uses different descriptor format for
5126 * TSO depending on ASIC revision. Due to TSO-capable firmware
5127 * license issue and lower performance of firmware based TSO
5128 * we only support hardware based TSO.
5129 */
5130 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5131 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5132 if (sc->bge_flags & BGE_FLAG_TSO3) {
5133 /*
5134 * For BCM5717 and newer controllers, hardware based TSO
5135 * uses the 14 lower bits of the bge_mss field to store the
5136 * MSS and the upper 2 bits to store the lowest 2 bits of
5137 * the IP/TCP header length. The upper 6 bits of the header
5138 * length are stored in the bge_flags[14:10,4] field. Jumbo
5139 * frames are supported.
5140 */
5141 *mss |= ((hlen & 0x3) << 14);
5142 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5143 } else {
5144 /*
5145 * For BCM5755 and newer controllers, hardware based TSO uses
5146 * the lower 11 bits to store the MSS and the upper 5 bits to
5147 * store the IP/TCP header length. Jumbo frames are not
5148 * supported.
5149 */
5150 *mss |= (hlen << 11);
5151 }
5152 return (m);
5153 }
5154
5155 /*
5156 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5157 * pointers to descriptors.
5158 */
5159 static int
bge_encap(struct bge_softc * sc,struct mbuf ** m_head,uint32_t * txidx)5160 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5161 {
5162 bus_dma_segment_t segs[BGE_NSEG_NEW];
5163 bus_dmamap_t map;
5164 struct bge_tx_bd *d;
5165 struct mbuf *m = *m_head;
5166 uint32_t idx = *txidx;
5167 uint16_t csum_flags, mss, vlan_tag;
5168 int nsegs, i, error;
5169
5170 csum_flags = 0;
5171 mss = 0;
5172 vlan_tag = 0;
5173 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5174 m->m_next != NULL) {
5175 *m_head = bge_check_short_dma(m);
5176 if (*m_head == NULL)
5177 return (ENOBUFS);
5178 m = *m_head;
5179 }
5180 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5181 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5182 if (*m_head == NULL)
5183 return (ENOBUFS);
5184 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5185 BGE_TXBDFLAG_CPU_POST_DMA;
5186 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5187 if (m->m_pkthdr.csum_flags & CSUM_IP)
5188 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5189 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5190 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5191 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5192 (error = bge_cksum_pad(m)) != 0) {
5193 m_freem(m);
5194 *m_head = NULL;
5195 return (error);
5196 }
5197 }
5198 }
5199
5200 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5201 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5202 m->m_pkthdr.len > ETHER_MAX_LEN)
5203 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5204 if (sc->bge_forced_collapse > 0 &&
5205 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5206 /*
5207 * Forcedly collapse mbuf chains to overcome hardware
5208 * limitation which only support a single outstanding
5209 * DMA read operation.
5210 */
5211 if (sc->bge_forced_collapse == 1)
5212 m = m_defrag(m, M_NOWAIT);
5213 else
5214 m = m_collapse(m, M_NOWAIT,
5215 sc->bge_forced_collapse);
5216 if (m == NULL)
5217 m = *m_head;
5218 *m_head = m;
5219 }
5220 }
5221
5222 map = sc->bge_cdata.bge_tx_dmamap[idx];
5223 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5224 &nsegs, BUS_DMA_NOWAIT);
5225 if (error == EFBIG) {
5226 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5227 if (m == NULL) {
5228 m_freem(*m_head);
5229 *m_head = NULL;
5230 return (ENOBUFS);
5231 }
5232 *m_head = m;
5233 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5234 m, segs, &nsegs, BUS_DMA_NOWAIT);
5235 if (error) {
5236 m_freem(m);
5237 *m_head = NULL;
5238 return (error);
5239 }
5240 } else if (error != 0)
5241 return (error);
5242
5243 /* Check if we have enough free send BDs. */
5244 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5245 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5246 return (ENOBUFS);
5247 }
5248
5249 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5250
5251 if (m->m_flags & M_VLANTAG) {
5252 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5253 vlan_tag = m->m_pkthdr.ether_vtag;
5254 }
5255
5256 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5257 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5258 /*
5259 * 5725 family of devices corrupts TSO packets when TSO DMA
5260 * buffers cross into regions which are within MSS bytes of
5261 * a 4GB boundary. If we encounter the condition, drop the
5262 * packet.
5263 */
5264 for (i = 0; ; i++) {
5265 d = &sc->bge_ldata.bge_tx_ring[idx];
5266 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5267 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5268 d->bge_len = segs[i].ds_len;
5269 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5270 d->bge_addr.bge_addr_lo)
5271 break;
5272 d->bge_flags = csum_flags;
5273 d->bge_vlan_tag = vlan_tag;
5274 d->bge_mss = mss;
5275 if (i == nsegs - 1)
5276 break;
5277 BGE_INC(idx, BGE_TX_RING_CNT);
5278 }
5279 if (i != nsegs - 1) {
5280 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5281 BUS_DMASYNC_POSTWRITE);
5282 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5283 m_freem(*m_head);
5284 *m_head = NULL;
5285 return (EIO);
5286 }
5287 } else {
5288 for (i = 0; ; i++) {
5289 d = &sc->bge_ldata.bge_tx_ring[idx];
5290 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5291 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5292 d->bge_len = segs[i].ds_len;
5293 d->bge_flags = csum_flags;
5294 d->bge_vlan_tag = vlan_tag;
5295 d->bge_mss = mss;
5296 if (i == nsegs - 1)
5297 break;
5298 BGE_INC(idx, BGE_TX_RING_CNT);
5299 }
5300 }
5301
5302 /* Mark the last segment as end of packet... */
5303 d->bge_flags |= BGE_TXBDFLAG_END;
5304
5305 /*
5306 * Insure that the map for this transmission
5307 * is placed at the array index of the last descriptor
5308 * in this chain.
5309 */
5310 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5311 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5312 sc->bge_cdata.bge_tx_chain[idx] = m;
5313 sc->bge_txcnt += nsegs;
5314
5315 BGE_INC(idx, BGE_TX_RING_CNT);
5316 *txidx = idx;
5317
5318 return (0);
5319 }
5320
5321 /*
5322 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5323 * to the mbuf data regions directly in the transmit descriptors.
5324 */
5325 static void
bge_start_locked(if_t ifp)5326 bge_start_locked(if_t ifp)
5327 {
5328 struct bge_softc *sc;
5329 struct mbuf *m_head;
5330 uint32_t prodidx;
5331 int count;
5332
5333 sc = if_getsoftc(ifp);
5334 BGE_LOCK_ASSERT(sc);
5335
5336 if (!sc->bge_link ||
5337 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5338 IFF_DRV_RUNNING)
5339 return;
5340
5341 prodidx = sc->bge_tx_prodidx;
5342
5343 for (count = 0; !if_sendq_empty(ifp);) {
5344 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5345 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5346 break;
5347 }
5348 m_head = if_dequeue(ifp);
5349 if (m_head == NULL)
5350 break;
5351
5352 /*
5353 * Pack the data into the transmit ring. If we
5354 * don't have room, set the OACTIVE flag and wait
5355 * for the NIC to drain the ring.
5356 */
5357 if (bge_encap(sc, &m_head, &prodidx)) {
5358 if (m_head == NULL)
5359 break;
5360 if_sendq_prepend(ifp, m_head);
5361 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5362 break;
5363 }
5364 ++count;
5365
5366 /*
5367 * If there's a BPF listener, bounce a copy of this frame
5368 * to him.
5369 */
5370 bpf_mtap_if(ifp, m_head);
5371 }
5372
5373 if (count > 0)
5374 bge_start_tx(sc, prodidx);
5375 }
5376
5377 static void
bge_start_tx(struct bge_softc * sc,uint32_t prodidx)5378 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5379 {
5380
5381 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5382 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5383 /* Transmit. */
5384 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5385 /* 5700 b2 errata */
5386 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5387 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5388
5389 sc->bge_tx_prodidx = prodidx;
5390
5391 /* Set a timeout in case the chip goes out to lunch. */
5392 sc->bge_timer = BGE_TX_TIMEOUT;
5393 }
5394
5395 /*
5396 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5397 * to the mbuf data regions directly in the transmit descriptors.
5398 */
5399 static void
bge_start(if_t ifp)5400 bge_start(if_t ifp)
5401 {
5402 struct bge_softc *sc;
5403
5404 sc = if_getsoftc(ifp);
5405 BGE_LOCK(sc);
5406 bge_start_locked(ifp);
5407 BGE_UNLOCK(sc);
5408 }
5409
5410 static void
bge_init_locked(struct bge_softc * sc)5411 bge_init_locked(struct bge_softc *sc)
5412 {
5413 if_t ifp;
5414 uint16_t *m;
5415 uint32_t mode;
5416
5417 BGE_LOCK_ASSERT(sc);
5418
5419 ifp = sc->bge_ifp;
5420
5421 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5422 return;
5423
5424 /* Cancel pending I/O and flush buffers. */
5425 bge_stop(sc);
5426
5427 bge_stop_fw(sc);
5428 bge_sig_pre_reset(sc, BGE_RESET_START);
5429 bge_reset(sc);
5430 bge_sig_legacy(sc, BGE_RESET_START);
5431 bge_sig_post_reset(sc, BGE_RESET_START);
5432
5433 bge_chipinit(sc);
5434
5435 /*
5436 * Init the various state machines, ring
5437 * control blocks and firmware.
5438 */
5439 if (bge_blockinit(sc)) {
5440 device_printf(sc->bge_dev, "initialization failure\n");
5441 return;
5442 }
5443
5444 ifp = sc->bge_ifp;
5445
5446 /* Specify MTU. */
5447 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5448 ETHER_HDR_LEN + ETHER_CRC_LEN +
5449 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5450
5451 /* Load our MAC address. */
5452 m = (uint16_t *)if_getlladdr(sc->bge_ifp);
5453 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5454 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5455
5456 /* Program promiscuous mode. */
5457 bge_setpromisc(sc);
5458
5459 /* Program multicast filter. */
5460 bge_setmulti(sc);
5461
5462 /* Program VLAN tag stripping. */
5463 bge_setvlan(sc);
5464
5465 /* Override UDP checksum offloading. */
5466 if (sc->bge_forced_udpcsum == 0)
5467 sc->bge_csum_features &= ~CSUM_UDP;
5468 else
5469 sc->bge_csum_features |= CSUM_UDP;
5470 if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5471 if_getcapenable(ifp) & IFCAP_TXCSUM) {
5472 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5473 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5474 }
5475
5476 /* Init RX ring. */
5477 if (bge_init_rx_ring_std(sc) != 0) {
5478 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5479 bge_stop(sc);
5480 return;
5481 }
5482
5483 /*
5484 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5485 * memory to insure that the chip has in fact read the first
5486 * entry of the ring.
5487 */
5488 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5489 uint32_t v, i;
5490 for (i = 0; i < 10; i++) {
5491 DELAY(20);
5492 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5493 if (v == (MCLBYTES - ETHER_ALIGN))
5494 break;
5495 }
5496 if (i == 10)
5497 device_printf (sc->bge_dev,
5498 "5705 A0 chip failed to load RX ring\n");
5499 }
5500
5501 /* Init jumbo RX ring. */
5502 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5503 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5504 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5505 if (bge_init_rx_ring_jumbo(sc) != 0) {
5506 device_printf(sc->bge_dev,
5507 "no memory for jumbo Rx buffers.\n");
5508 bge_stop(sc);
5509 return;
5510 }
5511 }
5512
5513 /* Init our RX return ring index. */
5514 sc->bge_rx_saved_considx = 0;
5515
5516 /* Init our RX/TX stat counters. */
5517 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5518
5519 /* Init TX ring. */
5520 bge_init_tx_ring(sc);
5521
5522 /* Enable TX MAC state machine lockup fix. */
5523 mode = CSR_READ_4(sc, BGE_TX_MODE);
5524 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5525 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5526 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5527 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5528 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5529 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5530 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5531 }
5532 /* Turn on transmitter. */
5533 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5534 DELAY(100);
5535
5536 /* Turn on receiver. */
5537 mode = CSR_READ_4(sc, BGE_RX_MODE);
5538 if (BGE_IS_5755_PLUS(sc))
5539 mode |= BGE_RXMODE_IPV6_ENABLE;
5540 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5541 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5542 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5543 DELAY(10);
5544
5545 /*
5546 * Set the number of good frames to receive after RX MBUF
5547 * Low Watermark has been reached. After the RX MAC receives
5548 * this number of frames, it will drop subsequent incoming
5549 * frames until the MBUF High Watermark is reached.
5550 */
5551 if (BGE_IS_57765_PLUS(sc))
5552 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5553 else
5554 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5555
5556 /* Clear MAC statistics. */
5557 if (BGE_IS_5705_PLUS(sc))
5558 bge_stats_clear_regs(sc);
5559
5560 /* Tell firmware we're alive. */
5561 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5562
5563 #ifdef DEVICE_POLLING
5564 /* Disable interrupts if we are polling. */
5565 if (if_getcapenable(ifp) & IFCAP_POLLING) {
5566 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5567 BGE_PCIMISCCTL_MASK_PCI_INTR);
5568 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5569 } else
5570 #endif
5571
5572 /* Enable host interrupts. */
5573 {
5574 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5575 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5576 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5577 }
5578
5579 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5580 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5581
5582 bge_ifmedia_upd_locked(ifp);
5583
5584 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5585 }
5586
5587 static void
bge_init(void * xsc)5588 bge_init(void *xsc)
5589 {
5590 struct bge_softc *sc = xsc;
5591
5592 BGE_LOCK(sc);
5593 bge_init_locked(sc);
5594 BGE_UNLOCK(sc);
5595 }
5596
5597 /*
5598 * Set media options.
5599 */
5600 static int
bge_ifmedia_upd(if_t ifp)5601 bge_ifmedia_upd(if_t ifp)
5602 {
5603 struct bge_softc *sc = if_getsoftc(ifp);
5604 int res;
5605
5606 BGE_LOCK(sc);
5607 res = bge_ifmedia_upd_locked(ifp);
5608 BGE_UNLOCK(sc);
5609
5610 return (res);
5611 }
5612
5613 static int
bge_ifmedia_upd_locked(if_t ifp)5614 bge_ifmedia_upd_locked(if_t ifp)
5615 {
5616 struct bge_softc *sc = if_getsoftc(ifp);
5617 struct mii_data *mii;
5618 struct mii_softc *miisc;
5619 struct ifmedia *ifm;
5620
5621 BGE_LOCK_ASSERT(sc);
5622
5623 ifm = &sc->bge_ifmedia;
5624
5625 /* If this is a 1000baseX NIC, enable the TBI port. */
5626 if (sc->bge_flags & BGE_FLAG_TBI) {
5627 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5628 return (EINVAL);
5629 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5630 case IFM_AUTO:
5631 /*
5632 * The BCM5704 ASIC appears to have a special
5633 * mechanism for programming the autoneg
5634 * advertisement registers in TBI mode.
5635 */
5636 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5637 uint32_t sgdig;
5638 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5639 if (sgdig & BGE_SGDIGSTS_DONE) {
5640 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5641 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5642 sgdig |= BGE_SGDIGCFG_AUTO |
5643 BGE_SGDIGCFG_PAUSE_CAP |
5644 BGE_SGDIGCFG_ASYM_PAUSE;
5645 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5646 sgdig | BGE_SGDIGCFG_SEND);
5647 DELAY(5);
5648 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5649 }
5650 }
5651 break;
5652 case IFM_1000_SX:
5653 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5654 BGE_CLRBIT(sc, BGE_MAC_MODE,
5655 BGE_MACMODE_HALF_DUPLEX);
5656 } else {
5657 BGE_SETBIT(sc, BGE_MAC_MODE,
5658 BGE_MACMODE_HALF_DUPLEX);
5659 }
5660 DELAY(40);
5661 break;
5662 default:
5663 return (EINVAL);
5664 }
5665 return (0);
5666 }
5667
5668 sc->bge_link_evt++;
5669 mii = device_get_softc(sc->bge_miibus);
5670 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5671 PHY_RESET(miisc);
5672 mii_mediachg(mii);
5673
5674 /*
5675 * Force an interrupt so that we will call bge_link_upd
5676 * if needed and clear any pending link state attention.
5677 * Without this we are not getting any further interrupts
5678 * for link state changes and thus will not UP the link and
5679 * not be able to send in bge_start_locked. The only
5680 * way to get things working was to receive a packet and
5681 * get an RX intr.
5682 * bge_tick should help for fiber cards and we might not
5683 * need to do this here if BGE_FLAG_TBI is set but as
5684 * we poll for fiber anyway it should not harm.
5685 */
5686 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5687 sc->bge_flags & BGE_FLAG_5788)
5688 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5689 else
5690 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5691
5692 return (0);
5693 }
5694
5695 /*
5696 * Report current media status.
5697 */
5698 static void
bge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)5699 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5700 {
5701 struct bge_softc *sc = if_getsoftc(ifp);
5702 struct mii_data *mii;
5703
5704 BGE_LOCK(sc);
5705
5706 if ((if_getflags(ifp) & IFF_UP) == 0) {
5707 BGE_UNLOCK(sc);
5708 return;
5709 }
5710 if (sc->bge_flags & BGE_FLAG_TBI) {
5711 ifmr->ifm_status = IFM_AVALID;
5712 ifmr->ifm_active = IFM_ETHER;
5713 if (CSR_READ_4(sc, BGE_MAC_STS) &
5714 BGE_MACSTAT_TBI_PCS_SYNCHED)
5715 ifmr->ifm_status |= IFM_ACTIVE;
5716 else {
5717 ifmr->ifm_active |= IFM_NONE;
5718 BGE_UNLOCK(sc);
5719 return;
5720 }
5721 ifmr->ifm_active |= IFM_1000_SX;
5722 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5723 ifmr->ifm_active |= IFM_HDX;
5724 else
5725 ifmr->ifm_active |= IFM_FDX;
5726 BGE_UNLOCK(sc);
5727 return;
5728 }
5729
5730 mii = device_get_softc(sc->bge_miibus);
5731 mii_pollstat(mii);
5732 ifmr->ifm_active = mii->mii_media_active;
5733 ifmr->ifm_status = mii->mii_media_status;
5734
5735 BGE_UNLOCK(sc);
5736 }
5737
5738 static int
bge_ioctl(if_t ifp,u_long command,caddr_t data)5739 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5740 {
5741 struct bge_softc *sc = if_getsoftc(ifp);
5742 struct ifreq *ifr = (struct ifreq *) data;
5743 struct mii_data *mii;
5744 int flags, mask, error = 0;
5745
5746 switch (command) {
5747 case SIOCSIFMTU:
5748 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5749 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5750 if (ifr->ifr_mtu < ETHERMIN ||
5751 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5752 error = EINVAL;
5753 break;
5754 }
5755 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5756 error = EINVAL;
5757 break;
5758 }
5759 BGE_LOCK(sc);
5760 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5761 if_setmtu(ifp, ifr->ifr_mtu);
5762 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5763 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5764 bge_init_locked(sc);
5765 }
5766 }
5767 BGE_UNLOCK(sc);
5768 break;
5769 case SIOCSIFFLAGS:
5770 BGE_LOCK(sc);
5771 if (if_getflags(ifp) & IFF_UP) {
5772 /*
5773 * If only the state of the PROMISC flag changed,
5774 * then just use the 'set promisc mode' command
5775 * instead of reinitializing the entire NIC. Doing
5776 * a full re-init means reloading the firmware and
5777 * waiting for it to start up, which may take a
5778 * second or two. Similarly for ALLMULTI.
5779 */
5780 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5781 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5782 if (flags & IFF_PROMISC)
5783 bge_setpromisc(sc);
5784 if (flags & IFF_ALLMULTI)
5785 bge_setmulti(sc);
5786 } else
5787 bge_init_locked(sc);
5788 } else {
5789 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5790 bge_stop(sc);
5791 }
5792 }
5793 sc->bge_if_flags = if_getflags(ifp);
5794 BGE_UNLOCK(sc);
5795 error = 0;
5796 break;
5797 case SIOCADDMULTI:
5798 case SIOCDELMULTI:
5799 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5800 BGE_LOCK(sc);
5801 bge_setmulti(sc);
5802 BGE_UNLOCK(sc);
5803 error = 0;
5804 }
5805 break;
5806 case SIOCSIFMEDIA:
5807 case SIOCGIFMEDIA:
5808 if (sc->bge_flags & BGE_FLAG_TBI) {
5809 error = ifmedia_ioctl(ifp, ifr,
5810 &sc->bge_ifmedia, command);
5811 } else {
5812 mii = device_get_softc(sc->bge_miibus);
5813 error = ifmedia_ioctl(ifp, ifr,
5814 &mii->mii_media, command);
5815 }
5816 break;
5817 case SIOCSIFCAP:
5818 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5819 #ifdef DEVICE_POLLING
5820 if (mask & IFCAP_POLLING) {
5821 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5822 error = ether_poll_register(bge_poll, ifp);
5823 if (error)
5824 return (error);
5825 BGE_LOCK(sc);
5826 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5827 BGE_PCIMISCCTL_MASK_PCI_INTR);
5828 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5829 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5830 BGE_UNLOCK(sc);
5831 } else {
5832 error = ether_poll_deregister(ifp);
5833 /* Enable interrupt even in error case */
5834 BGE_LOCK(sc);
5835 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5836 BGE_PCIMISCCTL_MASK_PCI_INTR);
5837 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5838 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5839 BGE_UNLOCK(sc);
5840 }
5841 }
5842 #endif
5843 if ((mask & IFCAP_TXCSUM) != 0 &&
5844 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5845 if_togglecapenable(ifp, IFCAP_TXCSUM);
5846 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5847 if_sethwassistbits(ifp,
5848 sc->bge_csum_features, 0);
5849 else
5850 if_sethwassistbits(ifp, 0,
5851 sc->bge_csum_features);
5852 }
5853
5854 if ((mask & IFCAP_RXCSUM) != 0 &&
5855 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5856 if_togglecapenable(ifp, IFCAP_RXCSUM);
5857
5858 if ((mask & IFCAP_TSO4) != 0 &&
5859 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5860 if_togglecapenable(ifp, IFCAP_TSO4);
5861 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5862 if_sethwassistbits(ifp, CSUM_TSO, 0);
5863 else
5864 if_sethwassistbits(ifp, 0, CSUM_TSO);
5865 }
5866
5867 if (mask & IFCAP_VLAN_MTU) {
5868 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5869 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5870 bge_init(sc);
5871 }
5872
5873 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5874 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5875 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5876 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5877 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5878 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5879 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5880 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5881 BGE_LOCK(sc);
5882 bge_setvlan(sc);
5883 BGE_UNLOCK(sc);
5884 }
5885 #ifdef VLAN_CAPABILITIES
5886 if_vlancap(ifp);
5887 #endif
5888 break;
5889 default:
5890 error = ether_ioctl(ifp, command, data);
5891 break;
5892 }
5893
5894 return (error);
5895 }
5896
5897 static void
bge_watchdog(struct bge_softc * sc)5898 bge_watchdog(struct bge_softc *sc)
5899 {
5900 if_t ifp;
5901 uint32_t status;
5902
5903 BGE_LOCK_ASSERT(sc);
5904
5905 if (sc->bge_timer == 0 || --sc->bge_timer)
5906 return;
5907
5908 /* If pause frames are active then don't reset the hardware. */
5909 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5910 status = CSR_READ_4(sc, BGE_RX_STS);
5911 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5912 /*
5913 * If link partner has us in XOFF state then wait for
5914 * the condition to clear.
5915 */
5916 CSR_WRITE_4(sc, BGE_RX_STS, status);
5917 sc->bge_timer = BGE_TX_TIMEOUT;
5918 return;
5919 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5920 (status & BGE_RXSTAT_RCVD_XON) != 0) {
5921 /*
5922 * If link partner has us in XOFF state then wait for
5923 * the condition to clear.
5924 */
5925 CSR_WRITE_4(sc, BGE_RX_STS, status);
5926 sc->bge_timer = BGE_TX_TIMEOUT;
5927 return;
5928 }
5929 /*
5930 * Any other condition is unexpected and the controller
5931 * should be reset.
5932 */
5933 }
5934
5935 ifp = sc->bge_ifp;
5936
5937 if_printf(ifp, "watchdog timeout -- resetting\n");
5938
5939 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5940 bge_init_locked(sc);
5941
5942 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5943 }
5944
5945 static void
bge_stop_block(struct bge_softc * sc,bus_size_t reg,uint32_t bit)5946 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5947 {
5948 int i;
5949
5950 BGE_CLRBIT(sc, reg, bit);
5951
5952 for (i = 0; i < BGE_TIMEOUT; i++) {
5953 if ((CSR_READ_4(sc, reg) & bit) == 0)
5954 return;
5955 DELAY(100);
5956 }
5957 }
5958
5959 /*
5960 * Stop the adapter and free any mbufs allocated to the
5961 * RX and TX lists.
5962 */
5963 static void
bge_stop(struct bge_softc * sc)5964 bge_stop(struct bge_softc *sc)
5965 {
5966 if_t ifp;
5967
5968 BGE_LOCK_ASSERT(sc);
5969
5970 ifp = sc->bge_ifp;
5971
5972 callout_stop(&sc->bge_stat_ch);
5973
5974 /* Disable host interrupts. */
5975 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5976 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5977
5978 /*
5979 * Tell firmware we're shutting down.
5980 */
5981 bge_stop_fw(sc);
5982 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5983
5984 /*
5985 * Disable all of the receiver blocks.
5986 */
5987 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5988 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5989 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5990 if (BGE_IS_5700_FAMILY(sc))
5991 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5992 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5993 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5994 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5995
5996 /*
5997 * Disable all of the transmit blocks.
5998 */
5999 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6000 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6001 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6002 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6003 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6004 if (BGE_IS_5700_FAMILY(sc))
6005 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6006 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6007
6008 /*
6009 * Shut down all of the memory managers and related
6010 * state machines.
6011 */
6012 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6013 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6014 if (BGE_IS_5700_FAMILY(sc))
6015 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6016
6017 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6018 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6019 if (!(BGE_IS_5705_PLUS(sc))) {
6020 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6021 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6022 }
6023 /* Update MAC statistics. */
6024 if (BGE_IS_5705_PLUS(sc))
6025 bge_stats_update_regs(sc);
6026
6027 bge_reset(sc);
6028 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6029 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6030
6031 /*
6032 * Keep the ASF firmware running if up.
6033 */
6034 if (sc->bge_asf_mode & ASF_STACKUP)
6035 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6036 else
6037 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6038
6039 /* Free the RX lists. */
6040 bge_free_rx_ring_std(sc);
6041
6042 /* Free jumbo RX list. */
6043 if (BGE_IS_JUMBO_CAPABLE(sc))
6044 bge_free_rx_ring_jumbo(sc);
6045
6046 /* Free TX buffers. */
6047 bge_free_tx_ring(sc);
6048
6049 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6050
6051 /* Clear MAC's link state (PHY may still have link UP). */
6052 if (bootverbose && sc->bge_link)
6053 if_printf(sc->bge_ifp, "link DOWN\n");
6054 sc->bge_link = 0;
6055
6056 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6057 }
6058
6059 /*
6060 * Stop all chip I/O so that the kernel's probe routines don't
6061 * get confused by errant DMAs when rebooting.
6062 */
6063 static int
bge_shutdown(device_t dev)6064 bge_shutdown(device_t dev)
6065 {
6066 struct bge_softc *sc;
6067
6068 sc = device_get_softc(dev);
6069 BGE_LOCK(sc);
6070 bge_stop(sc);
6071 BGE_UNLOCK(sc);
6072
6073 return (0);
6074 }
6075
6076 static int
bge_suspend(device_t dev)6077 bge_suspend(device_t dev)
6078 {
6079 struct bge_softc *sc;
6080
6081 sc = device_get_softc(dev);
6082 BGE_LOCK(sc);
6083 bge_stop(sc);
6084 BGE_UNLOCK(sc);
6085
6086 return (0);
6087 }
6088
6089 static int
bge_resume(device_t dev)6090 bge_resume(device_t dev)
6091 {
6092 struct bge_softc *sc;
6093 if_t ifp;
6094
6095 sc = device_get_softc(dev);
6096 BGE_LOCK(sc);
6097 ifp = sc->bge_ifp;
6098 if (if_getflags(ifp) & IFF_UP) {
6099 bge_init_locked(sc);
6100 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6101 bge_start_locked(ifp);
6102 }
6103 BGE_UNLOCK(sc);
6104
6105 return (0);
6106 }
6107
6108 static void
bge_link_upd(struct bge_softc * sc)6109 bge_link_upd(struct bge_softc *sc)
6110 {
6111 struct mii_data *mii;
6112 uint32_t link, status;
6113
6114 BGE_LOCK_ASSERT(sc);
6115
6116 /* Clear 'pending link event' flag. */
6117 sc->bge_link_evt = 0;
6118
6119 /*
6120 * Process link state changes.
6121 * Grrr. The link status word in the status block does
6122 * not work correctly on the BCM5700 rev AX and BX chips,
6123 * according to all available information. Hence, we have
6124 * to enable MII interrupts in order to properly obtain
6125 * async link changes. Unfortunately, this also means that
6126 * we have to read the MAC status register to detect link
6127 * changes, thereby adding an additional register access to
6128 * the interrupt handler.
6129 *
6130 * XXX: perhaps link state detection procedure used for
6131 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6132 */
6133
6134 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6135 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6136 status = CSR_READ_4(sc, BGE_MAC_STS);
6137 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6138 mii = device_get_softc(sc->bge_miibus);
6139 mii_pollstat(mii);
6140 if (!sc->bge_link &&
6141 mii->mii_media_status & IFM_ACTIVE &&
6142 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6143 sc->bge_link++;
6144 if (bootverbose)
6145 if_printf(sc->bge_ifp, "link UP\n");
6146 } else if (sc->bge_link &&
6147 (!(mii->mii_media_status & IFM_ACTIVE) ||
6148 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6149 sc->bge_link = 0;
6150 if (bootverbose)
6151 if_printf(sc->bge_ifp, "link DOWN\n");
6152 }
6153
6154 /* Clear the interrupt. */
6155 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6156 BGE_EVTENB_MI_INTERRUPT);
6157 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6158 BRGPHY_MII_ISR);
6159 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6160 BRGPHY_MII_IMR, BRGPHY_INTRS);
6161 }
6162 return;
6163 }
6164
6165 if (sc->bge_flags & BGE_FLAG_TBI) {
6166 status = CSR_READ_4(sc, BGE_MAC_STS);
6167 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6168 if (!sc->bge_link) {
6169 sc->bge_link++;
6170 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6171 BGE_CLRBIT(sc, BGE_MAC_MODE,
6172 BGE_MACMODE_TBI_SEND_CFGS);
6173 DELAY(40);
6174 }
6175 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6176 if (bootverbose)
6177 if_printf(sc->bge_ifp, "link UP\n");
6178 if_link_state_change(sc->bge_ifp,
6179 LINK_STATE_UP);
6180 }
6181 } else if (sc->bge_link) {
6182 sc->bge_link = 0;
6183 if (bootverbose)
6184 if_printf(sc->bge_ifp, "link DOWN\n");
6185 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6186 }
6187 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6188 /*
6189 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6190 * in status word always set. Workaround this bug by reading
6191 * PHY link status directly.
6192 */
6193 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6194
6195 if (link != sc->bge_link ||
6196 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6197 mii = device_get_softc(sc->bge_miibus);
6198 mii_pollstat(mii);
6199 if (!sc->bge_link &&
6200 mii->mii_media_status & IFM_ACTIVE &&
6201 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6202 sc->bge_link++;
6203 if (bootverbose)
6204 if_printf(sc->bge_ifp, "link UP\n");
6205 } else if (sc->bge_link &&
6206 (!(mii->mii_media_status & IFM_ACTIVE) ||
6207 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6208 sc->bge_link = 0;
6209 if (bootverbose)
6210 if_printf(sc->bge_ifp, "link DOWN\n");
6211 }
6212 }
6213 } else {
6214 /*
6215 * For controllers that call mii_tick, we have to poll
6216 * link status.
6217 */
6218 mii = device_get_softc(sc->bge_miibus);
6219 mii_pollstat(mii);
6220 bge_miibus_statchg(sc->bge_dev);
6221 }
6222
6223 /* Disable MAC attention when link is up. */
6224 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6225 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6226 BGE_MACSTAT_LINK_CHANGED);
6227 }
6228
6229 static void
bge_add_sysctls(struct bge_softc * sc)6230 bge_add_sysctls(struct bge_softc *sc)
6231 {
6232 struct sysctl_ctx_list *ctx;
6233 struct sysctl_oid_list *children;
6234
6235 ctx = device_get_sysctl_ctx(sc->bge_dev);
6236 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6237
6238 #ifdef BGE_REGISTER_DEBUG
6239 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6240 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6241 bge_sysctl_debug_info, "I", "Debug Information");
6242
6243 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6244 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6245 bge_sysctl_reg_read, "I", "MAC Register Read");
6246
6247 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6248 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6249 bge_sysctl_ape_read, "I", "APE Register Read");
6250
6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6252 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6253 bge_sysctl_mem_read, "I", "Memory Read");
6254
6255 #endif
6256
6257 /*
6258 * A common design characteristic for many Broadcom client controllers
6259 * is that they only support a single outstanding DMA read operation
6260 * on the PCIe bus. This means that it will take twice as long to fetch
6261 * a TX frame that is split into header and payload buffers as it does
6262 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6263 * these controllers, coalescing buffers to reduce the number of memory
6264 * reads is effective way to get maximum performance(about 940Mbps).
6265 * Without collapsing TX buffers the maximum TCP bulk transfer
6266 * performance is about 850Mbps. However forcing coalescing mbufs
6267 * consumes a lot of CPU cycles, so leave it off by default.
6268 */
6269 sc->bge_forced_collapse = 0;
6270 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6271 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6272 "Number of fragmented TX buffers of a frame allowed before "
6273 "forced collapsing");
6274
6275 sc->bge_msi = 1;
6276 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6277 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6278
6279 /*
6280 * It seems all Broadcom controllers have a bug that can generate UDP
6281 * datagrams with checksum value 0 when TX UDP checksum offloading is
6282 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6283 * Even though the probability of generating such UDP datagrams is
6284 * low, I don't want to see FreeBSD boxes to inject such datagrams
6285 * into network so disable UDP checksum offloading by default. Users
6286 * still override this behavior by setting a sysctl variable,
6287 * dev.bge.0.forced_udpcsum.
6288 */
6289 sc->bge_forced_udpcsum = 0;
6290 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6291 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6292 "Enable UDP checksum offloading even if controller can "
6293 "generate UDP checksum value 0");
6294
6295 if (BGE_IS_5705_PLUS(sc))
6296 bge_add_sysctl_stats_regs(sc, ctx, children);
6297 else
6298 bge_add_sysctl_stats(sc, ctx, children);
6299 }
6300
6301 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6302 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, \
6303 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \
6304 offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", desc)
6305
6306 static void
bge_add_sysctl_stats(struct bge_softc * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent)6307 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6308 struct sysctl_oid_list *parent)
6309 {
6310 struct sysctl_oid *tree;
6311 struct sysctl_oid_list *children, *schildren;
6312
6313 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6314 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6315 schildren = children = SYSCTL_CHILDREN(tree);
6316 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6317 children, COSFramesDroppedDueToFilters,
6318 "FramesDroppedDueToFilters");
6319 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6320 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6321 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6322 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6323 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6324 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6325 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6326 children, ifInDiscards, "InputDiscards");
6327 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6328 children, ifInErrors, "InputErrors");
6329 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6330 children, nicRecvThresholdHit, "RecvThresholdHit");
6331 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6332 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6333 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6334 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6335 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6336 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6337 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6338 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6339 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6340 children, nicRingStatusUpdate, "RingStatusUpdate");
6341 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6342 children, nicInterrupts, "Interrupts");
6343 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6344 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6345 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6346 children, nicSendThresholdHit, "SendThresholdHit");
6347
6348 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx",
6349 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6350 children = SYSCTL_CHILDREN(tree);
6351 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6352 children, rxstats.ifHCInOctets, "ifHCInOctets");
6353 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6354 children, rxstats.etherStatsFragments, "Fragments");
6355 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6356 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6357 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6358 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6359 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6360 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6361 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6362 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6363 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6364 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6365 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6366 children, rxstats.xoffPauseFramesReceived,
6367 "xoffPauseFramesReceived");
6368 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6369 children, rxstats.macControlFramesReceived,
6370 "ControlFramesReceived");
6371 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6372 children, rxstats.xoffStateEntered, "xoffStateEntered");
6373 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6374 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6375 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6376 children, rxstats.etherStatsJabbers, "Jabbers");
6377 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6378 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6379 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6380 children, rxstats.inRangeLengthError, "inRangeLengthError");
6381 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6382 children, rxstats.outRangeLengthError, "outRangeLengthError");
6383
6384 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx",
6385 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6386 children = SYSCTL_CHILDREN(tree);
6387 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6388 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6389 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6390 children, txstats.etherStatsCollisions, "Collisions");
6391 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6392 children, txstats.outXonSent, "XonSent");
6393 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6394 children, txstats.outXoffSent, "XoffSent");
6395 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6396 children, txstats.flowControlDone, "flowControlDone");
6397 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6398 children, txstats.dot3StatsInternalMacTransmitErrors,
6399 "InternalMacTransmitErrors");
6400 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6401 children, txstats.dot3StatsSingleCollisionFrames,
6402 "SingleCollisionFrames");
6403 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6404 children, txstats.dot3StatsMultipleCollisionFrames,
6405 "MultipleCollisionFrames");
6406 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6407 children, txstats.dot3StatsDeferredTransmissions,
6408 "DeferredTransmissions");
6409 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6410 children, txstats.dot3StatsExcessiveCollisions,
6411 "ExcessiveCollisions");
6412 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6413 children, txstats.dot3StatsLateCollisions,
6414 "LateCollisions");
6415 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6416 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6417 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6418 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6419 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6420 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6421 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6422 children, txstats.dot3StatsCarrierSenseErrors,
6423 "CarrierSenseErrors");
6424 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6425 children, txstats.ifOutDiscards, "Discards");
6426 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6427 children, txstats.ifOutErrors, "Errors");
6428 }
6429
6430 #undef BGE_SYSCTL_STAT
6431
6432 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6433 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6434
6435 static void
bge_add_sysctl_stats_regs(struct bge_softc * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * parent)6436 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6437 struct sysctl_oid_list *parent)
6438 {
6439 struct sysctl_oid *tree;
6440 struct sysctl_oid_list *child, *schild;
6441 struct bge_mac_stats *stats;
6442
6443 stats = &sc->bge_mac_stats;
6444 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6445 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6446 schild = child = SYSCTL_CHILDREN(tree);
6447 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6448 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6449 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6450 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6451 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6452 &stats->DmaWriteHighPriQueueFull,
6453 "NIC DMA Write High Priority Queue Full");
6454 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6455 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6456 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6457 &stats->InputDiscards, "Discarded Input Frames");
6458 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6459 &stats->InputErrors, "Input Errors");
6460 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6461 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6462
6463 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
6464 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6465 child = SYSCTL_CHILDREN(tree);
6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6467 &stats->ifHCInOctets, "Inbound Octets");
6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6469 &stats->etherStatsFragments, "Fragments");
6470 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6471 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6472 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6473 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6474 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6475 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6477 &stats->dot3StatsFCSErrors, "FCS Errors");
6478 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6479 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6481 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6482 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6483 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6484 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6485 &stats->macControlFramesReceived, "MAC Control Frames Received");
6486 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6487 &stats->xoffStateEntered, "XOFF State Entered");
6488 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6489 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6490 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6491 &stats->etherStatsJabbers, "Jabbers");
6492 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6493 &stats->etherStatsUndersizePkts, "Undersized Packets");
6494
6495 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
6496 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6497 child = SYSCTL_CHILDREN(tree);
6498 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6499 &stats->ifHCOutOctets, "Outbound Octets");
6500 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6501 &stats->etherStatsCollisions, "TX Collisions");
6502 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6503 &stats->outXonSent, "XON Sent");
6504 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6505 &stats->outXoffSent, "XOFF Sent");
6506 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6507 &stats->dot3StatsInternalMacTransmitErrors,
6508 "Internal MAC TX Errors");
6509 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6510 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6511 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6512 &stats->dot3StatsMultipleCollisionFrames,
6513 "Multiple Collision Frames");
6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6515 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6516 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6517 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6518 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6519 &stats->dot3StatsLateCollisions, "Late Collisions");
6520 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6521 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6523 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6525 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6526 }
6527
6528 #undef BGE_SYSCTL_STAT_ADD64
6529
6530 static int
bge_sysctl_stats(SYSCTL_HANDLER_ARGS)6531 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6532 {
6533 struct bge_softc *sc;
6534 uint32_t result;
6535 int offset;
6536
6537 sc = (struct bge_softc *)arg1;
6538 offset = arg2;
6539 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6540 offsetof(bge_hostaddr, bge_addr_lo));
6541 return (sysctl_handle_int(oidp, &result, 0, req));
6542 }
6543
6544 #ifdef BGE_REGISTER_DEBUG
6545 static int
bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)6546 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6547 {
6548 struct bge_softc *sc;
6549 uint16_t *sbdata;
6550 int error, result, sbsz;
6551 int i, j;
6552
6553 result = -1;
6554 error = sysctl_handle_int(oidp, &result, 0, req);
6555 if (error || (req->newptr == NULL))
6556 return (error);
6557
6558 if (result == 1) {
6559 sc = (struct bge_softc *)arg1;
6560
6561 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6562 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6563 sbsz = BGE_STATUS_BLK_SZ;
6564 else
6565 sbsz = 32;
6566 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6567 printf("Status Block:\n");
6568 BGE_LOCK(sc);
6569 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6570 sc->bge_cdata.bge_status_map,
6571 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6572 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6573 printf("%06x:", i);
6574 for (j = 0; j < 8; j++)
6575 printf(" %04x", sbdata[i++]);
6576 printf("\n");
6577 }
6578
6579 printf("Registers:\n");
6580 for (i = 0x800; i < 0xA00; ) {
6581 printf("%06x:", i);
6582 for (j = 0; j < 8; j++) {
6583 printf(" %08x", CSR_READ_4(sc, i));
6584 i += 4;
6585 }
6586 printf("\n");
6587 }
6588 BGE_UNLOCK(sc);
6589
6590 printf("Hardware Flags:\n");
6591 if (BGE_IS_5717_PLUS(sc))
6592 printf(" - 5717 Plus\n");
6593 if (BGE_IS_5755_PLUS(sc))
6594 printf(" - 5755 Plus\n");
6595 if (BGE_IS_575X_PLUS(sc))
6596 printf(" - 575X Plus\n");
6597 if (BGE_IS_5705_PLUS(sc))
6598 printf(" - 5705 Plus\n");
6599 if (BGE_IS_5714_FAMILY(sc))
6600 printf(" - 5714 Family\n");
6601 if (BGE_IS_5700_FAMILY(sc))
6602 printf(" - 5700 Family\n");
6603 if (sc->bge_flags & BGE_FLAG_JUMBO)
6604 printf(" - Supports Jumbo Frames\n");
6605 if (sc->bge_flags & BGE_FLAG_PCIX)
6606 printf(" - PCI-X Bus\n");
6607 if (sc->bge_flags & BGE_FLAG_PCIE)
6608 printf(" - PCI Express Bus\n");
6609 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6610 printf(" - No 3 LEDs\n");
6611 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6612 printf(" - RX Alignment Bug\n");
6613 }
6614
6615 return (error);
6616 }
6617
6618 static int
bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)6619 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6620 {
6621 struct bge_softc *sc;
6622 int error;
6623 uint16_t result;
6624 uint32_t val;
6625
6626 result = -1;
6627 error = sysctl_handle_int(oidp, &result, 0, req);
6628 if (error || (req->newptr == NULL))
6629 return (error);
6630
6631 if (result < 0x8000) {
6632 sc = (struct bge_softc *)arg1;
6633 val = CSR_READ_4(sc, result);
6634 printf("reg 0x%06X = 0x%08X\n", result, val);
6635 }
6636
6637 return (error);
6638 }
6639
6640 static int
bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)6641 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6642 {
6643 struct bge_softc *sc;
6644 int error;
6645 uint16_t result;
6646 uint32_t val;
6647
6648 result = -1;
6649 error = sysctl_handle_int(oidp, &result, 0, req);
6650 if (error || (req->newptr == NULL))
6651 return (error);
6652
6653 if (result < 0x8000) {
6654 sc = (struct bge_softc *)arg1;
6655 val = APE_READ_4(sc, result);
6656 printf("reg 0x%06X = 0x%08X\n", result, val);
6657 }
6658
6659 return (error);
6660 }
6661
6662 static int
bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)6663 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6664 {
6665 struct bge_softc *sc;
6666 int error;
6667 uint16_t result;
6668 uint32_t val;
6669
6670 result = -1;
6671 error = sysctl_handle_int(oidp, &result, 0, req);
6672 if (error || (req->newptr == NULL))
6673 return (error);
6674
6675 if (result < 0x8000) {
6676 sc = (struct bge_softc *)arg1;
6677 val = bge_readmem_ind(sc, result);
6678 printf("mem 0x%06X = 0x%08X\n", result, val);
6679 }
6680
6681 return (error);
6682 }
6683 #endif
6684
6685 static int
bge_get_eaddr_fw(struct bge_softc * sc,uint8_t ether_addr[])6686 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6687 {
6688 const char *mac_str;
6689 unsigned int o[ETHER_ADDR_LEN];
6690 char trail;
6691 int i, n, unit;
6692
6693 unit = device_get_unit(sc->bge_dev);
6694 if (resource_string_value("bge", unit, "mac", &mac_str) != 0)
6695 return (1);
6696
6697 /* Parse and validate; trailing-char check rejects garbage. */
6698 n = sscanf(mac_str, "%x:%x:%x:%x:%x:%x%c",
6699 &o[0], &o[1], &o[2], &o[3], &o[4], &o[5], &trail);
6700 if (n != 6)
6701 return (1);
6702 for (i = 0; i < ETHER_ADDR_LEN; i++) {
6703 if (o[i] > 0xff)
6704 return (1);
6705 ether_addr[i] = (uint8_t)o[i];
6706 }
6707 if (ETHER_IS_MULTICAST(ether_addr) ||
6708 ETHER_IS_ZERO(ether_addr))
6709 return (1);
6710 return (0);
6711 }
6712
6713 static int
bge_get_eaddr_mem(struct bge_softc * sc,uint8_t ether_addr[])6714 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6715 {
6716 uint32_t mac_addr;
6717
6718 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6719 if ((mac_addr >> 16) == 0x484b) {
6720 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6721 ether_addr[1] = (uint8_t)mac_addr;
6722 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6723 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6724 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6725 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6726 ether_addr[5] = (uint8_t)mac_addr;
6727 return (0);
6728 }
6729 return (1);
6730 }
6731
6732 static int
bge_get_eaddr_nvram(struct bge_softc * sc,uint8_t ether_addr[])6733 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6734 {
6735 int mac_offset = BGE_EE_MAC_OFFSET;
6736
6737 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6738 mac_offset = BGE_EE_MAC_OFFSET_5906;
6739
6740 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6741 ETHER_ADDR_LEN));
6742 }
6743
6744 static int
bge_get_eaddr_eeprom(struct bge_softc * sc,uint8_t ether_addr[])6745 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6746 {
6747
6748 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6749 return (1);
6750
6751 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6752 ETHER_ADDR_LEN));
6753 }
6754
6755 static int
bge_get_eaddr(struct bge_softc * sc,uint8_t eaddr[])6756 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6757 {
6758 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6759 /* NOTE: Order is critical */
6760 bge_get_eaddr_fw,
6761 bge_get_eaddr_mem,
6762 bge_get_eaddr_nvram,
6763 bge_get_eaddr_eeprom,
6764 NULL
6765 };
6766 const bge_eaddr_fcn_t *func;
6767
6768 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6769 if ((*func)(sc, eaddr) == 0)
6770 break;
6771 }
6772 return (*func == NULL ? ENXIO : 0);
6773 }
6774
6775 static uint64_t
bge_get_counter(if_t ifp,ift_counter cnt)6776 bge_get_counter(if_t ifp, ift_counter cnt)
6777 {
6778 struct bge_softc *sc;
6779 struct bge_mac_stats *stats;
6780
6781 sc = if_getsoftc(ifp);
6782 if (!BGE_IS_5705_PLUS(sc))
6783 return (if_get_counter_default(ifp, cnt));
6784 stats = &sc->bge_mac_stats;
6785
6786 switch (cnt) {
6787 case IFCOUNTER_IERRORS:
6788 return (stats->NoMoreRxBDs + stats->InputDiscards +
6789 stats->InputErrors);
6790 case IFCOUNTER_COLLISIONS:
6791 return (stats->etherStatsCollisions);
6792 default:
6793 return (if_get_counter_default(ifp, cnt));
6794 }
6795 }
6796
6797 #ifdef DEBUGNET
6798 static void
bge_debugnet_init(if_t ifp,int * nrxr,int * ncl,int * clsize)6799 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6800 {
6801 struct bge_softc *sc;
6802
6803 sc = if_getsoftc(ifp);
6804 BGE_LOCK(sc);
6805 /*
6806 * There is only one logical receive ring, but it is backed
6807 * by two actual rings, for cluster- and jumbo-sized mbufs.
6808 * Debugnet expects only one size, so if jumbo is in use,
6809 * this says we have two rings of jumbo mbufs, but that's
6810 * only a little wasteful.
6811 */
6812 *nrxr = 2;
6813 *ncl = DEBUGNET_MAX_IN_FLIGHT;
6814 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6815 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6816 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6817 *clsize = MJUM9BYTES;
6818 else
6819 *clsize = MCLBYTES;
6820 BGE_UNLOCK(sc);
6821 }
6822
6823 static void
bge_debugnet_event(if_t ifp __unused,enum debugnet_ev event __unused)6824 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
6825 {
6826 }
6827
6828 static int
bge_debugnet_transmit(if_t ifp,struct mbuf * m)6829 bge_debugnet_transmit(if_t ifp, struct mbuf *m)
6830 {
6831 struct bge_softc *sc;
6832 uint32_t prodidx;
6833 int error;
6834
6835 sc = if_getsoftc(ifp);
6836 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6837 IFF_DRV_RUNNING)
6838 return (1);
6839
6840 prodidx = sc->bge_tx_prodidx;
6841 error = bge_encap(sc, &m, &prodidx);
6842 if (error == 0)
6843 bge_start_tx(sc, prodidx);
6844 return (error);
6845 }
6846
6847 static int
bge_debugnet_poll(if_t ifp,int count)6848 bge_debugnet_poll(if_t ifp, int count)
6849 {
6850 struct bge_softc *sc;
6851 uint32_t rx_prod, tx_cons;
6852
6853 sc = if_getsoftc(ifp);
6854 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6855 IFF_DRV_RUNNING)
6856 return (1);
6857
6858 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6859 sc->bge_cdata.bge_status_map,
6860 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6861
6862 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6863 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6864
6865 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6866 sc->bge_cdata.bge_status_map,
6867 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6868
6869 (void)bge_rxeof(sc, rx_prod, 0);
6870 bge_txeof(sc, tx_cons);
6871 return (0);
6872 }
6873 #endif /* DEBUGNET */
6874