1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 The FreeBSD Foundation
5 *
6 * This driver was written by Gerald ND Aryeetey <gndaryee@uwaterloo.ca>
7 * under sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30 #include <sys/cdefs.h>
31 /*
32 * Microchip LAN7430/LAN7431 PCIe to Gigabit Ethernet Controller driver.
33 *
34 * Product information:
35 * LAN7430 https://www.microchip.com/en-us/product/LAN7430
36 * - Integrated IEEE 802.3 compliant PHY
37 * LAN7431 https://www.microchip.com/en-us/product/LAN7431
38 * - RGMII Interface
39 *
40 * This driver uses the iflib interface and the default 'ukphy' PHY driver.
41 *
42 * UNIMPLEMENTED FEATURES
43 * ----------------------
44 * A number of features supported by LAN743X device are not yet implemented in
45 * this driver:
46 *
47 * - Multiple (up to 4) RX queues support
48 * - Just needs to remove asserts and malloc multiple `rx_ring_data`
49 * structs based on ncpus.
50 * - RX/TX Checksum Offloading support
51 * - VLAN support
52 * - Receive Packet Filtering (Multicast Perfect/Hash Address) support
53 * - Wake on LAN (WoL) support
54 * - TX LSO support
55 * - Receive Side Scaling (RSS) support
56 * - Debugging Capabilities:
57 * - Could include MAC statistics and
58 * error status registers in sysctl.
59 */
60
61 #include <sys/param.h>
62 #include <sys/bus.h>
63 #include <sys/endian.h>
64 #include <sys/kdb.h>
65 #include <sys/kernel.h>
66 #include <sys/module.h>
67 #include <sys/rman.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <machine/bus.h>
71 #include <machine/resource.h>
72
73 #include <net/ethernet.h>
74 #include <net/if.h>
75 #include <net/if_var.h>
76 #include <net/if_types.h>
77 #include <net/if_media.h>
78 #include <net/iflib.h>
79
80 #include <dev/mgb/if_mgb.h>
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
85
86 #include "ifdi_if.h"
87 #include "miibus_if.h"
88
89 static const pci_vendor_info_t mgb_vendor_info_array[] = {
90 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_LAN7430_DEVICE_ID,
91 "Microchip LAN7430 PCIe Gigabit Ethernet Controller"),
92 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_LAN7431_DEVICE_ID,
93 "Microchip LAN7431 PCIe Gigabit Ethernet Controller"),
94 PVID(MGB_MICROCHIP_VENDOR_ID, MGB_PCI11414_DEVICE_ID,
95 "Microchip PCI11414 PCIe Gigabit Ethernet Controller"),
96 PVID_END
97 };
98
99 /* Device methods */
100 static device_register_t mgb_register;
101
102 /* IFLIB methods */
103 static ifdi_attach_pre_t mgb_attach_pre;
104 static ifdi_attach_post_t mgb_attach_post;
105 static ifdi_detach_t mgb_detach;
106
107 static ifdi_tx_queues_alloc_t mgb_tx_queues_alloc;
108 static ifdi_rx_queues_alloc_t mgb_rx_queues_alloc;
109 static ifdi_queues_free_t mgb_queues_free;
110
111 static ifdi_init_t mgb_init;
112 static ifdi_stop_t mgb_stop;
113
114 static ifdi_msix_intr_assign_t mgb_msix_intr_assign;
115 static ifdi_tx_queue_intr_enable_t mgb_tx_queue_intr_enable;
116 static ifdi_rx_queue_intr_enable_t mgb_rx_queue_intr_enable;
117 static ifdi_intr_enable_t mgb_intr_enable_all;
118 static ifdi_intr_disable_t mgb_intr_disable_all;
119
120 /* IFLIB_TXRX methods */
121 static int mgb_isc_txd_encap(void *,
122 if_pkt_info_t);
123 static void mgb_isc_txd_flush(void *,
124 uint16_t, qidx_t);
125 static int mgb_isc_txd_credits_update(void *,
126 uint16_t, bool);
127 static int mgb_isc_rxd_available(void *,
128 uint16_t, qidx_t, qidx_t);
129 static int mgb_isc_rxd_pkt_get(void *,
130 if_rxd_info_t);
131 static void mgb_isc_rxd_refill(void *,
132 if_rxd_update_t);
133 static void mgb_isc_rxd_flush(void *,
134 uint16_t, uint8_t, qidx_t);
135
136 /* Interrupts */
137 static driver_filter_t mgb_legacy_intr;
138 static driver_filter_t mgb_admin_intr;
139 static driver_filter_t mgb_rxq_intr;
140 static bool mgb_intr_test(struct mgb_softc *);
141
142 /* MII methods */
143 static miibus_readreg_t mgb_miibus_readreg;
144 static miibus_writereg_t mgb_miibus_writereg;
145 static miibus_linkchg_t mgb_miibus_linkchg;
146 static miibus_statchg_t mgb_miibus_statchg;
147
148 static int mgb_media_change(if_t);
149 static void mgb_media_status(if_t,
150 struct ifmediareq *);
151
152 /* Helper/Test functions */
153 static int mgb_test_bar(struct mgb_softc *);
154 static int mgb_alloc_regs(struct mgb_softc *);
155 static int mgb_release_regs(struct mgb_softc *);
156
157 static void mgb_get_ethaddr(struct mgb_softc *,
158 struct ether_addr *);
159
160 static int mgb_wait_for_bits(struct mgb_softc *,
161 int, int, int);
162
163 /* H/W init, reset and teardown helpers */
164 static int mgb_hw_init(struct mgb_softc *);
165 static int mgb_hw_teardown(struct mgb_softc *);
166 static int mgb_hw_reset(struct mgb_softc *);
167 static int mgb_mac_init(struct mgb_softc *);
168 static int mgb_dmac_reset(struct mgb_softc *);
169 static int mgb_phy_reset(struct mgb_softc *);
170
171 static int mgb_dma_init(struct mgb_softc *);
172 static int mgb_dma_tx_ring_init(struct mgb_softc *,
173 int);
174 static int mgb_dma_rx_ring_init(struct mgb_softc *,
175 int);
176
177 static int mgb_dmac_control(struct mgb_softc *,
178 int, int, enum mgb_dmac_cmd);
179 static int mgb_fct_control(struct mgb_softc *,
180 int, int, enum mgb_fct_cmd);
181
182 /*********************************************************************
183 * FreeBSD Device Interface Entry Points
184 *********************************************************************/
185
186 static device_method_t mgb_methods[] = {
187 /* Device interface */
188 DEVMETHOD(device_register, mgb_register),
189 DEVMETHOD(device_probe, iflib_device_probe),
190 DEVMETHOD(device_attach, iflib_device_attach),
191 DEVMETHOD(device_detach, iflib_device_detach),
192 DEVMETHOD(device_shutdown, iflib_device_shutdown),
193 DEVMETHOD(device_suspend, iflib_device_suspend),
194 DEVMETHOD(device_resume, iflib_device_resume),
195
196 /* MII Interface */
197 DEVMETHOD(miibus_readreg, mgb_miibus_readreg),
198 DEVMETHOD(miibus_writereg, mgb_miibus_writereg),
199 DEVMETHOD(miibus_linkchg, mgb_miibus_linkchg),
200 DEVMETHOD(miibus_statchg, mgb_miibus_statchg),
201
202 DEVMETHOD_END
203 };
204
205 static driver_t mgb_driver = {
206 "mgb", mgb_methods, sizeof(struct mgb_softc)
207 };
208
209 DRIVER_MODULE(mgb, pci, mgb_driver, NULL, NULL);
210 IFLIB_PNP_INFO(pci, mgb, mgb_vendor_info_array);
211 MODULE_VERSION(mgb, 1);
212
213 #if 0 /* MIIBUS_DEBUG */
214 /* If MIIBUS debug stuff is in attach then order matters. Use below instead. */
215 DRIVER_MODULE_ORDERED(miibus, mgb, miibus_driver, NULL, NULL,
216 SI_ORDER_ANY);
217 #endif /* MIIBUS_DEBUG */
218 DRIVER_MODULE(miibus, mgb, miibus_driver, NULL, NULL);
219
220 MODULE_DEPEND(mgb, pci, 1, 1, 1);
221 MODULE_DEPEND(mgb, ether, 1, 1, 1);
222 MODULE_DEPEND(mgb, miibus, 1, 1, 1);
223 MODULE_DEPEND(mgb, iflib, 1, 1, 1);
224
225 static device_method_t mgb_iflib_methods[] = {
226 DEVMETHOD(ifdi_attach_pre, mgb_attach_pre),
227 DEVMETHOD(ifdi_attach_post, mgb_attach_post),
228 DEVMETHOD(ifdi_detach, mgb_detach),
229
230 DEVMETHOD(ifdi_init, mgb_init),
231 DEVMETHOD(ifdi_stop, mgb_stop),
232
233 DEVMETHOD(ifdi_tx_queues_alloc, mgb_tx_queues_alloc),
234 DEVMETHOD(ifdi_rx_queues_alloc, mgb_rx_queues_alloc),
235 DEVMETHOD(ifdi_queues_free, mgb_queues_free),
236
237 DEVMETHOD(ifdi_msix_intr_assign, mgb_msix_intr_assign),
238 DEVMETHOD(ifdi_tx_queue_intr_enable, mgb_tx_queue_intr_enable),
239 DEVMETHOD(ifdi_rx_queue_intr_enable, mgb_rx_queue_intr_enable),
240 DEVMETHOD(ifdi_intr_enable, mgb_intr_enable_all),
241 DEVMETHOD(ifdi_intr_disable, mgb_intr_disable_all),
242
243 #if 0 /* Not yet implemented IFLIB methods */
244 /*
245 * Set multicast addresses, mtu and promiscuous mode
246 */
247 DEVMETHOD(ifdi_multi_set, mgb_multi_set),
248 DEVMETHOD(ifdi_mtu_set, mgb_mtu_set),
249 DEVMETHOD(ifdi_promisc_set, mgb_promisc_set),
250
251 /*
252 * Needed for VLAN support
253 */
254 DEVMETHOD(ifdi_vlan_register, mgb_vlan_register),
255 DEVMETHOD(ifdi_vlan_unregister, mgb_vlan_unregister),
256 DEVMETHOD(ifdi_needs_restart, mgb_if_needs_restart),
257
258 /*
259 * Needed for WOL support
260 * at the very least.
261 */
262 DEVMETHOD(ifdi_shutdown, mgb_shutdown),
263 DEVMETHOD(ifdi_suspend, mgb_suspend),
264 DEVMETHOD(ifdi_resume, mgb_resume),
265 #endif /* UNUSED_IFLIB_METHODS */
266 DEVMETHOD_END
267 };
268
269 static driver_t mgb_iflib_driver = {
270 "mgb", mgb_iflib_methods, sizeof(struct mgb_softc)
271 };
272
273 static struct if_txrx mgb_txrx = {
274 .ift_txd_encap = mgb_isc_txd_encap,
275 .ift_txd_flush = mgb_isc_txd_flush,
276 .ift_txd_credits_update = mgb_isc_txd_credits_update,
277 .ift_rxd_available = mgb_isc_rxd_available,
278 .ift_rxd_pkt_get = mgb_isc_rxd_pkt_get,
279 .ift_rxd_refill = mgb_isc_rxd_refill,
280 .ift_rxd_flush = mgb_isc_rxd_flush,
281
282 .ift_legacy_intr = mgb_legacy_intr
283 };
284
285 static struct if_shared_ctx mgb_sctx_init = {
286 .isc_magic = IFLIB_MAGIC,
287
288 .isc_q_align = PAGE_SIZE,
289 .isc_admin_intrcnt = 1,
290 .isc_flags = IFLIB_DRIVER_MEDIA /* | IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ*/,
291
292 .isc_vendor_info = mgb_vendor_info_array,
293 .isc_driver_version = "1",
294 .isc_driver = &mgb_iflib_driver,
295 /* 2 queues per set for TX and RX (ring queue, head writeback queue) */
296 .isc_ntxqs = 2,
297
298 .isc_tx_maxsize = MGB_DMA_MAXSEGS * MCLBYTES,
299 /* .isc_tx_nsegments = MGB_DMA_MAXSEGS, */
300 .isc_tx_maxsegsize = MCLBYTES,
301
302 .isc_ntxd_min = {1, 1}, /* Will want to make this bigger */
303 .isc_ntxd_max = {MGB_DMA_RING_SIZE, 1},
304 .isc_ntxd_default = {MGB_DMA_RING_SIZE, 1},
305
306 .isc_nrxqs = 2,
307
308 .isc_rx_maxsize = MCLBYTES,
309 .isc_rx_nsegments = 1,
310 .isc_rx_maxsegsize = MCLBYTES,
311
312 .isc_nrxd_min = {1, 1}, /* Will want to make this bigger */
313 .isc_nrxd_max = {MGB_DMA_RING_SIZE, 1},
314 .isc_nrxd_default = {MGB_DMA_RING_SIZE, 1},
315
316 .isc_nfl = 1, /*one free list since there is only one queue */
317 #if 0 /* UNUSED_CTX */
318
319 .isc_tso_maxsize = MGB_TSO_MAXSIZE + sizeof(struct ether_vlan_header),
320 .isc_tso_maxsegsize = MGB_TX_MAXSEGSIZE,
321 #endif /* UNUSED_CTX */
322 };
323
324 /*********************************************************************/
325
326 static void *
mgb_register(device_t dev)327 mgb_register(device_t dev)
328 {
329
330 return (&mgb_sctx_init);
331 }
332
333 static int
mgb_mii_attach(struct mgb_softc * sc)334 mgb_mii_attach(struct mgb_softc *sc)
335 {
336 struct mii_data *miid;
337 if_softc_ctx_t scctx;
338 int phyaddr;
339 int error;
340
341 scctx = iflib_get_softc_ctx(sc->ctx);
342
343 switch (pci_get_device(sc->dev)) {
344 case MGB_LAN7430_DEVICE_ID:
345 phyaddr = 1;
346 break;
347 case MGB_LAN7431_DEVICE_ID:
348 default:
349 phyaddr = MII_PHY_ANY;
350 break;
351 }
352
353 /* XXX: Would be nice(r) if locked methods were here */
354 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(sc->ctx),
355 mgb_media_change, mgb_media_status,
356 BMSR_DEFCAPMASK, phyaddr, MII_OFFSET_ANY, MIIF_DOPAUSE);
357 if (error != 0) {
358 device_printf(sc->dev, "Failed to attach MII interface\n");
359 return (error);
360 }
361
362 miid = device_get_softc(sc->miibus);
363 scctx->isc_media = &miid->mii_media;
364
365 return (0);
366 }
367
368 static int
mgb_attach_pre(if_ctx_t ctx)369 mgb_attach_pre(if_ctx_t ctx)
370 {
371 struct mgb_softc *sc;
372 if_softc_ctx_t scctx;
373 int error, rid;
374 struct ether_addr hwaddr;
375
376 sc = iflib_get_softc(ctx);
377 sc->ctx = ctx;
378 sc->dev = iflib_get_dev(ctx);
379 scctx = iflib_get_softc_ctx(ctx);
380
381 /* IFLIB required setup */
382 scctx->isc_txrx = &mgb_txrx;
383 scctx->isc_tx_nsegments = MGB_DMA_MAXSEGS;
384 /* Ring desc queues */
385 scctx->isc_txqsizes[0] = sizeof(struct mgb_ring_desc) *
386 scctx->isc_ntxd[0];
387 scctx->isc_rxqsizes[0] = sizeof(struct mgb_ring_desc) *
388 scctx->isc_nrxd[0];
389
390 /* Head WB queues */
391 scctx->isc_txqsizes[1] = sizeof(uint32_t) * scctx->isc_ntxd[1];
392 scctx->isc_rxqsizes[1] = sizeof(uint32_t) * scctx->isc_nrxd[1];
393
394 /* XXX: Must have 1 txqset, but can have up to 4 rxqsets */
395 scctx->isc_nrxqsets = 1;
396 scctx->isc_ntxqsets = 1;
397
398 /* scctx->isc_tx_csum_flags = (CSUM_TCP | CSUM_UDP) |
399 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6) | CSUM_TSO */
400 scctx->isc_tx_csum_flags = 0;
401 scctx->isc_capabilities = scctx->isc_capenable = 0;
402 #if 0
403 /*
404 * CSUM, TSO and VLAN support are TBD
405 */
406 IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 |
407 IFCAP_TSO4 | IFCAP_TSO6 |
408 IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 |
409 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
410 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO |
411 IFCAP_JUMBO_MTU;
412 scctx->isc_capabilities |= IFCAP_LRO | IFCAP_VLAN_HWFILTER;
413 #endif
414
415 /* get the BAR */
416 error = mgb_alloc_regs(sc);
417 if (error != 0) {
418 device_printf(sc->dev,
419 "Unable to allocate bus resource: registers.\n");
420 goto fail;
421 }
422
423 error = mgb_test_bar(sc);
424 if (error != 0)
425 goto fail;
426
427 error = mgb_hw_init(sc);
428 if (error != 0) {
429 device_printf(sc->dev,
430 "MGB device init failed. (err: %d)\n", error);
431 goto fail;
432 }
433
434 if (!sc->sgmii_en) {
435 error = mgb_mii_attach(sc);
436 if (error)
437 goto fail;
438 }
439
440 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev);
441 /** Setup PBA BAR **/
442 rid = pci_msix_pba_bar(sc->dev);
443 if (rid != scctx->isc_msix_bar) {
444 sc->pba = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
445 &rid, RF_ACTIVE);
446 if (sc->pba == NULL) {
447 error = ENXIO;
448 device_printf(sc->dev, "Failed to setup PBA BAR\n");
449 goto fail;
450 }
451 }
452
453 mgb_get_ethaddr(sc, &hwaddr);
454 if (ETHER_IS_BROADCAST(hwaddr.octet) ||
455 ETHER_IS_MULTICAST(hwaddr.octet) ||
456 ETHER_IS_ZERO(hwaddr.octet))
457 ether_gen_addr(iflib_get_ifp(ctx), &hwaddr);
458
459 /*
460 * XXX: if the MAC address was generated the linux driver
461 * writes it back to the device.
462 */
463 iflib_set_mac(ctx, hwaddr.octet);
464
465 /* Map all vectors to vector 0 (admin interrupts) by default. */
466 CSR_WRITE_REG(sc, MGB_INTR_VEC_RX_MAP, 0);
467 CSR_WRITE_REG(sc, MGB_INTR_VEC_TX_MAP, 0);
468 CSR_WRITE_REG(sc, MGB_INTR_VEC_OTHER_MAP, 0);
469
470 if (sc->sgmii_en) {
471 /* Unsure which speed to set, use 1Gbps as default. */
472 iflib_link_state_change(ctx, LINK_STATE_UP, IF_Mbps(1000));
473 }
474
475 return (0);
476
477 fail:
478 mgb_detach(ctx);
479 return (error);
480 }
481
482 static int
mgb_attach_post(if_ctx_t ctx)483 mgb_attach_post(if_ctx_t ctx)
484 {
485 struct mgb_softc *sc;
486
487 sc = iflib_get_softc(ctx);
488
489 device_printf(sc->dev, "Interrupt test: %s\n",
490 (mgb_intr_test(sc) ? "PASS" : "FAIL"));
491
492 return (0);
493 }
494
495 static int
mgb_detach(if_ctx_t ctx)496 mgb_detach(if_ctx_t ctx)
497 {
498 struct mgb_softc *sc;
499 int error;
500
501 sc = iflib_get_softc(ctx);
502
503 /* XXX: Should report errors but still detach everything. */
504 error = mgb_hw_teardown(sc);
505
506 /* Release IRQs */
507 iflib_irq_free(ctx, &sc->rx_irq);
508 iflib_irq_free(ctx, &sc->admin_irq);
509
510 bus_generic_detach(sc->dev);
511
512 if (sc->pba != NULL)
513 error = bus_release_resource(sc->dev, SYS_RES_MEMORY,
514 rman_get_rid(sc->pba), sc->pba);
515 sc->pba = NULL;
516
517 error = mgb_release_regs(sc);
518
519 return (error);
520 }
521
522 static int
mgb_media_change(if_t ifp)523 mgb_media_change(if_t ifp)
524 {
525 struct mii_data *miid;
526 struct mii_softc *miisc;
527 struct mgb_softc *sc;
528 if_ctx_t ctx;
529 int needs_reset;
530
531 ctx = if_getsoftc(ifp);
532 sc = iflib_get_softc(ctx);
533 miid = device_get_softc(sc->miibus);
534 LIST_FOREACH(miisc, &miid->mii_phys, mii_list)
535 PHY_RESET(miisc);
536
537 needs_reset = mii_mediachg(miid);
538 if (needs_reset != 0)
539 if_init(ifp, ctx);
540 return (needs_reset);
541 }
542
543 static void
mgb_media_status(if_t ifp,struct ifmediareq * ifmr)544 mgb_media_status(if_t ifp, struct ifmediareq *ifmr)
545 {
546 struct mgb_softc *sc;
547 struct mii_data *miid;
548
549 sc = iflib_get_softc(if_getsoftc(ifp));
550 miid = device_get_softc(sc->miibus);
551 if ((if_getflags(ifp) & IFF_UP) == 0)
552 return;
553
554 mii_pollstat(miid);
555 ifmr->ifm_active = miid->mii_media_active;
556 ifmr->ifm_status = miid->mii_media_status;
557 }
558
559 static int
mgb_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)560 mgb_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs,
561 int ntxqsets)
562 {
563 struct mgb_softc *sc;
564 struct mgb_ring_data *rdata;
565 int q;
566
567 sc = iflib_get_softc(ctx);
568 KASSERT(ntxqsets == 1, ("ntxqsets = %d", ntxqsets));
569 rdata = &sc->tx_ring_data;
570 for (q = 0; q < ntxqsets; q++) {
571 KASSERT(ntxqs == 2, ("ntxqs = %d", ntxqs));
572 /* Ring */
573 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * ntxqs + 0];
574 rdata->ring_bus_addr = paddrs[q * ntxqs + 0];
575
576 /* Head WB */
577 rdata->head_wb = (uint32_t *) vaddrs[q * ntxqs + 1];
578 rdata->head_wb_bus_addr = paddrs[q * ntxqs + 1];
579 }
580 return (0);
581 }
582
583 static int
mgb_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)584 mgb_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs,
585 int nrxqsets)
586 {
587 struct mgb_softc *sc;
588 struct mgb_ring_data *rdata;
589 int q;
590
591 sc = iflib_get_softc(ctx);
592 KASSERT(nrxqsets == 1, ("nrxqsets = %d", nrxqsets));
593 rdata = &sc->rx_ring_data;
594 for (q = 0; q < nrxqsets; q++) {
595 KASSERT(nrxqs == 2, ("nrxqs = %d", nrxqs));
596 /* Ring */
597 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * nrxqs + 0];
598 rdata->ring_bus_addr = paddrs[q * nrxqs + 0];
599
600 /* Head WB */
601 rdata->head_wb = (uint32_t *) vaddrs[q * nrxqs + 1];
602 rdata->head_wb_bus_addr = paddrs[q * nrxqs + 1];
603 }
604 return (0);
605 }
606
607 static void
mgb_queues_free(if_ctx_t ctx)608 mgb_queues_free(if_ctx_t ctx)
609 {
610 struct mgb_softc *sc;
611
612 sc = iflib_get_softc(ctx);
613
614 memset(&sc->rx_ring_data, 0, sizeof(struct mgb_ring_data));
615 memset(&sc->tx_ring_data, 0, sizeof(struct mgb_ring_data));
616 }
617
618 static void
mgb_init(if_ctx_t ctx)619 mgb_init(if_ctx_t ctx)
620 {
621 struct mgb_softc *sc;
622 struct mii_data *miid;
623 int error;
624
625 sc = iflib_get_softc(ctx);
626
627 error = mgb_dma_init(sc);
628 if (error != 0) {
629 device_printf(sc->dev, "DMA initialization failed: %d\n", error);
630 iflib_init_failed(ctx);
631 return;
632 }
633
634 /* XXX: Turn off perfect filtering, turn on (broad|multi|uni)cast rx */
635 CSR_CLEAR_REG(sc, MGB_RFE_CTL, MGB_RFE_ALLOW_PERFECT_FILTER);
636 CSR_UPDATE_REG(sc, MGB_RFE_CTL,
637 MGB_RFE_ALLOW_BROADCAST |
638 MGB_RFE_ALLOW_MULTICAST |
639 MGB_RFE_ALLOW_UNICAST);
640
641 if (sc->sgmii_en)
642 return;
643
644 miid = device_get_softc(sc->miibus);
645 error = mii_mediachg(miid);
646 /* Not much we can do if this fails. */
647 if (error)
648 device_printf(sc->dev, "%s: mii_mediachg returned %d", __func__,
649 error);
650 }
651
652 #if 0
653 static void
654 mgb_dump_some_stats(struct mgb_softc *sc)
655 {
656 int i;
657 int first_stat = 0x1200;
658 int last_stat = 0x12FC;
659
660 for (i = first_stat; i <= last_stat; i += 4)
661 if (CSR_READ_REG(sc, i) != 0)
662 device_printf(sc->dev, "0x%04x: 0x%08x\n", i,
663 CSR_READ_REG(sc, i));
664 char *stat_names[] = {
665 "MAC_ERR_STS ",
666 "FCT_INT_STS ",
667 "DMAC_CFG ",
668 "DMAC_CMD ",
669 "DMAC_INT_STS ",
670 "DMAC_INT_EN ",
671 "DMAC_RX_ERR_STS0 ",
672 "DMAC_RX_ERR_STS1 ",
673 "DMAC_RX_ERR_STS2 ",
674 "DMAC_RX_ERR_STS3 ",
675 "INT_STS ",
676 "INT_EN ",
677 "INT_VEC_EN ",
678 "INT_VEC_MAP0 ",
679 "INT_VEC_MAP1 ",
680 "INT_VEC_MAP2 ",
681 "TX_HEAD0",
682 "TX_TAIL0",
683 "DMAC_TX_ERR_STS0 ",
684 NULL
685 };
686 int stats[] = {
687 0x114,
688 0xA0,
689 0xC00,
690 0xC0C,
691 0xC10,
692 0xC14,
693 0xC60,
694 0xCA0,
695 0xCE0,
696 0xD20,
697 0x780,
698 0x788,
699 0x794,
700 0x7A0,
701 0x7A4,
702 0x780,
703 0xD58,
704 0xD5C,
705 0xD60,
706 0x0
707 };
708 i = 0;
709 printf("==============================\n");
710 while (stats[i++])
711 device_printf(sc->dev, "%s at offset 0x%04x = 0x%08x\n",
712 stat_names[i - 1], stats[i - 1],
713 CSR_READ_REG(sc, stats[i - 1]));
714 printf("==== TX RING DESCS ====\n");
715 for (i = 0; i < MGB_DMA_RING_SIZE; i++)
716 device_printf(sc->dev, "ring[%d].data0=0x%08x\n"
717 "ring[%d].data1=0x%08x\n"
718 "ring[%d].data2=0x%08x\n"
719 "ring[%d].data3=0x%08x\n",
720 i, sc->tx_ring_data.ring[i].ctl,
721 i, sc->tx_ring_data.ring[i].addr.low,
722 i, sc->tx_ring_data.ring[i].addr.high,
723 i, sc->tx_ring_data.ring[i].sts);
724 device_printf(sc->dev, "==== DUMP_TX_DMA_RAM ====\n");
725 CSR_WRITE_REG(sc, 0x24, 0xF); // DP_SEL & TX_RAM_0
726 for (i = 0; i < 128; i++) {
727 CSR_WRITE_REG(sc, 0x2C, i); // DP_ADDR
728
729 CSR_WRITE_REG(sc, 0x28, 0); // DP_CMD
730
731 while ((CSR_READ_REG(sc, 0x24) & 0x80000000) == 0) // DP_SEL & READY
732 DELAY(1000);
733
734 device_printf(sc->dev, "DMAC_TX_RAM_0[%u]=%08x\n", i,
735 CSR_READ_REG(sc, 0x30)); // DP_DATA
736 }
737 }
738 #endif
739
740 static void
mgb_stop(if_ctx_t ctx)741 mgb_stop(if_ctx_t ctx)
742 {
743 struct mgb_softc *sc ;
744 if_softc_ctx_t scctx;
745 int i;
746
747 sc = iflib_get_softc(ctx);
748 scctx = iflib_get_softc_ctx(ctx);
749
750 /* XXX: Could potentially timeout */
751 for (i = 0; i < scctx->isc_nrxqsets; i++) {
752 mgb_dmac_control(sc, MGB_DMAC_RX_START, 0, DMAC_STOP);
753 mgb_fct_control(sc, MGB_FCT_RX_CTL, 0, FCT_DISABLE);
754 }
755 for (i = 0; i < scctx->isc_ntxqsets; i++) {
756 mgb_dmac_control(sc, MGB_DMAC_TX_START, 0, DMAC_STOP);
757 mgb_fct_control(sc, MGB_FCT_TX_CTL, 0, FCT_DISABLE);
758 }
759 }
760
761 static int
mgb_legacy_intr(void * xsc)762 mgb_legacy_intr(void *xsc)
763 {
764 struct mgb_softc *sc;
765
766 sc = xsc;
767 iflib_admin_intr_deferred(sc->ctx);
768 return (FILTER_HANDLED);
769 }
770
771 static int
mgb_rxq_intr(void * xsc)772 mgb_rxq_intr(void *xsc)
773 {
774 struct mgb_softc *sc;
775 if_softc_ctx_t scctx;
776 uint32_t intr_sts, intr_en;
777 int qidx;
778
779 sc = xsc;
780 scctx = iflib_get_softc_ctx(sc->ctx);
781
782 intr_sts = CSR_READ_REG(sc, MGB_INTR_STS);
783 intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET);
784 intr_sts &= intr_en;
785
786 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) {
787 if ((intr_sts & MGB_INTR_STS_RX(qidx))){
788 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR,
789 MGB_INTR_STS_RX(qidx));
790 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_RX(qidx));
791 }
792 }
793 return (FILTER_SCHEDULE_THREAD);
794 }
795
796 static int
mgb_admin_intr(void * xsc)797 mgb_admin_intr(void *xsc)
798 {
799 struct mgb_softc *sc;
800 if_softc_ctx_t scctx;
801 uint32_t intr_sts, intr_en;
802 int qidx;
803
804 sc = xsc;
805 scctx = iflib_get_softc_ctx(sc->ctx);
806
807 intr_sts = CSR_READ_REG(sc, MGB_INTR_STS);
808 intr_en = CSR_READ_REG(sc, MGB_INTR_ENBL_SET);
809 intr_sts &= intr_en;
810
811 /* TODO: shouldn't continue if suspended */
812 if ((intr_sts & MGB_INTR_STS_ANY) == 0)
813 return (FILTER_STRAY);
814 if ((intr_sts & MGB_INTR_STS_TEST) != 0) {
815 sc->isr_test_flag = true;
816 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST);
817 return (FILTER_HANDLED);
818 }
819 if ((intr_sts & MGB_INTR_STS_RX_ANY) != 0) {
820 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) {
821 if ((intr_sts & MGB_INTR_STS_RX(qidx))){
822 iflib_rx_intr_deferred(sc->ctx, qidx);
823 }
824 }
825 return (FILTER_HANDLED);
826 }
827 /* XXX: TX interrupts should not occur */
828 if ((intr_sts & MGB_INTR_STS_TX_ANY) != 0) {
829 for (qidx = 0; qidx < scctx->isc_ntxqsets; qidx++) {
830 if ((intr_sts & MGB_INTR_STS_TX(qidx))) {
831 /* clear the interrupt sts and run handler */
832 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR,
833 MGB_INTR_STS_TX(qidx));
834 CSR_WRITE_REG(sc, MGB_INTR_STS,
835 MGB_INTR_STS_TX(qidx));
836 iflib_tx_intr_deferred(sc->ctx, qidx);
837 }
838 }
839 return (FILTER_HANDLED);
840 }
841
842 return (FILTER_SCHEDULE_THREAD);
843 }
844
845 static int
mgb_msix_intr_assign(if_ctx_t ctx,int msix)846 mgb_msix_intr_assign(if_ctx_t ctx, int msix)
847 {
848 struct mgb_softc *sc;
849 if_softc_ctx_t scctx;
850 int error, i, vectorid;
851 char irq_name[16];
852
853 sc = iflib_get_softc(ctx);
854 scctx = iflib_get_softc_ctx(ctx);
855
856 KASSERT(scctx->isc_nrxqsets == 1 && scctx->isc_ntxqsets == 1,
857 ("num rxqsets/txqsets != 1 "));
858
859 /*
860 * First vector should be admin interrupts, others vectors are TX/RX
861 *
862 * RIDs start at 1, and vector ids start at 0.
863 */
864 vectorid = 0;
865 error = iflib_irq_alloc_generic(ctx, &sc->admin_irq, vectorid + 1,
866 IFLIB_INTR_ADMIN, mgb_admin_intr, sc, 0, "admin");
867 if (error) {
868 device_printf(sc->dev,
869 "Failed to register admin interrupt handler\n");
870 return (error);
871 }
872
873 for (i = 0; i < scctx->isc_nrxqsets; i++) {
874 vectorid++;
875 snprintf(irq_name, sizeof(irq_name), "rxq%d", i);
876 error = iflib_irq_alloc_generic(ctx, &sc->rx_irq, vectorid + 1,
877 IFLIB_INTR_RXTX, mgb_rxq_intr, sc, i, irq_name);
878 if (error) {
879 device_printf(sc->dev,
880 "Failed to register rxq %d interrupt handler\n", i);
881 return (error);
882 }
883 CSR_UPDATE_REG(sc, MGB_INTR_VEC_RX_MAP,
884 MGB_INTR_VEC_MAP(vectorid, i));
885 }
886
887 /* Not actually mapping hw TX interrupts ... */
888 for (i = 0; i < scctx->isc_ntxqsets; i++) {
889 snprintf(irq_name, sizeof(irq_name), "txq%d", i);
890 iflib_softirq_alloc_generic(ctx, NULL, IFLIB_INTR_TX, NULL, i,
891 irq_name);
892 }
893
894 return (0);
895 }
896
897 static void
mgb_intr_enable_all(if_ctx_t ctx)898 mgb_intr_enable_all(if_ctx_t ctx)
899 {
900 struct mgb_softc *sc;
901 if_softc_ctx_t scctx;
902 int i, dmac_enable = 0, intr_sts = 0, vec_en = 0;
903
904 sc = iflib_get_softc(ctx);
905 scctx = iflib_get_softc_ctx(ctx);
906 intr_sts |= MGB_INTR_STS_ANY;
907 vec_en |= MGB_INTR_STS_ANY;
908
909 for (i = 0; i < scctx->isc_nrxqsets; i++) {
910 intr_sts |= MGB_INTR_STS_RX(i);
911 dmac_enable |= MGB_DMAC_RX_INTR_ENBL(i);
912 vec_en |= MGB_INTR_RX_VEC_STS(i);
913 }
914
915 /* TX interrupts aren't needed ... */
916
917 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, intr_sts);
918 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, vec_en);
919 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, dmac_enable);
920 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, dmac_enable);
921 }
922
923 static void
mgb_intr_disable_all(if_ctx_t ctx)924 mgb_intr_disable_all(if_ctx_t ctx)
925 {
926 struct mgb_softc *sc;
927
928 sc = iflib_get_softc(ctx);
929 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, UINT32_MAX);
930 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_CLR, UINT32_MAX);
931 CSR_WRITE_REG(sc, MGB_INTR_STS, UINT32_MAX);
932
933 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_CLR, UINT32_MAX);
934 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, UINT32_MAX);
935 }
936
937 static int
mgb_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)938 mgb_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
939 {
940 /* called after successful rx isr */
941 struct mgb_softc *sc;
942
943 sc = iflib_get_softc(ctx);
944 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_RX_VEC_STS(qid));
945 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_RX(qid));
946
947 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_RX_INTR_ENBL(qid));
948 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_RX_INTR_ENBL(qid));
949 return (0);
950 }
951
952 static int
mgb_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)953 mgb_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
954 {
955 /* XXX: not called (since tx interrupts not used) */
956 struct mgb_softc *sc;
957
958 sc = iflib_get_softc(ctx);
959
960 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET, MGB_INTR_STS_TX(qid));
961
962 CSR_WRITE_REG(sc, MGB_DMAC_INTR_STS, MGB_DMAC_TX_INTR_ENBL(qid));
963 CSR_WRITE_REG(sc, MGB_DMAC_INTR_ENBL_SET, MGB_DMAC_TX_INTR_ENBL(qid));
964 return (0);
965 }
966
967 static bool
mgb_intr_test(struct mgb_softc * sc)968 mgb_intr_test(struct mgb_softc *sc)
969 {
970 int i;
971
972 sc->isr_test_flag = false;
973 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST);
974 CSR_WRITE_REG(sc, MGB_INTR_VEC_ENBL_SET, MGB_INTR_STS_ANY);
975 CSR_WRITE_REG(sc, MGB_INTR_ENBL_SET,
976 MGB_INTR_STS_ANY | MGB_INTR_STS_TEST);
977 CSR_WRITE_REG(sc, MGB_INTR_SET, MGB_INTR_STS_TEST);
978 if (sc->isr_test_flag)
979 return (true);
980 for (i = 0; i < MGB_TIMEOUT; i++) {
981 DELAY(10);
982 if (sc->isr_test_flag)
983 break;
984 }
985 CSR_WRITE_REG(sc, MGB_INTR_ENBL_CLR, MGB_INTR_STS_TEST);
986 CSR_WRITE_REG(sc, MGB_INTR_STS, MGB_INTR_STS_TEST);
987 return (sc->isr_test_flag);
988 }
989
990 static int
mgb_isc_txd_encap(void * xsc,if_pkt_info_t ipi)991 mgb_isc_txd_encap(void *xsc , if_pkt_info_t ipi)
992 {
993 struct mgb_softc *sc;
994 struct mgb_ring_data *rdata;
995 struct mgb_ring_desc *txd;
996 bus_dma_segment_t *segs;
997 qidx_t pidx, nsegs;
998 uint32_t ctl;
999 int i;
1000
1001 KASSERT(ipi->ipi_qsidx == 0,
1002 ("tried to refill TX Channel %d.\n", ipi->ipi_qsidx));
1003 sc = xsc;
1004 rdata = &sc->tx_ring_data;
1005
1006 pidx = ipi->ipi_pidx;
1007 segs = ipi->ipi_segs;
1008 nsegs = ipi->ipi_nsegs;
1009
1010 /* For each seg, create a descriptor */
1011 for (i = 0; i < nsegs; ++i) {
1012 txd = &rdata->ring[pidx];
1013 ctl = (segs[i].ds_len & MGB_DESC_CTL_BUFLEN_MASK) |
1014 MGB_DESC_CTL_FCS;
1015 if (i == 0)
1016 ctl |= MGB_TX_DESC_CTL_FS;
1017 if (i == (nsegs - 1))
1018 ctl |= MGB_TX_DESC_CTL_LS | MGB_DESC_CTL_IOC;
1019 txd->ctl = htole32(ctl);
1020 txd->addr.low = htole32(CSR_TRANSLATE_ADDR_LOW32(
1021 segs[i].ds_addr));
1022 txd->addr.high = htole32(CSR_TRANSLATE_ADDR_HIGH32(
1023 segs[i].ds_addr));
1024 txd->sts = htole32((ipi->ipi_len << MGB_DESC_FRAME_LEN_SHIFT) &
1025 MGB_DESC_FRAME_LEN_MASK);
1026 pidx = MGB_NEXT_RING_IDX(pidx);
1027 }
1028 ipi->ipi_new_pidx = pidx;
1029 return (0);
1030 }
1031
1032 static void
mgb_isc_txd_flush(void * xsc,uint16_t txqid,qidx_t pidx)1033 mgb_isc_txd_flush(void *xsc, uint16_t txqid, qidx_t pidx)
1034 {
1035 struct mgb_softc *sc;
1036 struct mgb_ring_data *rdata;
1037
1038 KASSERT(txqid == 0, ("tried to flush TX Channel %d.\n", txqid));
1039 sc = xsc;
1040 rdata = &sc->tx_ring_data;
1041
1042 if (rdata->last_tail != pidx) {
1043 rdata->last_tail = pidx;
1044 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(txqid), rdata->last_tail);
1045 }
1046 }
1047
1048 static int
mgb_isc_txd_credits_update(void * xsc,uint16_t txqid,bool clear)1049 mgb_isc_txd_credits_update(void *xsc, uint16_t txqid, bool clear)
1050 {
1051 struct mgb_softc *sc;
1052 struct mgb_ring_desc *txd;
1053 struct mgb_ring_data *rdata;
1054 int processed = 0;
1055
1056 /*
1057 * > If clear is true, we need to report the number of TX command ring
1058 * > descriptors that have been processed by the device. If clear is
1059 * > false, we just need to report whether or not at least one TX
1060 * > command ring descriptor has been processed by the device.
1061 * - vmx driver
1062 */
1063 KASSERT(txqid == 0, ("tried to credits_update TX Channel %d.\n",
1064 txqid));
1065 sc = xsc;
1066 rdata = &sc->tx_ring_data;
1067
1068 while (*(rdata->head_wb) != rdata->last_head) {
1069 if (!clear)
1070 return (1);
1071
1072 txd = &rdata->ring[rdata->last_head];
1073 memset(txd, 0, sizeof(struct mgb_ring_desc));
1074 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head);
1075 processed++;
1076 }
1077
1078 return (processed);
1079 }
1080
1081 static int
mgb_isc_rxd_available(void * xsc,uint16_t rxqid,qidx_t idx,qidx_t budget)1082 mgb_isc_rxd_available(void *xsc, uint16_t rxqid, qidx_t idx, qidx_t budget)
1083 {
1084 struct mgb_softc *sc;
1085 struct mgb_ring_data *rdata;
1086 int avail = 0;
1087
1088 sc = xsc;
1089 KASSERT(rxqid == 0, ("tried to check availability in RX Channel %d.\n",
1090 rxqid));
1091
1092 rdata = &sc->rx_ring_data;
1093 for (; idx != *(rdata->head_wb); idx = MGB_NEXT_RING_IDX(idx)) {
1094 avail++;
1095 /* XXX: Could verify desc is device owned here */
1096 if (avail == budget)
1097 break;
1098 }
1099 return (avail);
1100 }
1101
1102 static int
mgb_isc_rxd_pkt_get(void * xsc,if_rxd_info_t ri)1103 mgb_isc_rxd_pkt_get(void *xsc, if_rxd_info_t ri)
1104 {
1105 struct mgb_softc *sc;
1106 struct mgb_ring_data *rdata;
1107 struct mgb_ring_desc rxd;
1108 int total_len;
1109
1110 KASSERT(ri->iri_qsidx == 0,
1111 ("tried to check availability in RX Channel %d\n", ri->iri_qsidx));
1112 sc = xsc;
1113 total_len = 0;
1114 rdata = &sc->rx_ring_data;
1115
1116 while (*(rdata->head_wb) != rdata->last_head) {
1117 /* copy ring desc and do swapping */
1118 rxd = rdata->ring[rdata->last_head];
1119 rxd.ctl = le32toh(rxd.ctl);
1120 rxd.addr.low = le32toh(rxd.ctl);
1121 rxd.addr.high = le32toh(rxd.ctl);
1122 rxd.sts = le32toh(rxd.ctl);
1123
1124 if ((rxd.ctl & MGB_DESC_CTL_OWN) != 0) {
1125 device_printf(sc->dev,
1126 "Tried to read descriptor ... "
1127 "found that it's owned by the driver\n");
1128 return (EINVAL);
1129 }
1130 if ((rxd.ctl & MGB_RX_DESC_CTL_FS) == 0) {
1131 device_printf(sc->dev,
1132 "Tried to read descriptor ... "
1133 "found that FS is not set.\n");
1134 device_printf(sc->dev, "Tried to read descriptor ... that it FS is not set.\n");
1135 return (EINVAL);
1136 }
1137 /* XXX: Multi-packet support */
1138 if ((rxd.ctl & MGB_RX_DESC_CTL_LS) == 0) {
1139 device_printf(sc->dev,
1140 "Tried to read descriptor ... "
1141 "found that LS is not set. (Multi-buffer packets not yet supported)\n");
1142 return (EINVAL);
1143 }
1144 ri->iri_frags[0].irf_flid = 0;
1145 ri->iri_frags[0].irf_idx = rdata->last_head;
1146 ri->iri_frags[0].irf_len = MGB_DESC_GET_FRAME_LEN(&rxd);
1147 total_len += ri->iri_frags[0].irf_len;
1148
1149 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head);
1150 break;
1151 }
1152 ri->iri_nfrags = 1;
1153 ri->iri_len = total_len;
1154
1155 return (0);
1156 }
1157
1158 static void
mgb_isc_rxd_refill(void * xsc,if_rxd_update_t iru)1159 mgb_isc_rxd_refill(void *xsc, if_rxd_update_t iru)
1160 {
1161 struct mgb_softc *sc;
1162 struct mgb_ring_data *rdata;
1163 struct mgb_ring_desc *rxd;
1164 uint64_t *paddrs;
1165 qidx_t *idxs;
1166 qidx_t idx;
1167 int count, len;
1168
1169 count = iru->iru_count;
1170 len = iru->iru_buf_size;
1171 idxs = iru->iru_idxs;
1172 paddrs = iru->iru_paddrs;
1173 KASSERT(iru->iru_qsidx == 0,
1174 ("tried to refill RX Channel %d.\n", iru->iru_qsidx));
1175
1176 sc = xsc;
1177 rdata = &sc->rx_ring_data;
1178
1179 while (count > 0) {
1180 idx = idxs[--count];
1181 rxd = &rdata->ring[idx];
1182
1183 rxd->sts = 0;
1184 rxd->addr.low =
1185 htole32(CSR_TRANSLATE_ADDR_LOW32(paddrs[count]));
1186 rxd->addr.high =
1187 htole32(CSR_TRANSLATE_ADDR_HIGH32(paddrs[count]));
1188 rxd->ctl = htole32(MGB_DESC_CTL_OWN |
1189 (len & MGB_DESC_CTL_BUFLEN_MASK));
1190 }
1191 return;
1192 }
1193
1194 static void
mgb_isc_rxd_flush(void * xsc,uint16_t rxqid,uint8_t flid,qidx_t pidx)1195 mgb_isc_rxd_flush(void *xsc, uint16_t rxqid, uint8_t flid, qidx_t pidx)
1196 {
1197 struct mgb_softc *sc;
1198
1199 sc = xsc;
1200
1201 KASSERT(rxqid == 0, ("tried to flush RX Channel %d.\n", rxqid));
1202 /*
1203 * According to the programming guide, last_tail must be set to
1204 * the last valid RX descriptor, rather than to the one past that.
1205 * Note that this is not true for the TX ring!
1206 */
1207 sc->rx_ring_data.last_tail = MGB_PREV_RING_IDX(pidx);
1208 CSR_WRITE_REG(sc, MGB_DMA_RX_TAIL(rxqid), sc->rx_ring_data.last_tail);
1209 return;
1210 }
1211
1212 static int
mgb_test_bar(struct mgb_softc * sc)1213 mgb_test_bar(struct mgb_softc *sc)
1214 {
1215 uint32_t id_rev, dev_id;
1216
1217 id_rev = CSR_READ_REG(sc, 0);
1218 dev_id = id_rev >> 16;
1219 if (dev_id == MGB_LAN7430_DEVICE_ID ||
1220 dev_id == MGB_LAN7431_DEVICE_ID ||
1221 dev_id == MGB_PCI11414_DEVICE_ID) {
1222 return (0);
1223 } else {
1224 device_printf(sc->dev, "ID check failed: 0x%x\n", dev_id);
1225 return (ENXIO);
1226 }
1227 }
1228
1229 static int
mgb_alloc_regs(struct mgb_softc * sc)1230 mgb_alloc_regs(struct mgb_softc *sc)
1231 {
1232 int rid;
1233
1234 rid = PCIR_BAR(MGB_BAR);
1235 pci_enable_busmaster(sc->dev);
1236 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1237 &rid, RF_ACTIVE);
1238 if (sc->regs == NULL)
1239 return (ENXIO);
1240
1241 return (0);
1242 }
1243
1244 static int
mgb_release_regs(struct mgb_softc * sc)1245 mgb_release_regs(struct mgb_softc *sc)
1246 {
1247 int error = 0;
1248
1249 if (sc->regs != NULL)
1250 error = bus_release_resource(sc->dev, SYS_RES_MEMORY,
1251 rman_get_rid(sc->regs), sc->regs);
1252 sc->regs = NULL;
1253 pci_disable_busmaster(sc->dev);
1254 return (error);
1255 }
1256
1257 static int
mgb_dma_init(struct mgb_softc * sc)1258 mgb_dma_init(struct mgb_softc *sc)
1259 {
1260 if_softc_ctx_t scctx;
1261 int ch, error = 0;
1262
1263 scctx = iflib_get_softc_ctx(sc->ctx);
1264
1265 for (ch = 0; ch < scctx->isc_nrxqsets; ch++)
1266 if ((error = mgb_dma_rx_ring_init(sc, ch)))
1267 goto fail;
1268
1269 for (ch = 0; ch < scctx->isc_ntxqsets; ch++)
1270 if ((error = mgb_dma_tx_ring_init(sc, ch)))
1271 goto fail;
1272
1273 fail:
1274 return (error);
1275 }
1276
1277 static int
mgb_dma_rx_ring_init(struct mgb_softc * sc,int channel)1278 mgb_dma_rx_ring_init(struct mgb_softc *sc, int channel)
1279 {
1280 struct mgb_ring_data *rdata;
1281 int ring_config, error = 0;
1282
1283 rdata = &sc->rx_ring_data;
1284 error = mgb_dmac_control(sc, MGB_DMAC_RX_START, channel, DMAC_RESET);
1285 if (error != 0) {
1286 device_printf(sc->dev, "Failed to reset RX DMAC.\n");
1287 goto fail;
1288 }
1289 KASSERT(MGB_DMAC_STATE_IS_INITIAL(sc, MGB_DMAC_RX_START, channel),
1290 ("Trying to init channels when not in init state\n"));
1291
1292 /* write ring address */
1293 if (rdata->ring_bus_addr == 0) {
1294 device_printf(sc->dev, "Invalid ring bus addr.\n");
1295 error = EINVAL;
1296 goto fail;
1297 }
1298
1299 CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_H(channel),
1300 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr));
1301 CSR_WRITE_REG(sc, MGB_DMA_RX_BASE_L(channel),
1302 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr));
1303
1304 /* write head pointer writeback address */
1305 if (rdata->head_wb_bus_addr == 0) {
1306 device_printf(sc->dev, "Invalid head wb bus addr.\n");
1307 error = EINVAL;
1308 goto fail;
1309 }
1310 CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_H(channel),
1311 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr));
1312 CSR_WRITE_REG(sc, MGB_DMA_RX_HEAD_WB_L(channel),
1313 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr));
1314
1315 /* Enable head pointer writeback */
1316 CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG0(channel), MGB_DMA_HEAD_WB_ENBL);
1317
1318 ring_config = CSR_READ_REG(sc, MGB_DMA_RX_CONFIG1(channel));
1319 /* ring size */
1320 ring_config &= ~MGB_DMA_RING_LEN_MASK;
1321 ring_config |= (MGB_DMA_RING_SIZE & MGB_DMA_RING_LEN_MASK);
1322 /* packet padding (PAD_2 is better for IP header alignment ...) */
1323 ring_config &= ~MGB_DMA_RING_PAD_MASK;
1324 ring_config |= (MGB_DMA_RING_PAD_0 & MGB_DMA_RING_PAD_MASK);
1325
1326 CSR_WRITE_REG(sc, MGB_DMA_RX_CONFIG1(channel), ring_config);
1327
1328 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_RX_HEAD(channel));
1329
1330 error = mgb_fct_control(sc, MGB_FCT_RX_CTL, channel, FCT_RESET);
1331 if (error != 0) {
1332 device_printf(sc->dev, "Failed to reset RX FCT.\n");
1333 goto fail;
1334 }
1335 error = mgb_fct_control(sc, MGB_FCT_RX_CTL, channel, FCT_ENABLE);
1336 if (error != 0) {
1337 device_printf(sc->dev, "Failed to enable RX FCT.\n");
1338 goto fail;
1339 }
1340 error = mgb_dmac_control(sc, MGB_DMAC_RX_START, channel, DMAC_START);
1341 if (error != 0)
1342 device_printf(sc->dev, "Failed to start RX DMAC.\n");
1343 fail:
1344 return (error);
1345 }
1346
1347 static int
mgb_dma_tx_ring_init(struct mgb_softc * sc,int channel)1348 mgb_dma_tx_ring_init(struct mgb_softc *sc, int channel)
1349 {
1350 struct mgb_ring_data *rdata;
1351 int ring_config, error = 0;
1352
1353 rdata = &sc->tx_ring_data;
1354 if ((error = mgb_fct_control(sc, MGB_FCT_TX_CTL, channel, FCT_RESET))) {
1355 device_printf(sc->dev, "Failed to reset TX FCT.\n");
1356 goto fail;
1357 }
1358 if ((error = mgb_fct_control(sc, MGB_FCT_TX_CTL, channel,
1359 FCT_ENABLE))) {
1360 device_printf(sc->dev, "Failed to enable TX FCT.\n");
1361 goto fail;
1362 }
1363 if ((error = mgb_dmac_control(sc, MGB_DMAC_TX_START, channel,
1364 DMAC_RESET))) {
1365 device_printf(sc->dev, "Failed to reset TX DMAC.\n");
1366 goto fail;
1367 }
1368 KASSERT(MGB_DMAC_STATE_IS_INITIAL(sc, MGB_DMAC_TX_START, channel),
1369 ("Trying to init channels in not init state\n"));
1370
1371 /* write ring address */
1372 if (rdata->ring_bus_addr == 0) {
1373 device_printf(sc->dev, "Invalid ring bus addr.\n");
1374 error = EINVAL;
1375 goto fail;
1376 }
1377 CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_H(channel),
1378 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr));
1379 CSR_WRITE_REG(sc, MGB_DMA_TX_BASE_L(channel),
1380 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr));
1381
1382 /* write ring size */
1383 ring_config = CSR_READ_REG(sc, MGB_DMA_TX_CONFIG1(channel));
1384 ring_config &= ~MGB_DMA_RING_LEN_MASK;
1385 ring_config |= (MGB_DMA_RING_SIZE & MGB_DMA_RING_LEN_MASK);
1386 CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG1(channel), ring_config);
1387
1388 /* Enable interrupt on completion and head pointer writeback */
1389 ring_config = (MGB_DMA_HEAD_WB_LS_ENBL | MGB_DMA_HEAD_WB_ENBL);
1390 CSR_WRITE_REG(sc, MGB_DMA_TX_CONFIG0(channel), ring_config);
1391
1392 /* write head pointer writeback address */
1393 if (rdata->head_wb_bus_addr == 0) {
1394 device_printf(sc->dev, "Invalid head wb bus addr.\n");
1395 error = EINVAL;
1396 goto fail;
1397 }
1398 CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_H(channel),
1399 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr));
1400 CSR_WRITE_REG(sc, MGB_DMA_TX_HEAD_WB_L(channel),
1401 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr));
1402
1403 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_TX_HEAD(channel));
1404 KASSERT(rdata->last_head == 0, ("MGB_DMA_TX_HEAD was not reset.\n"));
1405 rdata->last_tail = 0;
1406 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(channel), rdata->last_tail);
1407
1408 if ((error = mgb_dmac_control(sc, MGB_DMAC_TX_START, channel,
1409 DMAC_START)))
1410 device_printf(sc->dev, "Failed to start TX DMAC.\n");
1411 fail:
1412 return (error);
1413 }
1414
1415 static int
mgb_dmac_control(struct mgb_softc * sc,int start,int channel,enum mgb_dmac_cmd cmd)1416 mgb_dmac_control(struct mgb_softc *sc, int start, int channel,
1417 enum mgb_dmac_cmd cmd)
1418 {
1419 int error = 0;
1420
1421 switch (cmd) {
1422 case DMAC_RESET:
1423 CSR_WRITE_REG(sc, MGB_DMAC_CMD,
1424 MGB_DMAC_CMD_RESET(start, channel));
1425 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0,
1426 MGB_DMAC_CMD_RESET(start, channel));
1427 break;
1428
1429 case DMAC_START:
1430 /*
1431 * NOTE: this simplifies the logic, since it will never
1432 * try to start in STOP_PENDING, but it also increases work.
1433 */
1434 error = mgb_dmac_control(sc, start, channel, DMAC_STOP);
1435 if (error != 0)
1436 return (error);
1437 CSR_WRITE_REG(sc, MGB_DMAC_CMD,
1438 MGB_DMAC_CMD_START(start, channel));
1439 break;
1440
1441 case DMAC_STOP:
1442 CSR_WRITE_REG(sc, MGB_DMAC_CMD,
1443 MGB_DMAC_CMD_STOP(start, channel));
1444 error = mgb_wait_for_bits(sc, MGB_DMAC_CMD,
1445 MGB_DMAC_CMD_STOP(start, channel),
1446 MGB_DMAC_CMD_START(start, channel));
1447 break;
1448 }
1449 return (error);
1450 }
1451
1452 static int
mgb_fct_control(struct mgb_softc * sc,int reg,int channel,enum mgb_fct_cmd cmd)1453 mgb_fct_control(struct mgb_softc *sc, int reg, int channel,
1454 enum mgb_fct_cmd cmd)
1455 {
1456
1457 switch (cmd) {
1458 case FCT_RESET:
1459 CSR_WRITE_REG(sc, reg, MGB_FCT_RESET(channel));
1460 return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_RESET(channel)));
1461 case FCT_ENABLE:
1462 CSR_WRITE_REG(sc, reg, MGB_FCT_ENBL(channel));
1463 return (0);
1464 case FCT_DISABLE:
1465 CSR_WRITE_REG(sc, reg, MGB_FCT_DSBL(channel));
1466 return (mgb_wait_for_bits(sc, reg, 0, MGB_FCT_ENBL(channel)));
1467 }
1468 }
1469
1470 static int
mgb_hw_teardown(struct mgb_softc * sc)1471 mgb_hw_teardown(struct mgb_softc *sc)
1472 {
1473 int err = 0;
1474
1475 /* Stop MAC */
1476 CSR_CLEAR_REG(sc, MGB_MAC_RX, MGB_MAC_ENBL);
1477 CSR_CLEAR_REG(sc, MGB_MAC_TX, MGB_MAC_ENBL);
1478 if ((err = mgb_wait_for_bits(sc, MGB_MAC_RX, MGB_MAC_DSBL, 0)))
1479 return (err);
1480 if ((err = mgb_wait_for_bits(sc, MGB_MAC_TX, MGB_MAC_DSBL, 0)))
1481 return (err);
1482 return (err);
1483 }
1484
1485 static int
mgb_hw_init(struct mgb_softc * sc)1486 mgb_hw_init(struct mgb_softc *sc)
1487 {
1488 uint32_t sgmii_ctl;
1489 uint32_t reg;
1490 int error;
1491
1492 error = 0;
1493
1494 error = mgb_hw_reset(sc);
1495 if (error != 0)
1496 goto fail;
1497
1498 mgb_mac_init(sc);
1499
1500 error = mgb_phy_reset(sc);
1501 if (error != 0)
1502 goto fail;
1503
1504 /* Enable SGMII if needed. */
1505 reg = CSR_READ_REG(sc, STRAP_READ);
1506 if (bootverbose)
1507 device_printf(sc->dev, " Strap: %#b\n", reg,
1508 "\020"
1509 "\01ADV_PM_DISABLE"
1510 "\02RGMII_RXC_DELAY_EN"
1511 "\03RGMII_TXC_DELAY_EN"
1512 "\04BASE_X"
1513 "\05SGMII_2_5G"
1514 "\06SGMII_REFCLK"
1515 "\07SGMII_EN"
1516 "\10RMII_EN"
1517 "\27USE_SGMII_EN"
1518 "\30USE_RMII_EN");
1519 if ((reg & STRAP_READ_USE_SGMII_EN) != 0 &&
1520 (reg & STRAP_READ_SGMII_EN) != 0) {
1521 sgmii_ctl = CSR_READ_REG(sc, SGMII_CTL);
1522 sgmii_ctl |= SGMII_CTL_SGMII_ENABLE;
1523 sgmii_ctl &= ~SGMII_CTL_SGMII_POWER_DN;
1524 CSR_WRITE_REG(sc, SGMII_CTL, sgmii_ctl);
1525 sc->sgmii_en = true;
1526 }
1527
1528 error = mgb_dmac_reset(sc);
1529 if (error != 0)
1530 goto fail;
1531
1532 fail:
1533 return (error);
1534 }
1535
1536 static int
mgb_hw_reset(struct mgb_softc * sc)1537 mgb_hw_reset(struct mgb_softc *sc)
1538 {
1539
1540 CSR_UPDATE_REG(sc, MGB_HW_CFG, MGB_LITE_RESET);
1541 return (mgb_wait_for_bits(sc, MGB_HW_CFG, 0, MGB_LITE_RESET));
1542 }
1543
1544 static int
mgb_mac_init(struct mgb_softc * sc)1545 mgb_mac_init(struct mgb_softc *sc)
1546 {
1547
1548 /**
1549 * enable automatic duplex detection and
1550 * automatic speed detection
1551 */
1552 CSR_UPDATE_REG(sc, MGB_MAC_CR, MGB_MAC_ADD_ENBL | MGB_MAC_ASD_ENBL);
1553 CSR_UPDATE_REG(sc, MGB_MAC_TX, MGB_MAC_ENBL);
1554 CSR_UPDATE_REG(sc, MGB_MAC_RX, MGB_MAC_ENBL);
1555
1556 return (MGB_STS_OK);
1557 }
1558
1559 static int
mgb_phy_reset(struct mgb_softc * sc)1560 mgb_phy_reset(struct mgb_softc *sc)
1561 {
1562
1563 CSR_UPDATE_BYTE(sc, MGB_PMT_CTL, MGB_PHY_RESET);
1564 if (mgb_wait_for_bits(sc, MGB_PMT_CTL, 0, MGB_PHY_RESET) ==
1565 MGB_STS_TIMEOUT)
1566 return (MGB_STS_TIMEOUT);
1567 return (mgb_wait_for_bits(sc, MGB_PMT_CTL, MGB_PHY_READY, 0));
1568 }
1569
1570 static int
mgb_dmac_reset(struct mgb_softc * sc)1571 mgb_dmac_reset(struct mgb_softc *sc)
1572 {
1573
1574 CSR_WRITE_REG(sc, MGB_DMAC_CMD, MGB_DMAC_RESET);
1575 return (mgb_wait_for_bits(sc, MGB_DMAC_CMD, 0, MGB_DMAC_RESET));
1576 }
1577
1578 static int
mgb_wait_for_bits(struct mgb_softc * sc,int reg,int set_bits,int clear_bits)1579 mgb_wait_for_bits(struct mgb_softc *sc, int reg, int set_bits, int clear_bits)
1580 {
1581 int i, val;
1582
1583 i = 0;
1584 do {
1585 /*
1586 * XXX: Datasheets states delay should be > 5 microseconds
1587 * for device reset.
1588 */
1589 DELAY(100);
1590 val = CSR_READ_REG(sc, reg);
1591 if ((val & set_bits) == set_bits && (val & clear_bits) == 0)
1592 return (MGB_STS_OK);
1593 } while (i++ < MGB_TIMEOUT);
1594
1595 return (MGB_STS_TIMEOUT);
1596 }
1597
1598 static void
mgb_get_ethaddr(struct mgb_softc * sc,struct ether_addr * dest)1599 mgb_get_ethaddr(struct mgb_softc *sc, struct ether_addr *dest)
1600 {
1601
1602 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_L, &dest->octet[0], 4);
1603 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_H, &dest->octet[4], 2);
1604 }
1605
1606 static int
mgb_miibus_readreg(device_t dev,int phy,int reg)1607 mgb_miibus_readreg(device_t dev, int phy, int reg)
1608 {
1609 struct mgb_softc *sc;
1610 int mii_access;
1611
1612 sc = iflib_get_softc(device_get_softc(dev));
1613
1614 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) ==
1615 MGB_STS_TIMEOUT)
1616 return (EIO);
1617 mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT;
1618 mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT;
1619 mii_access |= MGB_MII_BUSY | MGB_MII_READ;
1620 CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access);
1621 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) ==
1622 MGB_STS_TIMEOUT)
1623 return (EIO);
1624 return (CSR_READ_2_BYTES(sc, MGB_MII_DATA));
1625 }
1626
1627 static int
mgb_miibus_writereg(device_t dev,int phy,int reg,int data)1628 mgb_miibus_writereg(device_t dev, int phy, int reg, int data)
1629 {
1630 struct mgb_softc *sc;
1631 int mii_access;
1632
1633 sc = iflib_get_softc(device_get_softc(dev));
1634
1635 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) ==
1636 MGB_STS_TIMEOUT)
1637 return (EIO);
1638 mii_access = (phy & MGB_MII_PHY_ADDR_MASK) << MGB_MII_PHY_ADDR_SHIFT;
1639 mii_access |= (reg & MGB_MII_REG_ADDR_MASK) << MGB_MII_REG_ADDR_SHIFT;
1640 mii_access |= MGB_MII_BUSY | MGB_MII_WRITE;
1641 CSR_WRITE_REG(sc, MGB_MII_DATA, data);
1642 CSR_WRITE_REG(sc, MGB_MII_ACCESS, mii_access);
1643 if (mgb_wait_for_bits(sc, MGB_MII_ACCESS, 0, MGB_MII_BUSY) ==
1644 MGB_STS_TIMEOUT)
1645 return (EIO);
1646 return (0);
1647 }
1648
1649 /* XXX: May need to lock these up */
1650 static void
mgb_miibus_statchg(device_t dev)1651 mgb_miibus_statchg(device_t dev)
1652 {
1653 struct mgb_softc *sc;
1654 struct mii_data *miid;
1655
1656 sc = iflib_get_softc(device_get_softc(dev));
1657 miid = device_get_softc(sc->miibus);
1658 /* Update baudrate in iflib */
1659 sc->baudrate = ifmedia_baudrate(miid->mii_media_active);
1660 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate);
1661 }
1662
1663 static void
mgb_miibus_linkchg(device_t dev)1664 mgb_miibus_linkchg(device_t dev)
1665 {
1666 struct mgb_softc *sc;
1667 struct mii_data *miid;
1668 int link_state;
1669
1670 sc = iflib_get_softc(device_get_softc(dev));
1671 miid = device_get_softc(sc->miibus);
1672 /* XXX: copied from miibus_linkchg **/
1673 if (miid->mii_media_status & IFM_AVALID) {
1674 if (miid->mii_media_status & IFM_ACTIVE)
1675 link_state = LINK_STATE_UP;
1676 else
1677 link_state = LINK_STATE_DOWN;
1678 } else
1679 link_state = LINK_STATE_UNKNOWN;
1680 sc->link_state = link_state;
1681 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate);
1682 }
1683