1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2020, Maxim Integrated
3
4 #include <linux/acpi.h>
5 #include <linux/delay.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <linux/regmap.h>
9 #include <linux/slab.h>
10 #include <sound/pcm.h>
11 #include <sound/pcm_params.h>
12 #include <sound/sdw.h>
13 #include <sound/soc.h>
14 #include <sound/tlv.h>
15 #include <linux/of.h>
16 #include <linux/soundwire/sdw.h>
17 #include <linux/soundwire/sdw_type.h>
18 #include <linux/soundwire/sdw_registers.h>
19 #include "max98373.h"
20 #include "max98373-sdw.h"
21
22 static const u32 max98373_sdw_cache_reg[] = {
23 MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
24 MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
25 MAX98373_R20B6_BDE_CUR_STATE_READBACK,
26 };
27
28 static const struct reg_default max98373_reg[] = {
29 {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
30 {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
31 {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
32 {MAX98373_R0044_SCP_CTRL, 0x00},
33 {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
34 {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
35 {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
36 {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
37 {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
38 {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
39 {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
40 {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
41 {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
42 {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
43 {MAX98373_R0100_DP1_INIT_STAT, 0x00},
44 {MAX98373_R0101_DP1_INIT_MASK, 0x00},
45 {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
46 {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
47 {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
48 {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
49 {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
50 {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
51 {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
52 {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
53 {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
54 {MAX98373_R0126_DP1_HCTRL, 0x00},
55 {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
56 {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
57 {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
58 {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
59 {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
60 {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
61 {MAX98373_R0136_DP1_HCTRL, 0x0136},
62 {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
63 {MAX98373_R0300_DP3_INIT_STAT, 0x00},
64 {MAX98373_R0301_DP3_INIT_MASK, 0x00},
65 {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
66 {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
67 {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
68 {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
69 {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
70 {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
71 {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
72 {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
73 {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
74 {MAX98373_R0326_DP3_HCTRL, 0x00},
75 {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
76 {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
77 {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
78 {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
79 {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
80 {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
81 {MAX98373_R0336_DP3_HCTRL, 0x00},
82 {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
83 {MAX98373_R2000_SW_RESET, 0x00},
84 {MAX98373_R2001_INT_RAW1, 0x00},
85 {MAX98373_R2002_INT_RAW2, 0x00},
86 {MAX98373_R2003_INT_RAW3, 0x00},
87 {MAX98373_R2004_INT_STATE1, 0x00},
88 {MAX98373_R2005_INT_STATE2, 0x00},
89 {MAX98373_R2006_INT_STATE3, 0x00},
90 {MAX98373_R2007_INT_FLAG1, 0x00},
91 {MAX98373_R2008_INT_FLAG2, 0x00},
92 {MAX98373_R2009_INT_FLAG3, 0x00},
93 {MAX98373_R200A_INT_EN1, 0x00},
94 {MAX98373_R200B_INT_EN2, 0x00},
95 {MAX98373_R200C_INT_EN3, 0x00},
96 {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
97 {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
98 {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
99 {MAX98373_R2010_IRQ_CTRL, 0x00},
100 {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
101 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
102 {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
103 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
104 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
105 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
106 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
107 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
108 {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
109 {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
110 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
111 {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
112 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
113 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
114 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
115 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
116 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
117 {MAX98373_R202B_PCM_RX_EN, 0x00},
118 {MAX98373_R202C_PCM_TX_EN, 0x00},
119 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
120 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
121 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
122 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
123 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
124 {MAX98373_R2034_ICC_TX_CNTL, 0x00},
125 {MAX98373_R2035_ICC_TX_EN, 0x00},
126 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
127 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
128 {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
129 {MAX98373_R203F_AMP_DSP_CFG, 0x02},
130 {MAX98373_R2040_TONE_GEN_CFG, 0x00},
131 {MAX98373_R2041_AMP_CFG, 0x03},
132 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
133 {MAX98373_R2043_AMP_EN, 0x00},
134 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
135 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
136 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
137 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
138 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
139 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
140 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
141 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
142 {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
143 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
144 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
145 {MAX98373_R2097_BDE_L1_THRESH, 0x00},
146 {MAX98373_R2098_BDE_L2_THRESH, 0x00},
147 {MAX98373_R2099_BDE_L3_THRESH, 0x00},
148 {MAX98373_R209A_BDE_L4_THRESH, 0x00},
149 {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
150 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
151 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
152 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
153 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
154 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
155 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
156 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
157 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
158 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
159 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
160 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
161 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
162 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
163 {MAX98373_R20B5_BDE_EN, 0x00},
164 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
165 {MAX98373_R20D1_DHT_CFG, 0x01},
166 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
167 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
168 {MAX98373_R20D4_DHT_EN, 0x00},
169 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
170 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
171 {MAX98373_R20E2_LIMITER_EN, 0x00},
172 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
173 {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
174 {MAX98373_R21FF_REV_ID, 0x42},
175 };
176
max98373_readable_register(struct device * dev,unsigned int reg)177 static bool max98373_readable_register(struct device *dev, unsigned int reg)
178 {
179 switch (reg) {
180 case MAX98373_R21FF_REV_ID:
181 case MAX98373_R2010_IRQ_CTRL:
182 /* SoundWire Control Port Registers */
183 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
184 /* Soundwire Data Port 1 Registers */
185 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
186 /* Soundwire Data Port 3 Registers */
187 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
188 case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
189 case MAX98373_R2014_THERM_WARN_THRESH
190 ... MAX98373_R2018_THERM_FOLDBACK_EN:
191 case MAX98373_R201E_PIN_DRIVE_STRENGTH
192 ... MAX98373_R2036_SOUNDWIRE_CTRL:
193 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
194 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
195 ... MAX98373_R2047_IV_SENSE_ADC_EN:
196 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
197 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
198 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
199 case MAX98373_R2097_BDE_L1_THRESH
200 ... MAX98373_R209B_BDE_THRESH_HYST:
201 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
202 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
203 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
204 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
205 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
206 ... MAX98373_R20FF_GLOBAL_SHDN:
207 return true;
208 default:
209 return false;
210 }
211 };
212
max98373_volatile_reg(struct device * dev,unsigned int reg)213 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
214 {
215 switch (reg) {
216 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
217 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
218 case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
219 case MAX98373_R20FF_GLOBAL_SHDN:
220 case MAX98373_R21FF_REV_ID:
221 /* SoundWire Control Port Registers */
222 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
223 /* Soundwire Data Port 1 Registers */
224 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
225 /* Soundwire Data Port 3 Registers */
226 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
227 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
228 return true;
229 default:
230 return false;
231 }
232 }
233
234 static const struct regmap_config max98373_sdw_regmap = {
235 .reg_bits = 32,
236 .val_bits = 8,
237 .max_register = MAX98373_R21FF_REV_ID,
238 .reg_defaults = max98373_reg,
239 .num_reg_defaults = ARRAY_SIZE(max98373_reg),
240 .readable_reg = max98373_readable_register,
241 .volatile_reg = max98373_volatile_reg,
242 .cache_type = REGCACHE_RBTREE,
243 .use_single_read = true,
244 .use_single_write = true,
245 };
246
247 /* Power management functions and structure */
max98373_suspend(struct device * dev)248 static int max98373_suspend(struct device *dev)
249 {
250 struct max98373_priv *max98373 = dev_get_drvdata(dev);
251 int i;
252
253 /* cache feedback register values before suspend */
254 for (i = 0; i < max98373->cache_num; i++)
255 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
256
257 regcache_cache_only(max98373->regmap, true);
258
259 return 0;
260 }
261
262 #define MAX98373_PROBE_TIMEOUT 5000
263
max98373_resume(struct device * dev)264 static int max98373_resume(struct device *dev)
265 {
266 struct sdw_slave *slave = dev_to_sdw_dev(dev);
267 struct max98373_priv *max98373 = dev_get_drvdata(dev);
268 int ret;
269
270 if (!max98373->first_hw_init)
271 return 0;
272
273 ret = sdw_slave_wait_for_init(slave, MAX98373_PROBE_TIMEOUT);
274 if (ret) {
275 sdw_show_ping_status(slave->bus, true);
276 return ret;
277 }
278
279 regcache_cache_only(max98373->regmap, false);
280 ret = regcache_sync(max98373->regmap);
281 if (ret) {
282 regcache_cache_only(max98373->regmap, true);
283 regcache_mark_dirty(max98373->regmap);
284 return ret;
285 }
286
287 return 0;
288 }
289
290 static const struct dev_pm_ops max98373_pm = {
291 SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
292 RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
293 };
294
max98373_read_prop(struct sdw_slave * slave)295 static int max98373_read_prop(struct sdw_slave *slave)
296 {
297 struct sdw_slave_prop *prop = &slave->prop;
298 int nval, i;
299 u32 bit;
300 unsigned long addr;
301 struct sdw_dpn_prop *dpn;
302
303 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
304
305 /* BITMAP: 00001000 Dataport 3 is active */
306 prop->source_ports = BIT(3);
307 /* BITMAP: 00000010 Dataport 1 is active */
308 prop->sink_ports = BIT(1);
309 prop->paging_support = true;
310 prop->clk_stop_timeout = 20;
311
312 nval = hweight32(prop->source_ports);
313 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
314 sizeof(*prop->src_dpn_prop),
315 GFP_KERNEL);
316 if (!prop->src_dpn_prop)
317 return -ENOMEM;
318
319 i = 0;
320 dpn = prop->src_dpn_prop;
321 addr = prop->source_ports;
322 for_each_set_bit(bit, &addr, 32) {
323 dpn[i].num = bit;
324 dpn[i].type = SDW_DPN_FULL;
325 dpn[i].simple_ch_prep_sm = true;
326 dpn[i].ch_prep_timeout = 10;
327 i++;
328 }
329
330 /* do this again for sink now */
331 nval = hweight32(prop->sink_ports);
332 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
333 sizeof(*prop->sink_dpn_prop),
334 GFP_KERNEL);
335 if (!prop->sink_dpn_prop)
336 return -ENOMEM;
337
338 i = 0;
339 dpn = prop->sink_dpn_prop;
340 addr = prop->sink_ports;
341 for_each_set_bit(bit, &addr, 32) {
342 dpn[i].num = bit;
343 dpn[i].type = SDW_DPN_FULL;
344 dpn[i].simple_ch_prep_sm = true;
345 dpn[i].ch_prep_timeout = 10;
346 i++;
347 }
348
349 /* set the timeout values */
350 prop->clk_stop_timeout = 20;
351
352 return 0;
353 }
354
max98373_io_init(struct sdw_slave * slave)355 static int max98373_io_init(struct sdw_slave *slave)
356 {
357 struct device *dev = &slave->dev;
358 struct max98373_priv *max98373 = dev_get_drvdata(dev);
359
360 regcache_cache_only(max98373->regmap, false);
361 if (max98373->first_hw_init)
362 regcache_cache_bypass(max98373->regmap, true);
363
364 /*
365 * PM runtime status is marked as 'active' only when a Slave reports as Attached
366 */
367 if (!max98373->first_hw_init)
368 /* update count of parent 'active' children */
369 pm_runtime_set_active(dev);
370
371 pm_runtime_get_noresume(dev);
372
373 /* Software Reset */
374 max98373_reset(max98373, dev);
375
376 /* Set soundwire mode */
377 regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
378 /* Enable ADC */
379 regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
380 /* Set default Soundwire clock */
381 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
382 /* Set default sampling rate for speaker and IVDAC */
383 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
384 /* IV default slot configuration */
385 regmap_write(max98373->regmap,
386 MAX98373_R2020_PCM_TX_HIZ_EN_1,
387 0xFF);
388 regmap_write(max98373->regmap,
389 MAX98373_R2021_PCM_TX_HIZ_EN_2,
390 0xFF);
391 /* L/R mix configuration */
392 regmap_write(max98373->regmap,
393 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
394 0x80);
395 regmap_write(max98373->regmap,
396 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
397 0x1);
398 /* Enable DC blocker */
399 regmap_write(max98373->regmap,
400 MAX98373_R203F_AMP_DSP_CFG,
401 0x3);
402 /* Enable IMON VMON DC blocker */
403 regmap_write(max98373->regmap,
404 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
405 0x7);
406 /* voltage, current slot configuration */
407 regmap_write(max98373->regmap,
408 MAX98373_R2022_PCM_TX_SRC_1,
409 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
410 max98373->v_slot) & 0xFF);
411 if (max98373->v_slot < 8)
412 regmap_update_bits(max98373->regmap,
413 MAX98373_R2020_PCM_TX_HIZ_EN_1,
414 1 << max98373->v_slot, 0);
415 else
416 regmap_update_bits(max98373->regmap,
417 MAX98373_R2021_PCM_TX_HIZ_EN_2,
418 1 << (max98373->v_slot - 8), 0);
419
420 if (max98373->i_slot < 8)
421 regmap_update_bits(max98373->regmap,
422 MAX98373_R2020_PCM_TX_HIZ_EN_1,
423 1 << max98373->i_slot, 0);
424 else
425 regmap_update_bits(max98373->regmap,
426 MAX98373_R2021_PCM_TX_HIZ_EN_2,
427 1 << (max98373->i_slot - 8), 0);
428
429 /* speaker feedback slot configuration */
430 regmap_write(max98373->regmap,
431 MAX98373_R2023_PCM_TX_SRC_2,
432 max98373->spkfb_slot & 0xFF);
433
434 /* Set interleave mode */
435 if (max98373->interleave_mode)
436 regmap_update_bits(max98373->regmap,
437 MAX98373_R2024_PCM_DATA_FMT_CFG,
438 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
439 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
440
441 /* Speaker enable */
442 regmap_update_bits(max98373->regmap,
443 MAX98373_R2043_AMP_EN,
444 MAX98373_SPK_EN_MASK, 1);
445
446 regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
447 regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
448
449 if (max98373->first_hw_init) {
450 regcache_cache_bypass(max98373->regmap, false);
451 regcache_mark_dirty(max98373->regmap);
452 }
453
454 max98373->first_hw_init = true;
455 max98373->hw_init = true;
456
457 pm_runtime_put_autosuspend(dev);
458
459 return 0;
460 }
461
max98373_clock_calculate(struct sdw_slave * slave,unsigned int clk_freq)462 static int max98373_clock_calculate(struct sdw_slave *slave,
463 unsigned int clk_freq)
464 {
465 int x, y;
466 static const int max98373_clk_family[] = {
467 7680000, 8400000, 9600000, 11289600,
468 12000000, 12288000, 13000000
469 };
470
471 for (x = 0; x < 4; x++)
472 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
473 if (clk_freq == (max98373_clk_family[y] >> x))
474 return (x << 3) + y;
475
476 /* Set default clock (12.288 Mhz) if the value is not in the list */
477 dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
478 clk_freq);
479 return 0x5;
480 }
481
max98373_clock_config(struct sdw_slave * slave,struct sdw_bus_params * params)482 static int max98373_clock_config(struct sdw_slave *slave,
483 struct sdw_bus_params *params)
484 {
485 struct device *dev = &slave->dev;
486 struct max98373_priv *max98373 = dev_get_drvdata(dev);
487 unsigned int clk_freq, value;
488
489 clk_freq = (params->curr_dr_freq >> 1);
490
491 /*
492 * Select the proper value for the register based on the
493 * requested clock. If the value is not in the list,
494 * use reasonable default - 12.288 Mhz
495 */
496 value = max98373_clock_calculate(slave, clk_freq);
497
498 /* SWCLK */
499 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
500
501 /* The default Sampling Rate value for IV is 48KHz*/
502 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
503
504 return 0;
505 }
506
507 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
508 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
509
max98373_sdw_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)510 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
511 struct snd_pcm_hw_params *params,
512 struct snd_soc_dai *dai)
513 {
514 struct snd_soc_component *component = dai->component;
515 struct max98373_priv *max98373 =
516 snd_soc_component_get_drvdata(component);
517 struct sdw_stream_config stream_config = {0};
518 struct sdw_port_config port_config = {0};
519 struct sdw_stream_runtime *sdw_stream;
520 int ret, chan_sz, sampling_rate;
521
522 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
523
524 if (!sdw_stream)
525 return -EINVAL;
526
527 if (!max98373->slave)
528 return -EINVAL;
529
530 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
531
532 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
533 port_config.num = 1;
534
535 if (max98373->slot) {
536 stream_config.ch_count = max98373->slot;
537 port_config.ch_mask = max98373->rx_mask;
538 }
539 } else {
540 port_config.num = 3;
541
542 /* only IV are supported by capture */
543 stream_config.ch_count = 2;
544 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
545 }
546
547 ret = sdw_stream_add_slave(max98373->slave, &stream_config,
548 &port_config, 1, sdw_stream);
549 if (ret) {
550 dev_err(dai->dev, "Unable to configure port\n");
551 return ret;
552 }
553
554 if (params_channels(params) > 16) {
555 dev_err(component->dev, "Unsupported channels %d\n",
556 params_channels(params));
557 return -EINVAL;
558 }
559
560 /* Channel size configuration */
561 switch (snd_pcm_format_width(params_format(params))) {
562 case 16:
563 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
564 break;
565 case 24:
566 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
567 break;
568 case 32:
569 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
570 break;
571 default:
572 dev_err(component->dev, "Channel size unsupported %d\n",
573 params_format(params));
574 return -EINVAL;
575 }
576
577 max98373->ch_size = snd_pcm_format_width(params_format(params));
578
579 regmap_update_bits(max98373->regmap,
580 MAX98373_R2024_PCM_DATA_FMT_CFG,
581 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
582
583 dev_dbg(component->dev, "Format supported %d", params_format(params));
584
585 /* Sampling rate configuration */
586 switch (params_rate(params)) {
587 case 8000:
588 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
589 break;
590 case 11025:
591 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
592 break;
593 case 12000:
594 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
595 break;
596 case 16000:
597 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
598 break;
599 case 22050:
600 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
601 break;
602 case 24000:
603 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
604 break;
605 case 32000:
606 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
607 break;
608 case 44100:
609 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
610 break;
611 case 48000:
612 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
613 break;
614 case 88200:
615 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
616 break;
617 case 96000:
618 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
619 break;
620 default:
621 dev_err(component->dev, "Rate %d is not supported\n",
622 params_rate(params));
623 return -EINVAL;
624 }
625
626 /* set correct sampling frequency */
627 regmap_update_bits(max98373->regmap,
628 MAX98373_R2028_PCM_SR_SETUP_2,
629 MAX98373_PCM_SR_SET2_SR_MASK,
630 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
631
632 /* set sampling rate of IV */
633 regmap_update_bits(max98373->regmap,
634 MAX98373_R2028_PCM_SR_SETUP_2,
635 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
636 sampling_rate);
637
638 return 0;
639 }
640
max98373_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)641 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
642 struct snd_soc_dai *dai)
643 {
644 struct snd_soc_component *component = dai->component;
645 struct max98373_priv *max98373 =
646 snd_soc_component_get_drvdata(component);
647 struct sdw_stream_runtime *sdw_stream =
648 snd_soc_dai_get_dma_data(dai, substream);
649
650 if (!max98373->slave)
651 return -EINVAL;
652
653 sdw_stream_remove_slave(max98373->slave, sdw_stream);
654 return 0;
655 }
656
max98373_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)657 static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
658 void *sdw_stream, int direction)
659 {
660 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
661
662 return 0;
663 }
664
max98373_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)665 static void max98373_shutdown(struct snd_pcm_substream *substream,
666 struct snd_soc_dai *dai)
667 {
668 snd_soc_dai_set_dma_data(dai, substream, NULL);
669 }
670
max98373_sdw_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)671 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
672 unsigned int tx_mask,
673 unsigned int rx_mask,
674 int slots, int slot_width)
675 {
676 struct snd_soc_component *component = dai->component;
677 struct max98373_priv *max98373 =
678 snd_soc_component_get_drvdata(component);
679
680 /* tx_mask is unused since it's irrelevant for I/V feedback */
681 if (tx_mask)
682 return -EINVAL;
683
684 if (!rx_mask && !slots && !slot_width)
685 max98373->tdm_mode = false;
686 else
687 max98373->tdm_mode = true;
688
689 max98373->rx_mask = rx_mask;
690 max98373->slot = slots;
691
692 return 0;
693 }
694
695 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
696 .hw_params = max98373_sdw_dai_hw_params,
697 .hw_free = max98373_pcm_hw_free,
698 .set_stream = max98373_set_sdw_stream,
699 .shutdown = max98373_shutdown,
700 .set_tdm_slot = max98373_sdw_set_tdm_slot,
701 };
702
703 static struct snd_soc_dai_driver max98373_sdw_dai[] = {
704 {
705 .name = "max98373-aif1",
706 .playback = {
707 .stream_name = "HiFi Playback",
708 .channels_min = 1,
709 .channels_max = 2,
710 .rates = MAX98373_RATES,
711 .formats = MAX98373_FORMATS,
712 },
713 .capture = {
714 .stream_name = "HiFi Capture",
715 .channels_min = 1,
716 .channels_max = 2,
717 .rates = MAX98373_RATES,
718 .formats = MAX98373_FORMATS,
719 },
720 .ops = &max98373_dai_sdw_ops,
721 }
722 };
723
max98373_init(struct sdw_slave * slave,struct regmap * regmap)724 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
725 {
726 struct max98373_priv *max98373;
727 int ret;
728 int i;
729 struct device *dev = &slave->dev;
730
731 /* Allocate and assign private driver data structure */
732 max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
733 if (!max98373)
734 return -ENOMEM;
735
736 dev_set_drvdata(dev, max98373);
737 max98373->regmap = regmap;
738 max98373->slave = slave;
739
740 regcache_cache_only(max98373->regmap, true);
741
742 max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg);
743 max98373->cache = devm_kcalloc(dev, max98373->cache_num,
744 sizeof(*max98373->cache),
745 GFP_KERNEL);
746 if (!max98373->cache)
747 return -ENOMEM;
748
749 for (i = 0; i < max98373->cache_num; i++)
750 max98373->cache[i].reg = max98373_sdw_cache_reg[i];
751
752 /* Read voltage and slot configuration */
753 max98373_slot_config(dev, max98373);
754
755 max98373->hw_init = false;
756 max98373->first_hw_init = false;
757
758 /* codec registration */
759 ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
760 max98373_sdw_dai,
761 ARRAY_SIZE(max98373_sdw_dai));
762 if (ret < 0) {
763 dev_err(dev, "Failed to register codec: %d\n", ret);
764 return ret;
765 }
766
767 /* set autosuspend parameters */
768 pm_runtime_set_autosuspend_delay(dev, 3000);
769 pm_runtime_use_autosuspend(dev);
770
771 /* make sure the device does not suspend immediately */
772 pm_runtime_mark_last_busy(dev);
773
774 pm_runtime_enable(dev);
775
776 /* important note: the device is NOT tagged as 'active' and will remain
777 * 'suspended' until the hardware is enumerated/initialized. This is required
778 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
779 * fail with -EACCESS because of race conditions between card creation and enumeration
780 */
781
782 return 0;
783 }
784
max98373_update_status(struct sdw_slave * slave,enum sdw_slave_status status)785 static int max98373_update_status(struct sdw_slave *slave,
786 enum sdw_slave_status status)
787 {
788 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
789
790 if (status == SDW_SLAVE_UNATTACHED)
791 max98373->hw_init = false;
792
793 /*
794 * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
795 */
796 if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
797 return 0;
798
799 /* perform I/O transfers required for Slave initialization */
800 return max98373_io_init(slave);
801 }
802
max98373_bus_config(struct sdw_slave * slave,struct sdw_bus_params * params)803 static int max98373_bus_config(struct sdw_slave *slave,
804 struct sdw_bus_params *params)
805 {
806 int ret;
807
808 ret = max98373_clock_config(slave, params);
809 if (ret < 0)
810 dev_err(&slave->dev, "Invalid clk config");
811
812 return ret;
813 }
814
815 /*
816 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
817 * port_prep are not defined for now
818 */
819 static const struct sdw_slave_ops max98373_slave_ops = {
820 .read_prop = max98373_read_prop,
821 .update_status = max98373_update_status,
822 .bus_config = max98373_bus_config,
823 };
824
max98373_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)825 static int max98373_sdw_probe(struct sdw_slave *slave,
826 const struct sdw_device_id *id)
827 {
828 struct regmap *regmap;
829
830 /* Regmap Initialization */
831 regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
832 if (IS_ERR(regmap))
833 return PTR_ERR(regmap);
834
835 return max98373_init(slave, regmap);
836 }
837
max98373_sdw_remove(struct sdw_slave * slave)838 static void max98373_sdw_remove(struct sdw_slave *slave)
839 {
840 pm_runtime_disable(&slave->dev);
841 }
842
843 #if defined(CONFIG_OF)
844 static const struct of_device_id max98373_of_match[] = {
845 { .compatible = "maxim,max98373", },
846 {},
847 };
848 MODULE_DEVICE_TABLE(of, max98373_of_match);
849 #endif
850
851 #ifdef CONFIG_ACPI
852 static const struct acpi_device_id max98373_acpi_match[] = {
853 { "MX98373", 0 },
854 {},
855 };
856 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
857 #endif
858
859 static const struct sdw_device_id max98373_id[] = {
860 SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
861 {},
862 };
863 MODULE_DEVICE_TABLE(sdw, max98373_id);
864
865 static struct sdw_driver max98373_sdw_driver = {
866 .driver = {
867 .name = "max98373",
868 .of_match_table = of_match_ptr(max98373_of_match),
869 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
870 .pm = pm_ptr(&max98373_pm),
871 },
872 .probe = max98373_sdw_probe,
873 .remove = max98373_sdw_remove,
874 .ops = &max98373_slave_ops,
875 .id_table = max98373_id,
876 };
877
878 module_sdw_driver(max98373_sdw_driver);
879
880 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
881 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
882 MODULE_LICENSE("GPL v2");
883