1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/pcs/pcs-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 /* Synopsys Core versions */ 30 #define DWMAC_CORE_3_40 0x34 31 #define DWMAC_CORE_3_50 0x35 32 #define DWMAC_CORE_3_70 0x37 33 #define DWMAC_CORE_4_00 0x40 34 #define DWMAC_CORE_4_10 0x41 35 #define DWMAC_CORE_5_00 0x50 36 #define DWMAC_CORE_5_10 0x51 37 #define DWMAC_CORE_5_20 0x52 38 #define DWXGMAC_CORE_2_10 0x21 39 #define DWXGMAC_CORE_2_20 0x22 40 #define DWXLGMAC_CORE_2_00 0x20 41 42 /* Device ID */ 43 #define DWXGMAC_ID 0x76 44 #define DWXLGMAC_ID 0x27 45 46 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 47 48 /* TX and RX Descriptor Length, these need to be power of two. 49 * TX descriptor length less than 64 may cause transmit queue timed out error. 50 * RX descriptor length less than 64 may cause inconsistent Rx chain error. 51 */ 52 #define DMA_MIN_TX_SIZE 64 53 #define DMA_MAX_TX_SIZE 1024 54 #define DMA_DEFAULT_TX_SIZE 512 55 #define DMA_MIN_RX_SIZE 64 56 #define DMA_MAX_RX_SIZE 1024 57 #define DMA_DEFAULT_RX_SIZE 512 58 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 59 60 #undef FRAME_FILTER_DEBUG 61 /* #define FRAME_FILTER_DEBUG */ 62 63 struct stmmac_q_tx_stats { 64 u64_stats_t tx_bytes; 65 u64_stats_t tx_set_ic_bit; 66 u64_stats_t tx_tso_frames; 67 u64_stats_t tx_tso_nfrags; 68 }; 69 70 struct stmmac_napi_tx_stats { 71 u64_stats_t tx_packets; 72 u64_stats_t tx_pkt_n; 73 u64_stats_t poll; 74 u64_stats_t tx_clean; 75 u64_stats_t tx_set_ic_bit; 76 }; 77 78 struct stmmac_txq_stats { 79 /* Updates protected by tx queue lock. */ 80 struct u64_stats_sync q_syncp; 81 struct stmmac_q_tx_stats q; 82 83 /* Updates protected by NAPI poll logic. */ 84 struct u64_stats_sync napi_syncp; 85 struct stmmac_napi_tx_stats napi; 86 } ____cacheline_aligned_in_smp; 87 88 struct stmmac_napi_rx_stats { 89 u64_stats_t rx_bytes; 90 u64_stats_t rx_packets; 91 u64_stats_t rx_pkt_n; 92 u64_stats_t poll; 93 }; 94 95 struct stmmac_rxq_stats { 96 /* Updates protected by NAPI poll logic. */ 97 struct u64_stats_sync napi_syncp; 98 struct stmmac_napi_rx_stats napi; 99 } ____cacheline_aligned_in_smp; 100 101 /* Updates on each CPU protected by not allowing nested irqs. */ 102 struct stmmac_pcpu_stats { 103 struct u64_stats_sync syncp; 104 u64_stats_t rx_normal_irq_n[MTL_MAX_RX_QUEUES]; 105 u64_stats_t tx_normal_irq_n[MTL_MAX_TX_QUEUES]; 106 }; 107 108 /* Extra statistic and debug information exposed by ethtool */ 109 struct stmmac_extra_stats { 110 /* Transmit errors */ 111 unsigned long tx_underflow ____cacheline_aligned; 112 unsigned long tx_carrier; 113 unsigned long tx_losscarrier; 114 unsigned long vlan_tag; 115 unsigned long tx_deferred; 116 unsigned long tx_vlan; 117 unsigned long tx_jabber; 118 unsigned long tx_frame_flushed; 119 unsigned long tx_payload_error; 120 unsigned long tx_ip_header_error; 121 unsigned long tx_collision; 122 /* Receive errors */ 123 unsigned long rx_desc; 124 unsigned long sa_filter_fail; 125 unsigned long overflow_error; 126 unsigned long ipc_csum_error; 127 unsigned long rx_collision; 128 unsigned long rx_crc_errors; 129 unsigned long dribbling_bit; 130 unsigned long rx_length; 131 unsigned long rx_mii; 132 unsigned long rx_multicast; 133 unsigned long rx_gmac_overflow; 134 unsigned long rx_watchdog; 135 unsigned long da_rx_filter_fail; 136 unsigned long sa_rx_filter_fail; 137 unsigned long rx_missed_cntr; 138 unsigned long rx_overflow_cntr; 139 unsigned long rx_vlan; 140 unsigned long rx_split_hdr_pkt_n; 141 /* Tx/Rx IRQ error info */ 142 unsigned long tx_undeflow_irq; 143 unsigned long tx_process_stopped_irq; 144 unsigned long tx_jabber_irq; 145 unsigned long rx_overflow_irq; 146 unsigned long rx_buf_unav_irq; 147 unsigned long rx_process_stopped_irq; 148 unsigned long rx_watchdog_irq; 149 unsigned long tx_early_irq; 150 unsigned long fatal_bus_error_irq; 151 /* Tx/Rx IRQ Events */ 152 unsigned long rx_early_irq; 153 unsigned long threshold; 154 unsigned long irq_receive_pmt_irq_n; 155 /* MMC info */ 156 unsigned long mmc_tx_irq_n; 157 unsigned long mmc_rx_irq_n; 158 unsigned long mmc_rx_csum_offload_irq_n; 159 /* EEE */ 160 unsigned long irq_tx_path_in_lpi_mode_n; 161 unsigned long irq_tx_path_exit_lpi_mode_n; 162 unsigned long irq_rx_path_in_lpi_mode_n; 163 unsigned long irq_rx_path_exit_lpi_mode_n; 164 unsigned long phy_eee_wakeup_error_n; 165 /* Extended RDES status */ 166 unsigned long ip_hdr_err; 167 unsigned long ip_payload_err; 168 unsigned long ip_csum_bypassed; 169 unsigned long ipv4_pkt_rcvd; 170 unsigned long ipv6_pkt_rcvd; 171 unsigned long no_ptp_rx_msg_type_ext; 172 unsigned long ptp_rx_msg_type_sync; 173 unsigned long ptp_rx_msg_type_follow_up; 174 unsigned long ptp_rx_msg_type_delay_req; 175 unsigned long ptp_rx_msg_type_delay_resp; 176 unsigned long ptp_rx_msg_type_pdelay_req; 177 unsigned long ptp_rx_msg_type_pdelay_resp; 178 unsigned long ptp_rx_msg_type_pdelay_follow_up; 179 unsigned long ptp_rx_msg_type_announce; 180 unsigned long ptp_rx_msg_type_management; 181 unsigned long ptp_rx_msg_pkt_reserved_type; 182 unsigned long ptp_frame_type; 183 unsigned long ptp_ver; 184 unsigned long timestamp_dropped; 185 unsigned long av_pkt_rcvd; 186 unsigned long av_tagged_pkt_rcvd; 187 unsigned long vlan_tag_priority_val; 188 unsigned long l3_filter_match; 189 unsigned long l4_filter_match; 190 unsigned long l3_l4_filter_no_match; 191 /* PCS */ 192 unsigned long irq_pcs_ane_n; 193 unsigned long irq_pcs_link_n; 194 unsigned long irq_rgmii_n; 195 unsigned long pcs_link; 196 unsigned long pcs_duplex; 197 unsigned long pcs_speed; 198 /* debug register */ 199 unsigned long mtl_tx_status_fifo_full; 200 unsigned long mtl_tx_fifo_not_empty; 201 unsigned long mmtl_fifo_ctrl; 202 unsigned long mtl_tx_fifo_read_ctrl_write; 203 unsigned long mtl_tx_fifo_read_ctrl_wait; 204 unsigned long mtl_tx_fifo_read_ctrl_read; 205 unsigned long mtl_tx_fifo_read_ctrl_idle; 206 unsigned long mac_tx_in_pause; 207 unsigned long mac_tx_frame_ctrl_xfer; 208 unsigned long mac_tx_frame_ctrl_idle; 209 unsigned long mac_tx_frame_ctrl_wait; 210 unsigned long mac_tx_frame_ctrl_pause; 211 unsigned long mac_gmii_tx_proto_engine; 212 unsigned long mtl_rx_fifo_fill_level_full; 213 unsigned long mtl_rx_fifo_fill_above_thresh; 214 unsigned long mtl_rx_fifo_fill_below_thresh; 215 unsigned long mtl_rx_fifo_fill_level_empty; 216 unsigned long mtl_rx_fifo_read_ctrl_flush; 217 unsigned long mtl_rx_fifo_read_ctrl_read_data; 218 unsigned long mtl_rx_fifo_read_ctrl_status; 219 unsigned long mtl_rx_fifo_read_ctrl_idle; 220 unsigned long mtl_rx_fifo_ctrl_active; 221 unsigned long mac_rx_frame_ctrl_fifo; 222 unsigned long mac_gmii_rx_proto_engine; 223 /* EST */ 224 unsigned long mtl_est_cgce; 225 unsigned long mtl_est_hlbs; 226 unsigned long mtl_est_hlbf; 227 unsigned long mtl_est_btre; 228 unsigned long mtl_est_btrlm; 229 unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES]; 230 unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES]; 231 /* per queue statistics */ 232 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES]; 233 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES]; 234 struct stmmac_pcpu_stats __percpu *pcpu_stats; 235 unsigned long rx_dropped; 236 unsigned long rx_errors; 237 unsigned long tx_dropped; 238 unsigned long tx_errors; 239 }; 240 241 /* Safety Feature statistics exposed by ethtool */ 242 struct stmmac_safety_stats { 243 unsigned long mac_errors[32]; 244 unsigned long mtl_errors[32]; 245 unsigned long dma_errors[32]; 246 unsigned long dma_dpp_errors[32]; 247 }; 248 249 /* Number of fields in Safety Stats */ 250 #define STMMAC_SAFETY_FEAT_SIZE \ 251 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 252 253 /* CSR Frequency Access Defines*/ 254 #define CSR_F_35M 35000000 255 #define CSR_F_60M 60000000 256 #define CSR_F_100M 100000000 257 #define CSR_F_150M 150000000 258 #define CSR_F_250M 250000000 259 #define CSR_F_300M 300000000 260 #define CSR_F_500M 500000000 261 #define CSR_F_800M 800000000 262 263 #define MAC_CSR_H_FRQ_MASK 0x20 264 265 #define HASH_TABLE_SIZE 64 266 #define PAUSE_TIME 0xffff 267 268 /* Flow Control defines */ 269 #define FLOW_OFF 0 270 #define FLOW_RX 1 271 #define FLOW_TX 2 272 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 273 274 /* PCS defines */ 275 #define STMMAC_PCS_RGMII (1 << 0) 276 #define STMMAC_PCS_SGMII (1 << 1) 277 278 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 279 280 /* DMA HW feature register fields */ 281 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 282 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 283 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 284 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 285 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 286 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 287 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 288 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 289 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 290 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 291 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 292 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 293 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 294 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 295 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 296 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 297 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 298 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 299 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 300 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 301 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 302 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 303 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 304 /* Timestamping with Internal System Time */ 305 #define DMA_HW_FEAT_INTTSEN 0x02000000 306 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 307 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 308 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 309 #define DEFAULT_DMA_PBL 8 310 311 /* MSI defines */ 312 #define STMMAC_MSI_VEC_MAX 32 313 314 /* PCS status and mask defines */ 315 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 316 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 317 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 318 319 /* Max/Min RI Watchdog Timer count value */ 320 #define MAX_DMA_RIWT 0xff 321 #define MIN_DMA_RIWT 0x10 322 #define DEF_DMA_RIWT 0xa0 323 /* Tx coalesce parameters */ 324 #define STMMAC_COAL_TX_TIMER 5000 325 #define STMMAC_MAX_COAL_TX_TICK 100000 326 #define STMMAC_TX_MAX_FRAMES 256 327 #define STMMAC_TX_FRAMES 25 328 #define STMMAC_RX_FRAMES 0 329 330 /* Packets types */ 331 enum packets_types { 332 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 333 PACKET_PTPQ = 0x2, /* PTP Packets */ 334 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 335 PACKET_UPQ = 0x4, /* Untagged Packets */ 336 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 337 }; 338 339 /* Rx IPC status */ 340 enum rx_frame_status { 341 good_frame = 0x0, 342 discard_frame = 0x1, 343 csum_none = 0x2, 344 llc_snap = 0x4, 345 dma_own = 0x8, 346 rx_not_ls = 0x10, 347 }; 348 349 /* Tx status */ 350 enum tx_frame_status { 351 tx_done = 0x0, 352 tx_not_ls = 0x1, 353 tx_err = 0x2, 354 tx_dma_own = 0x4, 355 tx_err_bump_tc = 0x8, 356 }; 357 358 enum dma_irq_status { 359 tx_hard_error = 0x1, 360 tx_hard_error_bump_tc = 0x2, 361 handle_rx = 0x4, 362 handle_tx = 0x8, 363 }; 364 365 enum dma_irq_dir { 366 DMA_DIR_RX = 0x1, 367 DMA_DIR_TX = 0x2, 368 DMA_DIR_RXTX = 0x3, 369 }; 370 371 enum request_irq_err { 372 REQ_IRQ_ERR_ALL, 373 REQ_IRQ_ERR_TX, 374 REQ_IRQ_ERR_RX, 375 REQ_IRQ_ERR_SFTY, 376 REQ_IRQ_ERR_SFTY_UE, 377 REQ_IRQ_ERR_SFTY_CE, 378 REQ_IRQ_ERR_LPI, 379 REQ_IRQ_ERR_WOL, 380 REQ_IRQ_ERR_MAC, 381 REQ_IRQ_ERR_NO, 382 }; 383 384 /* EEE and LPI defines */ 385 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 386 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 387 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 388 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 389 390 /* FPE defines */ 391 #define FPE_EVENT_UNKNOWN 0 392 #define FPE_EVENT_TRSP BIT(0) 393 #define FPE_EVENT_TVER BIT(1) 394 #define FPE_EVENT_RRSP BIT(2) 395 #define FPE_EVENT_RVER BIT(3) 396 397 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 398 399 /* DMA HW capabilities */ 400 struct dma_features { 401 unsigned int mbps_10_100; 402 unsigned int mbps_1000; 403 unsigned int half_duplex; 404 unsigned int hash_filter; 405 unsigned int multi_addr; 406 unsigned int pcs; 407 unsigned int sma_mdio; 408 unsigned int pmt_remote_wake_up; 409 unsigned int pmt_magic_frame; 410 unsigned int rmon; 411 /* IEEE 1588-2002 */ 412 unsigned int time_stamp; 413 /* IEEE 1588-2008 */ 414 unsigned int atime_stamp; 415 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 416 unsigned int eee; 417 unsigned int av; 418 unsigned int hash_tb_sz; 419 unsigned int tsoen; 420 /* TX and RX csum */ 421 unsigned int tx_coe; 422 unsigned int rx_coe; 423 unsigned int rx_coe_type1; 424 unsigned int rx_coe_type2; 425 unsigned int rxfifo_over_2048; 426 /* TX and RX number of channels */ 427 unsigned int number_rx_channel; 428 unsigned int number_tx_channel; 429 /* TX and RX number of queues */ 430 unsigned int number_rx_queues; 431 unsigned int number_tx_queues; 432 /* PPS output */ 433 unsigned int pps_out_num; 434 /* Number of Traffic Classes */ 435 unsigned int numtc; 436 /* DCB Feature Enable */ 437 unsigned int dcben; 438 /* IEEE 1588 High Word Register Enable */ 439 unsigned int advthword; 440 /* PTP Offload Enable */ 441 unsigned int ptoen; 442 /* One-Step Timestamping Enable */ 443 unsigned int osten; 444 /* Priority-Based Flow Control Enable */ 445 unsigned int pfcen; 446 /* Alternate (enhanced) DESC mode */ 447 unsigned int enh_desc; 448 /* TX and RX FIFO sizes */ 449 unsigned int tx_fifo_size; 450 unsigned int rx_fifo_size; 451 /* Automotive Safety Package */ 452 unsigned int asp; 453 /* RX Parser */ 454 unsigned int frpsel; 455 unsigned int frpbs; 456 unsigned int frpes; 457 unsigned int addr64; 458 unsigned int host_dma_width; 459 unsigned int rssen; 460 unsigned int vlhash; 461 unsigned int sphen; 462 unsigned int vlins; 463 unsigned int dvlan; 464 unsigned int l3l4fnum; 465 unsigned int arpoffsel; 466 /* One Step for PTP over UDP/IP Feature Enable */ 467 unsigned int pou_ost_en; 468 /* Tx Timestamp FIFO Depth */ 469 unsigned int ttsfd; 470 /* Queue/Channel-Based VLAN tag insertion on Tx */ 471 unsigned int cbtisel; 472 /* Supported Parallel Instruction Processor Engines */ 473 unsigned int frppipe_num; 474 /* Number of Extended VLAN Tag Filters */ 475 unsigned int nrvf_num; 476 /* TSN Features */ 477 unsigned int estwid; 478 unsigned int estdep; 479 unsigned int estsel; 480 unsigned int fpesel; 481 unsigned int tbssel; 482 /* Number of DMA channels enabled for TBS */ 483 unsigned int tbs_ch_num; 484 /* Per-Stream Filtering Enable */ 485 unsigned int sgfsel; 486 /* Numbers of Auxiliary Snapshot Inputs */ 487 unsigned int aux_snapshot_n; 488 /* Timestamp System Time Source */ 489 unsigned int tssrc; 490 /* Enhanced DMA Enable */ 491 unsigned int edma; 492 /* Different Descriptor Cache Enable */ 493 unsigned int ediffc; 494 /* VxLAN/NVGRE Enable */ 495 unsigned int vxn; 496 /* Debug Memory Interface Enable */ 497 unsigned int dbgmem; 498 /* Number of Policing Counters */ 499 unsigned int pcsel; 500 }; 501 502 /* RX Buffer size must be multiple of 4/8/16 bytes */ 503 #define BUF_SIZE_16KiB 16368 504 #define BUF_SIZE_8KiB 8188 505 #define BUF_SIZE_4KiB 4096 506 #define BUF_SIZE_2KiB 2048 507 508 /* Power Down and WOL */ 509 #define PMT_NOT_SUPPORTED 0 510 #define PMT_SUPPORTED 1 511 512 /* Common MAC defines */ 513 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 514 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 515 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 516 517 /* Default LPI timers */ 518 #define STMMAC_DEFAULT_LIT_LS 0x3E8 519 #define STMMAC_DEFAULT_TWT_LS 0x1E 520 #define STMMAC_ET_MAX 0xFFFFF 521 522 /* Common LPI register bits */ 523 #define LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */ 524 #define LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable, gmac4 only */ 525 #define LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */ 526 #define LPI_CTRL_STATUS_PLSEN BIT(18) /* Enable PHY Link Status */ 527 #define LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */ 528 #define LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */ 529 #define LPI_CTRL_STATUS_RLPIST BIT(9) /* Receive LPI state, gmac1000 only? */ 530 #define LPI_CTRL_STATUS_TLPIST BIT(8) /* Transmit LPI state, gmac1000 only? */ 531 #define LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */ 532 #define LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */ 533 #define LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */ 534 #define LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */ 535 536 #define STMMAC_CHAIN_MODE 0x1 537 #define STMMAC_RING_MODE 0x2 538 539 #define JUMBO_LEN 9000 540 541 /* Receive Side Scaling */ 542 #define STMMAC_RSS_HASH_KEY_SIZE 40 543 #define STMMAC_RSS_MAX_TABLE_SIZE 256 544 545 /* VLAN */ 546 #define STMMAC_VLAN_NONE 0x0 547 #define STMMAC_VLAN_REMOVE 0x1 548 #define STMMAC_VLAN_INSERT 0x2 549 #define STMMAC_VLAN_REPLACE 0x3 550 551 struct mac_device_info; 552 553 struct mac_link { 554 u32 caps; 555 u32 speed_mask; 556 u32 speed10; 557 u32 speed100; 558 u32 speed1000; 559 u32 speed2500; 560 u32 duplex; 561 struct { 562 u32 speed2500; 563 u32 speed5000; 564 u32 speed10000; 565 } xgmii; 566 struct { 567 u32 speed25000; 568 u32 speed40000; 569 u32 speed50000; 570 u32 speed100000; 571 } xlgmii; 572 }; 573 574 struct mii_regs { 575 unsigned int addr; /* MII Address */ 576 unsigned int data; /* MII Data */ 577 unsigned int addr_shift; /* MII address shift */ 578 unsigned int reg_shift; /* MII reg shift */ 579 unsigned int addr_mask; /* MII address mask */ 580 unsigned int reg_mask; /* MII reg mask */ 581 unsigned int clk_csr_shift; 582 unsigned int clk_csr_mask; 583 }; 584 585 struct mac_device_info { 586 const struct stmmac_ops *mac; 587 const struct stmmac_desc_ops *desc; 588 const struct stmmac_dma_ops *dma; 589 const struct stmmac_mode_ops *mode; 590 const struct stmmac_hwtimestamp *ptp; 591 const struct stmmac_tc_ops *tc; 592 const struct stmmac_mmc_ops *mmc; 593 const struct stmmac_est_ops *est; 594 const struct stmmac_vlan_ops *vlan; 595 struct dw_xpcs *xpcs; 596 struct phylink_pcs *phylink_pcs; 597 struct mii_regs mii; /* MII register Addresses */ 598 struct mac_link link; 599 void __iomem *pcsr; /* vpointer to device CSRs */ 600 unsigned int multicast_filter_bins; 601 unsigned int unicast_filter_entries; 602 unsigned int mcast_bits_log2; 603 unsigned int rx_csum; 604 unsigned int pcs; 605 unsigned int pmt; 606 unsigned int ps; 607 unsigned int xlgmac; 608 unsigned int num_vlan; 609 u32 vlan_filter[32]; 610 bool vlan_fail_q_en; 611 u8 vlan_fail_q; 612 bool hw_vlan_en; 613 }; 614 615 struct stmmac_rx_routing { 616 u32 reg_mask; 617 u32 reg_shift; 618 }; 619 620 int dwmac100_setup(struct stmmac_priv *priv); 621 int dwmac1000_setup(struct stmmac_priv *priv); 622 int dwmac4_setup(struct stmmac_priv *priv); 623 int dwxgmac2_setup(struct stmmac_priv *priv); 624 int dwxlgmac2_setup(struct stmmac_priv *priv); 625 626 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 627 unsigned int high, unsigned int low); 628 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 629 unsigned int high, unsigned int low); 630 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 631 632 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 633 unsigned int high, unsigned int low); 634 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 635 unsigned int high, unsigned int low); 636 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 637 638 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 639 640 #endif /* __COMMON_H__ */ 641