1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include <linux/firmware.h>
9 #include <linux/slab.h>
10 #include <drv_types.h>
11 #include <rtl8723b_hal.h>
12 #include "hal_com_h2c.h"
13
_FWDownloadEnable(struct adapter * padapter,bool enable)14 static void _FWDownloadEnable(struct adapter *padapter, bool enable)
15 {
16 u8 tmp, count = 0;
17
18 if (enable) {
19 /* 8051 enable */
20 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
21 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04);
22
23 tmp = rtw_read8(padapter, REG_MCUFWDL);
24 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
25
26 do {
27 tmp = rtw_read8(padapter, REG_MCUFWDL);
28 if (tmp & 0x01)
29 break;
30 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
31 msleep(1);
32 } while (count++ < 100);
33
34 /* 8051 reset */
35 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
36 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
37 } else {
38 /* MCU firmware download disable. */
39 tmp = rtw_read8(padapter, REG_MCUFWDL);
40 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
41 }
42 }
43
_BlockWrite(struct adapter * padapter,void * buffer,u32 buffSize)44 static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize)
45 {
46 int ret = _SUCCESS;
47
48 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
49 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
50 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
51 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
52 u32 remainSize_p1 = 0, remainSize_p2 = 0;
53 u8 *bufferPtr = buffer;
54 u32 i = 0, offset = 0;
55
56 /* 3 Phase #1 */
57 blockCount_p1 = buffSize / blockSize_p1;
58 remainSize_p1 = buffSize % blockSize_p1;
59
60 for (i = 0; i < blockCount_p1; i++) {
61 ret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1)));
62 if (ret == _FAIL) {
63 netdev_dbg(padapter->pnetdev, "write failed at %s %d, block:%d\n",
64 __func__, __LINE__, i);
65 goto exit;
66 }
67 }
68
69 /* 3 Phase #2 */
70 if (remainSize_p1) {
71 offset = blockCount_p1 * blockSize_p1;
72
73 blockCount_p2 = remainSize_p1/blockSize_p2;
74 remainSize_p2 = remainSize_p1%blockSize_p2;
75 }
76
77 /* 3 Phase #3 */
78 if (remainSize_p2) {
79 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
80
81 blockCount_p3 = remainSize_p2 / blockSize_p3;
82
83 for (i = 0; i < blockCount_p3; i++) {
84 ret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
85
86 if (ret == _FAIL) {
87 netdev_dbg(padapter->pnetdev, "write failed at %s %d, block:%d\n",
88 __func__, __LINE__, i);
89 goto exit;
90 }
91 }
92 }
93 exit:
94 return ret;
95 }
96
_PageWrite(struct adapter * padapter,u32 page,void * buffer,u32 size)97 static int _PageWrite(
98 struct adapter *padapter,
99 u32 page,
100 void *buffer,
101 u32 size
102 )
103 {
104 u8 value8;
105 u8 u8Page = (u8) (page & 0x07);
106
107 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page;
108 rtw_write8(padapter, REG_MCUFWDL+2, value8);
109
110 return _BlockWrite(padapter, buffer, size);
111 }
112
_WriteFW(struct adapter * padapter,void * buffer,u32 size)113 static int _WriteFW(struct adapter *padapter, void *buffer, u32 size)
114 {
115 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
116 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
117 int ret = _SUCCESS;
118 u32 pageNums, remainSize;
119 u32 page, offset;
120 u8 *bufferPtr = buffer;
121
122 pageNums = size / MAX_DLFW_PAGE_SIZE;
123 remainSize = size % MAX_DLFW_PAGE_SIZE;
124
125 for (page = 0; page < pageNums; page++) {
126 offset = page * MAX_DLFW_PAGE_SIZE;
127 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE);
128
129 if (ret == _FAIL) {
130 netdev_dbg(padapter->pnetdev, "page write failed at %s %d\n",
131 __func__, __LINE__);
132 goto exit;
133 }
134 }
135
136 if (remainSize) {
137 offset = pageNums * MAX_DLFW_PAGE_SIZE;
138 page = pageNums;
139 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
140
141 if (ret == _FAIL) {
142 netdev_dbg(padapter->pnetdev, "remaining page write failed at %s %d\n",
143 __func__, __LINE__);
144 goto exit;
145 }
146 }
147
148 exit:
149 return ret;
150 }
151
_8051Reset8723(struct adapter * padapter)152 void _8051Reset8723(struct adapter *padapter)
153 {
154 u8 cpu_rst;
155 u8 io_rst;
156
157
158 /* Reset 8051(WLMCU) IO wrapper */
159 /* 0x1c[8] = 0 */
160 /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */
161 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
162 io_rst &= ~BIT(0);
163 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
164
165 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
166 cpu_rst &= ~BIT(2);
167 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
168
169 /* Enable 8051 IO wrapper */
170 /* 0x1c[8] = 1 */
171 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1);
172 io_rst |= BIT(0);
173 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst);
174
175 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
176 cpu_rst |= BIT(2);
177 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst);
178 }
179
180 u8 g_fwdl_chksum_fail;
181
polling_fwdl_chksum(struct adapter * adapter,u32 min_cnt,u32 timeout_ms)182 static s32 polling_fwdl_chksum(
183 struct adapter *adapter, u32 min_cnt, u32 timeout_ms
184 )
185 {
186 s32 ret = _FAIL;
187 u32 value32;
188 unsigned long start = jiffies;
189 u32 cnt = 0;
190
191 /* polling CheckSum report */
192 do {
193 cnt++;
194 value32 = rtw_read32(adapter, REG_MCUFWDL);
195 if (value32 & FWDL_ChkSum_rpt || adapter->bSurpriseRemoved || adapter->bDriverStopped)
196 break;
197 yield();
198 } while (jiffies_to_msecs(jiffies-start) < timeout_ms || cnt < min_cnt);
199
200 if (!(value32 & FWDL_ChkSum_rpt)) {
201 goto exit;
202 }
203
204 if (g_fwdl_chksum_fail) {
205 g_fwdl_chksum_fail--;
206 goto exit;
207 }
208
209 ret = _SUCCESS;
210
211 exit:
212
213 return ret;
214 }
215
216 u8 g_fwdl_wintint_rdy_fail;
217
_FWFreeToGo(struct adapter * adapter,u32 min_cnt,u32 timeout_ms)218 static s32 _FWFreeToGo(struct adapter *adapter, u32 min_cnt, u32 timeout_ms)
219 {
220 s32 ret = _FAIL;
221 u32 value32;
222 unsigned long start = jiffies;
223 u32 cnt = 0;
224
225 value32 = rtw_read32(adapter, REG_MCUFWDL);
226 value32 |= MCUFWDL_RDY;
227 value32 &= ~WINTINI_RDY;
228 rtw_write32(adapter, REG_MCUFWDL, value32);
229
230 _8051Reset8723(adapter);
231
232 /* polling for FW ready */
233 do {
234 cnt++;
235 value32 = rtw_read32(adapter, REG_MCUFWDL);
236 if (value32 & WINTINI_RDY || adapter->bSurpriseRemoved || adapter->bDriverStopped)
237 break;
238 yield();
239 } while (jiffies_to_msecs(jiffies - start) < timeout_ms || cnt < min_cnt);
240
241 if (!(value32 & WINTINI_RDY)) {
242 goto exit;
243 }
244
245 if (g_fwdl_wintint_rdy_fail) {
246 g_fwdl_wintint_rdy_fail--;
247 goto exit;
248 }
249
250 ret = _SUCCESS;
251
252 exit:
253
254 return ret;
255 }
256
257 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
258
rtl8723b_FirmwareSelfReset(struct adapter * padapter)259 void rtl8723b_FirmwareSelfReset(struct adapter *padapter)
260 {
261 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
262 u8 u1bTmp;
263 u8 Delay = 100;
264
265 if (
266 !(IS_FW_81xxC(padapter) && ((pHalData->FirmwareVersion < 0x21) || (pHalData->FirmwareVersion == 0x21 && pHalData->FirmwareSubVersion < 0x01)))
267 ) { /* after 88C Fw v33.1 */
268 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
269 rtw_write8(padapter, REG_HMETFR+3, 0x20);
270
271 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
272 while (u1bTmp & BIT2) {
273 Delay--;
274 if (Delay == 0)
275 break;
276 udelay(50);
277 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
278 }
279
280 if (Delay == 0) {
281 /* force firmware reset */
282 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
283 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
284 }
285 }
286 }
287
288 /* */
289 /* Description: */
290 /* Download 8192C firmware code. */
291 /* */
292 /* */
rtl8723b_FirmwareDownload(struct adapter * padapter,bool bUsedWoWLANFw)293 s32 rtl8723b_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw)
294 {
295 s32 rtStatus = _SUCCESS;
296 u8 write_fw = 0;
297 unsigned long fwdl_start_time;
298 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
299 struct rt_firmware *pFirmware;
300 struct rt_firmware *pBTFirmware;
301 struct rt_firmware_hdr *pFwHdr = NULL;
302 u8 *pFirmwareBuf;
303 u32 FirmwareLen;
304 const struct firmware *fw;
305 struct device *device = dvobj_to_dev(padapter->dvobj);
306 u8 *fwfilepath;
307 struct dvobj_priv *psdpriv = padapter->dvobj;
308 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
309 u8 tmp_ps;
310
311 pFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
312 if (!pFirmware)
313 return _FAIL;
314 pBTFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL);
315 if (!pBTFirmware) {
316 kfree(pFirmware);
317 return _FAIL;
318 }
319 tmp_ps = rtw_read8(padapter, 0xa3);
320 tmp_ps &= 0xf8;
321 tmp_ps |= 0x02;
322 /* 1. write 0xA3[:2:0] = 3b'010 */
323 rtw_write8(padapter, 0xa3, tmp_ps);
324 /* 2. read power_state = 0xA0[1:0] */
325 tmp_ps = rtw_read8(padapter, 0xa0);
326 tmp_ps &= 0x03;
327 if (tmp_ps != 0x01)
328 pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
329
330 fwfilepath = "rtlwifi/rtl8723bs_nic.bin";
331
332 pr_info("rtl8723bs: acquire FW from file:%s\n", fwfilepath);
333
334 rtStatus = request_firmware(&fw, fwfilepath, device);
335 if (rtStatus) {
336 pr_err("Request firmware failed with error 0x%x\n", rtStatus);
337 rtStatus = _FAIL;
338 goto exit;
339 }
340
341 if (!fw) {
342 pr_err("Firmware %s not available\n", fwfilepath);
343 rtStatus = _FAIL;
344 goto exit;
345 }
346
347 if (fw->size > FW_8723B_SIZE) {
348 rtStatus = _FAIL;
349 goto exit;
350 }
351
352 pFirmware->fw_buffer_sz = kmemdup(fw->data, fw->size, GFP_KERNEL);
353 if (!pFirmware->fw_buffer_sz) {
354 rtStatus = _FAIL;
355 goto exit;
356 }
357
358 pFirmware->fw_length = fw->size;
359 release_firmware(fw);
360 if (pFirmware->fw_length > FW_8723B_SIZE) {
361 rtStatus = _FAIL;
362 netdev_emerg(padapter->pnetdev,
363 "Firmware size:%u exceed %u\n",
364 pFirmware->fw_length, FW_8723B_SIZE);
365 goto release_fw1;
366 }
367
368 pFirmwareBuf = pFirmware->fw_buffer_sz;
369 FirmwareLen = pFirmware->fw_length;
370
371 /* To Check Fw header. Added by tynli. 2009.12.04. */
372 pFwHdr = (struct rt_firmware_hdr *)pFirmwareBuf;
373
374 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->version);
375 pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->subversion);
376 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->signature);
377
378 if (IS_FW_HEADER_EXIST_8723B(pFwHdr)) {
379 /* Shift 32 bytes for FW header */
380 pFirmwareBuf = pFirmwareBuf + 32;
381 FirmwareLen = FirmwareLen - 32;
382 }
383
384 /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */
385 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
386 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */
387 rtw_write8(padapter, REG_MCUFWDL, 0x00);
388 rtl8723b_FirmwareSelfReset(padapter);
389 }
390
391 _FWDownloadEnable(padapter, true);
392 fwdl_start_time = jiffies;
393 while (
394 !padapter->bDriverStopped &&
395 !padapter->bSurpriseRemoved &&
396 (write_fw++ < 3 || jiffies_to_msecs(jiffies - fwdl_start_time) < 500)
397 ) {
398 /* reset FWDL chksum */
399 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
400
401 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
402 if (rtStatus != _SUCCESS)
403 continue;
404
405 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
406 if (rtStatus == _SUCCESS)
407 break;
408 }
409 _FWDownloadEnable(padapter, false);
410 if (_SUCCESS != rtStatus)
411 goto fwdl_stat;
412
413 rtStatus = _FWFreeToGo(padapter, 10, 200);
414 if (_SUCCESS != rtStatus)
415 goto fwdl_stat;
416
417 fwdl_stat:
418
419 exit:
420 kfree(pFirmware->fw_buffer_sz);
421 kfree(pFirmware);
422 release_fw1:
423 kfree(pBTFirmware);
424 return rtStatus;
425 }
426
rtl8723b_InitializeFirmwareVars(struct adapter * padapter)427 void rtl8723b_InitializeFirmwareVars(struct adapter *padapter)
428 {
429 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
430
431 /* Init Fw LPS related. */
432 adapter_to_pwrctl(padapter)->fw_current_in_ps_mode = false;
433
434 /* Init H2C cmd. */
435 rtw_write8(padapter, REG_HMETFR, 0x0f);
436
437 /* Init H2C counter. by tynli. 2009.12.09. */
438 pHalData->LastHMEBoxNum = 0;
439 /* pHalData->H2CQueueHead = 0; */
440 /* pHalData->H2CQueueTail = 0; */
441 /* pHalData->H2CStopInsertQueue = false; */
442 }
443
444 /* */
445 /* Efuse related code */
446 /* */
hal_EfuseSwitchToBank(struct adapter * padapter,u8 bank,bool bPseudoTest)447 static u8 hal_EfuseSwitchToBank(
448 struct adapter *padapter, u8 bank, bool bPseudoTest
449 )
450 {
451 u8 bRet = false;
452 u32 value32 = 0;
453 #ifdef HAL_EFUSE_MEMORY
454 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
455 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
456 #endif
457
458
459 if (bPseudoTest) {
460 #ifdef HAL_EFUSE_MEMORY
461 pEfuseHal->fakeEfuseBank = bank;
462 #else
463 fakeEfuseBank = bank;
464 #endif
465 bRet = true;
466 } else {
467 value32 = rtw_read32(padapter, EFUSE_TEST);
468 bRet = true;
469 switch (bank) {
470 case 0:
471 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
472 break;
473 case 1:
474 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
475 break;
476 case 2:
477 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
478 break;
479 case 3:
480 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
481 break;
482 default:
483 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
484 bRet = false;
485 break;
486 }
487 rtw_write32(padapter, EFUSE_TEST, value32);
488 }
489
490 return bRet;
491 }
492
Hal_GetEfuseDefinition(struct adapter * padapter,u8 efuseType,u8 type,void * pOut,bool bPseudoTest)493 void Hal_GetEfuseDefinition(
494 struct adapter *padapter,
495 u8 efuseType,
496 u8 type,
497 void *pOut,
498 bool bPseudoTest
499 )
500 {
501 switch (type) {
502 case TYPE_EFUSE_MAX_SECTION:
503 {
504 u8 *pMax_section = pOut;
505
506 if (efuseType == EFUSE_WIFI)
507 *pMax_section = EFUSE_MAX_SECTION_8723B;
508 else
509 *pMax_section = EFUSE_BT_MAX_SECTION;
510 }
511 break;
512
513 case TYPE_EFUSE_REAL_CONTENT_LEN:
514 {
515 u16 *pu2Tmp = pOut;
516
517 if (efuseType == EFUSE_WIFI)
518 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
519 else
520 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
521 }
522 break;
523
524 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
525 {
526 u16 *pu2Tmp = pOut;
527
528 if (efuseType == EFUSE_WIFI)
529 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
530 else
531 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK);
532 }
533 break;
534
535 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
536 {
537 u16 *pu2Tmp = pOut;
538
539 if (efuseType == EFUSE_WIFI)
540 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES);
541 else
542 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3));
543 }
544 break;
545
546 case TYPE_EFUSE_MAP_LEN:
547 {
548 u16 *pu2Tmp = pOut;
549
550 if (efuseType == EFUSE_WIFI)
551 *pu2Tmp = EFUSE_MAX_MAP_LEN;
552 else
553 *pu2Tmp = EFUSE_BT_MAP_LEN;
554 }
555 break;
556
557 case TYPE_EFUSE_PROTECT_BYTES_BANK:
558 {
559 u8 *pu1Tmp = pOut;
560
561 if (efuseType == EFUSE_WIFI)
562 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
563 else
564 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
565 }
566 break;
567
568 case TYPE_EFUSE_CONTENT_LEN_BANK:
569 {
570 u16 *pu2Tmp = pOut;
571
572 if (efuseType == EFUSE_WIFI)
573 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B;
574 else
575 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
576 }
577 break;
578
579 default:
580 {
581 u8 *pu1Tmp = pOut;
582 *pu1Tmp = 0;
583 }
584 break;
585 }
586 }
587
588 #define VOLTAGE_V25 0x03
589
590 /* */
591 /* The following is for compile ok */
592 /* That should be merged with the original in the future */
593 /* */
594 #define EFUSE_ACCESS_ON_8723 0x69 /* For RTL8723 only. */
595 #define REG_EFUSE_ACCESS_8723 0x00CF /* Efuse access protection for RTL8723 */
596
Hal_EfusePowerSwitch(struct adapter * padapter,u8 bWrite,u8 PwrState)597 void Hal_EfusePowerSwitch(
598 struct adapter *padapter, u8 bWrite, u8 PwrState
599 )
600 {
601 u8 tempval;
602 u16 tmpV16;
603
604
605 if (PwrState) {
606 /* To avoid cannot access efuse registers after disable/enable several times during DTM test. */
607 /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */
608 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
609 if (tempval & BIT(0)) { /* SDIO local register is suspend */
610 u8 count = 0;
611
612
613 tempval &= ~BIT(0);
614 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL, tempval);
615
616 /* check 0x86[1:0]= 10'2h, wait power state to leave suspend */
617 do {
618 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL);
619 tempval &= 0x3;
620 if (tempval == 0x02)
621 break;
622
623 count++;
624 if (count >= 100)
625 break;
626
627 mdelay(10);
628 } while (1);
629 }
630
631 rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723);
632
633 /* Reset: 0x0000h[28], default valid */
634 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
635 if (!(tmpV16 & FEN_ELDR)) {
636 tmpV16 |= FEN_ELDR;
637 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
638 }
639
640 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
641 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
642 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
643 tmpV16 |= (LOADER_CLK_EN | ANA8M);
644 rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
645 }
646
647 if (bWrite) {
648 /* Enable LDO 2.5V before read/write action */
649 tempval = rtw_read8(padapter, EFUSE_TEST+3);
650 tempval &= 0x0F;
651 tempval |= (VOLTAGE_V25 << 4);
652 rtw_write8(padapter, EFUSE_TEST+3, (tempval | 0x80));
653
654 /* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */
655 }
656 } else {
657 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
658
659 if (bWrite) {
660 /* Disable LDO 2.5V after read/write action */
661 tempval = rtw_read8(padapter, EFUSE_TEST+3);
662 rtw_write8(padapter, EFUSE_TEST+3, (tempval & 0x7F));
663 }
664
665 }
666 }
667
hal_ReadEFuse_WiFi(struct adapter * padapter,u16 _offset,u16 _size_byte,u8 * pbuf,bool bPseudoTest)668 static void hal_ReadEFuse_WiFi(
669 struct adapter *padapter,
670 u16 _offset,
671 u16 _size_byte,
672 u8 *pbuf,
673 bool bPseudoTest
674 )
675 {
676 #ifdef HAL_EFUSE_MEMORY
677 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
678 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
679 #endif
680 u8 *efuseTbl = NULL;
681 u16 eFuse_Addr = 0;
682 u8 offset, wden;
683 u8 efuseHeader, efuseExtHdr, efuseData;
684 u16 i, total, used;
685 u8 efuse_usage = 0;
686
687 /* */
688 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
689 /* */
690 if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN)
691 return;
692
693 efuseTbl = rtw_malloc(EFUSE_MAX_MAP_LEN);
694 if (!efuseTbl)
695 return;
696
697 /* 0xff will be efuse default value instead of 0x00. */
698 memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
699
700 /* switch bank back to bank 0 for later BT and wifi use. */
701 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
702
703 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
704 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
705 if (efuseHeader == 0xFF)
706 break;
707
708 /* Check PG header for section num. */
709 if (EXT_HEADER(efuseHeader)) { /* extended header */
710 offset = GET_HDR_OFFSET_2_0(efuseHeader);
711
712 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
713 if (ALL_WORDS_DISABLED(efuseExtHdr))
714 continue;
715
716 offset |= ((efuseExtHdr & 0xF0) >> 1);
717 wden = (efuseExtHdr & 0x0F);
718 } else {
719 offset = ((efuseHeader >> 4) & 0x0f);
720 wden = (efuseHeader & 0x0f);
721 }
722
723 if (offset < EFUSE_MAX_SECTION_8723B) {
724 u16 addr;
725 /* Get word enable value from PG header */
726
727 addr = offset * PGPKT_DATA_SIZE;
728 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
729 /* Check word enable condition in the section */
730 if (!(wden & (0x01<<i))) {
731 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
732 efuseTbl[addr] = efuseData;
733
734 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
735 efuseTbl[addr+1] = efuseData;
736 }
737 addr += 2;
738 }
739 } else {
740 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
741 }
742 }
743
744 /* Copy from Efuse map to output pointer memory!!! */
745 for (i = 0; i < _size_byte; i++)
746 pbuf[i] = efuseTbl[_offset+i];
747
748 /* Calculate Efuse utilization */
749 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
750 used = eFuse_Addr - 1;
751 efuse_usage = (u8)((used*100)/total);
752 if (bPseudoTest) {
753 #ifdef HAL_EFUSE_MEMORY
754 pEfuseHal->fakeEfuseUsedBytes = used;
755 #else
756 fakeEfuseUsedBytes = used;
757 #endif
758 } else {
759 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
760 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
761 }
762
763 kfree(efuseTbl);
764 }
765
hal_ReadEFuse_BT(struct adapter * padapter,u16 _offset,u16 _size_byte,u8 * pbuf,bool bPseudoTest)766 static void hal_ReadEFuse_BT(
767 struct adapter *padapter,
768 u16 _offset,
769 u16 _size_byte,
770 u8 *pbuf,
771 bool bPseudoTest
772 )
773 {
774 #ifdef HAL_EFUSE_MEMORY
775 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
776 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
777 #endif
778 u8 *efuseTbl;
779 u8 bank;
780 u16 eFuse_Addr;
781 u8 efuseHeader, efuseExtHdr, efuseData;
782 u8 offset, wden;
783 u16 i, total, used;
784 u8 efuse_usage;
785
786
787 /* */
788 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
789 /* */
790 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN)
791 return;
792
793 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
794 if (!efuseTbl)
795 return;
796
797 /* 0xff will be efuse default value instead of 0x00. */
798 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
799
800 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
801
802 for (bank = 1; bank < 3; bank++) { /* 8723b Max bake 0~2 */
803 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false)
804 goto exit;
805
806 eFuse_Addr = 0;
807
808 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
809 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
810 if (efuseHeader == 0xFF)
811 break;
812
813 /* Check PG header for section num. */
814 if (EXT_HEADER(efuseHeader)) { /* extended header */
815 offset = GET_HDR_OFFSET_2_0(efuseHeader);
816
817 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
818 if (ALL_WORDS_DISABLED(efuseExtHdr))
819 continue;
820
821
822 offset |= ((efuseExtHdr & 0xF0) >> 1);
823 wden = (efuseExtHdr & 0x0F);
824 } else {
825 offset = ((efuseHeader >> 4) & 0x0f);
826 wden = (efuseHeader & 0x0f);
827 }
828
829 if (offset < EFUSE_BT_MAX_SECTION) {
830 u16 addr = offset * PGPKT_DATA_SIZE;
831
832 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
833 /* Check word enable condition in the section */
834 if (!(wden & (0x01<<i))) {
835 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
836 efuseTbl[addr] = efuseData;
837
838 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
839 efuseTbl[addr+1] = efuseData;
840 }
841 addr += 2;
842 }
843 } else {
844 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2;
845 }
846 }
847
848 if ((eFuse_Addr - 1) < total)
849 break;
850
851 }
852
853 /* switch bank back to bank 0 for later BT and wifi use. */
854 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
855
856 /* Copy from Efuse map to output pointer memory!!! */
857 for (i = 0; i < _size_byte; i++)
858 pbuf[i] = efuseTbl[_offset+i];
859
860 /* */
861 /* Calculate Efuse utilization. */
862 /* */
863 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
864 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1;
865 efuse_usage = (u8)((used*100)/total);
866 if (bPseudoTest) {
867 #ifdef HAL_EFUSE_MEMORY
868 pEfuseHal->fakeBTEfuseUsedBytes = used;
869 #else
870 fakeBTEfuseUsedBytes = used;
871 #endif
872 } else {
873 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
874 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
875 }
876
877 exit:
878 kfree(efuseTbl);
879 }
880
Hal_ReadEFuse(struct adapter * padapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,bool bPseudoTest)881 void Hal_ReadEFuse(
882 struct adapter *padapter,
883 u8 efuseType,
884 u16 _offset,
885 u16 _size_byte,
886 u8 *pbuf,
887 bool bPseudoTest
888 )
889 {
890 if (efuseType == EFUSE_WIFI)
891 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
892 else
893 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
894 }
895
hal_EfuseGetCurrentSize_WiFi(struct adapter * padapter,bool bPseudoTest)896 static u16 hal_EfuseGetCurrentSize_WiFi(
897 struct adapter *padapter, bool bPseudoTest
898 )
899 {
900 #ifdef HAL_EFUSE_MEMORY
901 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
902 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
903 #endif
904 u16 efuse_addr = 0;
905 u16 start_addr = 0; /* for debug */
906 u8 hworden = 0;
907 u8 efuse_data, word_cnts = 0;
908 u32 count = 0; /* for debug */
909
910
911 if (bPseudoTest) {
912 #ifdef HAL_EFUSE_MEMORY
913 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
914 #else
915 efuse_addr = (u16)fakeEfuseUsedBytes;
916 #endif
917 } else
918 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
919
920 start_addr = efuse_addr;
921
922 /* switch bank back to bank 0 for later BT and wifi use. */
923 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
924
925 count = 0;
926 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
927 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false)
928 goto error;
929
930 if (efuse_data == 0xFF)
931 break;
932
933 if ((start_addr != 0) && (efuse_addr == start_addr)) {
934 count++;
935
936 efuse_data = 0xFF;
937 if (count < 4) {
938 /* try again! */
939
940 if (count > 2) {
941 /* try again form address 0 */
942 efuse_addr = 0;
943 start_addr = 0;
944 }
945
946 continue;
947 }
948
949 goto error;
950 }
951
952 if (EXT_HEADER(efuse_data)) {
953 efuse_addr++;
954 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
955 if (ALL_WORDS_DISABLED(efuse_data))
956 continue;
957
958 hworden = efuse_data & 0x0F;
959 } else {
960 hworden = efuse_data & 0x0F;
961 }
962
963 word_cnts = Efuse_CalculateWordCnts(hworden);
964 efuse_addr += (word_cnts*2)+1;
965 }
966
967 if (bPseudoTest) {
968 #ifdef HAL_EFUSE_MEMORY
969 pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
970 #else
971 fakeEfuseUsedBytes = efuse_addr;
972 #endif
973 } else
974 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
975
976 goto exit;
977
978 error:
979 /* report max size to prevent write efuse */
980 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
981
982 exit:
983
984 return efuse_addr;
985 }
986
hal_EfuseGetCurrentSize_BT(struct adapter * padapter,u8 bPseudoTest)987 static u16 hal_EfuseGetCurrentSize_BT(struct adapter *padapter, u8 bPseudoTest)
988 {
989 #ifdef HAL_EFUSE_MEMORY
990 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
991 struct efuse_hal *pEfuseHal = &pHalData->EfuseHal;
992 #endif
993 u16 btusedbytes;
994 u16 efuse_addr;
995 u8 bank, startBank;
996 u8 hworden = 0;
997 u8 efuse_data, word_cnts = 0;
998 u16 retU2 = 0;
999
1000 if (bPseudoTest) {
1001 #ifdef HAL_EFUSE_MEMORY
1002 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
1003 #else
1004 btusedbytes = fakeBTEfuseUsedBytes;
1005 #endif
1006 } else
1007 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
1008
1009 efuse_addr = (u16)((btusedbytes%EFUSE_BT_REAL_BANK_CONTENT_LEN));
1010 startBank = (u8)(1+(btusedbytes/EFUSE_BT_REAL_BANK_CONTENT_LEN));
1011
1012 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
1013
1014 for (bank = startBank; bank < 3; bank++) {
1015 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false)
1016 /* bank = EFUSE_MAX_BANK; */
1017 break;
1018
1019 /* only when bank is switched we have to reset the efuse_addr. */
1020 if (bank != startBank)
1021 efuse_addr = 0;
1022
1023 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1024 if (efuse_OneByteRead(padapter, efuse_addr,
1025 &efuse_data, bPseudoTest) == false)
1026 /* bank = EFUSE_MAX_BANK; */
1027 break;
1028
1029 if (efuse_data == 0xFF)
1030 break;
1031
1032 if (EXT_HEADER(efuse_data)) {
1033 efuse_addr++;
1034 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1035
1036 if (ALL_WORDS_DISABLED(efuse_data)) {
1037 efuse_addr++;
1038 continue;
1039 }
1040
1041 hworden = efuse_data & 0x0F;
1042 } else {
1043 hworden = efuse_data & 0x0F;
1044 }
1045
1046 word_cnts = Efuse_CalculateWordCnts(hworden);
1047 /* read next header */
1048 efuse_addr += (word_cnts*2)+1;
1049 }
1050
1051 /* Check if we need to check next bank efuse */
1052 if (efuse_addr < retU2)
1053 break; /* don't need to check next bank. */
1054 }
1055
1056 retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr;
1057 if (bPseudoTest) {
1058 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
1059 } else {
1060 pEfuseHal->BTEfuseUsedBytes = retU2;
1061 }
1062
1063 return retU2;
1064 }
1065
Hal_EfuseGetCurrentSize(struct adapter * padapter,u8 efuseType,bool bPseudoTest)1066 u16 Hal_EfuseGetCurrentSize(
1067 struct adapter *padapter, u8 efuseType, bool bPseudoTest
1068 )
1069 {
1070 u16 ret = 0;
1071
1072 if (efuseType == EFUSE_WIFI)
1073 ret = hal_EfuseGetCurrentSize_WiFi(padapter, bPseudoTest);
1074 else
1075 ret = hal_EfuseGetCurrentSize_BT(padapter, bPseudoTest);
1076
1077 return ret;
1078 }
1079
ReadChipVersion8723B(struct adapter * padapter)1080 static struct hal_version ReadChipVersion8723B(struct adapter *padapter)
1081 {
1082 u32 value32;
1083 struct hal_version ChipVersion;
1084 struct hal_com_data *pHalData;
1085
1086 /* YJ, TODO, move read chip type here */
1087 pHalData = GET_HAL_DATA(padapter);
1088
1089 value32 = rtw_read32(padapter, REG_SYS_CFG);
1090 ChipVersion.ICType = CHIP_8723B;
1091 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
1092 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
1093 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
1094
1095 /* For regulator mode. by tynli. 2011.01.14 */
1096 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
1097
1098 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
1099 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */
1100
1101 /* For multi-function consideration. Added by Roger, 2010.10.06. */
1102 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
1103 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
1104 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
1105 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
1106 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
1107 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
1108
1109 dump_chip_info(ChipVersion);
1110
1111 pHalData->VersionID = ChipVersion;
1112
1113 return ChipVersion;
1114 }
1115
rtl8723b_read_chip_version(struct adapter * padapter)1116 void rtl8723b_read_chip_version(struct adapter *padapter)
1117 {
1118 ReadChipVersion8723B(padapter);
1119 }
1120
rtl8723b_InitBeaconParameters(struct adapter * padapter)1121 void rtl8723b_InitBeaconParameters(struct adapter *padapter)
1122 {
1123 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1124 u16 val16;
1125 u8 val8 = DIS_TSF_UDT;
1126
1127
1128 val16 = val8 | (val8 << 8); /* port0 and port1 */
1129
1130 /* Enable prot0 beacon function for PSTDMA */
1131 val16 |= EN_BCN_FUNCTION;
1132
1133 rtw_write16(padapter, REG_BCN_CTRL, val16);
1134
1135 /* TODO: Remove these magic number */
1136 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
1137 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
1138 /* so don't set this register on STA mode. */
1139 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
1140 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723B); /* 5ms */
1141 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B); /* 2ms */
1142
1143 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
1144 /* because test chip does not contension before sending beacon. by tynli. 2009.11.03 */
1145 rtw_write16(padapter, REG_BCNTCFG, 0x660F);
1146
1147 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
1148 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE);
1149 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
1150 pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2);
1151 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
1152 }
1153
_InitBurstPktLen_8723BS(struct adapter * Adapter)1154 void _InitBurstPktLen_8723BS(struct adapter *Adapter)
1155 {
1156 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1157
1158 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7)); /* enable single pkt ampdu */
1159 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8723B, 0x18); /* for VHT packet length 11K */
1160 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8723B, 0x1F);
1161 rtw_write8(Adapter, REG_PIFS_8723B, 0x00);
1162 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7)));
1163 if (pHalData->AMPDUBurstMode)
1164 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8723B, 0x5F);
1165 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8723B, 0x70);
1166
1167 /* ARFB table 9 for 11ac 5G 2SS */
1168 rtw_write32(Adapter, REG_ARFR0_8723B, 0x00000010);
1169 if (IS_NORMAL_CHIP(pHalData->VersionID))
1170 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0xfffff000);
1171 else
1172 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0x3e0ff000);
1173
1174 /* ARFB table 10 for 11ac 5G 1SS */
1175 rtw_write32(Adapter, REG_ARFR1_8723B, 0x00000010);
1176 rtw_write32(Adapter, REG_ARFR1_8723B+4, 0x003ff000);
1177 }
1178
ResumeTxBeacon(struct adapter * padapter)1179 static void ResumeTxBeacon(struct adapter *padapter)
1180 {
1181 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1182
1183 pHalData->RegFwHwTxQCtrl |= BIT(6);
1184 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
1185 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
1186 pHalData->RegReg542 |= BIT(0);
1187 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
1188 }
1189
StopTxBeacon(struct adapter * padapter)1190 static void StopTxBeacon(struct adapter *padapter)
1191 {
1192 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1193
1194 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
1195 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
1196 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
1197 pHalData->RegReg542 &= ~BIT(0);
1198 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
1199 }
1200
_BeaconFunctionEnable(struct adapter * padapter,u8 Enable,u8 Linked)1201 static void _BeaconFunctionEnable(struct adapter *padapter, u8 Enable, u8 Linked)
1202 {
1203 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
1204 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F);
1205 }
1206
rtl8723b_SetBeaconRelatedRegisters(struct adapter * padapter)1207 void rtl8723b_SetBeaconRelatedRegisters(struct adapter *padapter)
1208 {
1209 u8 val8;
1210 u32 value32;
1211 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1212 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1213 u32 bcn_ctrl_reg;
1214
1215 /* reset TSF, enable update TSF, correcting TSF On Beacon */
1216
1217 /* REG_BCN_INTERVAL */
1218 /* REG_BCNDMATIM */
1219 /* REG_ATIMWND */
1220 /* REG_TBTT_PROHIBIT */
1221 /* REG_DRVERLYINT */
1222 /* REG_BCN_MAX_ERR */
1223 /* REG_BCNTCFG (0x510) */
1224 /* REG_DUAL_TSF_RST */
1225 /* REG_BCN_CTRL (0x550) */
1226
1227
1228 bcn_ctrl_reg = REG_BCN_CTRL;
1229
1230 /* */
1231 /* ATIM window */
1232 /* */
1233 rtw_write16(padapter, REG_ATIMWND, 2);
1234
1235 /* */
1236 /* Beacon interval (in unit of TU). */
1237 /* */
1238 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
1239
1240 rtl8723b_InitBeaconParameters(padapter);
1241
1242 rtw_write8(padapter, REG_SLOT, 0x09);
1243
1244 /* */
1245 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
1246 /* */
1247 value32 = rtw_read32(padapter, REG_TCR);
1248 value32 &= ~TSFRST;
1249 rtw_write32(padapter, REG_TCR, value32);
1250
1251 value32 |= TSFRST;
1252 rtw_write32(padapter, REG_TCR, value32);
1253
1254 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
1255 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == true) {
1256 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
1257 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
1258 }
1259
1260 _BeaconFunctionEnable(padapter, true, true);
1261
1262 ResumeTxBeacon(padapter);
1263 val8 = rtw_read8(padapter, bcn_ctrl_reg);
1264 val8 |= DIS_BCNQ_SUB;
1265 rtw_write8(padapter, bcn_ctrl_reg, val8);
1266 }
1267
hal_notch_filter_8723b(struct adapter * adapter,bool enable)1268 void hal_notch_filter_8723b(struct adapter *adapter, bool enable)
1269 {
1270 if (enable)
1271 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
1272 else
1273 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
1274 }
1275
UpdateHalRAMask8723B(struct adapter * padapter,u32 mac_id,u8 rssi_level)1276 void UpdateHalRAMask8723B(struct adapter *padapter, u32 mac_id, u8 rssi_level)
1277 {
1278 u32 mask, rate_bitmap;
1279 u8 shortGIrate = false;
1280 struct sta_info *psta;
1281 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1282 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1283 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1284 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1285
1286 if (mac_id >= NUM_STA) /* CAM_SIZE */
1287 return;
1288
1289 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1290 if (!psta)
1291 return;
1292
1293 shortGIrate = query_ra_short_GI(psta);
1294
1295 mask = psta->ra_mask;
1296
1297 rate_bitmap = 0xffffffff;
1298 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level);
1299
1300 mask &= rate_bitmap;
1301
1302 rate_bitmap = hal_btcoex_GetRaMask(padapter);
1303 mask &= ~rate_bitmap;
1304
1305 if (pHalData->fw_ractrl) {
1306 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask);
1307 }
1308
1309 /* set correct initial date rate for each mac_id */
1310 pdmpriv->INIDATA_RATE[mac_id] = psta->init_rate;
1311 }
1312
rtl8723b_InitAntenna_Selection(struct adapter * padapter)1313 void rtl8723b_InitAntenna_Selection(struct adapter *padapter)
1314 {
1315 u8 val;
1316
1317 val = rtw_read8(padapter, REG_LEDCFG2);
1318 /* Let 8051 take control antenna setting */
1319 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1320 rtw_write8(padapter, REG_LEDCFG2, val);
1321 }
1322
rtl8723b_init_default_value(struct adapter * padapter)1323 void rtl8723b_init_default_value(struct adapter *padapter)
1324 {
1325 struct hal_com_data *pHalData;
1326 struct dm_priv *pdmpriv;
1327 u8 i;
1328
1329
1330 pHalData = GET_HAL_DATA(padapter);
1331 pdmpriv = &pHalData->dmpriv;
1332
1333 padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
1334
1335 /* init default value */
1336 pHalData->fw_ractrl = false;
1337 pHalData->bIQKInitialized = false;
1338 if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
1339 pHalData->LastHMEBoxNum = 0;
1340
1341 pHalData->bIQKInitialized = false;
1342
1343 /* init dm default value */
1344 pdmpriv->TM_Trigger = 0;/* for IQK */
1345 /* pdmpriv->binitialized = false; */
1346 /* pdmpriv->prv_traffic_idx = 3; */
1347 /* pdmpriv->initialize = 0; */
1348
1349 pdmpriv->ThermalValue_HP_index = 0;
1350 for (i = 0; i < HP_THERMAL_NUM; i++)
1351 pdmpriv->ThermalValue_HP[i] = 0;
1352
1353 /* init Efuse variables */
1354 pHalData->EfuseUsedBytes = 0;
1355 pHalData->EfuseUsedPercentage = 0;
1356 #ifdef HAL_EFUSE_MEMORY
1357 pHalData->EfuseHal.fakeEfuseBank = 0;
1358 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
1359 memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
1360 memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
1361 memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
1362 pHalData->EfuseHal.BTEfuseUsedBytes = 0;
1363 pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
1364 memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
1365 memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1366 memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1367 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
1368 memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE);
1369 memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1370 memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
1371 #endif
1372 }
1373
GetEEPROMSize8723B(struct adapter * padapter)1374 u8 GetEEPROMSize8723B(struct adapter *padapter)
1375 {
1376 u8 size = 0;
1377 u32 cr;
1378
1379 cr = rtw_read16(padapter, REG_9346CR);
1380 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1381 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1382
1383 return size;
1384 }
1385
1386 /* */
1387 /* */
1388 /* LLT R/W/Init function */
1389 /* */
1390 /* */
rtl8723b_InitLLTTable(struct adapter * padapter)1391 s32 rtl8723b_InitLLTTable(struct adapter *padapter)
1392 {
1393 unsigned long start, passing_time;
1394 u32 val32;
1395 s32 ret = _FAIL;
1396
1397 val32 = rtw_read32(padapter, REG_AUTO_LLT);
1398 val32 |= BIT_AUTO_INIT_LLT;
1399 rtw_write32(padapter, REG_AUTO_LLT, val32);
1400
1401 start = jiffies;
1402
1403 do {
1404 val32 = rtw_read32(padapter, REG_AUTO_LLT);
1405 if (!(val32 & BIT_AUTO_INIT_LLT)) {
1406 ret = _SUCCESS;
1407 break;
1408 }
1409
1410 passing_time = jiffies_to_msecs(jiffies - start);
1411 if (passing_time > 1000)
1412 break;
1413
1414 msleep(1);
1415 } while (1);
1416
1417 return ret;
1418 }
1419
hal_get_chnl_group_8723b(u8 channel,u8 * group)1420 static void hal_get_chnl_group_8723b(u8 channel, u8 *group)
1421 {
1422 if (1 <= channel && channel <= 2)
1423 *group = 0;
1424 else if (3 <= channel && channel <= 5)
1425 *group = 1;
1426 else if (6 <= channel && channel <= 8)
1427 *group = 2;
1428 else if (9 <= channel && channel <= 11)
1429 *group = 3;
1430 else if (12 <= channel && channel <= 14)
1431 *group = 4;
1432 }
1433
Hal_InitPGData(struct adapter * padapter,u8 * PROMContent)1434 void Hal_InitPGData(struct adapter *padapter, u8 *PROMContent)
1435 {
1436 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1437
1438 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1439 if (!pEEPROM->EepromOrEfuse) {
1440 /* Read EFUSE real map to shadow. */
1441 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1442 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
1443 }
1444 } else {/* autoload fail */
1445 if (!pEEPROM->EepromOrEfuse)
1446 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false);
1447 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B);
1448 }
1449 }
1450
Hal_EfuseParseIDCode(struct adapter * padapter,u8 * hwinfo)1451 void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo)
1452 {
1453 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1454 /* struct hal_com_data *pHalData = GET_HAL_DATA(padapter); */
1455 u16 EEPROMId;
1456
1457
1458 /* Check 0x8129 again for making sure autoload status!! */
1459 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
1460 if (EEPROMId != RTL_EEPROM_ID) {
1461 pEEPROM->bautoload_fail_flag = true;
1462 } else
1463 pEEPROM->bautoload_fail_flag = false;
1464 }
1465
Hal_ReadPowerValueFromPROM_8723B(struct adapter * Adapter,struct TxPowerInfo24G * pwrInfo24G,u8 * PROMContent,bool AutoLoadFail)1466 static void Hal_ReadPowerValueFromPROM_8723B(
1467 struct adapter *Adapter,
1468 struct TxPowerInfo24G *pwrInfo24G,
1469 u8 *PROMContent,
1470 bool AutoLoadFail
1471 )
1472 {
1473 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1474 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_8723B, group, TxCount = 0;
1475
1476 memset(pwrInfo24G, 0, sizeof(struct TxPowerInfo24G));
1477
1478 if (0xFF == PROMContent[eeAddr+1])
1479 AutoLoadFail = true;
1480
1481 if (AutoLoadFail) {
1482 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
1483 /* 2.4G default value */
1484 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1485 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1486 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1487 }
1488
1489 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1490 if (TxCount == 0) {
1491 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
1492 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
1493 } else {
1494 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1495 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1496 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1497 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1498 }
1499 }
1500 }
1501
1502 return;
1503 }
1504
1505 pHalData->bTXPowerDataReadFromEEPORM = true; /* YJ, move, 120316 */
1506
1507 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
1508 /* 2 2.4G default value */
1509 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1510 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
1511 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
1512 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1513 }
1514
1515 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
1516 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
1517 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
1518 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
1519 }
1520
1521 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1522 if (TxCount == 0) {
1523 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
1524 if (PROMContent[eeAddr] == 0xFF)
1525 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
1526 else {
1527 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
1528 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1529 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
1530 }
1531
1532 if (PROMContent[eeAddr] == 0xFF)
1533 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
1534 else {
1535 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
1536 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1537 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
1538 }
1539 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
1540 eeAddr++;
1541 } else {
1542 if (PROMContent[eeAddr] == 0xFF)
1543 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1544 else {
1545 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
1546 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1547 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
1548 }
1549
1550 if (PROMContent[eeAddr] == 0xFF)
1551 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1552 else {
1553 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
1554 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1555 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
1556 }
1557 eeAddr++;
1558
1559 if (PROMContent[eeAddr] == 0xFF)
1560 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1561 else {
1562 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
1563 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1564 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
1565 }
1566
1567 if (PROMContent[eeAddr] == 0xFF)
1568 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
1569 else {
1570 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
1571 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
1572 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
1573 }
1574 eeAddr++;
1575 }
1576 }
1577 }
1578 }
1579
1580
Hal_EfuseParseTxPowerInfo_8723B(struct adapter * padapter,u8 * PROMContent,bool AutoLoadFail)1581 void Hal_EfuseParseTxPowerInfo_8723B(
1582 struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail
1583 )
1584 {
1585 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1586 struct TxPowerInfo24G pwrInfo24G;
1587 u8 rfPath, ch, TxCount = 1;
1588
1589 Hal_ReadPowerValueFromPROM_8723B(padapter, &pwrInfo24G, PROMContent, AutoLoadFail);
1590 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1591 for (ch = 0 ; ch < CHANNEL_MAX_NUMBER; ch++) {
1592 u8 group = 0;
1593
1594 hal_get_chnl_group_8723b(ch + 1, &group);
1595
1596 if (ch == 14-1) {
1597 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5];
1598 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
1599 } else {
1600 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];
1601 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group];
1602 }
1603 }
1604
1605 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1606 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount];
1607 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount];
1608 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount];
1609 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount];
1610 }
1611 }
1612
1613 /* 2010/10/19 MH Add Regulator recognize for CU. */
1614 if (!AutoLoadFail) {
1615 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723B]&0x7); /* bit0~2 */
1616 if (PROMContent[EEPROM_RF_BOARD_OPTION_8723B] == 0xFF)
1617 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
1618 } else
1619 pHalData->EEPROMRegulatory = 0;
1620 }
1621
Hal_EfuseParseBTCoexistInfo_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1622 void Hal_EfuseParseBTCoexistInfo_8723B(
1623 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1624 )
1625 {
1626 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1627 u8 tempval;
1628 u32 tmpu4;
1629
1630 if (!AutoLoadFail) {
1631 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
1632 if (tmpu4 & BT_FUNC_EN)
1633 pHalData->EEPROMBluetoothCoexist = true;
1634 else
1635 pHalData->EEPROMBluetoothCoexist = false;
1636
1637 pHalData->EEPROMBluetoothType = BT_RTL8723B;
1638
1639 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B];
1640 if (tempval != 0xFF) {
1641 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
1642 /* EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A; */
1643 /* EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B */
1644 if (tempval & BIT(6))
1645 pHalData->ant_path = RF_PATH_B;
1646 else
1647 pHalData->ant_path = RF_PATH_A;
1648 } else {
1649 pHalData->EEPROMBluetoothAntNum = Ant_x1;
1650 if (pHalData->PackageType == PACKAGE_QFN68)
1651 pHalData->ant_path = RF_PATH_B;
1652 else
1653 pHalData->ant_path = RF_PATH_A;
1654 }
1655 } else {
1656 pHalData->EEPROMBluetoothCoexist = false;
1657 pHalData->EEPROMBluetoothType = BT_RTL8723B;
1658 pHalData->EEPROMBluetoothAntNum = Ant_x1;
1659 pHalData->ant_path = RF_PATH_A;
1660 }
1661
1662 if (padapter->registrypriv.ant_num > 0) {
1663 switch (padapter->registrypriv.ant_num) {
1664 case 1:
1665 pHalData->EEPROMBluetoothAntNum = Ant_x1;
1666 break;
1667 case 2:
1668 pHalData->EEPROMBluetoothAntNum = Ant_x2;
1669 break;
1670 default:
1671 break;
1672 }
1673 }
1674
1675 hal_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist);
1676 hal_btcoex_SetPgAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
1677 if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
1678 hal_btcoex_SetSingleAntPath(padapter, pHalData->ant_path);
1679 }
1680
Hal_EfuseParseEEPROMVer_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1681 void Hal_EfuseParseEEPROMVer_8723B(
1682 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1683 )
1684 {
1685 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1686
1687 if (!AutoLoadFail)
1688 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723B];
1689 else
1690 pHalData->EEPROMVersion = 1;
1691 }
1692
1693
1694
Hal_EfuseParsePackageType_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1695 void Hal_EfuseParsePackageType_8723B(
1696 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1697 )
1698 {
1699 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1700 u8 package;
1701 u8 efuseContent;
1702
1703 Efuse_PowerSwitch(padapter, false, true);
1704 efuse_OneByteRead(padapter, 0x1FB, &efuseContent, false);
1705 Efuse_PowerSwitch(padapter, false, false);
1706
1707 package = efuseContent & 0x7;
1708 switch (package) {
1709 case 0x4:
1710 pHalData->PackageType = PACKAGE_TFBGA79;
1711 break;
1712 case 0x5:
1713 pHalData->PackageType = PACKAGE_TFBGA90;
1714 break;
1715 case 0x6:
1716 pHalData->PackageType = PACKAGE_QFN68;
1717 break;
1718 case 0x7:
1719 pHalData->PackageType = PACKAGE_TFBGA80;
1720 break;
1721
1722 default:
1723 pHalData->PackageType = PACKAGE_DEFAULT;
1724 break;
1725 }
1726 }
1727
1728
Hal_EfuseParseVoltage_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1729 void Hal_EfuseParseVoltage_8723B(
1730 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1731 )
1732 {
1733 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1734
1735 /* memcpy(pEEPROM->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8723B], 1); */
1736 pEEPROM->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723B] & 0xf0) >> 4;
1737 }
1738
Hal_EfuseParseChnlPlan_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1739 void Hal_EfuseParseChnlPlan_8723B(
1740 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1741 )
1742 {
1743 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan(
1744 padapter,
1745 hwinfo ? hwinfo[EEPROM_ChannelPlan_8723B] : 0xFF,
1746 padapter->registrypriv.channel_plan,
1747 RT_CHANNEL_DOMAIN_WORLD_NULL,
1748 AutoLoadFail
1749 );
1750
1751 Hal_ChannelPlanToRegulation(padapter, padapter->mlmepriv.ChannelPlan);
1752 }
1753
Hal_EfuseParseCustomerID_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1754 void Hal_EfuseParseCustomerID_8723B(
1755 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1756 )
1757 {
1758 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1759
1760 if (!AutoLoadFail)
1761 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723B];
1762 else
1763 pHalData->EEPROMCustomerID = 0;
1764 }
1765
Hal_EfuseParseAntennaDiversity_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1766 void Hal_EfuseParseAntennaDiversity_8723B(
1767 struct adapter *padapter,
1768 u8 *hwinfo,
1769 bool AutoLoadFail
1770 )
1771 {
1772 }
1773
Hal_EfuseParseXtal_8723B(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1774 void Hal_EfuseParseXtal_8723B(
1775 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1776 )
1777 {
1778 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1779
1780 if (!AutoLoadFail) {
1781 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8723B];
1782 if (pHalData->CrystalCap == 0xFF)
1783 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B; /* what value should 8812 set? */
1784 } else
1785 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B;
1786 }
1787
1788
Hal_EfuseParseThermalMeter_8723B(struct adapter * padapter,u8 * PROMContent,u8 AutoLoadFail)1789 void Hal_EfuseParseThermalMeter_8723B(
1790 struct adapter *padapter, u8 *PROMContent, u8 AutoLoadFail
1791 )
1792 {
1793 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1794
1795 /* */
1796 /* ThermalMeter from EEPROM */
1797 /* */
1798 if (!AutoLoadFail)
1799 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8723B];
1800 else
1801 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
1802
1803 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoLoadFail) {
1804 pHalData->bAPKThermalMeterIgnore = true;
1805 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B;
1806 }
1807 }
1808
1809
Hal_ReadRFGainOffset(struct adapter * Adapter,u8 * PROMContent,bool AutoloadFail)1810 void Hal_ReadRFGainOffset(
1811 struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail
1812 )
1813 {
1814 /* */
1815 /* BB_RF Gain Offset from EEPROM */
1816 /* */
1817
1818 if (!AutoloadFail) {
1819 Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET];
1820 Adapter->eeprompriv.EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL);
1821 } else {
1822 Adapter->eeprompriv.EEPROMRFGainOffset = 0;
1823 Adapter->eeprompriv.EEPROMRFGainVal = 0xFF;
1824 }
1825 }
1826
BWMapping_8723B(struct adapter * Adapter,struct pkt_attrib * pattrib)1827 u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
1828 {
1829 u8 BWSettingOfDesc = 0;
1830 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1831
1832 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
1833 if (pattrib->bwmode == CHANNEL_WIDTH_40)
1834 BWSettingOfDesc = 1;
1835 else
1836 BWSettingOfDesc = 0;
1837 } else
1838 BWSettingOfDesc = 0;
1839
1840 /* if (pTcb->bBTTxPacket) */
1841 /* BWSettingOfDesc = 0; */
1842
1843 return BWSettingOfDesc;
1844 }
1845
SCMapping_8723B(struct adapter * Adapter,struct pkt_attrib * pattrib)1846 u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib)
1847 {
1848 u8 SCSettingOfDesc = 0;
1849 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1850
1851 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
1852 if (pattrib->bwmode == CHANNEL_WIDTH_40) {
1853 SCSettingOfDesc = HT_DATA_SC_DONOT_CARE;
1854 } else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
1855 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) {
1856 SCSettingOfDesc = HT_DATA_SC_20_UPPER_OF_40MHZ;
1857 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) {
1858 SCSettingOfDesc = HT_DATA_SC_20_LOWER_OF_40MHZ;
1859 } else {
1860 SCSettingOfDesc = HT_DATA_SC_DONOT_CARE;
1861 }
1862 }
1863 } else {
1864 SCSettingOfDesc = HT_DATA_SC_DONOT_CARE;
1865 }
1866
1867 return SCSettingOfDesc;
1868 }
1869
rtl8723b_cal_txdesc_chksum(struct tx_desc * ptxdesc)1870 static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc)
1871 {
1872 u16 *usPtr = (u16 *)ptxdesc;
1873 u32 count;
1874 u32 index;
1875 u16 checksum = 0;
1876
1877
1878 /* Clear first */
1879 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
1880
1881 /* checksum is always calculated by first 32 bytes, */
1882 /* and it doesn't depend on TX DESC length. */
1883 /* Thomas, Lucas@SD4, 20130515 */
1884 count = 16;
1885
1886 for (index = 0; index < count; index++) {
1887 checksum |= le16_to_cpu(*(__le16 *)(usPtr + index));
1888 }
1889
1890 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
1891 }
1892
fill_txdesc_sectype(struct pkt_attrib * pattrib)1893 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
1894 {
1895 u8 sectype = 0;
1896 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
1897 switch (pattrib->encrypt) {
1898 /* SEC_TYPE */
1899 case _WEP40_:
1900 case _WEP104_:
1901 case _TKIP_:
1902 case _TKIP_WTMIC_:
1903 sectype = 1;
1904 break;
1905
1906 case _AES_:
1907 sectype = 3;
1908 break;
1909
1910 case _NO_PRIVACY_:
1911 default:
1912 break;
1913 }
1914 }
1915 return sectype;
1916 }
1917
fill_txdesc_vcs_8723b(struct adapter * padapter,struct pkt_attrib * pattrib,struct txdesc_8723b * ptxdesc)1918 static void fill_txdesc_vcs_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, struct txdesc_8723b *ptxdesc)
1919 {
1920 if (pattrib->vcs_mode) {
1921 switch (pattrib->vcs_mode) {
1922 case RTS_CTS:
1923 ptxdesc->rtsen = 1;
1924 /* ENABLE HW RTS */
1925 ptxdesc->hw_rts_en = 1;
1926 break;
1927
1928 case CTS_TO_SELF:
1929 ptxdesc->cts2self = 1;
1930 break;
1931
1932 case NONE_VCS:
1933 default:
1934 break;
1935 }
1936
1937 ptxdesc->rtsrate = 8; /* RTS Rate =24M */
1938 ptxdesc->rts_ratefb_lmt = 0xF;
1939
1940 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
1941 ptxdesc->rts_short = 1;
1942
1943 /* Set RTS BW */
1944 if (pattrib->ht_en)
1945 ptxdesc->rts_sc = SCMapping_8723B(padapter, pattrib);
1946 }
1947 }
1948
fill_txdesc_phy_8723b(struct adapter * padapter,struct pkt_attrib * pattrib,struct txdesc_8723b * ptxdesc)1949 static void fill_txdesc_phy_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, struct txdesc_8723b *ptxdesc)
1950 {
1951 if (pattrib->ht_en) {
1952 ptxdesc->data_bw = BWMapping_8723B(padapter, pattrib);
1953
1954 ptxdesc->data_sc = SCMapping_8723B(padapter, pattrib);
1955 }
1956 }
1957
rtl8723b_fill_default_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)1958 static void rtl8723b_fill_default_txdesc(
1959 struct xmit_frame *pxmitframe, u8 *pbuf
1960 )
1961 {
1962 struct adapter *padapter;
1963 struct hal_com_data *pHalData;
1964 struct mlme_ext_priv *pmlmeext;
1965 struct mlme_ext_info *pmlmeinfo;
1966 struct pkt_attrib *pattrib;
1967 struct txdesc_8723b *ptxdesc;
1968 s32 bmcst;
1969
1970 memset(pbuf, 0, TXDESC_SIZE);
1971
1972 padapter = pxmitframe->padapter;
1973 pHalData = GET_HAL_DATA(padapter);
1974 pmlmeext = &padapter->mlmeextpriv;
1975 pmlmeinfo = &(pmlmeext->mlmext_info);
1976
1977 pattrib = &pxmitframe->attrib;
1978 bmcst = is_multicast_ether_addr(pattrib->ra);
1979
1980 ptxdesc = (struct txdesc_8723b *)pbuf;
1981
1982 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
1983 u8 drv_userate = 0;
1984
1985 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
1986 ptxdesc->rate_id = pattrib->raid;
1987 ptxdesc->qsel = pattrib->qsel;
1988 ptxdesc->seq = pattrib->seqnum;
1989
1990 ptxdesc->sectype = fill_txdesc_sectype(pattrib);
1991 fill_txdesc_vcs_8723b(padapter, pattrib, ptxdesc);
1992
1993 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
1994 drv_userate = 1;
1995
1996 if (
1997 (pattrib->ether_type != 0x888e) &&
1998 (pattrib->ether_type != 0x0806) &&
1999 (pattrib->ether_type != 0x88B4) &&
2000 (pattrib->dhcp_pkt != 1) &&
2001 (drv_userate != 1)
2002 ) {
2003 /* Non EAP & ARP & DHCP type data packet */
2004
2005 if (pattrib->ampdu_en) {
2006 ptxdesc->agg_en = 1; /* AGG EN */
2007 ptxdesc->max_agg_num = 0x1f;
2008 ptxdesc->ampdu_density = pattrib->ampdu_spacing;
2009 } else
2010 ptxdesc->bk = 1; /* AGG BK */
2011
2012 fill_txdesc_phy_8723b(padapter, pattrib, ptxdesc);
2013
2014 ptxdesc->data_ratefb_lmt = 0x1F;
2015
2016 if (!pHalData->fw_ractrl) {
2017 ptxdesc->userate = 1;
2018
2019 if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7))
2020 ptxdesc->data_short = 1;
2021
2022 ptxdesc->datarate = pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & 0x7F;
2023 }
2024
2025 if (padapter->fix_rate != 0xFF) { /* modify data rate by iwpriv */
2026 ptxdesc->userate = 1;
2027 if (padapter->fix_rate & BIT(7))
2028 ptxdesc->data_short = 1;
2029
2030 ptxdesc->datarate = (padapter->fix_rate & 0x7F);
2031 ptxdesc->disdatafb = 1;
2032 }
2033
2034 if (pattrib->ldpc)
2035 ptxdesc->data_ldpc = 1;
2036 if (pattrib->stbc)
2037 ptxdesc->data_stbc = 1;
2038 } else {
2039 /* EAP data packet and ARP packet. */
2040 /* Use the 1M data rate to send the EAP/ARP packet. */
2041 /* This will maybe make the handshake smooth. */
2042
2043 ptxdesc->bk = 1; /* AGG BK */
2044 ptxdesc->userate = 1; /* driver uses rate */
2045 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
2046 ptxdesc->data_short = 1;/* DATA_SHORT */
2047 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
2048 }
2049
2050 ptxdesc->usb_txagg_num = pxmitframe->agg_num;
2051 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
2052 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2053 ptxdesc->qsel = pattrib->qsel;
2054 ptxdesc->rate_id = pattrib->raid; /* Rate ID */
2055 ptxdesc->seq = pattrib->seqnum;
2056 ptxdesc->userate = 1; /* driver uses rate, 1M */
2057
2058 ptxdesc->mbssid = pattrib->mbssid & 0xF;
2059
2060 ptxdesc->rty_lmt_en = 1; /* retry limit enable */
2061 if (pattrib->retry_ctrl) {
2062 ptxdesc->data_rt_lmt = 6;
2063 } else {
2064 ptxdesc->data_rt_lmt = 12;
2065 }
2066
2067 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
2068
2069 /* CCX-TXRPT ack for xmit mgmt frames. */
2070 if (pxmitframe->ack_report) {
2071 ptxdesc->spe_rpt = 1;
2072 ptxdesc->sw_define = (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no);
2073 }
2074 } else {
2075 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2076 ptxdesc->rate_id = pattrib->raid; /* Rate ID */
2077 ptxdesc->qsel = pattrib->qsel;
2078 ptxdesc->seq = pattrib->seqnum;
2079 ptxdesc->userate = 1; /* driver uses rate */
2080 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
2081 }
2082
2083 ptxdesc->pktlen = pattrib->last_txcmdsz;
2084 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ;
2085
2086 if (bmcst)
2087 ptxdesc->bmc = 1;
2088
2089 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
2090 * (1) The sequence number of each non-Qos frame / broadcast /
2091 * multicast / mgnt frame should be controlled by Hw because Fw
2092 * will also send null data which we cannot control when Fw LPS
2093 * enable.
2094 * --> default enable non-Qos data sequence number. 2010.06.23.
2095 * by tynli.
2096 * (2) Enable HW SEQ control for beacon packet, because we use
2097 * Hw beacon.
2098 * (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos
2099 * packets.
2100 * 2010.06.23. Added by tynli.
2101 */
2102 if (!pattrib->qos_en) /* Hw set sequence number */
2103 ptxdesc->en_hwseq = 1; /* HWSEQ_EN */
2104 }
2105
2106 /* Description:
2107 *
2108 * Parameters:
2109 * pxmitframe xmitframe
2110 * pbuf where to fill tx desc
2111 */
rtl8723b_update_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)2112 void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
2113 {
2114 struct tx_desc *pdesc;
2115
2116 rtl8723b_fill_default_txdesc(pxmitframe, pbuf);
2117 pdesc = (struct tx_desc *)pbuf;
2118 rtl8723b_cal_txdesc_chksum(pdesc);
2119 }
2120
2121 /* */
2122 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
2123 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
2124 /* Fw can tell Hw to send these packet derectly. */
2125 /* Added by tynli. 2009.10.15. */
2126 /* */
2127 /* type1:pspoll, type2:null */
rtl8723b_fill_fake_txdesc(struct adapter * padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)2128 void rtl8723b_fill_fake_txdesc(
2129 struct adapter *padapter,
2130 u8 *pDesc,
2131 u32 BufferLen,
2132 u8 IsPsPoll,
2133 u8 IsBTQosNull,
2134 u8 bDataFrame
2135 )
2136 {
2137 /* Clear all status */
2138 memset(pDesc, 0, TXDESC_SIZE);
2139
2140 SET_TX_DESC_FIRST_SEG_8723B(pDesc, 1); /* bFirstSeg; */
2141 SET_TX_DESC_LAST_SEG_8723B(pDesc, 1); /* bLastSeg; */
2142
2143 SET_TX_DESC_OFFSET_8723B(pDesc, 0x28); /* Offset = 32 */
2144
2145 SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen); /* Buffer size + command header */
2146 SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
2147
2148 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error value by Hw. */
2149 if (IsPsPoll) {
2150 SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1);
2151 } else {
2152 SET_TX_DESC_HWSEQ_EN_8723B(pDesc, 1); /* Hw set sequence number */
2153 SET_TX_DESC_HWSEQ_SEL_8723B(pDesc, 0);
2154 }
2155
2156 if (IsBTQosNull) {
2157 SET_TX_DESC_BT_INT_8723B(pDesc, 1);
2158 }
2159
2160 SET_TX_DESC_USE_RATE_8723B(pDesc, 1); /* use data rate which is set by Sw */
2161 SET_TX_DESC_OWN_8723B((u8 *)pDesc, 1);
2162
2163 SET_TX_DESC_TX_RATE_8723B(pDesc, DESC8723B_RATE1M);
2164
2165 /* */
2166 /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */
2167 /* */
2168 if (bDataFrame) {
2169 u32 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
2170
2171 switch (EncAlg) {
2172 case _NO_PRIVACY_:
2173 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
2174 break;
2175 case _WEP40_:
2176 case _WEP104_:
2177 case _TKIP_:
2178 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x1);
2179 break;
2180 case _SMS4_:
2181 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x2);
2182 break;
2183 case _AES_:
2184 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x3);
2185 break;
2186 default:
2187 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0);
2188 break;
2189 }
2190 }
2191
2192 /* USB interface drop packet if the checksum of descriptor isn't correct. */
2193 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
2194 rtl8723b_cal_txdesc_chksum((struct tx_desc *)pDesc);
2195 }
2196
hw_var_set_opmode(struct adapter * padapter,u8 variable,u8 * val)2197 static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val)
2198 {
2199 u8 val8;
2200 u8 mode = *((u8 *)val);
2201
2202 {
2203 /* disable Port0 TSF update */
2204 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2205 val8 |= DIS_TSF_UDT;
2206 rtw_write8(padapter, REG_BCN_CTRL, val8);
2207
2208 /* set net_type */
2209 Set_MSR(padapter, mode);
2210
2211 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
2212 {
2213 StopTxBeacon(padapter);
2214 }
2215
2216 /* disable atim wnd */
2217 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM);
2218 /* rtw_write8(padapter, REG_BCN_CTRL, 0x18); */
2219 } else if (mode == _HW_STATE_ADHOC_) {
2220 ResumeTxBeacon(padapter);
2221 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_BCNQ_SUB);
2222 } else if (mode == _HW_STATE_AP_) {
2223
2224 ResumeTxBeacon(padapter);
2225
2226 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|DIS_BCNQ_SUB);
2227
2228 /* Set RCR */
2229 rtw_write32(padapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0, reject ICV_ERR packet */
2230 /* enable to rx data frame */
2231 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2232 /* enable to rx ps-poll */
2233 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
2234
2235 /* Beacon Control related register for first time */
2236 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
2237
2238 /* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
2239 rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */
2240 rtw_write16(padapter, REG_BCNTCFG, 0x00);
2241 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
2242 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
2243
2244 /* reset TSF */
2245 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2246
2247 /* enable BCN0 Function for if1 */
2248 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
2249 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT|EN_BCN_FUNCTION|EN_TXBCN_RPT|DIS_BCNQ_SUB));
2250
2251 /* SW_BCN_SEL - Port0 */
2252 /* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */
2253 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
2254
2255 /* select BCN on port 0 */
2256 rtw_write8(
2257 padapter,
2258 REG_CCK_CHECK_8723B,
2259 (rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL)
2260 );
2261
2262 /* dis BCN1 ATIM WND if if2 is station */
2263 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
2264 val8 |= DIS_ATIM;
2265 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
2266 }
2267 }
2268 }
2269
hw_var_set_macaddr(struct adapter * padapter,u8 variable,u8 * val)2270 static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val)
2271 {
2272 u8 idx = 0;
2273 u32 reg_macid = REG_MACID;
2274
2275 for (idx = 0 ; idx < 6; idx++)
2276 rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]);
2277 }
2278
hw_var_set_bssid(struct adapter * padapter,u8 variable,u8 * val)2279 static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val)
2280 {
2281 u8 idx = 0;
2282 u32 reg_bssid = REG_BSSID;
2283
2284 for (idx = 0 ; idx < 6; idx++)
2285 rtw_write8(padapter, (reg_bssid+idx), val[idx]);
2286 }
2287
hw_var_set_bcn_func(struct adapter * padapter,u8 variable,u8 * val)2288 static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val)
2289 {
2290 u32 bcn_ctrl_reg = REG_BCN_CTRL;
2291
2292 if (*(u8 *)val)
2293 rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
2294 else {
2295 u8 val8;
2296 val8 = rtw_read8(padapter, bcn_ctrl_reg);
2297 val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
2298
2299 /* Always enable port0 beacon function for PSTDMA */
2300 if (REG_BCN_CTRL == bcn_ctrl_reg)
2301 val8 |= EN_BCN_FUNCTION;
2302
2303 rtw_write8(padapter, bcn_ctrl_reg, val8);
2304 }
2305 }
2306
hw_var_set_correct_tsf(struct adapter * padapter,u8 variable,u8 * val)2307 static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val)
2308 {
2309 u8 val8;
2310 u64 tsf;
2311 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2312 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2313
2314 tsf = pmlmeext->TSFValue-do_div(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024))-1024; /* us */
2315
2316 if (
2317 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
2318 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
2319 )
2320 StopTxBeacon(padapter);
2321
2322 {
2323 /* disable related TSF function */
2324 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2325 val8 &= ~EN_BCN_FUNCTION;
2326 rtw_write8(padapter, REG_BCN_CTRL, val8);
2327
2328 rtw_write32(padapter, REG_TSFTR, tsf);
2329 rtw_write32(padapter, REG_TSFTR+4, tsf>>32);
2330
2331 /* enable related TSF function */
2332 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2333 val8 |= EN_BCN_FUNCTION;
2334 rtw_write8(padapter, REG_BCN_CTRL, val8);
2335 }
2336
2337 if (
2338 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ||
2339 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
2340 )
2341 ResumeTxBeacon(padapter);
2342 }
2343
hw_var_set_mlme_disconnect(struct adapter * padapter,u8 variable,u8 * val)2344 static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val)
2345 {
2346 u8 val8;
2347
2348 /* Set RCR to not to receive data frame when NO LINK state */
2349 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); */
2350 /* reject all data frames */
2351 rtw_write16(padapter, REG_RXFLTMAP2, 0);
2352
2353 /* reset TSF */
2354 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2355
2356 /* disable update TSF */
2357 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2358 val8 |= DIS_TSF_UDT;
2359 rtw_write8(padapter, REG_BCN_CTRL, val8);
2360 }
2361
hw_var_set_mlme_sitesurvey(struct adapter * padapter,u8 variable,u8 * val)2362 static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val)
2363 {
2364 u32 value_rcr, rcr_clear_bit, reg_bcn_ctl;
2365 u16 value_rxfltmap2;
2366 u8 val8;
2367 struct hal_com_data *pHalData;
2368 struct mlme_priv *pmlmepriv;
2369
2370
2371 pHalData = GET_HAL_DATA(padapter);
2372 pmlmepriv = &padapter->mlmepriv;
2373
2374 reg_bcn_ctl = REG_BCN_CTRL;
2375
2376 rcr_clear_bit = RCR_CBSSID_BCN;
2377
2378 /* config RCR to receive different BSSID & not to receive data frame */
2379 value_rxfltmap2 = 0;
2380
2381 if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == true))
2382 rcr_clear_bit = RCR_CBSSID_BCN;
2383
2384 value_rcr = rtw_read32(padapter, REG_RCR);
2385
2386 if (*((u8 *)val)) {
2387 /* under sitesurvey */
2388 value_rcr &= ~(rcr_clear_bit);
2389 rtw_write32(padapter, REG_RCR, value_rcr);
2390
2391 rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2);
2392
2393 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2394 /* disable update TSF */
2395 val8 = rtw_read8(padapter, reg_bcn_ctl);
2396 val8 |= DIS_TSF_UDT;
2397 rtw_write8(padapter, reg_bcn_ctl, val8);
2398 }
2399
2400 /* Save original RRSR setting. */
2401 pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR);
2402 } else {
2403 /* sitesurvey done */
2404 if (check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)))
2405 /* enable to rx data frame */
2406 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2407
2408 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2409 /* enable update TSF */
2410 val8 = rtw_read8(padapter, reg_bcn_ctl);
2411 val8 &= ~DIS_TSF_UDT;
2412 rtw_write8(padapter, reg_bcn_ctl, val8);
2413 }
2414
2415 value_rcr |= rcr_clear_bit;
2416 rtw_write32(padapter, REG_RCR, value_rcr);
2417
2418 /* Restore original RRSR setting. */
2419 rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR);
2420 }
2421 }
2422
hw_var_set_mlme_join(struct adapter * padapter,u8 variable,u8 * val)2423 static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val)
2424 {
2425 u8 val8;
2426 u16 val16;
2427 u32 val32;
2428 u8 RetryLimit = 0x30;
2429 u8 type = *(u8 *)val;
2430 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
2431 struct eeprom_priv *pEEPROM;
2432
2433
2434 pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2435
2436 if (type == 0) { /* prepare to join */
2437 /* enable to rx data frame.Accept all data frame */
2438 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */
2439 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2440
2441 val32 = rtw_read32(padapter, REG_RCR);
2442 if (padapter->in_cta_test)
2443 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
2444 else
2445 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
2446 rtw_write32(padapter, REG_RCR, val32);
2447
2448 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
2449 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48;
2450 else /* Ad-hoc Mode */
2451 RetryLimit = 0x7;
2452 } else if (type == 1) /* joinbss_event call back when join res < 0 */
2453 rtw_write16(padapter, REG_RXFLTMAP2, 0x00);
2454 else if (type == 2) { /* sta add event call back */
2455 /* enable update TSF */
2456 val8 = rtw_read8(padapter, REG_BCN_CTRL);
2457 val8 &= ~DIS_TSF_UDT;
2458 rtw_write8(padapter, REG_BCN_CTRL, val8);
2459
2460 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
2461 RetryLimit = 0x7;
2462 }
2463
2464 val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT);
2465 rtw_write16(padapter, REG_RL, val16);
2466 }
2467
CCX_FwC2HTxRpt_8723b(struct adapter * padapter,u8 * pdata,u8 len)2468 void CCX_FwC2HTxRpt_8723b(struct adapter *padapter, u8 *pdata, u8 len)
2469 {
2470
2471 #define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
2472 #define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
2473
2474 if (GET_8723B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) {
2475 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
2476 }
2477 /*
2478 else if (seq_no != padapter->xmitpriv.seq_no) {
2479 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
2480 }
2481 */
2482 else
2483 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
2484 }
2485
c2h_id_filter_ccx_8723b(u8 * buf)2486 s32 c2h_id_filter_ccx_8723b(u8 *buf)
2487 {
2488 struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
2489 s32 ret = false;
2490 if (c2h_evt->id == C2H_CCX_TX_RPT)
2491 ret = true;
2492
2493 return ret;
2494 }
2495
2496
c2h_handler_8723b(struct adapter * padapter,u8 * buf)2497 s32 c2h_handler_8723b(struct adapter *padapter, u8 *buf)
2498 {
2499 struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf;
2500 s32 ret = _SUCCESS;
2501
2502 if (!pC2hEvent) {
2503 ret = _FAIL;
2504 goto exit;
2505 }
2506
2507 switch (pC2hEvent->id) {
2508 case C2H_AP_RPT_RSP:
2509 break;
2510 case C2H_DBG:
2511 {
2512 }
2513 break;
2514
2515 case C2H_CCX_TX_RPT:
2516 /* CCX_FwC2HTxRpt(padapter, QueueID, pC2hEvent->payload); */
2517 break;
2518
2519 case C2H_EXT_RA_RPT:
2520 /* C2HExtRaRptHandler(padapter, pC2hEvent->payload, C2hEvent.CmdLen); */
2521 break;
2522
2523 case C2H_HW_INFO_EXCH:
2524 break;
2525
2526 case C2H_8723B_BT_INFO:
2527 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload);
2528 break;
2529
2530 default:
2531 break;
2532 }
2533
2534 /* Clear event to notify FW we have read the command. */
2535 /* Note: */
2536 /* If this field isn't clear, the FW won't update the next command message. */
2537 /* rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); */
2538 exit:
2539 return ret;
2540 }
2541
process_c2h_event(struct adapter * padapter,struct c2h_evt_hdr_t * pC2hEvent,u8 * c2hBuf)2542 static void process_c2h_event(struct adapter *padapter, struct c2h_evt_hdr_t *pC2hEvent, u8 *c2hBuf)
2543 {
2544 if (!c2hBuf)
2545 return;
2546
2547 switch (pC2hEvent->CmdID) {
2548 case C2H_AP_RPT_RSP:
2549 break;
2550 case C2H_DBG:
2551 {
2552 }
2553 break;
2554
2555 case C2H_CCX_TX_RPT:
2556 /* CCX_FwC2HTxRpt(padapter, QueueID, tmpBuf); */
2557 break;
2558
2559 case C2H_EXT_RA_RPT:
2560 /* C2HExtRaRptHandler(padapter, tmpBuf, C2hEvent.CmdLen); */
2561 break;
2562
2563 case C2H_HW_INFO_EXCH:
2564 break;
2565
2566 case C2H_8723B_BT_INFO:
2567 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf);
2568 break;
2569
2570 default:
2571 break;
2572 }
2573 }
2574
C2HPacketHandler_8723B(struct adapter * padapter,u8 * pbuffer,u16 length)2575 void C2HPacketHandler_8723B(struct adapter *padapter, u8 *pbuffer, u16 length)
2576 {
2577 struct c2h_evt_hdr_t C2hEvent;
2578 u8 *tmpBuf = NULL;
2579 C2hEvent.CmdID = pbuffer[0];
2580 C2hEvent.CmdSeq = pbuffer[1];
2581 C2hEvent.CmdLen = length-2;
2582 tmpBuf = pbuffer+2;
2583
2584 process_c2h_event(padapter, &C2hEvent, tmpBuf);
2585 /* c2h_handler_8723b(padapter,&C2hEvent); */
2586 }
2587
SetHwReg8723B(struct adapter * padapter,u8 variable,u8 * val)2588 void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
2589 {
2590 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
2591 u8 val8;
2592 u32 val32;
2593
2594 switch (variable) {
2595 case HW_VAR_MEDIA_STATUS:
2596 val8 = rtw_read8(padapter, MSR) & 0x0c;
2597 val8 |= *val;
2598 rtw_write8(padapter, MSR, val8);
2599 break;
2600
2601 case HW_VAR_MEDIA_STATUS1:
2602 val8 = rtw_read8(padapter, MSR) & 0x03;
2603 val8 |= *val << 2;
2604 rtw_write8(padapter, MSR, val8);
2605 break;
2606
2607 case HW_VAR_SET_OPMODE:
2608 hw_var_set_opmode(padapter, variable, val);
2609 break;
2610
2611 case HW_VAR_MAC_ADDR:
2612 hw_var_set_macaddr(padapter, variable, val);
2613 break;
2614
2615 case HW_VAR_BSSID:
2616 hw_var_set_bssid(padapter, variable, val);
2617 break;
2618
2619 case HW_VAR_BASIC_RATE:
2620 {
2621 struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;
2622 u16 BrateCfg = 0;
2623 u16 rrsr_2g_force_mask = (RRSR_11M|RRSR_5_5M|RRSR_1M);
2624 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES);
2625
2626 HalSetBrateCfg(padapter, val, &BrateCfg);
2627
2628 /* apply force and allow mask */
2629 BrateCfg |= rrsr_2g_force_mask;
2630 BrateCfg &= rrsr_2g_allow_mask;
2631
2632 /* IOT consideration */
2633 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
2634 /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
2635 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0)
2636 BrateCfg |= RRSR_6M;
2637 }
2638
2639 pHalData->BasicRateSet = BrateCfg;
2640
2641 /* Set RRSR rate table. */
2642 rtw_write16(padapter, REG_RRSR, BrateCfg);
2643 rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0);
2644 }
2645 break;
2646
2647 case HW_VAR_TXPAUSE:
2648 rtw_write8(padapter, REG_TXPAUSE, *val);
2649 break;
2650
2651 case HW_VAR_BCN_FUNC:
2652 hw_var_set_bcn_func(padapter, variable, val);
2653 break;
2654
2655 case HW_VAR_CORRECT_TSF:
2656 hw_var_set_correct_tsf(padapter, variable, val);
2657 break;
2658
2659 case HW_VAR_CHECK_BSSID:
2660 {
2661 u32 val32;
2662 val32 = rtw_read32(padapter, REG_RCR);
2663 if (*val)
2664 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN;
2665 else
2666 val32 &= ~(RCR_CBSSID_DATA|RCR_CBSSID_BCN);
2667 rtw_write32(padapter, REG_RCR, val32);
2668 }
2669 break;
2670
2671 case HW_VAR_MLME_DISCONNECT:
2672 hw_var_set_mlme_disconnect(padapter, variable, val);
2673 break;
2674
2675 case HW_VAR_MLME_SITESURVEY:
2676 hw_var_set_mlme_sitesurvey(padapter, variable, val);
2677
2678 hal_btcoex_ScanNotify(padapter, *val?true:false);
2679 break;
2680
2681 case HW_VAR_MLME_JOIN:
2682 hw_var_set_mlme_join(padapter, variable, val);
2683
2684 switch (*val) {
2685 case 0:
2686 /* prepare to join */
2687 hal_btcoex_ConnectNotify(padapter, true);
2688 break;
2689 case 1:
2690 /* joinbss_event callback when join res < 0 */
2691 hal_btcoex_ConnectNotify(padapter, false);
2692 break;
2693 case 2:
2694 /* sta add event callback */
2695 /* rtw_btcoex_MediaStatusNotify(padapter, RT_MEDIA_CONNECT); */
2696 break;
2697 }
2698 break;
2699
2700 case HW_VAR_ON_RCR_AM:
2701 val32 = rtw_read32(padapter, REG_RCR);
2702 val32 |= RCR_AM;
2703 rtw_write32(padapter, REG_RCR, val32);
2704 break;
2705
2706 case HW_VAR_OFF_RCR_AM:
2707 val32 = rtw_read32(padapter, REG_RCR);
2708 val32 &= ~RCR_AM;
2709 rtw_write32(padapter, REG_RCR, val32);
2710 break;
2711
2712 case HW_VAR_BEACON_INTERVAL:
2713 rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val));
2714 break;
2715
2716 case HW_VAR_SLOT_TIME:
2717 rtw_write8(padapter, REG_SLOT, *val);
2718 break;
2719
2720 case HW_VAR_RESP_SIFS:
2721 /* SIFS_Timer = 0x0a0a0808; */
2722 /* RESP_SIFS for CCK */
2723 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */
2724 rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]); /* SIFS_R2T_CCK(0x08) */
2725 /* RESP_SIFS for OFDM */
2726 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */
2727 rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
2728 break;
2729
2730 case HW_VAR_ACK_PREAMBLE:
2731 {
2732 u8 regTmp = 0;
2733 u8 bShortPreamble = *val;
2734
2735 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
2736 /* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */
2737 if (bShortPreamble)
2738 regTmp |= 0x80;
2739 rtw_write8(padapter, REG_RRSR+2, regTmp);
2740 }
2741 break;
2742
2743 case HW_VAR_CAM_EMPTY_ENTRY:
2744 {
2745 u8 ucIndex = *val;
2746 u8 i;
2747 u32 ulCommand = 0;
2748 u32 ulContent = 0;
2749 u32 ulEncAlgo = CAM_AES;
2750
2751 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
2752 /* filled id in CAM config 2 byte */
2753 if (i == 0) {
2754 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
2755 /* ulContent |= CAM_VALID; */
2756 } else
2757 ulContent = 0;
2758
2759 /* polling bit, and No Write enable, and address */
2760 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
2761 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
2762 /* write content 0 is equal to mark as invalid */
2763 rtw_write32(padapter, WCAMI, ulContent); /* mdelay(40); */
2764 rtw_write32(padapter, RWCAM, ulCommand); /* mdelay(40); */
2765 }
2766 }
2767 break;
2768
2769 case HW_VAR_CAM_INVALID_ALL:
2770 rtw_write32(padapter, RWCAM, BIT(31)|BIT(30));
2771 break;
2772
2773 case HW_VAR_CAM_WRITE:
2774 {
2775 u32 cmd;
2776 u32 *cam_val = (u32 *)val;
2777
2778 rtw_write32(padapter, WCAMI, cam_val[0]);
2779
2780 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
2781 rtw_write32(padapter, RWCAM, cmd);
2782 }
2783 break;
2784
2785 case HW_VAR_AC_PARAM_VO:
2786 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
2787 break;
2788
2789 case HW_VAR_AC_PARAM_VI:
2790 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
2791 break;
2792
2793 case HW_VAR_AC_PARAM_BE:
2794 pHalData->AcParam_BE = ((u32 *)(val))[0];
2795 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
2796 break;
2797
2798 case HW_VAR_AC_PARAM_BK:
2799 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
2800 break;
2801
2802 case HW_VAR_ACM_CTRL:
2803 {
2804 u8 ctrl = *((u8 *)val);
2805 u8 hwctrl = 0;
2806
2807 if (ctrl != 0) {
2808 hwctrl |= AcmHw_HwEn;
2809
2810 if (ctrl & BIT(1)) /* BE */
2811 hwctrl |= AcmHw_BeqEn;
2812
2813 if (ctrl & BIT(2)) /* VI */
2814 hwctrl |= AcmHw_ViqEn;
2815
2816 if (ctrl & BIT(3)) /* VO */
2817 hwctrl |= AcmHw_VoqEn;
2818 }
2819
2820 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
2821 }
2822 break;
2823
2824 case HW_VAR_AMPDU_FACTOR:
2825 {
2826 u32 AMPDULen = (*((u8 *)val));
2827
2828 if (AMPDULen < HT_AGG_SIZE_32K)
2829 AMPDULen = (0x2000 << (*((u8 *)val)))-1;
2830 else
2831 AMPDULen = 0x7fff;
2832
2833 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, AMPDULen);
2834 }
2835 break;
2836
2837 case HW_VAR_H2C_FW_PWRMODE:
2838 {
2839 u8 psmode = *val;
2840
2841 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
2842 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
2843 if (psmode != PS_MODE_ACTIVE) {
2844 ODM_RF_Saving(&pHalData->odmpriv, true);
2845 }
2846
2847 /* if (psmode != PS_MODE_ACTIVE) { */
2848 /* rtl8723b_set_lowpwr_lps_cmd(padapter, true); */
2849 /* else { */
2850 /* rtl8723b_set_lowpwr_lps_cmd(padapter, false); */
2851 /* */
2852 rtl8723b_set_FwPwrMode_cmd(padapter, psmode);
2853 }
2854 break;
2855 case HW_VAR_H2C_PS_TUNE_PARAM:
2856 rtl8723b_set_FwPsTuneParam_cmd(padapter);
2857 break;
2858
2859 case HW_VAR_H2C_FW_JOINBSSRPT:
2860 rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val);
2861 break;
2862
2863 case HW_VAR_INITIAL_GAIN:
2864 {
2865 struct dig_t *pDigTable = &pHalData->odmpriv.DM_DigTable;
2866 u32 rx_gain = *(u32 *)val;
2867
2868 if (rx_gain == 0xff) {/* restore rx gain */
2869 ODM_Write_DIG(&pHalData->odmpriv, pDigTable->BackupIGValue);
2870 } else {
2871 pDigTable->BackupIGValue = pDigTable->CurIGValue;
2872 ODM_Write_DIG(&pHalData->odmpriv, rx_gain);
2873 }
2874 }
2875 break;
2876
2877 case HW_VAR_EFUSE_USAGE:
2878 pHalData->EfuseUsedPercentage = *val;
2879 break;
2880
2881 case HW_VAR_EFUSE_BYTES:
2882 pHalData->EfuseUsedBytes = *((u16 *)val);
2883 break;
2884
2885 case HW_VAR_EFUSE_BT_USAGE:
2886 #ifdef HAL_EFUSE_MEMORY
2887 pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
2888 #endif
2889 break;
2890
2891 case HW_VAR_EFUSE_BT_BYTES:
2892 #ifdef HAL_EFUSE_MEMORY
2893 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
2894 #else
2895 BTEfuseUsedBytes = *((u16 *)val);
2896 #endif
2897 break;
2898
2899 case HW_VAR_FIFO_CLEARN_UP:
2900 {
2901 #define RW_RELEASE_EN BIT(18)
2902 #define RXDMA_IDLE BIT(17)
2903
2904 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
2905 u8 trycnt = 100;
2906
2907 /* pause tx */
2908 rtw_write8(padapter, REG_TXPAUSE, 0xff);
2909
2910 /* keep sn */
2911 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
2912
2913 if (!pwrpriv->bkeepfwalive) {
2914 /* RX DMA stop */
2915 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
2916 val32 |= RW_RELEASE_EN;
2917 rtw_write32(padapter, REG_RXPKT_NUM, val32);
2918 do {
2919 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
2920 val32 &= RXDMA_IDLE;
2921 if (val32)
2922 break;
2923 } while (--trycnt);
2924
2925 /* RQPN Load 0 */
2926 rtw_write16(padapter, REG_RQPN_NPQ, 0);
2927 rtw_write32(padapter, REG_RQPN, 0x80000000);
2928 mdelay(2);
2929 }
2930 }
2931 break;
2932
2933 case HW_VAR_APFM_ON_MAC:
2934 pHalData->bMacPwrCtrlOn = *val;
2935 break;
2936
2937 case HW_VAR_NAV_UPPER:
2938 {
2939 u32 usNavUpper = *((u32 *)val);
2940
2941 if (usNavUpper > HAL_NAV_UPPER_UNIT_8723B * 0xFF)
2942 break;
2943
2944 usNavUpper = DIV_ROUND_UP(usNavUpper,
2945 HAL_NAV_UPPER_UNIT_8723B);
2946 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
2947 }
2948 break;
2949
2950 case HW_VAR_H2C_MEDIA_STATUS_RPT:
2951 {
2952 u16 mstatus_rpt = (*(u16 *)val);
2953 u8 mstatus, macId;
2954
2955 mstatus = (u8) (mstatus_rpt & 0xFF);
2956 macId = (u8)(mstatus_rpt >> 8);
2957 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, mstatus, macId);
2958 }
2959 break;
2960 case HW_VAR_BCN_VALID:
2961 {
2962 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
2963 val8 = rtw_read8(padapter, REG_TDECTRL+2);
2964 val8 |= BIT(0);
2965 rtw_write8(padapter, REG_TDECTRL+2, val8);
2966 }
2967 break;
2968
2969 case HW_VAR_DL_BCN_SEL:
2970 {
2971 /* SW_BCN_SEL - Port0 */
2972 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
2973 val8 &= ~BIT(4);
2974 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
2975 }
2976 break;
2977
2978 case HW_VAR_DO_IQK:
2979 pHalData->bNeedIQK = true;
2980 break;
2981
2982 case HW_VAR_DL_RSVD_PAGE:
2983 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)
2984 rtl8723b_download_BTCoex_AP_mode_rsvd_page(padapter);
2985 else
2986 rtl8723b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
2987 break;
2988
2989 case HW_VAR_MACID_SLEEP:
2990 /* Input is MACID */
2991 val32 = *(u32 *)val;
2992 if (val32 > 31)
2993 break;
2994
2995 val8 = (u8)val32; /* macid is between 0~31 */
2996
2997 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
2998 if (val32 & BIT(val8))
2999 break;
3000 val32 |= BIT(val8);
3001 rtw_write32(padapter, REG_MACID_SLEEP, val32);
3002 break;
3003
3004 case HW_VAR_MACID_WAKEUP:
3005 /* Input is MACID */
3006 val32 = *(u32 *)val;
3007 if (val32 > 31)
3008 break;
3009
3010 val8 = (u8)val32; /* macid is between 0~31 */
3011
3012 val32 = rtw_read32(padapter, REG_MACID_SLEEP);
3013 if (!(val32 & BIT(val8)))
3014 break;
3015 val32 &= ~BIT(val8);
3016 rtw_write32(padapter, REG_MACID_SLEEP, val32);
3017 break;
3018
3019 default:
3020 SetHwReg(padapter, variable, val);
3021 break;
3022 }
3023 }
3024
GetHwReg8723B(struct adapter * padapter,u8 variable,u8 * val)3025 void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val)
3026 {
3027 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
3028 u8 val8;
3029 u16 val16;
3030
3031 switch (variable) {
3032 case HW_VAR_TXPAUSE:
3033 *val = rtw_read8(padapter, REG_TXPAUSE);
3034 break;
3035
3036 case HW_VAR_BCN_VALID:
3037 {
3038 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
3039 val8 = rtw_read8(padapter, REG_TDECTRL+2);
3040 *val = (BIT(0) & val8) ? true : false;
3041 }
3042 break;
3043
3044 case HW_VAR_FWLPS_RF_ON:
3045 {
3046 /* When we halt NIC, we should check if FW LPS is leave. */
3047 u32 valRCR;
3048
3049 if (
3050 padapter->bSurpriseRemoved ||
3051 (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)
3052 ) {
3053 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
3054 /* because Fw is unload. */
3055 *val = true;
3056 } else {
3057 valRCR = rtw_read32(padapter, REG_RCR);
3058 valRCR &= 0x00070000;
3059 if (valRCR)
3060 *val = false;
3061 else
3062 *val = true;
3063 }
3064 }
3065 break;
3066
3067 case HW_VAR_EFUSE_USAGE:
3068 *val = pHalData->EfuseUsedPercentage;
3069 break;
3070
3071 case HW_VAR_EFUSE_BYTES:
3072 *((u16 *)val) = pHalData->EfuseUsedBytes;
3073 break;
3074
3075 case HW_VAR_EFUSE_BT_USAGE:
3076 #ifdef HAL_EFUSE_MEMORY
3077 *val = pHalData->EfuseHal.BTEfuseUsedPercentage;
3078 #endif
3079 break;
3080
3081 case HW_VAR_EFUSE_BT_BYTES:
3082 #ifdef HAL_EFUSE_MEMORY
3083 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
3084 #else
3085 *((u16 *)val) = BTEfuseUsedBytes;
3086 #endif
3087 break;
3088
3089 case HW_VAR_APFM_ON_MAC:
3090 *val = pHalData->bMacPwrCtrlOn;
3091 break;
3092 case HW_VAR_CHK_HI_QUEUE_EMPTY:
3093 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
3094 *val = (val16 & BIT(10)) ? true : false;
3095 break;
3096 default:
3097 GetHwReg(padapter, variable, val);
3098 break;
3099 }
3100 }
3101
3102 /* Description:
3103 * Change default setting of specified variable.
3104 */
SetHalDefVar8723B(struct adapter * padapter,enum hal_def_variable variable,void * pval)3105 u8 SetHalDefVar8723B(struct adapter *padapter, enum hal_def_variable variable, void *pval)
3106 {
3107 u8 bResult = _SUCCESS;
3108
3109 switch (variable) {
3110 default:
3111 bResult = SetHalDefVar(padapter, variable, pval);
3112 break;
3113 }
3114
3115 return bResult;
3116 }
3117
3118 /* Description:
3119 * Query setting of specified variable.
3120 */
GetHalDefVar8723B(struct adapter * padapter,enum hal_def_variable variable,void * pval)3121 u8 GetHalDefVar8723B(struct adapter *padapter, enum hal_def_variable variable, void *pval)
3122 {
3123 u8 bResult = _SUCCESS;
3124
3125 switch (variable) {
3126 case HAL_DEF_MAX_RECVBUF_SZ:
3127 *((u32 *)pval) = MAX_RECVBUF_SZ;
3128 break;
3129
3130 case HAL_DEF_RX_PACKET_OFFSET:
3131 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ*8;
3132 break;
3133
3134 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3135 /* Stanley@BB.SD3 suggests 16K can get stable performance */
3136 /* The experiment was done on SDIO interface */
3137 /* coding by Lucas@20130730 */
3138 *(u32 *)pval = IEEE80211_HT_MAX_AMPDU_16K;
3139 break;
3140 case HAL_DEF_TX_LDPC:
3141 case HAL_DEF_RX_LDPC:
3142 *((u8 *)pval) = false;
3143 break;
3144 case HAL_DEF_TX_STBC:
3145 *((u8 *)pval) = 0;
3146 break;
3147 case HAL_DEF_RX_STBC:
3148 *((u8 *)pval) = 1;
3149 break;
3150 case HAL_DEF_EXPLICIT_BEAMFORMER:
3151 case HAL_DEF_EXPLICIT_BEAMFORMEE:
3152 *((u8 *)pval) = false;
3153 break;
3154
3155 case HW_DEF_RA_INFO_DUMP:
3156 {
3157 u8 mac_id = *(u8 *)pval;
3158 u32 cmd = 0x40000100 | mac_id;
3159
3160 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
3161 msleep(10);
3162 rtw_read32(padapter, 0x2F0); // info 1
3163
3164 cmd = 0x40000400 | mac_id;
3165 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd);
3166 msleep(10);
3167 rtw_read32(padapter, 0x2F0); // info 1
3168 rtw_read32(padapter, 0x2F4); // info 2
3169 rtw_read32(padapter, 0x2F8); // rate mask 1
3170 rtw_read32(padapter, 0x2FC); // rate mask 2
3171 }
3172 break;
3173
3174 case HAL_DEF_TX_PAGE_BOUNDARY:
3175 if (!padapter->registrypriv.wifi_spec) {
3176 *(u8 *)pval = TX_PAGE_BOUNDARY_8723B;
3177 } else {
3178 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
3179 }
3180 break;
3181
3182 case HAL_DEF_MACID_SLEEP:
3183 *(u8 *)pval = true; /* support macid sleep */
3184 break;
3185
3186 default:
3187 bResult = GetHalDefVar(padapter, variable, pval);
3188 break;
3189 }
3190
3191 return bResult;
3192 }
3193
rtl8723b_start_thread(struct adapter * padapter)3194 void rtl8723b_start_thread(struct adapter *padapter)
3195 {
3196 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
3197
3198 xmitpriv->SdioXmitThread = kthread_run(rtl8723bs_xmit_thread, padapter, "RTWHALXT");
3199 }
3200
rtl8723b_stop_thread(struct adapter * padapter)3201 void rtl8723b_stop_thread(struct adapter *padapter)
3202 {
3203 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
3204
3205 /* stop xmit_buf_thread */
3206 if (xmitpriv->SdioXmitThread) {
3207 complete(&xmitpriv->SdioXmitStart);
3208 wait_for_completion(&xmitpriv->SdioXmitTerminate);
3209 xmitpriv->SdioXmitThread = NULL;
3210 }
3211 }
3212