1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2015 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2019 Joyent, Inc. 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 27 * Copyright 2023 Racktop Systems, Inc. 28 * Copyright 2026 Hans Rosenfeld 29 */ 30 31 /* 32 * Copyright (c) 2000 to 2010, LSI Corporation. 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms of all code within 36 * this file that is exclusively owned by LSI, with or without 37 * modification, is permitted provided that, in addition to the CDDL 1.0 38 * License requirements, the following conditions are met: 39 * 40 * Neither the name of the author nor the names of its contributors may be 41 * used to endorse or promote products derived from this software without 42 * specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 47 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 48 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 50 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 51 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 52 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 53 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 55 * DAMAGE. 56 */ 57 58 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 59 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 60 61 #include <sys/byteorder.h> 62 #include <sys/queue.h> 63 #include <sys/refhash.h> 64 #include <sys/isa_defs.h> 65 #include <sys/sunmdi.h> 66 #include <sys/mdi_impldefs.h> 67 #include <sys/ddi_ufm.h> 68 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 69 #include <sys/scsi/adapters/mpi/mpi2_tool.h> 70 #include <sys/scsi/adapters/mpi/mpi2_cnfg.h> 71 72 #ifdef __cplusplus 73 extern "C" { 74 #endif 75 76 /* 77 * Compile options 78 */ 79 #ifdef DEBUG 80 #define MPTSAS_DEBUG /* turn on debugging code */ 81 #endif /* DEBUG */ 82 83 #define MPTSAS_INITIAL_SOFT_SPACE 4 84 85 /* 86 * Note below macro definition and data type definition 87 * are used for phy mask handling, it should be changed 88 * simultaneously. 89 */ 90 #define MPTSAS_MAX_PHYS 24 91 typedef uint32_t mptsas_phymask_t; 92 93 #define MPTSAS_INVALID_DEVHDL 0xffff 94 #define MPTSAS_SATA_GUID "sata-guid" 95 96 /* 97 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP 98 * targets. There's no need to go overboard here, as the ordinary paths for 99 * I/O do not normally require hashed target lookups. These should be good 100 * enough and then some for any fabric within the hardware's capabilities. 101 */ 102 #define MPTSAS_SMP_BUCKET_COUNT 23 103 #define MPTSAS_TARGET_BUCKET_COUNT 97 104 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13 105 106 /* 107 * MPT HW defines 108 */ 109 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 110 #define MPTSAS_MAX_DISKS_IN_VOL 10 111 #define MPTSAS_MAX_HOTSPARES 2 112 #define MPTSAS_MAX_RAIDVOLS 2 113 #define MPTSAS_MAX_RAIDCONFIGS 5 114 115 /* 116 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 117 * plus two means the prefix 'w' and end of the string '\0'. 118 */ 119 #define MPTSAS_WWN_STRLEN (16 + 2) 120 #define MPTSAS_MAX_GUID_LEN 64 121 122 /* 123 * DMA routine flags 124 */ 125 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 126 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 127 #define MPTSAS_DMA_HANDLE_BOUND 0x8 128 129 /* 130 * If the HBA supports DMA or bus-mastering, you may have your own 131 * scatter-gather list for physically non-contiguous memory in one 132 * I/O operation; if so, there's probably a size for that list. 133 * It must be placed in the ddi_dma_lim_t structure, so that the system 134 * DMA-support routines can use it to break up the I/O request, so we 135 * define it here. 136 */ 137 #define MPTSAS_MAX_DMA_SEGS 257 138 139 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 140 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 141 142 #define MPTSAS_SGE_SIZE(mpt) \ 143 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \ 144 sizeof (MPI2_SGE_SIMPLE64)) 145 146 /* 147 * Calculating how many 64-bit DMA simple elements can be stored in the first 148 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 149 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 150 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words 151 * (16 bytes). 152 */ 153 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 154 ((mpt->m_req_frame_size - \ 155 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \ 156 MPTSAS_SGE_SIZE(mpt)) 157 158 /* 159 * Scatter-gather list structure defined by HBA hardware 160 */ 161 typedef struct NcrTableIndirect { /* Table Indirect entries */ 162 uint32_t count; /* 24 bit count */ 163 union { 164 uint32_t address32; /* 32 bit address */ 165 struct { 166 uint32_t Low; 167 uint32_t High; 168 } address64; /* 64 bit address */ 169 } addr; 170 } mptti_t; 171 172 /* 173 * preferred pkt_private length in 64-bit quantities 174 */ 175 #ifdef _LP64 176 #define PKT_PRIV_SIZE 2 177 #define PKT_PRIV_LEN 16 /* in bytes */ 178 #else /* _ILP32 */ 179 #define PKT_PRIV_SIZE 1 180 #define PKT_PRIV_LEN 8 /* in bytes */ 181 #endif 182 183 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 184 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 185 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 186 187 /* 188 * get offset of item in structure 189 */ 190 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 191 192 /* 193 * WWID provided by LSI firmware is generated by firmware but the WWID is not 194 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 195 * address. According LSI's confirmation, the top nibble of RAID WWID is 196 * meanless, so the consensus between Solaris and OBP is to replace top nibble 197 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 198 * format unit address. 199 */ 200 #define MPTSAS_RAID_WWID(wwid) \ 201 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 202 203 typedef struct mptsas_target_addr { 204 uint64_t mta_wwn; 205 mptsas_phymask_t mta_phymask; 206 } mptsas_target_addr_t; 207 208 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd); 209 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t; 210 211 typedef struct mptsas_target { 212 mptsas_target_addr_t m_addr; 213 refhash_link_t m_link; 214 uint8_t m_dr_flag; 215 uint16_t m_devhdl; 216 uint32_t m_deviceinfo; 217 uint8_t m_phynum; 218 uint32_t m_dups; 219 mptsas_active_cmdq_t m_active_cmdq; 220 int32_t m_t_throttle; 221 int32_t m_t_ncmds; 222 int32_t m_reset_delay; 223 int32_t m_t_nwait; 224 225 uint16_t m_qfull_retry_interval; 226 uint8_t m_qfull_retries; 227 uint16_t m_io_flags; 228 uint16_t m_enclosure; 229 uint16_t m_slot_num; 230 uint32_t m_tgt_unconfigured; 231 } mptsas_target_t; 232 233 /* 234 * If you change this structure, be sure that mptsas_smp_target_copy() 235 * does the right thing. 236 */ 237 typedef struct mptsas_smp { 238 mptsas_target_addr_t m_addr; 239 refhash_link_t m_link; 240 uint16_t m_devhdl; 241 uint32_t m_deviceinfo; 242 uint16_t m_pdevhdl; 243 uint32_t m_pdevinfo; 244 } mptsas_smp_t; 245 246 /* 247 * This represents a single enclosure. Targets point to an enclosure through 248 * their m_enclosure member. 249 */ 250 typedef struct mptsas_enclosure { 251 list_node_t me_link; 252 uint16_t me_enchdl; 253 uint16_t me_flags; 254 uint16_t me_nslots; 255 uint16_t me_fslot; 256 uint8_t *me_slotleds; 257 } mptsas_enclosure_t; 258 259 typedef struct mptsas_cache_frames { 260 ddi_dma_handle_t m_dma_hdl; 261 ddi_acc_handle_t m_acc_hdl; 262 caddr_t m_frames_addr; 263 uint64_t m_phys_addr; 264 } mptsas_cache_frames_t; 265 266 typedef struct mptsas_cmd { 267 uint_t cmd_flags; /* flags from scsi_init_pkt */ 268 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 269 ddi_dma_cookie_t cmd_cookie; 270 uint_t cmd_cookiec; 271 uint_t cmd_winindex; 272 uint_t cmd_nwin; 273 uint_t cmd_cur_cookie; 274 off_t cmd_dma_offset; 275 size_t cmd_dma_len; 276 uint32_t cmd_totaldmacount; 277 caddr_t cmd_arq_buf; 278 279 int cmd_pkt_flags; 280 281 /* pending expiration time for command in active slot */ 282 hrtime_t cmd_active_expiration; 283 TAILQ_ENTRY(mptsas_cmd) cmd_active_link; 284 285 struct scsi_pkt *cmd_pkt; 286 struct scsi_arq_status cmd_scb; 287 uchar_t cmd_cdblen; /* length of cdb */ 288 uchar_t cmd_rqslen; /* len of requested rqsense */ 289 uchar_t cmd_privlen; 290 uint16_t cmd_extrqslen; /* len of extended rqsense */ 291 uint16_t cmd_extrqschunks; /* len in map chunks */ 292 uint16_t cmd_extrqsidx; /* Index into map */ 293 uint_t cmd_scblen; 294 uint32_t cmd_dmacount; 295 uint64_t cmd_dma_addr; 296 uchar_t cmd_age; 297 ushort_t cmd_qfull_retries; 298 uchar_t cmd_queued; /* true if queued */ 299 struct mptsas_cmd *cmd_linkp; 300 mptti_t *cmd_sg; /* Scatter/Gather structure */ 301 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 302 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 303 uint32_t cmd_slot; 304 uint32_t ioc_cmd_slot; 305 306 mptsas_cache_frames_t *cmd_extra_frames; 307 308 uint32_t cmd_rfm; 309 mptsas_target_t *cmd_tgt_addr; 310 } mptsas_cmd_t; 311 312 /* 313 * These are the defined cmd_flags for this structure. 314 */ 315 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 316 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 317 #define CFLAG_FINISHED 0x000004 /* command completed */ 318 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 319 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 320 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 321 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 322 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 323 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 324 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 325 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 326 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 327 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 328 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 329 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 330 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 331 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 332 #define CFLAG_FREE 0x010000 /* packet is on free list */ 333 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 334 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 335 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 336 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 337 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 338 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 339 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 340 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 341 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 342 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 343 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 344 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 345 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 346 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 347 348 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 349 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 353 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 354 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 357 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 358 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 359 360 #define MPTSAS_HASH_ARRAY_SIZE 16 361 /* 362 * hash table definition 363 */ 364 365 #define MPTSAS_HASH_FIRST 0xffff 366 #define MPTSAS_HASH_NEXT 0x0000 367 368 typedef struct mptsas_dma_alloc_state 369 { 370 ddi_dma_handle_t handle; 371 caddr_t memp; 372 size_t size; 373 ddi_acc_handle_t accessp; 374 ddi_dma_cookie_t cookie; 375 } mptsas_dma_alloc_state_t; 376 377 /* 378 * passthrough request structure 379 */ 380 typedef struct mptsas_pt_request { 381 uint8_t *request; 382 uint32_t request_size; 383 uint32_t data_size; 384 uint32_t dataout_size; 385 uint32_t direction; 386 uint8_t simple; 387 uint16_t sgl_offset; 388 ddi_dma_cookie_t data_cookie; 389 ddi_dma_cookie_t dataout_cookie; 390 } mptsas_pt_request_t; 391 392 /* 393 * config page request structure 394 */ 395 typedef struct mptsas_config_request { 396 uint32_t page_address; 397 uint8_t action; 398 uint8_t page_type; 399 uint8_t page_number; 400 uint8_t page_length; 401 uint8_t page_version; 402 uint8_t ext_page_type; 403 uint16_t ext_page_length; 404 } mptsas_config_request_t; 405 406 typedef struct mptsas_fw_diagnostic_buffer { 407 mptsas_dma_alloc_state_t buffer_data; 408 uint8_t extended_type; 409 uint8_t buffer_type; 410 uint8_t force_release; 411 uint32_t product_specific[23]; 412 uint8_t immediate; 413 uint8_t enabled; 414 uint8_t valid_data; 415 uint8_t owned_by_firmware; 416 uint32_t unique_id; 417 } mptsas_fw_diagnostic_buffer_t; 418 419 /* 420 * FW diag request structure 421 */ 422 typedef struct mptsas_diag_request { 423 mptsas_fw_diagnostic_buffer_t *pBuffer; 424 uint8_t function; 425 } mptsas_diag_request_t; 426 427 typedef struct mptsas_hash_node { 428 void *data; 429 struct mptsas_hash_node *next; 430 } mptsas_hash_node_t; 431 432 typedef struct mptsas_hash_table { 433 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 434 /* 435 * last position in traverse 436 */ 437 struct mptsas_hash_node *cur; 438 uint16_t line; 439 440 } mptsas_hash_table_t; 441 442 /* 443 * RAID volume information 444 */ 445 typedef struct mptsas_raidvol { 446 ushort_t m_israid; 447 uint16_t m_raidhandle; 448 uint64_t m_raidwwid; 449 uint8_t m_state; 450 uint32_t m_statusflags; 451 uint32_t m_settings; 452 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 453 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 454 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 455 uint64_t m_raidsize; 456 int m_raidlevel; 457 int m_ndisks; 458 mptsas_target_t *m_raidtgt; 459 } mptsas_raidvol_t; 460 461 /* 462 * RAID configurations 463 */ 464 typedef struct mptsas_raidconfig { 465 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 466 uint16_t m_physdisk_devhdl[ 467 MPTSAS_MAX_DISKS_IN_CONFIG]; 468 uint8_t m_native; 469 } m_raidconfig_t; 470 471 /* 472 * Track outstanding commands. The index into the m_slot array is the SMID 473 * (system message ID) of the outstanding command. SMID 0 is reserved by the 474 * software/firmware protocol and is never used for any command we generate; 475 * as such, the assertion m_slot[0] == NULL is universally true. The last 476 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for 477 * task management commands. No normal SCSI or ATA command will ever occupy 478 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any 479 * time that a consistent view of the target array is obtainable. 480 * 481 * As such, m_n_normal is the maximum number of slots available to ordinary 482 * commands, and the relationship: 483 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2 484 * always holds after initialisation. 485 */ 486 typedef struct mptsas_slots { 487 size_t m_size; /* size of struct, bytes */ 488 uint_t m_n_normal; /* see above */ 489 uint_t m_rotor; /* next slot idx to consider */ 490 mptsas_cmd_t *m_slot[1]; 491 } mptsas_slots_t; 492 493 /* 494 * Structure to hold command and packets for event ack 495 * and task management commands. 496 */ 497 typedef struct m_event_struct { 498 struct mptsas_cmd m_event_cmd; 499 struct m_event_struct *m_event_linkp; 500 /* 501 * event member record the failure event and eventcntx 502 * event member would be used in send ack pending process 503 */ 504 uint32_t m_event; 505 uint32_t m_eventcntx; 506 uint_t in_use; 507 struct scsi_pkt m_event_pkt; /* must be last */ 508 /* ... scsi_pkt_size() */ 509 } m_event_struct_t; 510 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 511 sizeof (struct scsi_pkt) + scsi_pkt_size()) 512 513 #define MAX_IOC_COMMANDS 8 514 515 /* 516 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 517 * A new event ack command requests mptsas_cmd and scsi_pkt structures 518 * from this pool, and returns it back when done. 519 */ 520 521 typedef struct m_replyh_arg { 522 void *mpt; 523 uint32_t rfm; 524 } m_replyh_arg_t; 525 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 526 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 527 528 /* 529 * Flags for DR handler topology change 530 */ 531 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 532 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 533 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 534 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 535 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 536 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 537 538 typedef struct mptsas_topo_change_list { 539 void *mpt; 540 uint_t event; 541 union { 542 uint8_t physport; 543 mptsas_phymask_t phymask; 544 } un; 545 uint16_t devhdl; 546 void *object; 547 uint8_t flags; 548 struct mptsas_topo_change_list *next; 549 } mptsas_topo_change_list_t; 550 551 552 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 553 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 554 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 555 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 556 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 557 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 558 559 /* 560 * Status types when calling mptsas_get_target_device_info 561 */ 562 #define DEV_INFO_SUCCESS 0x0 563 #define DEV_INFO_FAIL_PAGE0 0x1 564 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 565 #define DEV_INFO_PHYS_DISK 0x3 566 #define DEV_INFO_FAIL_ALLOC 0x4 567 #define DEV_INFO_FAIL_GUID 0x5 568 569 /* 570 * mpt hotplug event defines 571 */ 572 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 573 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 574 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 575 576 /* 577 * SMP target hotplug events 578 */ 579 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 580 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 581 #define MPTSAS_DR_EVENT_MASK 0x3F 582 583 /* 584 * mpt hotplug status definition for m_dr_flag 585 */ 586 587 /* 588 * MPTSAS_DR_INACTIVE 589 * 590 * The target is in a normal operating state. 591 * No dynamic reconfiguration operation is in progress. 592 */ 593 #define MPTSAS_DR_INACTIVE 0x0 594 /* 595 * MPTSAS_DR_INTRANSITION 596 * 597 * The target is in a transition mode since 598 * hotplug event happens and offline procedure has not 599 * been finished 600 */ 601 #define MPTSAS_DR_INTRANSITION 0x1 602 603 typedef struct mptsas_tgt_private { 604 int t_lun; 605 struct mptsas_target *t_private; 606 } mptsas_tgt_private_t; 607 608 /* 609 * The following defines are used in mptsas_set_init_mode to track the current 610 * state as we progress through reprogramming the HBA from target mode into 611 * initiator mode. 612 */ 613 614 #define IOUC_READ_PAGE0 0x00000100 615 #define IOUC_READ_PAGE1 0x00000200 616 #define IOUC_WRITE_PAGE1 0x00000400 617 #define IOUC_DONE 0x00000800 618 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 619 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 620 621 /* 622 * Last allocated slot is used for TM requests. Since only m_max_requests 623 * frames are allocated, the last SMID will be m_max_requests - 1. 624 */ 625 #define MPTSAS_SLOTS_SIZE(mpt) \ 626 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 627 mpt->m_max_requests)) 628 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 629 630 /* 631 * Macro for phy_flags 632 */ 633 634 typedef struct smhba_info { 635 kmutex_t phy_mutex; 636 uint8_t phy_id; 637 uint64_t sas_addr; 638 char path[8]; 639 uint16_t owner_devhdl; 640 uint16_t attached_devhdl; 641 uint8_t attached_phy_identify; 642 uint32_t attached_phy_info; 643 uint8_t programmed_link_rate; 644 uint8_t hw_link_rate; 645 uint8_t change_count; 646 uint32_t phy_info; 647 uint8_t negotiated_link_rate; 648 uint8_t port_num; 649 kstat_t *phy_stats; 650 uint32_t invalid_dword_count; 651 uint32_t running_disparity_error_count; 652 uint32_t loss_of_dword_sync_count; 653 uint32_t phy_reset_problem_count; 654 void *mpt; 655 } smhba_info_t; 656 657 typedef struct mptsas_phy_info { 658 uint8_t port_num; 659 uint8_t port_flags; 660 uint16_t ctrl_devhdl; 661 uint32_t phy_device_type; 662 uint16_t attached_devhdl; 663 mptsas_phymask_t phy_mask; 664 smhba_info_t smhba_info; 665 } mptsas_phy_info_t; 666 667 668 typedef struct mptsas_doneq_thread_arg { 669 void *mpt; 670 uint64_t t; 671 } mptsas_doneq_thread_arg_t; 672 673 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 674 typedef struct mptsas_doneq_thread_list { 675 mptsas_cmd_t *doneq; 676 mptsas_cmd_t **donetail; 677 kthread_t *threadp; 678 kcondvar_t cv; 679 ushort_t reserv1; 680 uint32_t reserv2; 681 kmutex_t mutex; 682 uint32_t flag; 683 uint32_t len; 684 mptsas_doneq_thread_arg_t arg; 685 } mptsas_doneq_thread_list_t; 686 687 typedef struct mptsas { 688 int m_instance; 689 690 struct mptsas *m_next; 691 692 scsi_hba_tran_t *m_tran; 693 smp_hba_tran_t *m_smptran; 694 kmutex_t m_mutex; 695 kmutex_t m_passthru_mutex; 696 kcondvar_t m_cv; 697 kcondvar_t m_passthru_cv; 698 kcondvar_t m_fw_cv; 699 kcondvar_t m_config_cv; 700 kcondvar_t m_fw_diag_cv; 701 dev_info_t *m_dip; 702 703 /* 704 * soft state flags 705 */ 706 uint_t m_softstate; 707 708 refhash_t *m_targets; 709 refhash_t *m_smp_targets; 710 list_t m_enclosures; 711 refhash_t *m_tmp_targets; 712 713 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 714 uint8_t m_num_raid_configs; 715 716 struct mptsas_slots *m_active; /* outstanding cmds */ 717 718 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 719 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 720 721 kmutex_t m_tx_waitq_mutex; 722 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 723 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 724 int m_tx_draining; /* TX queue draining flag */ 725 726 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 727 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 728 729 /* 730 * variables for helper threads (fan-out interrupts) 731 */ 732 mptsas_doneq_thread_list_t *m_doneq_thread_id; 733 uint32_t m_doneq_thread_n; 734 uint32_t m_doneq_thread_threshold; 735 uint32_t m_doneq_length_threshold; 736 uint32_t m_doneq_len; 737 kcondvar_t m_doneq_thread_cv; 738 kmutex_t m_doneq_mutex; 739 740 int m_ncmds; /* number of outstanding commands */ 741 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 742 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 743 744 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 745 746 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 747 748 ushort_t m_devid; /* device id of chip. */ 749 uchar_t m_revid; /* revision of chip. */ 750 uint16_t m_svid; /* subsystem Vendor ID of chip */ 751 uint16_t m_ssid; /* subsystem Device ID of chip */ 752 753 uchar_t m_sync_offset; /* default offset for this chip. */ 754 755 timeout_id_t m_quiesce_timeid; 756 757 ddi_dma_handle_t m_dma_req_frame_hdl; 758 ddi_acc_handle_t m_acc_req_frame_hdl; 759 ddi_dma_handle_t m_dma_req_sense_hdl; 760 ddi_acc_handle_t m_acc_req_sense_hdl; 761 ddi_dma_handle_t m_dma_reply_frame_hdl; 762 ddi_acc_handle_t m_acc_reply_frame_hdl; 763 ddi_dma_handle_t m_dma_free_queue_hdl; 764 ddi_acc_handle_t m_acc_free_queue_hdl; 765 ddi_dma_handle_t m_dma_post_queue_hdl; 766 ddi_acc_handle_t m_acc_post_queue_hdl; 767 768 /* 769 * list of reset notification requests 770 */ 771 struct scsi_reset_notify_entry *m_reset_notify_listf; 772 773 /* 774 * qfull handling 775 */ 776 timeout_id_t m_restart_cmd_timeid; 777 778 /* 779 * scsi reset delay per bus 780 */ 781 uint_t m_scsi_reset_delay; 782 783 int m_pm_idle_delay; 784 785 uchar_t m_polled_intr; /* intr was polled. */ 786 uchar_t m_suspended; /* true if driver is suspended */ 787 788 struct kmem_cache *m_kmem_cache; 789 struct kmem_cache *m_cache_frames; 790 791 /* 792 * hba options. 793 */ 794 uint_t m_options; 795 796 int m_in_callback; 797 798 int m_power_level; /* current power level */ 799 800 int m_busy; /* power management busy state */ 801 802 off_t m_pmcsr_offset; /* PMCSR offset */ 803 804 ddi_acc_handle_t m_config_handle; 805 806 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 807 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 808 ddi_device_acc_attr_t m_dev_acc_attr; 809 ddi_device_acc_attr_t m_reg_acc_attr; 810 811 /* 812 * request/reply variables 813 */ 814 caddr_t m_req_frame; 815 uint64_t m_req_frame_dma_addr; 816 caddr_t m_req_sense; 817 caddr_t m_extreq_sense; 818 uint_t m_extreq_sense_refcount; 819 kcondvar_t m_extreq_sense_refcount_cv; 820 uint64_t m_req_sense_dma_addr; 821 caddr_t m_reply_frame; 822 uint64_t m_reply_frame_dma_addr; 823 caddr_t m_free_queue; 824 uint64_t m_free_queue_dma_addr; 825 caddr_t m_post_queue; 826 uint64_t m_post_queue_dma_addr; 827 struct map *m_erqsense_map; 828 829 m_replyh_arg_t *m_replyh_args; 830 831 uint16_t m_max_requests; 832 uint16_t m_req_frame_size; 833 uint16_t m_req_sense_size; 834 835 /* 836 * Max frames per request reprted in IOC Facts 837 */ 838 uint8_t m_max_chain_depth; 839 /* 840 * Max frames per request which is used in reality. It's adjusted 841 * according DMA SG length attribute, and shall not exceed the 842 * m_max_chain_depth. 843 */ 844 uint8_t m_max_request_frames; 845 846 uint16_t m_free_queue_depth; 847 uint16_t m_post_queue_depth; 848 uint16_t m_max_replies; 849 uint32_t m_free_index; 850 uint32_t m_post_index; 851 uint8_t m_reply_frame_size; 852 uint32_t m_ioc_capabilities; 853 854 /* 855 * indicates if the firmware was upload by the driver 856 * at boot time 857 */ 858 ushort_t m_fwupload; 859 860 uint16_t m_productid; 861 862 /* 863 * per instance data structures for dma memory resources for 864 * MPI handshake protocol. only one handshake cmd can run at a time. 865 */ 866 ddi_dma_handle_t m_hshk_dma_hdl; 867 ddi_acc_handle_t m_hshk_acc_hdl; 868 caddr_t m_hshk_memp; 869 size_t m_hshk_dma_size; 870 871 /* Firmware version on the card at boot time */ 872 uint32_t m_fwversion; 873 874 /* MSI specific fields */ 875 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 876 int m_intr_type; /* What type of interrupt */ 877 int m_intr_cnt; /* # of intrs count returned */ 878 size_t m_intr_size; /* Size of intr array */ 879 uint_t m_intr_pri; /* Interrupt priority */ 880 int m_intr_cap; /* Interrupt capabilities */ 881 ddi_taskq_t *m_event_taskq; 882 883 /* SAS specific information */ 884 885 union { 886 uint64_t m_base_wwid; /* Base WWID */ 887 struct { 888 #ifdef _BIG_ENDIAN 889 uint32_t m_base_wwid_hi; 890 uint32_t m_base_wwid_lo; 891 #else 892 uint32_t m_base_wwid_lo; 893 uint32_t m_base_wwid_hi; 894 #endif 895 } sasaddr; 896 } un; 897 898 uint8_t m_num_phys; /* # of PHYs */ 899 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 900 uint8_t m_port_chng; /* initiator port changes */ 901 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 902 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 903 904 /* FMA Capabilities */ 905 int m_fm_capabilities; 906 ddi_taskq_t *m_dr_taskq; 907 int m_mpxio_enable; 908 uint8_t m_done_traverse_dev; 909 uint8_t m_done_traverse_smp; 910 uint8_t m_done_traverse_enc; 911 int m_diag_action_in_progress; 912 uint16_t m_dev_handle; 913 uint16_t m_smp_devhdl; 914 915 /* DDI UFM Handle */ 916 ddi_ufm_handle_t *m_ufmh; 917 918 /* 919 * Event recording 920 */ 921 uint8_t m_event_index; 922 uint32_t m_event_number; 923 uint32_t m_event_mask[4]; 924 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 925 926 /* 927 * FW diag Buffer List 928 */ 929 mptsas_fw_diagnostic_buffer_t 930 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 931 932 /* IOC type flags */ 933 uint8_t m_is_sea_ioc; 934 uint8_t m_is_gen35_ioc; 935 936 /* GEN3 support */ 937 uint8_t m_MPI25; 938 939 /* 940 * Event Replay flag (MUR support) 941 */ 942 uint8_t m_event_replay; 943 944 /* 945 * IR Capable flag 946 */ 947 uint8_t m_ir_capable; 948 949 /* 950 * Is HBA processing a diag reset? 951 */ 952 uint8_t m_in_reset; 953 954 /* 955 * index for the pci memory BAR 956 */ 957 uint8_t m_mem_bar; 958 959 /* 960 * per instance cmd data structures for task management cmds 961 */ 962 m_event_struct_t m_event_task_mgmt; /* must be last */ 963 /* ... scsi_pkt_size */ 964 } mptsas_t; 965 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 966 sizeof (struct scsi_pkt) + scsi_pkt_size()) 967 /* 968 * Only one of below two conditions is satisfied, we 969 * think the target is associated to the iport and 970 * allow call into mptsas_probe_lun(). 971 * 1. physicalsport == physport 972 * 2. (phymask & (1 << physport)) == 0 973 * The condition #2 is because LSI uses lowest PHY 974 * number as the value of physical port when auto port 975 * configuration. 976 */ 977 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 978 ((physicalport == physport) || (dynamicport && (phymask & \ 979 (1 << physport)))) 980 981 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 982 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 983 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 984 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 985 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 986 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 987 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 988 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 989 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 990 991 /* 992 * These should eventually migrate into the mpt header files 993 * that may become the /kernel/misc/mpt module... 994 */ 995 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 996 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 997 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 998 mptsas_put_msg_Function(hdl, mp, Function); \ 999 mptsas_put_msg_Lun(hdl, mp, Lun) 1000 1001 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 1002 ddi_put16(hdl, &(mp)->DevHandle, (val)) 1003 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 1004 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 1005 #define mptsas_put_msg_Function(hdl, mp, val) \ 1006 ddi_put8(hdl, &(mp)->Function, (val)) 1007 #define mptsas_put_msg_Lun(hdl, mp, val) \ 1008 ddi_put8(hdl, &(mp)->LUN[1], (val)) 1009 1010 #define mptsas_get_msg_Function(hdl, mp) \ 1011 ddi_get8(hdl, &(mp)->Function) 1012 1013 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 1014 ddi_get8(hdl, &(mp)->MsgFlags) 1015 1016 #define MPTSAS_ENABLE_DRWE(hdl) \ 1017 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1018 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 1019 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1020 MPI2_WRSEQ_1ST_KEY_VALUE); \ 1021 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1022 MPI2_WRSEQ_2ND_KEY_VALUE); \ 1023 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1024 MPI2_WRSEQ_3RD_KEY_VALUE); \ 1025 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1026 MPI2_WRSEQ_4TH_KEY_VALUE); \ 1027 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1028 MPI2_WRSEQ_5TH_KEY_VALUE); \ 1029 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1030 MPI2_WRSEQ_6TH_KEY_VALUE); 1031 1032 /* 1033 * m_options flags 1034 */ 1035 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 1036 1037 /* 1038 * m_softstate flags 1039 */ 1040 #define MPTSAS_SS_DRAINING 0x02 1041 #define MPTSAS_SS_QUIESCED 0x04 1042 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1043 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1044 1045 /* 1046 * regspec defines. 1047 */ 1048 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1049 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1050 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1051 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1052 1053 /* 1054 * Handy constants 1055 */ 1056 #define FALSE 0 1057 #define TRUE 1 1058 #define UNDEFINED -1 1059 #define FAILED -2 1060 1061 /* 1062 * power management. 1063 */ 1064 #define MPTSAS_POWER_ON(mpt) { \ 1065 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1066 PCI_PMCSR_D0); \ 1067 delay(drv_usectohz(10000)); \ 1068 (void) pci_restore_config_regs(mpt->m_dip); \ 1069 mptsas_setup_cmd_reg(mpt); \ 1070 } 1071 1072 #define MPTSAS_POWER_OFF(mpt) { \ 1073 (void) pci_save_config_regs(mpt->m_dip); \ 1074 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1075 PCI_PMCSR_D3HOT); \ 1076 mpt->m_power_level = PM_LEVEL_D3; \ 1077 } 1078 1079 /* 1080 * inq_dtype: 1081 * Bits 5 through 7 are the Peripheral Device Qualifier 1082 * 001b: device not connected to the LUN 1083 * Bits 0 through 4 are the Peripheral Device Type 1084 * 1fh: Unknown or no device type 1085 * 1086 * Although the inquiry may return success, the following value 1087 * means no valid LUN connected. 1088 */ 1089 #define MPTSAS_VALID_LUN(sd_inq) \ 1090 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1091 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1092 1093 /* 1094 * Default is to have 10 retries on receiving QFULL status and 1095 * each retry to be after 100 ms. 1096 */ 1097 #define QFULL_RETRIES 10 1098 #define QFULL_RETRY_INTERVAL 100 1099 1100 /* 1101 * Handy macros 1102 */ 1103 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1104 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1105 1106 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1107 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1108 1109 /* 1110 * poll time for mptsas_pollret() and mptsas_wait_intr() 1111 */ 1112 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1113 1114 /* 1115 * default time for mptsas_do_passthru 1116 */ 1117 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1118 1119 /* 1120 * macro to return the effective address of a given per-target field 1121 */ 1122 #define EFF_ADDR(start, offset) ((start) + (offset)) 1123 1124 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1125 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1126 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1127 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1128 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1129 1130 1131 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1132 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1133 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1134 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1135 1136 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1137 1138 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1139 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1140 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1141 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1142 1143 #define MPTSAS_GET_ISTAT(mpt) (mptsas_hirrd((mpt), \ 1144 &(mpt)->m_reg->HostInterruptStatus)) 1145 1146 #define MPTSAS_SET_SIGP(P) \ 1147 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1148 1149 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1150 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1151 1152 #define MPTSAS_GET_INTCODE(P) (mptsas_hirrd(mpt, \ 1153 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1154 1155 1156 #define MPTSAS_START_CMD(mpt, req_desc) \ 1157 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \ 1158 req_desc & 0xffffffffu); \ 1159 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \ 1160 (req_desc >> 32) & 0xffffffffu); 1161 1162 #define INTPENDING(mpt) \ 1163 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1164 1165 /* 1166 * Mask all interrupts to disable 1167 */ 1168 #define MPTSAS_DISABLE_INTR(mpt) \ 1169 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1170 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1171 1172 /* 1173 * Mask Doorbell and Reset interrupts to enable reply desc int. 1174 */ 1175 #define MPTSAS_ENABLE_INTR(mpt) \ 1176 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1177 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1178 1179 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1180 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1181 1182 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1183 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1184 1185 #define ClrSetBits32(hdl, reg, clr, set) \ 1186 ddi_put32(hdl, (reg), \ 1187 ((mptsas_hirrd(mpt, (reg)) & ~(clr)) | (set))) 1188 1189 #define ClrSetBits(reg, clr, set) \ 1190 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1191 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1192 1193 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1194 if ((cmdp = mpt->m_waitq) != NULL) { \ 1195 /* If the queue is now empty fix the tail pointer */ \ 1196 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1197 mpt->m_waitqtail = &mpt->m_waitq; \ 1198 cmdp->cmd_linkp = NULL; \ 1199 cmdp->cmd_queued = FALSE; \ 1200 } 1201 1202 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1203 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1204 /* If the queue is now empty fix the tail pointer */ \ 1205 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1206 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1207 cmdp->cmd_linkp = NULL; \ 1208 cmdp->cmd_queued = FALSE; \ 1209 } 1210 1211 /* 1212 * defaults for the global properties 1213 */ 1214 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1215 #define DEFAULT_TAG_AGE_LIMIT 2 1216 #define DEFAULT_WD_TICK 1 1217 1218 /* 1219 * invalid hostid. 1220 */ 1221 #define MPTSAS_INVALID_HOSTID -1 1222 1223 /* 1224 * Get/Set hostid from SCSI port configuration page 1225 */ 1226 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1227 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1228 1229 /* 1230 * Config space. 1231 */ 1232 #define MPTSAS_LATENCY_TIMER 0x40 1233 1234 /* 1235 * Offset to firmware version 1236 */ 1237 #define MPTSAS_FW_VERSION_OFFSET 9 1238 1239 /* 1240 * Offset and masks to get at the ProductId field 1241 */ 1242 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1243 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1244 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1245 1246 /* 1247 * Subsystem ID for HBAs. 1248 */ 1249 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1250 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1251 1252 /* 1253 * reset delay tick 1254 */ 1255 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1256 1257 /* 1258 * Ioc reset return values 1259 */ 1260 #define MPTSAS_RESET_FAIL -1 1261 #define MPTSAS_NO_RESET 0 1262 #define MPTSAS_SUCCESS_HARDRESET 1 1263 #define MPTSAS_SUCCESS_MUR 2 1264 1265 /* 1266 * throttle support. 1267 */ 1268 #define MAX_THROTTLE 32 1269 #define HOLD_THROTTLE 0 1270 #define DRAIN_THROTTLE -1 1271 #define QFULL_THROTTLE -2 1272 1273 /* 1274 * Passthrough/config request flags 1275 */ 1276 #define MPTSAS_DATA_ALLOCATED 0x0001 1277 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1278 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1279 #define MPTSAS_ADDRESS_REPLY 0x0008 1280 #define MPTSAS_CMD_TIMEOUT 0x0010 1281 1282 /* 1283 * response code tlr flag 1284 */ 1285 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1286 1287 /* 1288 * System Events 1289 */ 1290 #ifndef DDI_VENDOR_LSI 1291 #define DDI_VENDOR_LSI "LSI" 1292 #endif /* DDI_VENDOR_LSI */ 1293 1294 /* 1295 * Shared functions 1296 */ 1297 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1298 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1299 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1300 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1301 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1302 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1303 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1304 uint8_t type, int mode); 1305 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1306 uint8_t type, int mode); 1307 int mptsas_download_firmware(); 1308 int mptsas_can_download_firmware(); 1309 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1310 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1311 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1312 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1313 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1314 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1315 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1316 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1317 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1318 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1319 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1320 uint32_t mptsas_hirrd(mptsas_t *mpt, uint32_t *regaddr); 1321 1322 /* 1323 * impl functions 1324 */ 1325 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1326 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1327 int mptsas_ioc_reset(mptsas_t *mpt, int); 1328 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1329 ddi_acc_handle_t accessp); 1330 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1331 ddi_acc_handle_t accessp); 1332 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1333 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1334 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1335 uint64_t SGEaddress); 1336 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1337 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1338 uint8_t pageversion, uint16_t extpagelength, 1339 uint32_t SGEflagslength, uint64_t SGEaddress); 1340 1341 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1342 struct scsi_pkt **pkt); 1343 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1344 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1345 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1346 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1347 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1348 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1349 1350 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1351 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1352 int mode); 1353 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1354 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1355 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1356 int mptsas_restart_ioc(mptsas_t *mpt); 1357 void mptsas_update_driver_data(struct mptsas *mpt); 1358 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1359 1360 /* 1361 * init functions 1362 */ 1363 int mptsas_ioc_get_facts(mptsas_t *mpt); 1364 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1365 int mptsas_ioc_enable_port(mptsas_t *mpt); 1366 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1367 int mptsas_ioc_init(mptsas_t *mpt); 1368 1369 /* 1370 * configuration pages operation 1371 */ 1372 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1373 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1374 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1375 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags); 1376 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1377 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1378 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1379 mptsas_smp_t *info); 1380 int mptsas_set_ioc_params(mptsas_t *mpt); 1381 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1382 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1383 uint64_t *sas_wwn, uint8_t *portwidth); 1384 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1385 int mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1386 smhba_info_t *info); 1387 int mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1388 smhba_info_t *info); 1389 int mptsas_get_manufacture_page0(mptsas_t *mpt); 1390 int mptsas_get_enclosure_page0(mptsas_t *mpt, uint32_t page_address, 1391 mptsas_enclosure_t *mpe); 1392 void mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1393 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1394 int mptsas_smhba_phy_init(mptsas_t *mpt); 1395 /* 1396 * RAID functions 1397 */ 1398 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1399 int mptsas_get_raid_info(mptsas_t *mpt); 1400 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1401 uint8_t physdisknum); 1402 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1403 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1404 1405 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1406 /* 1407 * debugging. 1408 * MPTSAS_DBGLOG_LINECNT must be a power of 2. 1409 */ 1410 #define MPTSAS_DBGLOG_LINECNT 128 1411 #define MPTSAS_DBGLOG_LINELEN 256 1412 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN) 1413 1414 #if defined(MPTSAS_DEBUG) 1415 1416 extern uint32_t mptsas_debugprt_flags; 1417 extern uint32_t mptsas_debuglog_flags; 1418 1419 void mptsas_printf(char *fmt, ...); 1420 void mptsas_debug_log(char *fmt, ...); 1421 1422 #define MPTSAS_DBGPR(m, args) \ 1423 if (mptsas_debugprt_flags & (m)) \ 1424 mptsas_printf args; \ 1425 if (mptsas_debuglog_flags & (m)) \ 1426 mptsas_debug_log args 1427 #else /* ! defined(MPTSAS_DEBUG) */ 1428 #define MPTSAS_DBGPR(m, args) 1429 #endif /* defined(MPTSAS_DEBUG) */ 1430 1431 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1432 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1433 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1434 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1435 1436 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1437 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1438 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1439 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1440 1441 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1442 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1443 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1444 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1445 1446 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1447 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1448 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1449 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */ 1450 1451 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */ 1452 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1453 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1454 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1455 1456 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1457 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1458 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1459 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1460 1461 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1462 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1463 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1464 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */ 1465 1466 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1467 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1468 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1469 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1470 1471 /* 1472 * auto request sense 1473 */ 1474 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1475 (pkt)->pkt_flags = (flag), \ 1476 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1477 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1478 (pkt)->pkt_address.a_lun 1479 1480 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1481 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1482 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1483 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1484 1485 1486 #ifdef __cplusplus 1487 } 1488 #endif 1489 1490 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1491