1 /*****************************************************************************
2
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *****************************************************************************/
33
34 #include "opt_inet.h"
35 #include "opt_inet6.h"
36 #include "opt_rss.h"
37
38 #include "ixgbe.h"
39 #include "mdio_if.h"
40 #include "ixgbe_sriov.h"
41 #include "ifdi_if.h"
42 #include "if_ix_mdio_hw.h"
43 #include "if_ix_mdio.h"
44
45 #include <net/netmap.h>
46 #include <dev/mdio/mdio.h>
47 #include <dev/netmap/netmap_kern.h>
48
49 /************************************************************************
50 * Driver version
51 ************************************************************************/
52 static const char ixgbe_driver_version[] = "5.0.1-k";
53
54 /* Bound one admin-task invocation while still coalescing new requests. */
55 #define IXGBE_ADMIN_TASK_BUDGET 8
56
57 /************************************************************************
58 * PCI Device ID Table
59 *
60 * Used by probe to select devices to load on
61 * Last field stores an index into ixgbe_strings
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
65 ************************************************************************/
66 static const pci_vendor_info_t ixgbe_vendor_info_array[] =
67 {
68 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT,
69 "Intel(R) 82598EB AF (Dual Fiber)"),
70 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT,
71 "Intel(R) 82598EB AF (Fiber)"),
72 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4,
73 "Intel(R) 82598EB AT (CX4)"),
74 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT,
75 "Intel(R) 82598EB AT"),
76 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2,
77 "Intel(R) 82598EB AT2"),
78 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598, "Intel(R) 82598"),
79 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT,
80 "Intel(R) 82598EB AF DA (Dual Fiber)"),
81 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT,
82 "Intel(R) 82598EB AT (Dual CX4)"),
83 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR,
84 "Intel(R) 82598EB AF (Dual Fiber LR)"),
85 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM,
86 "Intel(R) 82598EB AF (Dual Fiber SR)"),
87 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM,
88 "Intel(R) 82598EB LOM"),
89 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX,
90 "Intel(R) 82598EB BX Backplane"),
91 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4,
92 "Intel(R) X520 82599 (KX4)"),
93 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ,
94 "Intel(R) X520 82599 (KX4 Mezzanine)"),
95 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP,
96 "Intel(R) X520 82599ES (SFI/SFP+)"),
97 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR,
98 "Intel(R) X520 82599ES (KR Backplane)"),
99 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM,
100 "Intel(R) X520-P2 82599 (SFP+)"),
101 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM,
102 "Intel(R) X520 82599 (XAUI/BX4)"),
103 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4,
104 "Intel(R) X520 82599 (Dual CX4)"),
105 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM,
106 "Intel(R) X520-T 82599 LOM"),
107 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS,
108 "Intel(R) X520 82599 LS"),
109 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE,
110 "Intel(R) X520 82599 (Combined Backplane)"),
111 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE,
112 "Intel(R) X520 82599 (Backplane w/FCoE)"),
113 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2,
114 "Intel(R) X520 82599 (Dual SFP+)"),
115 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE,
116 "Intel(R) X520 82599 (Dual SFP+ w/FCoE)"),
117 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP,
118 "Intel(R) X520-1 82599EN (SFP+)"),
119 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP,
120 "Intel(R) X520-4 82599 (Quad SFP+)"),
121 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP,
122 "Intel(R) X520-Q1 82599 (QSFP+)"),
123 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T,
124 "Intel(R) X540-AT2"),
125 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"),
126 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"),
127 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"),
128 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR,
129 "Intel(R) X552 (KR Backplane)"),
130 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4,
131 "Intel(R) X552 (KX4 Backplane)"),
132 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T,
133 "Intel(R) X552/X557-AT (10GBASE-T)"),
134 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T,
135 "Intel(R) X552 (1000BASE-T)"),
136 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP,
137 "Intel(R) X552 (SFP+)"),
138 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI,
139 "Intel(R) X552 (XFI Backplane)"),
140 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR,
141 "Intel(R) X553 (KR Backplane)"),
142 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L,
143 "Intel(R) X553 L (KR Backplane)"),
144 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP,
145 "Intel(R) X553 (SFP+)"),
146 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N,
147 "Intel(R) X553 N (SFP+)"),
148 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP,
149 "Intel(R) X553 (QSFP+)"),
150 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N,
151 "Intel(R) X553 N (QSFP+)"),
152 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII,
153 "Intel(R) X553 (1GbE SGMII)"),
154 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L,
155 "Intel(R) X553 L (1GbE SGMII)"),
156 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T,
157 "Intel(R) X553/X557-AT (10GBASE-T)"),
158 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T,
159 "Intel(R) X553 (1GbE)"),
160 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L,
161 "Intel(R) X553 L (1GbE)"),
162 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_BYPASS,
163 "Intel(R) X540-T2 (Bypass)"),
164 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS,
165 "Intel(R) X520 82599 (Bypass)"),
166 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_BACKPLANE,
167 "Intel(R) E610 (Backplane)"),
168 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SFP,
169 "Intel(R) E610 (SFP)"),
170 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_2_5G_T,
171 "Intel(R) E610 (2.5 GbE)"),
172 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_10G_T,
173 "Intel(R) E610 (10 GbE)"),
174 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SGMII,
175 "Intel(R) E610 (SGMII)"),
176 /* required last entry */
177 PVID_END
178 };
179
180 static void *ixgbe_register(device_t);
181 static int ixgbe_if_attach_pre(if_ctx_t);
182 static int ixgbe_if_attach_post(if_ctx_t);
183 static int ixgbe_if_detach(if_ctx_t);
184 static int ixgbe_if_shutdown(if_ctx_t);
185 static int ixgbe_if_suspend(if_ctx_t);
186 static int ixgbe_if_resume(if_ctx_t);
187 #ifdef PCI_IOV
188 static int ixgbe_device_iov_init(device_t, uint16_t, const nvlist_t *);
189 #endif
190
191 static void ixgbe_if_stop(if_ctx_t);
192 void ixgbe_if_enable_intr(if_ctx_t);
193 static void ixgbe_if_disable_intr(if_ctx_t);
194 static void ixgbe_link_intr_enable(if_ctx_t);
195 static int ixgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
196 static void ixgbe_if_media_status(if_ctx_t, struct ifmediareq *);
197 static int ixgbe_if_media_change(if_ctx_t);
198 static int ixgbe_if_msix_intr_assign(if_ctx_t, int);
199 static int ixgbe_if_mtu_set(if_ctx_t, uint32_t);
200 static void ixgbe_if_crcstrip_set(if_ctx_t, int, int);
201 static void ixgbe_if_multi_set(if_ctx_t);
202 static int ixgbe_if_promisc_set(if_ctx_t, int);
203 static int ixgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
204 int);
205 static int ixgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
206 int);
207 static void ixgbe_if_queues_free(if_ctx_t);
208 static void ixgbe_if_timer(if_ctx_t, uint16_t);
209 static const char *ixgbe_link_speed_to_str(u32 link_speed);
210 static void ixgbe_if_update_admin_status(if_ctx_t);
211 static void ixgbe_if_vlan_register(if_ctx_t, u16);
212 static void ixgbe_if_vlan_unregister(if_ctx_t, u16);
213 static int ixgbe_if_i2c_req(if_ctx_t, struct ifi2creq *);
214 static bool ixgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
215 static void ixgbe_if_led_func(if_ctx_t, int);
216 static void ixgbe_led_restore(struct ixgbe_softc *);
217 int ixgbe_intr(void *);
218
219 static int ixgbe_if_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data);
220
221 /************************************************************************
222 * Function prototypes
223 ************************************************************************/
224 static uint64_t ixgbe_if_get_counter(if_ctx_t, ift_counter);
225
226 static void ixgbe_enable_queue(struct ixgbe_softc *, u32);
227 static void ixgbe_disable_queue(struct ixgbe_softc *, u32);
228 static void ixgbe_add_device_sysctls(if_ctx_t);
229 static int ixgbe_allocate_pci_resources(if_ctx_t);
230 static int ixgbe_setup_low_power_mode(if_ctx_t, bool);
231
232 static void ixgbe_config_dmac(struct ixgbe_softc *);
233 static void ixgbe_configure_ivars(struct ixgbe_softc *);
234 static void ixgbe_set_ivar(struct ixgbe_softc *, u8, u8, s8);
235 static u8 *ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *);
236 static bool ixgbe_sfp_probe(if_ctx_t);
237
238 static void ixgbe_free_pci_resources(if_ctx_t);
239
240 static int ixgbe_msix_link(void *);
241 static int ixgbe_msix_que(void *);
242 static void ixgbe_initialize_rss_mapping(struct ixgbe_softc *);
243 static void ixgbe_initialize_receive_units(if_ctx_t);
244 static void ixgbe_initialize_transmit_units(if_ctx_t);
245
246 static int ixgbe_setup_interface(if_ctx_t);
247 static void ixgbe_init_device_features(struct ixgbe_softc *);
248 static void ixgbe_check_fan_failure(struct ixgbe_softc *, u32, bool);
249 static void ixgbe_sbuf_fw_version(struct ixgbe_hw *, struct sbuf *);
250 static void ixgbe_print_fw_version(if_ctx_t);
251 static void ixgbe_add_media_types(if_ctx_t);
252 static void ixgbe_update_stats_counters(struct ixgbe_softc *);
253 static void ixgbe_config_link(if_ctx_t);
254 static void ixgbe_get_slot_info(struct ixgbe_softc *);
255 static void ixgbe_fw_mode_timer(void *);
256 static void ixgbe_configure_wakeup(if_ctx_t);
257 static void ixgbe_configure_wakeup_mta(if_ctx_t);
258 static void ixgbe_prepare_wakeup(if_ctx_t, bool);
259 static void ixgbe_enable_rx_drop(struct ixgbe_softc *);
260 static void ixgbe_disable_rx_drop(struct ixgbe_softc *);
261
262 static void ixgbe_add_hw_stats(struct ixgbe_softc *);
263 static int ixgbe_set_flowcntl(struct ixgbe_softc *, int);
264 static int ixgbe_set_advertise(struct ixgbe_softc *, int);
265 static int ixgbe_get_default_advertise(struct ixgbe_softc *);
266 static void ixgbe_config_gpie(struct ixgbe_softc *);
267 static void ixgbe_config_delay_values(struct ixgbe_softc *);
268
269 static void ixgbe_add_debug_sysctls(struct ixgbe_softc *sc);
270 static void ixgbe_add_debug_dump_sysctls(struct ixgbe_softc *sc);
271 static int ixgbe_debug_dump_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd);
272 static u8 ixgbe_debug_dump_print_cluster(struct ixgbe_softc *sc,
273 struct sbuf *sbuf, u8 cluster_id);
274 static int ixgbe_nvm_access_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd);
275
276 /* Sysctl handlers */
277 static int ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS);
278 static int ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS);
279 static int ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS);
280 static int ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS);
281 static int ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS);
282 static int ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS);
283 static int ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
284 #ifdef IXGBE_DEBUG
285 static int ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS);
286 static int ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS);
287 #endif
288 static int ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS);
289 static int ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS);
290 static int ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS);
291 static int ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS);
292 static int ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS);
293 static int ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
294
295 static int ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS);
296 static int ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS);
297
298 /* Deferred interrupt tasklets */
299 static void ixgbe_handle_msf(void *);
300 static bool ixgbe_handle_mod(void *);
301 static void ixgbe_handle_phy(void *);
302 static u32 ixgbe_handle_fw_event(void *);
303
304 static int ixgbe_enable_lse(struct ixgbe_softc *sc);
305 static int ixgbe_disable_lse(struct ixgbe_softc *sc);
306
307 /************************************************************************
308 * FreeBSD Device Interface Entry Points
309 ************************************************************************/
310 static device_method_t ix_methods[] = {
311 /* Device interface */
312 DEVMETHOD(device_register, ixgbe_register),
313 DEVMETHOD(device_probe, iflib_device_probe),
314 DEVMETHOD(device_attach, iflib_device_attach),
315 DEVMETHOD(device_detach, iflib_device_detach),
316 DEVMETHOD(device_shutdown, iflib_device_shutdown),
317 DEVMETHOD(device_suspend, iflib_device_suspend),
318 DEVMETHOD(device_resume, iflib_device_resume),
319 #ifdef PCI_IOV
320 DEVMETHOD(pci_iov_init, ixgbe_device_iov_init),
321 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit_restart),
322 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf),
323 #endif /* PCI_IOV */
324 DEVMETHOD(bus_add_child, device_add_child_ordered),
325 DEVMETHOD(mdio_readreg, ixgbe_mdio_readreg_c22),
326 DEVMETHOD(mdio_writereg, ixgbe_mdio_writereg_c22),
327
328 DEVMETHOD_END
329 };
330
331 static driver_t ix_driver = {
332 "ix", ix_methods, sizeof(struct ixgbe_softc),
333 };
334
335 DRIVER_MODULE(mdio, ix, mdio_driver, 0, 0); /* needs to happen before ix */
336 DRIVER_MODULE_ORDERED(ix, pci, ix_driver, NULL, NULL, SI_ORDER_ANY); /* needs to be last */
337 IFLIB_PNP_INFO(pci, ix_driver, ixgbe_vendor_info_array);
338 MODULE_DEPEND(ix, pci, 1, 1, 1);
339 MODULE_DEPEND(ix, ether, 1, 1, 1);
340 MODULE_DEPEND(ix, iflib, 1, 1, 1);
341 MODULE_DEPEND(ix, mdio, 1, 1, 1);
342
343 #ifdef PCI_IOV
344 static int
ixgbe_device_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * params)345 ixgbe_device_iov_init(device_t dev, uint16_t num_vfs,
346 const nvlist_t *params)
347 {
348 struct ixgbe_softc *sc;
349 if_ctx_t ctx;
350 int error;
351
352 ctx = device_get_softc(dev);
353 sc = iflib_get_softc(ctx);
354 error = ixgbe_iov_validate(sc, num_vfs);
355 if (error != 0)
356 return (error);
357 return (iflib_device_iov_init_restart(dev, num_vfs, params));
358 }
359 #endif
360
361 static device_method_t ixgbe_if_methods[] = {
362 DEVMETHOD(ifdi_attach_pre, ixgbe_if_attach_pre),
363 DEVMETHOD(ifdi_attach_post, ixgbe_if_attach_post),
364 DEVMETHOD(ifdi_detach, ixgbe_if_detach),
365 DEVMETHOD(ifdi_shutdown, ixgbe_if_shutdown),
366 DEVMETHOD(ifdi_suspend, ixgbe_if_suspend),
367 DEVMETHOD(ifdi_resume, ixgbe_if_resume),
368 DEVMETHOD(ifdi_init, ixgbe_if_init),
369 DEVMETHOD(ifdi_stop, ixgbe_if_stop),
370 DEVMETHOD(ifdi_msix_intr_assign, ixgbe_if_msix_intr_assign),
371 DEVMETHOD(ifdi_intr_enable, ixgbe_if_enable_intr),
372 DEVMETHOD(ifdi_intr_disable, ixgbe_if_disable_intr),
373 DEVMETHOD(ifdi_link_intr_enable, ixgbe_link_intr_enable),
374 DEVMETHOD(ifdi_tx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable),
375 DEVMETHOD(ifdi_rx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable),
376 DEVMETHOD(ifdi_tx_queues_alloc, ixgbe_if_tx_queues_alloc),
377 DEVMETHOD(ifdi_rx_queues_alloc, ixgbe_if_rx_queues_alloc),
378 DEVMETHOD(ifdi_queues_free, ixgbe_if_queues_free),
379 DEVMETHOD(ifdi_update_admin_status, ixgbe_if_update_admin_status),
380 DEVMETHOD(ifdi_multi_set, ixgbe_if_multi_set),
381 DEVMETHOD(ifdi_mtu_set, ixgbe_if_mtu_set),
382 DEVMETHOD(ifdi_crcstrip_set, ixgbe_if_crcstrip_set),
383 DEVMETHOD(ifdi_media_status, ixgbe_if_media_status),
384 DEVMETHOD(ifdi_media_change, ixgbe_if_media_change),
385 DEVMETHOD(ifdi_promisc_set, ixgbe_if_promisc_set),
386 DEVMETHOD(ifdi_timer, ixgbe_if_timer),
387 DEVMETHOD(ifdi_vlan_register, ixgbe_if_vlan_register),
388 DEVMETHOD(ifdi_vlan_unregister, ixgbe_if_vlan_unregister),
389 DEVMETHOD(ifdi_get_counter, ixgbe_if_get_counter),
390 DEVMETHOD(ifdi_i2c_req, ixgbe_if_i2c_req),
391 DEVMETHOD(ifdi_needs_restart, ixgbe_if_needs_restart),
392 DEVMETHOD(ifdi_priv_ioctl, ixgbe_if_priv_ioctl),
393 DEVMETHOD(ifdi_led_func, ixgbe_if_led_func),
394 #ifdef PCI_IOV
395 DEVMETHOD(ifdi_iov_init, ixgbe_if_iov_init),
396 DEVMETHOD(ifdi_iov_uninit, ixgbe_if_iov_uninit),
397 DEVMETHOD(ifdi_iov_vf_add, ixgbe_if_iov_vf_add),
398 #endif /* PCI_IOV */
399 DEVMETHOD_END
400 };
401
402 /*
403 * TUNEABLE PARAMETERS:
404 */
405
406 static SYSCTL_NODE(_hw, OID_AUTO, ix, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
407 "IXGBE driver parameters");
408 static driver_t ixgbe_if_driver = {
409 "ixgbe_if", ixgbe_if_methods, sizeof(struct ixgbe_softc)
410 };
411
412 static int ixgbe_max_interrupt_rate = (4000000 / IXGBE_LOW_LATENCY);
413 SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
414 &ixgbe_max_interrupt_rate, 0, "Maximum interrupts per second");
415
416 /* Flow control setting, default to full */
417 static int ixgbe_flow_control = ixgbe_fc_full;
418 SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN,
419 &ixgbe_flow_control, 0, "Default flow control used for all adapters");
420
421 /* Advertise Speed, default to 0 (auto) */
422 static int ixgbe_advertise_speed = 0;
423 SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN,
424 &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters");
425
426 /*
427 * Smart speed setting, default to on
428 * this only works as a compile option
429 * right now as its during attach, set
430 * this to 'ixgbe_smart_speed_off' to
431 * disable.
432 */
433 static int ixgbe_smart_speed = ixgbe_smart_speed_on;
434
435 /*
436 * MSI-X should be the default for best performance,
437 * but this allows it to be forced off for testing.
438 */
439 static int ixgbe_enable_msix = 1;
440 SYSCTL_INT(_hw_ix, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixgbe_enable_msix,
441 0,
442 "Enable MSI-X interrupts");
443
444 /*
445 * Defining this on will allow the use
446 * of unsupported SFP+ modules, note that
447 * doing so you are on your own :)
448 */
449 static int allow_unsupported_sfp = false;
450 SYSCTL_INT(_hw_ix, OID_AUTO, unsupported_sfp, CTLFLAG_RDTUN,
451 &allow_unsupported_sfp, 0,
452 "Allow unsupported SFP modules...use at your own risk");
453
454 /*
455 * Not sure if Flow Director is fully baked,
456 * so we'll default to turning it off.
457 */
458 static int ixgbe_enable_fdir = 0;
459 SYSCTL_INT(_hw_ix, OID_AUTO, enable_fdir, CTLFLAG_RDTUN, &ixgbe_enable_fdir,
460 0,
461 "Enable Flow Director");
462
463 /* Receive-Side Scaling */
464 static int ixgbe_enable_rss = 1;
465 SYSCTL_INT(_hw_ix, OID_AUTO, enable_rss, CTLFLAG_RDTUN, &ixgbe_enable_rss,
466 0,
467 "Enable Receive-Side Scaling (RSS)");
468
469 /*
470 * AIM: Adaptive Interrupt Moderation
471 * which means that the interrupt rate
472 * is varied over time based on the
473 * traffic for that interrupt vector
474 */
475 static int ixgbe_enable_aim = false;
476 SYSCTL_INT(_hw_ix, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &ixgbe_enable_aim,
477 0,
478 "Enable adaptive interrupt moderation");
479
480 #if 0
481 /* Keep running tab on them for sanity check */
482 static int ixgbe_total_ports;
483 #endif
484
485 MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations");
486
487 /*
488 * For Flow Director: this is the number of TX packets we sample
489 * for the filter pool, this means every 20th packet will be probed.
490 *
491 * This feature can be disabled by setting this to 0.
492 */
493 static int atr_sample_rate = 20;
494
495 extern struct if_txrx ixgbe_txrx;
496
497 static struct if_shared_ctx ixgbe_sctx_init = {
498 .isc_magic = IFLIB_MAGIC,
499 .isc_q_align = PAGE_SIZE,/* max(DBA_ALIGN, PAGE_SIZE) */
500 .isc_tx_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header),
501 .isc_tx_maxsegsize = PAGE_SIZE,
502 .isc_tso_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header),
503 .isc_tso_maxsegsize = PAGE_SIZE,
504 .isc_rx_maxsize = PAGE_SIZE*4,
505 .isc_rx_nsegments = 1,
506 .isc_rx_maxsegsize = PAGE_SIZE*4,
507 .isc_nfl = 1,
508 .isc_ntxqs = 1,
509 .isc_nrxqs = 1,
510
511 .isc_admin_intrcnt = 1,
512 .isc_vendor_info = ixgbe_vendor_info_array,
513 .isc_driver_version = ixgbe_driver_version,
514 .isc_driver = &ixgbe_if_driver,
515 .isc_flags = IFLIB_TSO_INIT_IP,
516
517 .isc_nrxd_min = {MIN_RXD},
518 .isc_ntxd_min = {MIN_TXD},
519 .isc_nrxd_max = {MAX_RXD},
520 .isc_ntxd_max = {MAX_TXD},
521 .isc_nrxd_default = {DEFAULT_RXD},
522 .isc_ntxd_default = {DEFAULT_TXD},
523 };
524
525 /************************************************************************
526 * ixgbe_if_tx_queues_alloc
527 ************************************************************************/
528 static int
ixgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)529 ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
530 int ntxqs, int ntxqsets)
531 {
532 struct ixgbe_softc *sc = iflib_get_softc(ctx);
533 if_softc_ctx_t scctx = sc->shared;
534 struct ix_tx_queue *que;
535 int i, j, error;
536
537 MPASS(sc->num_tx_queues > 0);
538 MPASS(sc->num_tx_queues == ntxqsets);
539 MPASS(ntxqs == 1);
540
541 /* Allocate queue structure memory */
542 sc->tx_queues =
543 (struct ix_tx_queue *)malloc(sizeof(struct ix_tx_queue) *
544 ntxqsets, M_IXGBE, M_NOWAIT | M_ZERO);
545 if (!sc->tx_queues) {
546 device_printf(iflib_get_dev(ctx),
547 "Unable to allocate TX ring memory\n");
548 return (ENOMEM);
549 }
550
551 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) {
552 struct tx_ring *txr = &que->txr;
553
554 /* In case SR-IOV is enabled, align the index properly */
555 txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i);
556
557 txr->sc = que->sc = sc;
558
559 /* Allocate report status array */
560 txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) *
561 scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO);
562 if (txr->tx_rsq == NULL) {
563 error = ENOMEM;
564 goto fail;
565 }
566 for (j = 0; j < scctx->isc_ntxd[0]; j++)
567 txr->tx_rsq[j] = QIDX_INVALID;
568 /* get virtual and physical address of the hardware queues */
569 txr->tail = IXGBE_TDT(txr->me);
570 txr->tx_base = (union ixgbe_adv_tx_desc *)vaddrs[i];
571 txr->tx_paddr = paddrs[i];
572
573 txr->bytes = 0;
574 txr->total_packets = 0;
575
576 /* Set the rate at which we sample packets */
577 if (sc->feat_en & IXGBE_FEATURE_FDIR)
578 txr->atr_sample = atr_sample_rate;
579
580 }
581
582 device_printf(iflib_get_dev(ctx), "allocated for %d queues\n",
583 sc->num_tx_queues);
584
585 return (0);
586
587 fail:
588 ixgbe_if_queues_free(ctx);
589
590 return (error);
591 } /* ixgbe_if_tx_queues_alloc */
592
593 /************************************************************************
594 * ixgbe_if_rx_queues_alloc
595 ************************************************************************/
596 static int
ixgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)597 ixgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
598 int nrxqs, int nrxqsets)
599 {
600 struct ixgbe_softc *sc = iflib_get_softc(ctx);
601 struct ix_rx_queue *que;
602 int i;
603
604 MPASS(sc->num_rx_queues > 0);
605 MPASS(sc->num_rx_queues == nrxqsets);
606 MPASS(nrxqs == 1);
607
608 /* Allocate queue structure memory */
609 sc->rx_queues =
610 (struct ix_rx_queue *)malloc(sizeof(struct ix_rx_queue)*nrxqsets,
611 M_IXGBE, M_NOWAIT | M_ZERO);
612 if (!sc->rx_queues) {
613 device_printf(iflib_get_dev(ctx),
614 "Unable to allocate TX ring memory\n");
615 return (ENOMEM);
616 }
617
618 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
619 struct rx_ring *rxr = &que->rxr;
620
621 /* In case SR-IOV is enabled, align the index properly */
622 rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i);
623
624 rxr->sc = que->sc = sc;
625
626 /* get the virtual and physical address of the hw queues */
627 rxr->tail = IXGBE_RDT(rxr->me);
628 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i];
629 rxr->rx_paddr = paddrs[i];
630 rxr->bytes = 0;
631 rxr->que = que;
632 }
633
634 device_printf(iflib_get_dev(ctx), "allocated for %d rx queues\n",
635 sc->num_rx_queues);
636
637 return (0);
638 } /* ixgbe_if_rx_queues_alloc */
639
640 /************************************************************************
641 * ixgbe_if_queues_free
642 ************************************************************************/
643 static void
ixgbe_if_queues_free(if_ctx_t ctx)644 ixgbe_if_queues_free(if_ctx_t ctx)
645 {
646 struct ixgbe_softc *sc = iflib_get_softc(ctx);
647 struct ix_tx_queue *tx_que = sc->tx_queues;
648 struct ix_rx_queue *rx_que = sc->rx_queues;
649 int i;
650
651 if (tx_que != NULL) {
652 for (i = 0; i < sc->num_tx_queues; i++, tx_que++) {
653 struct tx_ring *txr = &tx_que->txr;
654 if (txr->tx_rsq == NULL)
655 break;
656
657 free(txr->tx_rsq, M_IXGBE);
658 txr->tx_rsq = NULL;
659 }
660
661 free(sc->tx_queues, M_IXGBE);
662 sc->tx_queues = NULL;
663 }
664 if (rx_que != NULL) {
665 free(sc->rx_queues, M_IXGBE);
666 sc->rx_queues = NULL;
667 }
668 } /* ixgbe_if_queues_free */
669
670 /************************************************************************
671 * ixgbe_initialize_rss_mapping
672 ************************************************************************/
673 static void
ixgbe_initialize_rss_mapping(struct ixgbe_softc * sc)674 ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc)
675 {
676 struct ixgbe_hw *hw = &sc->hw;
677 bool per_pool_rss;
678 u32 reta = 0, mrqc, rss_fields, rss_key[10];
679 int i, index_mult, j, queue_id, reta_queues, table_size;
680 u32 rss_hash_config;
681 #ifdef PCI_IOV
682 u32 pfmrqc;
683 #endif
684
685 if (sc->feat_en & IXGBE_FEATURE_RSS) {
686 /* Fetch the configured RSS key */
687 rss_getkey((uint8_t *)&rss_key);
688 } else {
689 /* set up random bits */
690 arc4rand(&rss_key, sizeof(rss_key), 0);
691 }
692
693 /* Set multiplier for RETA setup and table size based on MAC */
694 index_mult = 0x1;
695 per_pool_rss = false;
696 table_size = 128;
697 switch (sc->hw.mac.type) {
698 case ixgbe_mac_82598EB:
699 index_mult = 0x11;
700 break;
701 case ixgbe_mac_X550:
702 case ixgbe_mac_X550EM_x:
703 case ixgbe_mac_X550EM_a:
704 case ixgbe_mac_E610:
705 table_size = 512;
706 #ifdef PCI_IOV
707 if (sc->iov_mode != IXGBE_NO_VM) {
708 per_pool_rss = true;
709 table_size = 64;
710 }
711 #endif
712 break;
713 default:
714 break;
715 }
716
717 /*
718 * The global RETA is shared by the PF and VFs on 82599 and X540.
719 * X550-family devices instead use per-pool tables in multiple-RSS
720 * mode; initialize only the PF pool here because each VF owns and
721 * programs its own key and redirection table.
722 * On the shared tables, program all four queue indices while SR-IOV
723 * is active so a VF can use its full queue grant even when the PF uses
724 * fewer queues. PSRTYPE.RQPL limits the subset selected in each pool.
725 */
726 reta_queues = sc->num_rx_queues;
727 #ifdef PCI_IOV
728 if (sc->iov_mode != IXGBE_NO_VM && !per_pool_rss)
729 reta_queues = MAX(reta_queues, 4);
730 #endif
731
732 /* Set up the redirection table */
733 for (i = 0, j = 0; i < table_size; i++, j++) {
734 if (j == reta_queues)
735 j = 0;
736
737 if (sc->feat_en & IXGBE_FEATURE_RSS) {
738 /*
739 * Fetch the RSS bucket id for the given indirection
740 * entry. Cap it at the number of queue indices that must
741 * be represented in the shared table.
742 */
743 queue_id = rss_get_indirection_to_bucket(i);
744 queue_id = queue_id % reta_queues;
745 } else
746 queue_id = (j * index_mult);
747
748 /*
749 * The low 8 bits are for hash value (n+0);
750 * The next 8 bits are for hash value (n+1), etc.
751 */
752 reta = reta >> 8;
753 reta = reta | (((uint32_t)queue_id) << 24);
754 if ((i & 3) == 3) {
755 if (per_pool_rss) {
756 #ifdef PCI_IOV
757 IXGBE_WRITE_REG(hw,
758 IXGBE_PFVFRETA(i >> 2, sc->pool), reta);
759 #endif
760 } else if (i < 128)
761 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
762 else
763 IXGBE_WRITE_REG(hw,
764 IXGBE_ERETA((i >> 2) - 32), reta);
765 reta = 0;
766 }
767 }
768
769 /* Now fill our hash function seeds */
770 for (i = 0; i < 10; i++) {
771 if (per_pool_rss) {
772 #ifdef PCI_IOV
773 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, sc->pool),
774 rss_key[i]);
775 #endif
776 } else
777 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]);
778 }
779
780 /* Perform hash on these packet types */
781 if (sc->feat_en & IXGBE_FEATURE_RSS)
782 rss_hash_config = rss_gethashconfig();
783 else {
784 /*
785 * Disable UDP - IP fragments aren't currently being handled
786 * and so we end up with a mix of 2-tuple and 4-tuple
787 * traffic.
788 */
789 rss_hash_config = RSS_HASHTYPE_RSS_IPV4 |
790 RSS_HASHTYPE_RSS_TCP_IPV4 |
791 RSS_HASHTYPE_RSS_IPV6 |
792 RSS_HASHTYPE_RSS_TCP_IPV6 |
793 RSS_HASHTYPE_RSS_IPV6_EX |
794 RSS_HASHTYPE_RSS_TCP_IPV6_EX;
795 }
796
797 mrqc = ixgbe_get_mrqc(sc->iov_mode);
798 rss_fields = 0;
799 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
800 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4;
801 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
802 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
803 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6)
804 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6;
805 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6)
806 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
807 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX)
808 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
809 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX)
810 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
811 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
812 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
813 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6)
814 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
815 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX)
816 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
817 if (hw->mac.type == ixgbe_mac_E610) {
818 /* E610 folds IPv6 extension headers into the base selectors. */
819 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
820 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6;
821 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
822 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
823 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
824 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
825 rss_fields &= ~(IXGBE_MRQC_RSS_FIELD_IPV6_EX |
826 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
827 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP);
828 }
829
830 if (per_pool_rss) {
831 #ifdef PCI_IOV
832 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
833 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
834
835 pfmrqc = IXGBE_MRQC_RSSEN | rss_fields;
836 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(sc->pool), pfmrqc);
837 #endif
838 } else {
839 mrqc |= rss_fields;
840 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
841 }
842 } /* ixgbe_initialize_rss_mapping */
843
844 /************************************************************************
845 * ixgbe_initialize_receive_units - Setup receive registers and features.
846 ************************************************************************/
847 #define BSIZEPKT_ROUNDUP ((1<<IXGBE_SRRCTL_BSIZEPKT_SHIFT)-1)
848
849 static void
ixgbe_initialize_receive_units(if_ctx_t ctx)850 ixgbe_initialize_receive_units(if_ctx_t ctx)
851 {
852 struct ixgbe_softc *sc = iflib_get_softc(ctx);
853 if_softc_ctx_t scctx = sc->shared;
854 struct ixgbe_hw *hw = &sc->hw;
855 if_t ifp = iflib_get_ifp(ctx);
856 struct ix_rx_queue *que;
857 int i, j;
858 u32 bufsz, fctrl, srrctl, rxcsum;
859 u32 hlreg;
860
861 /*
862 * Make sure receives are disabled while
863 * setting up the descriptor ring
864 */
865 ixgbe_disable_rx(hw);
866
867 /* Enable broadcasts */
868 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
869 fctrl |= IXGBE_FCTRL_BAM;
870 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
871 fctrl |= IXGBE_FCTRL_DPF;
872 fctrl |= IXGBE_FCTRL_PMCF;
873 }
874 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
875
876 /* Set for Jumbo Frames? */
877 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
878 if (if_getmtu(ifp) > ETHERMTU)
879 hlreg |= IXGBE_HLREG0_JUMBOEN;
880 else
881 hlreg &= ~IXGBE_HLREG0_JUMBOEN;
882 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg);
883
884 bufsz = (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
885 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
886
887 /* Setup the Base and Length of the Rx Descriptor Ring */
888 for (i = 0, que = sc->rx_queues; i < sc->num_rx_queues; i++, que++) {
889 struct rx_ring *rxr = &que->rxr;
890 u64 rdba = rxr->rx_paddr;
891
892 j = rxr->me;
893
894 /* Setup the Base and Length of the Rx Descriptor Ring */
895 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j),
896 (rdba & 0x00000000ffffffffULL));
897 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
898 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j),
899 scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc));
900
901 /* Set up the SRRCTL register */
902 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(j));
903 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
904 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
905 srrctl |= bufsz;
906 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
907
908 /*
909 * Set DROP_EN iff we have no flow control and >1 queue.
910 * Note that srrctl was cleared shortly before during reset,
911 * so we do not need to clear the bit, but do it just in case
912 * this code is moved elsewhere.
913 */
914 if (sc->num_rx_queues > 1 &&
915 sc->hw.fc.requested_mode == ixgbe_fc_none) {
916 srrctl |= IXGBE_SRRCTL_DROP_EN;
917 } else {
918 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
919 }
920
921 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl);
922
923 /* Setup the HW Rx Head and Tail Descriptor Pointers */
924 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
925 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
926
927 /* Set the driver rx tail address */
928 rxr->tail = IXGBE_RDT(rxr->me);
929 }
930
931 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
932 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
933 IXGBE_PSRTYPE_UDPHDR |
934 IXGBE_PSRTYPE_IPV4HDR |
935 IXGBE_PSRTYPE_IPV6HDR;
936
937 /*
938 * In VMDq+RSS mode PSRTYPE is per pool, and RQPL controls
939 * how many receive queues RSS may select within that pool.
940 * The PF occupies the last pool rather than pool zero.
941 */
942 #ifdef PCI_IOV
943 if (sc->iov_mode != IXGBE_NO_VM) {
944 if (sc->num_rx_queues > 3)
945 psrtype |= 2u << IXGBE_PSRTYPE_RQPL_SHIFT;
946 else if (sc->num_rx_queues > 1)
947 psrtype |= 1u << IXGBE_PSRTYPE_RQPL_SHIFT;
948 }
949 #endif
950 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(sc->pool), psrtype);
951 }
952
953 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
954
955 ixgbe_initialize_rss_mapping(sc);
956
957 if (sc->feat_en & IXGBE_FEATURE_RSS) {
958 /* RSS and RX IPP Checksum are mutually exclusive */
959 rxcsum |= IXGBE_RXCSUM_PCSD;
960 }
961
962 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
963 rxcsum |= IXGBE_RXCSUM_PCSD;
964
965 /* This is useful for calculating UDP/IP fragment checksums */
966 if (!(rxcsum & IXGBE_RXCSUM_PCSD))
967 rxcsum |= IXGBE_RXCSUM_IPPCSE;
968
969 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
970
971 } /* ixgbe_initialize_receive_units */
972
973 /************************************************************************
974 * ixgbe_initialize_transmit_units - Enable transmit units.
975 ************************************************************************/
976 static void
ixgbe_initialize_transmit_units(if_ctx_t ctx)977 ixgbe_initialize_transmit_units(if_ctx_t ctx)
978 {
979 struct ixgbe_softc *sc = iflib_get_softc(ctx);
980 struct ixgbe_hw *hw = &sc->hw;
981 if_softc_ctx_t scctx = sc->shared;
982 struct ix_tx_queue *que;
983 int i;
984
985 /* Setup the Base and Length of the Tx Descriptor Ring */
986 for (i = 0, que = sc->tx_queues; i < sc->num_tx_queues;
987 i++, que++) {
988 struct tx_ring *txr = &que->txr;
989 u64 tdba = txr->tx_paddr;
990 u32 txctrl = 0;
991 int j = txr->me;
992
993 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
994 (tdba & 0x00000000ffffffffULL));
995 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
996 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j),
997 scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc));
998
999 /* Setup the HW Tx Head and Tail descriptor pointers */
1000 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1001 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1002
1003 /* Cache the tail address */
1004 txr->tail = IXGBE_TDT(txr->me);
1005
1006 txr->tx_rs_cidx = txr->tx_rs_pidx;
1007 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1008 for (int k = 0; k < scctx->isc_ntxd[0]; k++)
1009 txr->tx_rsq[k] = QIDX_INVALID;
1010
1011 /* Disable Head Writeback */
1012 /*
1013 * Note: for X550 series devices, these registers are actually
1014 * prefixed with TPH_ isntead of DCA_, but the addresses and
1015 * fields remain the same.
1016 */
1017 switch (hw->mac.type) {
1018 case ixgbe_mac_82598EB:
1019 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1020 break;
1021 default:
1022 txctrl =
1023 IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1024 break;
1025 }
1026 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1027 switch (hw->mac.type) {
1028 case ixgbe_mac_82598EB:
1029 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1030 break;
1031 default:
1032 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j),
1033 txctrl);
1034 break;
1035 }
1036
1037 }
1038
1039 if (hw->mac.type != ixgbe_mac_82598EB) {
1040 u32 dmatxctl, rttdcs;
1041
1042 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1043 dmatxctl |= IXGBE_DMATXCTL_TE;
1044 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
1045 /* Disable arbiter to set MTQC */
1046 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1047 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1048 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1049 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
1050 ixgbe_get_mtqc(sc->iov_mode));
1051 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1052 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1053 }
1054
1055 } /* ixgbe_initialize_transmit_units */
1056
1057 static int
ixgbe_check_fw_api_version(struct ixgbe_softc * sc)1058 ixgbe_check_fw_api_version(struct ixgbe_softc *sc)
1059 {
1060 struct ixgbe_hw *hw = &sc->hw;
1061 if (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) {
1062 device_printf(sc->dev,
1063 "The driver for the device stopped because the NVM "
1064 "image is newer than expected. You must install the "
1065 "most recent version of the network driver.\n");
1066 return (EOPNOTSUPP);
1067 } else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR &&
1068 hw->api_min_ver > (IXGBE_FW_API_VER_MINOR + 2)) {
1069 device_printf(sc->dev,
1070 "The driver for the device detected a newer version of "
1071 "the NVM image than expected. Please install the most "
1072 "recent version of the network driver.\n");
1073 } else if (hw->api_maj_ver < IXGBE_FW_API_VER_MAJOR ||
1074 hw->api_min_ver < IXGBE_FW_API_VER_MINOR - 2) {
1075 device_printf(sc->dev,
1076 "The driver for the device detected an older version "
1077 "of the NVM image than expected. "
1078 "Please update the NVM image.\n");
1079 }
1080 return (0);
1081 }
1082
1083 /************************************************************************
1084 * ixgbe_register
1085 ************************************************************************/
1086 static void *
ixgbe_register(device_t dev)1087 ixgbe_register(device_t dev)
1088 {
1089 return (&ixgbe_sctx_init);
1090 } /* ixgbe_register */
1091
1092 /************************************************************************
1093 * ixgbe_if_attach_pre - Device initialization routine, part 1
1094 *
1095 * Called when the driver is being loaded.
1096 * Identifies the type of hardware, initializes the hardware,
1097 * and initializes iflib structures.
1098 *
1099 * return 0 on success, positive on failure
1100 ************************************************************************/
1101 static int
ixgbe_if_attach_pre(if_ctx_t ctx)1102 ixgbe_if_attach_pre(if_ctx_t ctx)
1103 {
1104 struct ixgbe_softc *sc;
1105 device_t dev;
1106 if_softc_ctx_t scctx;
1107 struct ixgbe_hw *hw;
1108 int error = 0;
1109 u32 ctrl_ext;
1110 size_t i;
1111
1112 INIT_DEBUGOUT("ixgbe_attach: begin");
1113
1114 /* Allocate, clear, and link in our adapter structure */
1115 dev = iflib_get_dev(ctx);
1116 sc = iflib_get_softc(ctx);
1117 sc->hw.back = sc;
1118 sc->ctx = ctx;
1119 sc->dev = dev;
1120 scctx = sc->shared = iflib_get_softc_ctx(ctx);
1121 sc->media = iflib_get_media(ctx);
1122 hw = &sc->hw;
1123
1124 /* Determine hardware revision */
1125 hw->vendor_id = pci_get_vendor(dev);
1126 hw->device_id = pci_get_device(dev);
1127 hw->revision_id = pci_get_revid(dev);
1128 hw->subsystem_vendor_id = pci_get_subvendor(dev);
1129 hw->subsystem_device_id = pci_get_subdevice(dev);
1130
1131 /* Do base PCI setup - map BAR0 */
1132 if (ixgbe_allocate_pci_resources(ctx)) {
1133 device_printf(dev, "Allocation of PCI resources failed\n");
1134 return (ENXIO);
1135 }
1136
1137 /* let hardware know driver is loaded */
1138 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1139 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1140 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1141
1142 /*
1143 * Initialize the shared code
1144 */
1145 if (ixgbe_init_shared_code(hw) != 0) {
1146 device_printf(dev, "Unable to initialize the shared code\n");
1147 error = ENXIO;
1148 goto err_pci;
1149 }
1150
1151 if (hw->mac.type == ixgbe_mac_E610)
1152 ixgbe_init_aci(hw);
1153
1154 sc->do_debug_dump = false;
1155
1156 if (hw->mac.ops.fw_recovery_mode &&
1157 hw->mac.ops.fw_recovery_mode(hw)) {
1158 device_printf(dev,
1159 "Firmware recovery mode detected. Limiting "
1160 "functionality.\nRefer to the Intel(R) Ethernet Adapters "
1161 "and Devices User Guide for details on firmware recovery "
1162 "mode.");
1163 error = ENOSYS;
1164 goto err_pci;
1165 }
1166
1167 /* 82598 Does not support SR-IOV, initialize everything else */
1168 if (hw->mac.type >= ixgbe_mac_82599_vf) {
1169 for (i = 0; i < sc->num_vfs; i++)
1170 hw->mbx.ops[i].init_params(hw);
1171 }
1172
1173 hw->allow_unsupported_sfp = allow_unsupported_sfp;
1174
1175 if (hw->mac.type != ixgbe_mac_82598EB)
1176 hw->phy.smart_speed = ixgbe_smart_speed;
1177
1178 ixgbe_init_device_features(sc);
1179
1180 /* Verify adapter fan is still functional (if applicable) */
1181 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) {
1182 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1183 ixgbe_check_fan_failure(sc, esdp, false);
1184 }
1185
1186 /* Ensure SW/FW semaphore is free */
1187 ixgbe_init_swfw_semaphore(hw);
1188
1189 /* Enable EEE power saving */
1190 if (sc->feat_en & IXGBE_FEATURE_EEE)
1191 hw->mac.ops.setup_eee(hw, true);
1192
1193 /* Set an initial default flow control value */
1194 hw->fc.requested_mode = ixgbe_flow_control;
1195
1196 hw->phy.reset_if_overtemp = true;
1197 error = ixgbe_reset_hw(hw);
1198 hw->phy.reset_if_overtemp = false;
1199 if (error == IXGBE_ERR_SFP_NOT_PRESENT) {
1200 /*
1201 * No optics in this port, set up
1202 * so the timer routine will probe
1203 * for later insertion.
1204 */
1205 sc->sfp_probe = true;
1206 error = 0;
1207 } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1208 device_printf(dev, "Unsupported SFP+ module detected!\n");
1209 error = EIO;
1210 goto err_pci;
1211 } else if (error) {
1212 device_printf(dev, "Hardware initialization failed\n");
1213 error = EIO;
1214 goto err_pci;
1215 }
1216
1217 /* Make sure we have a good EEPROM before we read from it */
1218 if (ixgbe_validate_eeprom_checksum(&sc->hw, NULL) < 0) {
1219 device_printf(dev, "The EEPROM Checksum Is Not Valid\n");
1220 error = EIO;
1221 goto err_pci;
1222 }
1223
1224 error = ixgbe_start_hw(hw);
1225 switch (error) {
1226 case IXGBE_ERR_EEPROM_VERSION:
1227 device_printf(dev,
1228 "This device is a pre-production adapter/LOM. Please be"
1229 " aware there may be issues associated with your"
1230 " hardware.\nIf you are experiencing problems please"
1231 " contact your Intel or hardware representative who"
1232 " provided you with this hardware.\n");
1233 break;
1234 case IXGBE_ERR_SFP_NOT_SUPPORTED:
1235 device_printf(dev, "Unsupported SFP+ Module\n");
1236 error = EIO;
1237 goto err_pci;
1238 case IXGBE_ERR_SFP_NOT_PRESENT:
1239 device_printf(dev, "No SFP+ Module found\n");
1240 /* falls thru */
1241 default:
1242 break;
1243 }
1244
1245 /* Check the FW API version and enable FW logging support for E610 */
1246 if (hw->mac.type == ixgbe_mac_E610) {
1247 if (ixgbe_check_fw_api_version(sc)) {
1248 error = EIO;
1249 goto err_pci;
1250 }
1251 ixgbe_fwlog_set_support_ena(hw);
1252 }
1253
1254 /* Most of the iflib initialization... */
1255
1256 iflib_set_mac(ctx, hw->mac.addr);
1257 switch (sc->hw.mac.type) {
1258 case ixgbe_mac_X550:
1259 case ixgbe_mac_X550EM_x:
1260 case ixgbe_mac_X550EM_a:
1261 scctx->isc_rss_table_size = 512;
1262 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 64;
1263 break;
1264 default:
1265 scctx->isc_rss_table_size = 128;
1266 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 16;
1267 }
1268
1269 /* Allow legacy interrupts */
1270 ixgbe_txrx.ift_legacy_intr = ixgbe_intr;
1271
1272 scctx->isc_txqsizes[0] =
1273 roundup2(scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc) +
1274 sizeof(u32), DBA_ALIGN),
1275 scctx->isc_rxqsizes[0] =
1276 roundup2(scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc),
1277 DBA_ALIGN);
1278
1279 /* XXX */
1280 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO |
1281 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO;
1282 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
1283 scctx->isc_tx_nsegments = IXGBE_82598_SCATTER;
1284 } else {
1285 scctx->isc_tx_csum_flags |= CSUM_SCTP |CSUM_IP6_SCTP;
1286 scctx->isc_tx_nsegments = IXGBE_82599_SCATTER;
1287 }
1288
1289 scctx->isc_msix_bar = pci_msix_table_bar(dev);
1290
1291 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
1292 scctx->isc_tx_tso_size_max = IXGBE_TSO_SIZE;
1293 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
1294
1295 scctx->isc_txrx = &ixgbe_txrx;
1296
1297 scctx->isc_capabilities = scctx->isc_capenable = IXGBE_CAPS;
1298 ixgbe_configure_wakeup(ctx);
1299
1300 return (0);
1301
1302 err_pci:
1303 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
1304 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD;
1305 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
1306 ixgbe_free_pci_resources(ctx);
1307
1308 if (hw->mac.type == ixgbe_mac_E610)
1309 ixgbe_shutdown_aci(hw);
1310
1311 return (error);
1312 } /* ixgbe_if_attach_pre */
1313
1314 /*********************************************************************
1315 * ixgbe_if_attach_post - Device initialization routine, part 2
1316 *
1317 * Called during driver load, but after interrupts and
1318 * resources have been allocated and configured.
1319 * Sets up some data structures not relevant to iflib.
1320 *
1321 * return 0 on success, positive on failure
1322 *********************************************************************/
1323 static int
ixgbe_if_attach_post(if_ctx_t ctx)1324 ixgbe_if_attach_post(if_ctx_t ctx)
1325 {
1326 device_t dev;
1327 struct ixgbe_softc *sc;
1328 struct ixgbe_hw *hw;
1329 int error = 0;
1330
1331 dev = iflib_get_dev(ctx);
1332 sc = iflib_get_softc(ctx);
1333 hw = &sc->hw;
1334 ixgbe_init_iov_recovery(sc);
1335
1336 if (sc->intr_type == IFLIB_INTR_LEGACY &&
1337 (sc->feat_cap & IXGBE_FEATURE_LEGACY_IRQ) == 0) {
1338 device_printf(dev, "Device does not support legacy interrupts");
1339 error = ENXIO;
1340 goto err;
1341 }
1342
1343 /* Allocate multicast array memory. */
1344 sc->mta = malloc(sizeof(*sc->mta) * MAX_NUM_MULTICAST_ADDRESSES,
1345 M_IXGBE, M_NOWAIT);
1346 if (sc->mta == NULL) {
1347 device_printf(dev,
1348 "Can not allocate multicast setup array\n");
1349 error = ENOMEM;
1350 goto err;
1351 }
1352
1353 /* hw.ix defaults init */
1354 ixgbe_set_advertise(sc, ixgbe_advertise_speed);
1355
1356 /* Enable the optics for 82599 SFP+ fiber */
1357 ixgbe_enable_tx_laser(hw);
1358
1359 /* Enable power to the phy. */
1360 ixgbe_set_phy_power(hw, true);
1361
1362 ixgbe_initialize_iov(sc);
1363
1364 error = ixgbe_setup_interface(ctx);
1365 if (error) {
1366 device_printf(dev, "Interface setup failed: %d\n", error);
1367 goto err;
1368 }
1369
1370 ixgbe_if_update_admin_status(ctx);
1371
1372 /* Initialize statistics */
1373 ixgbe_update_stats_counters(sc);
1374 ixgbe_add_hw_stats(sc);
1375
1376 /* Check PCIE slot type/speed/width */
1377 ixgbe_get_slot_info(sc);
1378
1379 /*
1380 * Do time init and sysctl init here, but
1381 * only on the first port of a bypass sc.
1382 */
1383 ixgbe_bypass_init(sc);
1384
1385 /* Display NVM and Option ROM versions */
1386 ixgbe_print_fw_version(ctx);
1387
1388 /* Set an initial dmac value */
1389 sc->dmac = 0;
1390 /* Set initial advertised speeds (if applicable) */
1391 sc->advertise = ixgbe_get_default_advertise(sc);
1392
1393 if (sc->feat_cap & IXGBE_FEATURE_SRIOV)
1394 ixgbe_define_iov_schemas(dev, &error);
1395
1396 /* Add sysctls */
1397 ixgbe_add_device_sysctls(ctx);
1398
1399 /* Add MDIO bus if required / supported */
1400 ixgbe_mdio_attach(sc);
1401
1402 /* Init recovery mode timer and state variable */
1403 if (sc->feat_en & IXGBE_FEATURE_RECOVERY_MODE) {
1404 sc->recovery_mode = 0;
1405
1406 /* Set up the timer callout */
1407 callout_init(&sc->fw_mode_timer, true);
1408
1409 /* Start the task */
1410 callout_reset(&sc->fw_mode_timer, hz, ixgbe_fw_mode_timer, sc);
1411 }
1412
1413 return (0);
1414 err:
1415 return (error);
1416 } /* ixgbe_if_attach_post */
1417
1418 /************************************************************************
1419 * ixgbe_configure_wakeup
1420 *
1421 * Advertise the wake modes supported by this board and port. The NVM
1422 * APME setting selects the initial magic-packet policy.
1423 ************************************************************************/
1424 static void
ixgbe_configure_wakeup(if_ctx_t ctx)1425 ixgbe_configure_wakeup(if_ctx_t ctx)
1426 {
1427 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1428 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1429 struct ixgbe_hw *hw = &sc->hw;
1430 device_t dev = iflib_get_dev(ctx);
1431 u16 dev_caps = 0;
1432 u16 subdevice_id;
1433 u16 wol_cap;
1434 bool apme, supported;
1435
1436 supported = false;
1437 subdevice_id = hw->subsystem_device_id;
1438 if (hw->mac.ops.set_lan_id != NULL)
1439 hw->mac.ops.set_lan_id(hw);
1440
1441 /* X540 and newer advertise per-port WoL support in the NVM. */
1442 if (hw->mac.type >= ixgbe_mac_X540) {
1443 if (ixgbe_get_device_caps(hw, &dev_caps) == IXGBE_SUCCESS) {
1444 wol_cap = dev_caps & IXGBE_DEVICE_CAPS_WOL_MASK;
1445 if (wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1 ||
1446 (wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0 &&
1447 hw->bus.func == 0))
1448 supported = true;
1449 }
1450 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1451 /* 82599 WoL support is board and, in some cases, port specific. */
1452 switch (hw->device_id) {
1453 case IXGBE_DEV_ID_82599_SFP:
1454 switch (subdevice_id) {
1455 case IXGBE_SUBDEV_ID_82599_560FLR:
1456 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
1457 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
1458 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
1459 supported = hw->bus.func == 0;
1460 break;
1461 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
1462 case IXGBE_SUBDEV_ID_82599_SFP:
1463 case IXGBE_SUBDEV_ID_82599_RNDC:
1464 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
1465 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
1466 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
1467 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
1468 supported = true;
1469 break;
1470 default:
1471 break;
1472 }
1473 break;
1474 case IXGBE_DEV_ID_82599EN_SFP:
1475 supported =
1476 subdevice_id == IXGBE_SUBDEV_ID_82599EN_SFP_OCP1;
1477 break;
1478 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1479 supported =
1480 subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ;
1481 break;
1482 case IXGBE_DEV_ID_82599_KX4:
1483 supported = true;
1484 break;
1485 default:
1486 break;
1487 }
1488 }
1489 if (!pci_has_pme(dev, PCI_POWERSTATE_D3_HOT))
1490 supported = false;
1491 apme = supported &&
1492 (IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) & IXGBE_GRC_APME) != 0;
1493
1494 scctx->isc_capabilities &= ~IFCAP_WOL;
1495 scctx->isc_capenable &= ~IFCAP_WOL;
1496 if (supported) {
1497 scctx->isc_capabilities |= IFCAP_WOL;
1498 if (apme)
1499 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1500 }
1501
1502 /* hw->wol_enabled describes the policy active in hardware, not support. */
1503 hw->wol_enabled = false;
1504 sc->wol_filters = 0;
1505 } /* ixgbe_configure_wakeup */
1506
1507 /************************************************************************
1508 * ixgbe_setup_interface
1509 *
1510 * Setup networking device structure and register an interface.
1511 ************************************************************************/
1512 static int
ixgbe_setup_interface(if_ctx_t ctx)1513 ixgbe_setup_interface(if_ctx_t ctx)
1514 {
1515 if_t ifp = iflib_get_ifp(ctx);
1516 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1517
1518 INIT_DEBUGOUT("ixgbe_setup_interface: begin");
1519
1520 if_setbaudrate(ifp, IF_Gbps(10));
1521
1522 sc->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
1523
1524 sc->phy_layer = ixgbe_get_supported_physical_layer(&sc->hw);
1525
1526 ixgbe_add_media_types(ctx);
1527
1528 /* Autoselect media by default */
1529 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1530
1531 return (0);
1532 } /* ixgbe_setup_interface */
1533
1534 /************************************************************************
1535 * ixgbe_if_get_counter
1536 ************************************************************************/
1537 static uint64_t
ixgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)1538 ixgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
1539 {
1540 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1541 if_t ifp = iflib_get_ifp(ctx);
1542
1543 switch (cnt) {
1544 case IFCOUNTER_IPACKETS:
1545 return (sc->ipackets);
1546 case IFCOUNTER_OPACKETS:
1547 return (sc->opackets);
1548 case IFCOUNTER_IBYTES:
1549 return (sc->ibytes);
1550 case IFCOUNTER_OBYTES:
1551 return (sc->obytes);
1552 case IFCOUNTER_IMCASTS:
1553 return (sc->imcasts);
1554 case IFCOUNTER_OMCASTS:
1555 return (sc->omcasts);
1556 case IFCOUNTER_COLLISIONS:
1557 return (0);
1558 case IFCOUNTER_IQDROPS:
1559 return (sc->iqdrops);
1560 case IFCOUNTER_IERRORS:
1561 return (sc->ierrors);
1562 default:
1563 return (if_get_counter_default(ifp, cnt));
1564 }
1565 } /* ixgbe_if_get_counter */
1566
1567 /************************************************************************
1568 * ixgbe_if_i2c_req
1569 ************************************************************************/
1570 static int
ixgbe_if_i2c_req(if_ctx_t ctx,struct ifi2creq * req)1571 ixgbe_if_i2c_req(if_ctx_t ctx, struct ifi2creq *req)
1572 {
1573 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1574 struct ixgbe_hw *hw = &sc->hw;
1575 int i;
1576
1577 if (hw->phy.ops.read_i2c_byte == NULL)
1578 return (ENXIO);
1579 for (i = 0; i < req->len; i++)
1580 hw->phy.ops.read_i2c_byte(hw, req->offset + i,
1581 req->dev_addr, &req->data[i]);
1582 return (0);
1583 } /* ixgbe_if_i2c_req */
1584
1585 /* ixgbe_if_needs_restart - Tell iflib when the driver needs to be
1586 * reinitialized
1587 * @ctx: iflib context
1588 * @event: event code to check
1589 *
1590 * Defaults to returning false for unknown events.
1591 *
1592 * @returns true if iflib needs to reinit the interface
1593 */
1594 static bool
ixgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1595 ixgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1596 {
1597 switch (event) {
1598 case IFLIB_RESTART_VLAN_CONFIG:
1599 default:
1600 return (false);
1601 }
1602 }
1603
1604 /************************************************************************
1605 * ixgbe_if_priv_ioctl - Ioctl handler for driver
1606 *
1607 * Handler for custom driver specific ioctls
1608 *
1609 * return 0 on success, positive on failure
1610 ************************************************************************/
1611 static int
ixgbe_if_priv_ioctl(if_ctx_t ctx,u_long command,caddr_t data)1612 ixgbe_if_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data)
1613 {
1614 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1615 struct ifdrv *ifd;
1616 device_t dev = sc->dev;
1617
1618 /* Make sure the command type is valid */
1619 switch (command) {
1620 case SIOCSDRVSPEC:
1621 case SIOCGDRVSPEC:
1622 /* Accepted commands */
1623 break;
1624 case SIOCGPRIVATE_0:
1625 /*
1626 * Although we do not support this ioctl command, it's expected
1627 * that iflib will forward it to the IFDI_PRIV_IOCTL handler.
1628 * Do not print a message in this case.
1629 */
1630 return (ENOTSUP);
1631 default:
1632 /*
1633 * If we get a different command for this function, it's
1634 * definitely unexpected, so log a message indicating what
1635 * command we got for debugging purposes.
1636 */
1637 device_printf(dev,
1638 "%s: unexpected ioctl command %08lx\n",
1639 __func__, command);
1640 return (EINVAL);
1641 }
1642
1643 ifd = (struct ifdrv *)data;
1644
1645 switch (ifd->ifd_cmd) {
1646 case IXGBE_NVM_ACCESS:
1647 IOCTL_DEBUGOUT("ioctl: NVM ACCESS");
1648 return (ixgbe_nvm_access_ioctl(sc, ifd));
1649 case IXGBE_DEBUG_DUMP:
1650 IOCTL_DEBUGOUT("ioctl: DEBUG DUMP");
1651 return (ixgbe_debug_dump_ioctl(sc, ifd));
1652 default:
1653 IOCTL_DEBUGOUT1(
1654 "ioctl: UNKNOWN SIOC(S|G)DRVSPEC (0x%X) command\n",
1655 (int)ifd->ifd_cmd);
1656 return (EINVAL);
1657 }
1658
1659 return (0);
1660 }
1661
1662 /************************************************************************
1663 * ixgbe_nvm_access_ioctl
1664 *
1665 * Handles an NVM access ioctl request
1666 ************************************************************************/
1667 static int
ixgbe_nvm_access_ioctl(struct ixgbe_softc * sc,struct ifdrv * ifd)1668 ixgbe_nvm_access_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd)
1669 {
1670 struct ixgbe_nvm_access_data *data;
1671 struct ixgbe_nvm_access_cmd *cmd;
1672 struct ixgbe_hw *hw = &sc->hw;
1673 size_t ifd_len = ifd->ifd_len;
1674 size_t malloc_len;
1675 device_t dev = sc->dev;
1676 s32 status;
1677 u8 *nvm_buffer;
1678 int error = 0;
1679
1680 /*
1681 * ifioctl forwards SIOCxDRVSPEC to iflib without conducting
1682 * a privilege check. Subsequently, iflib passes the ioctl to the driver
1683 * without verifying privileges. To prevent non-privileged threads from
1684 * accessing this interface, perform a privilege check at this point.
1685 */
1686 error = priv_check(curthread, PRIV_DRIVER);
1687 if (error)
1688 return (error);
1689
1690 if (ifd_len < sizeof(*cmd)) {
1691 device_printf(dev,
1692 "%s: ifdrv length is too small. Got %zu, "
1693 "but expected %zu\n",
1694 __func__, ifd_len, sizeof(*cmd));
1695 return (EINVAL);
1696 }
1697
1698 if (ifd->ifd_data == NULL) {
1699 device_printf(dev, "%s: No ifd data buffer.\n",
1700 __func__);
1701 return (EINVAL);
1702 }
1703
1704 malloc_len = max(ifd_len, sizeof(*data) + sizeof(*cmd));
1705
1706 nvm_buffer = (u8 *)malloc(malloc_len, M_IXGBE, M_ZERO | M_NOWAIT);
1707 if (!nvm_buffer)
1708 return (ENOMEM);
1709
1710 /* Copy the NVM access command and data in from user space */
1711 error = copyin(ifd->ifd_data, nvm_buffer, ifd_len);
1712 if (error) {
1713 device_printf(dev, "%s: Failed to copy data in, error: %d\n",
1714 __func__, error);
1715 goto cleanup_free_nvm_buffer;
1716 }
1717
1718 /*
1719 * The NVM command structure is immediately followed by data which
1720 * varies in size based on the command.
1721 */
1722 cmd = (struct ixgbe_nvm_access_cmd *)nvm_buffer;
1723 data = (struct ixgbe_nvm_access_data *)
1724 (nvm_buffer + sizeof(struct ixgbe_nvm_access_cmd));
1725
1726 /* Handle the NVM access request */
1727 status = ixgbe_handle_nvm_access(hw, cmd, data);
1728 if (status) {
1729 device_printf(dev, "%s: NVM access request failed, error %d\n",
1730 __func__, status);
1731 }
1732
1733 /* Copy the possibly modified contents of the handled request out */
1734 error = copyout(nvm_buffer, ifd->ifd_data, ifd_len);
1735 if (error) {
1736 device_printf(dev, "%s: Copying response back to "
1737 "user space failed, error %d\n",
1738 __func__, error);
1739 goto cleanup_free_nvm_buffer;
1740 }
1741
1742 /* Convert private status to an error code for proper ioctl response */
1743 switch (status) {
1744 case IXGBE_SUCCESS:
1745 error = 0;
1746 break;
1747 case IXGBE_ERR_OUT_OF_RANGE:
1748 error = ENOTTY;
1749 break;
1750 case IXGBE_ERR_PARAM:
1751 default:
1752 error = EINVAL;
1753 break;
1754 }
1755
1756 cleanup_free_nvm_buffer:
1757 free(nvm_buffer, M_IXGBE);
1758 return (error);
1759 }
1760
1761 /************************************************************************
1762 * ixgbe_debug_dump_ioctl
1763 *
1764 * Makes debug dump of internal FW/HW data.
1765 ************************************************************************/
1766 static int
ixgbe_debug_dump_ioctl(struct ixgbe_softc * sc,struct ifdrv * ifd)1767 ixgbe_debug_dump_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd)
1768 {
1769 struct ixgbe_debug_dump_cmd *dd_cmd;
1770 struct ixgbe_hw *hw = &sc->hw;
1771 size_t ifd_len = ifd->ifd_len;
1772 device_t dev = sc->dev;
1773 s32 error = 0;
1774
1775 if (!(sc->feat_en & IXGBE_FEATURE_DBG_DUMP))
1776 return (ENODEV);
1777
1778 /* Data returned from ACI command */
1779 u16 ret_buf_size = 0;
1780 u16 ret_next_cluster = 0;
1781 u16 ret_next_table = 0;
1782 u32 ret_next_index = 0;
1783
1784 /*
1785 * ifioctl forwards SIOCxDRVSPEC to iflib without conducting
1786 * a privilege check. Subsequently, iflib passes the ioctl to the driver
1787 * without verifying privileges. To prevent non-privileged threads from
1788 * accessing this interface, perform a privilege check at this point.
1789 */
1790 error = priv_check(curthread, PRIV_DRIVER);
1791 if (error)
1792 return (error);
1793
1794 if (ifd_len < sizeof(*dd_cmd)) {
1795 device_printf(dev,
1796 "%s: ifdrv length is too small. Got %zu, "
1797 "but expected %zu\n",
1798 __func__, ifd_len, sizeof(*dd_cmd));
1799 return (EINVAL);
1800 }
1801
1802 if (ifd->ifd_data == NULL) {
1803 device_printf(dev, "%s: No ifd data buffer.\n",
1804 __func__);
1805 return (EINVAL);
1806 }
1807
1808 dd_cmd = (struct ixgbe_debug_dump_cmd *)malloc(ifd_len, M_IXGBE,
1809 M_NOWAIT | M_ZERO);
1810 if (!dd_cmd) {
1811 error = -ENOMEM;
1812 goto out;
1813 }
1814 /* copy data from userspace */
1815 error = copyin(ifd->ifd_data, dd_cmd, ifd_len);
1816 if (error) {
1817 device_printf(dev, "%s: Failed to copy data in, error: %d\n",
1818 __func__, error);
1819 goto out;
1820 }
1821
1822 /* ACI command requires buf_size arg to be grater than 0 */
1823 if (dd_cmd->data_size == 0) {
1824 device_printf(dev, "%s: data_size must be greater than 0\n",
1825 __func__);
1826 error = EINVAL;
1827 goto out;
1828 }
1829
1830 /* Zero the data buffer memory space */
1831 memset(dd_cmd->data, 0, ifd_len - sizeof(*dd_cmd));
1832
1833 error = ixgbe_aci_get_internal_data(hw, dd_cmd->cluster_id,
1834 dd_cmd->table_id, dd_cmd->offset, dd_cmd->data, dd_cmd->data_size,
1835 &ret_buf_size, &ret_next_cluster, &ret_next_table, &ret_next_index);
1836 if (error) {
1837 device_printf(dev,
1838 "%s: Failed to get internal FW/HW data, error: %d\n",
1839 __func__, error);
1840 goto out;
1841 }
1842
1843 dd_cmd->cluster_id = ret_next_cluster;
1844 dd_cmd->table_id = ret_next_table;
1845 dd_cmd->offset = ret_next_index;
1846 dd_cmd->data_size = ret_buf_size;
1847
1848 error = copyout(dd_cmd, ifd->ifd_data, ifd->ifd_len);
1849 if (error) {
1850 device_printf(dev,
1851 "%s: Failed to copy data out, error: %d\n",
1852 __func__, error);
1853 }
1854
1855 out:
1856 free(dd_cmd, M_IXGBE);
1857
1858 return (error);
1859 }
1860
1861 /************************************************************************
1862 * ixgbe_add_media_types
1863 ************************************************************************/
1864 static void
ixgbe_add_media_types(if_ctx_t ctx)1865 ixgbe_add_media_types(if_ctx_t ctx)
1866 {
1867 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1868 struct ixgbe_hw *hw = &sc->hw;
1869 device_t dev = iflib_get_dev(ctx);
1870 u64 layer;
1871
1872 layer = sc->phy_layer = ixgbe_get_supported_physical_layer(hw);
1873
1874 /* Media types with matching FreeBSD media defines */
1875 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T)
1876 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1877 if (layer & IXGBE_PHYSICAL_LAYER_5000BASE_T)
1878 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL);
1879 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_T)
1880 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
1881 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T)
1882 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1883 if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX)
1884 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1885 if (layer & IXGBE_PHYSICAL_LAYER_10BASE_T)
1886 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1887
1888 if (hw->mac.type == ixgbe_mac_X550) {
1889 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
1890 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL);
1891 }
1892
1893 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU ||
1894 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) {
1895 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_TWINAX, 0,
1896 NULL);
1897 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1898 }
1899
1900 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) {
1901 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_LR, 0, NULL);
1902 if (hw->phy.multispeed_fiber)
1903 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0,
1904 NULL);
1905 }
1906 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_BX) {
1907 device_printf(dev, "Media supported: 10Gbase-BX\n");
1908 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_BX, 0, NULL);
1909 }
1910 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR) {
1911 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL);
1912 if (hw->phy.multispeed_fiber)
1913 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0,
1914 NULL);
1915 } else if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX)
1916 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1917 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4)
1918 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL);
1919
1920 #ifdef IFM_ETH_XTYPE
1921 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR)
1922 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1923 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4)
1924 ifmedia_add( sc->media, IFM_ETHER | IFM_10G_KX4, 0, NULL);
1925 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX)
1926 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1927 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX)
1928 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_KX, 0, NULL);
1929 #else
1930 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) {
1931 device_printf(dev, "Media supported: 10GbaseKR\n");
1932 device_printf(dev, "10GbaseKR mapped to 10GbaseSR\n");
1933 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL);
1934 }
1935 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) {
1936 device_printf(dev, "Media supported: 10GbaseKX4\n");
1937 device_printf(dev, "10GbaseKX4 mapped to 10GbaseCX4\n");
1938 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL);
1939 }
1940 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) {
1941 device_printf(dev, "Media supported: 1000baseKX\n");
1942 device_printf(dev, "1000baseKX mapped to 1000baseCX\n");
1943 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1944 }
1945 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) {
1946 device_printf(dev, "Media supported: 2500baseKX\n");
1947 device_printf(dev, "2500baseKX mapped to 2500baseSX\n");
1948 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_SX, 0, NULL);
1949 }
1950 #endif
1951 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_BX) {
1952 device_printf(dev, "Media supported: 1000baseBX\n");
1953 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_BX, 0, NULL);
1954 }
1955
1956 if (hw->device_id == IXGBE_DEV_ID_82598AT) {
1957 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
1958 0, NULL);
1959 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1960 }
1961
1962 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1963 } /* ixgbe_add_media_types */
1964
1965 /************************************************************************
1966 * ixgbe_is_sfp
1967 ************************************************************************/
1968 static inline bool
ixgbe_is_sfp(struct ixgbe_hw * hw)1969 ixgbe_is_sfp(struct ixgbe_hw *hw)
1970 {
1971 switch (hw->mac.type) {
1972 case ixgbe_mac_82598EB:
1973 if (hw->phy.type == ixgbe_phy_nl)
1974 return (true);
1975 return (false);
1976 case ixgbe_mac_82599EB:
1977 switch (hw->mac.ops.get_media_type(hw)) {
1978 case ixgbe_media_type_fiber:
1979 case ixgbe_media_type_fiber_qsfp:
1980 return (true);
1981 default:
1982 return (false);
1983 }
1984 case ixgbe_mac_X550EM_x:
1985 case ixgbe_mac_X550EM_a:
1986 case ixgbe_mac_E610:
1987 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1988 return (true);
1989 return (false);
1990 default:
1991 return (false);
1992 }
1993 } /* ixgbe_is_sfp */
1994
1995 /************************************************************************
1996 * ixgbe_config_link
1997 ************************************************************************/
1998 static void
ixgbe_config_link(if_ctx_t ctx)1999 ixgbe_config_link(if_ctx_t ctx)
2000 {
2001 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2002 struct ixgbe_hw *hw = &sc->hw;
2003 u32 autoneg, err = 0;
2004 bool sfp, negotiate;
2005
2006 sfp = ixgbe_is_sfp(hw);
2007
2008 if (sfp) {
2009 /* ixgbe_if_stop() disables it on every 82599 SFP port. */
2010 ixgbe_enable_tx_laser(hw);
2011 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MOD);
2012 iflib_admin_intr_deferred(ctx);
2013 } else {
2014 if (hw->mac.ops.check_link)
2015 err = ixgbe_check_link(hw, &sc->link_speed,
2016 &sc->link_up, false);
2017 if (err)
2018 return;
2019 autoneg = hw->phy.autoneg_advertised;
2020 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
2021 err = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2022 &negotiate);
2023 if (err)
2024 return;
2025
2026 if (hw->mac.type == ixgbe_mac_X550 &&
2027 hw->phy.autoneg_advertised == 0) {
2028 /*
2029 * 2.5G and 5G autonegotiation speeds on X550
2030 * are disabled by default due to reported
2031 * interoperability issues with some switches.
2032 *
2033 * The second condition checks if any operations
2034 * involving setting autonegotiation speeds have
2035 * been performed prior to this ixgbe_config_link()
2036 * call.
2037 *
2038 * If hw->phy.autoneg_advertised does not
2039 * equal 0, this means that the user might have
2040 * set autonegotiation speeds via the sysctl
2041 * before bringing the interface up. In this
2042 * case, we should not disable 2.5G and 5G
2043 * since that speeds might be selected by the
2044 * user.
2045 *
2046 * Otherwise (i.e. if hw->phy.autoneg_advertised
2047 * is set to 0), it is the first time we set
2048 * autonegotiation preferences and the default
2049 * set of speeds should exclude 2.5G and 5G.
2050 */
2051 autoneg &= ~(IXGBE_LINK_SPEED_2_5GB_FULL |
2052 IXGBE_LINK_SPEED_5GB_FULL);
2053 }
2054
2055 if (hw->mac.type == ixgbe_mac_E610) {
2056 hw->phy.ops.init(hw);
2057 err = ixgbe_enable_lse(sc);
2058 if (err)
2059 device_printf(sc->dev,
2060 "Failed to enable Link Status Event, "
2061 "error: %d", err);
2062 }
2063
2064 if (hw->mac.ops.setup_link)
2065 err = hw->mac.ops.setup_link(hw, autoneg,
2066 sc->link_up);
2067 }
2068 } /* ixgbe_config_link */
2069
2070 /************************************************************************
2071 * ixgbe_update_stats_counters - Update board statistics counters.
2072 ************************************************************************/
2073 static void
ixgbe_update_stats_counters(struct ixgbe_softc * sc)2074 ixgbe_update_stats_counters(struct ixgbe_softc *sc)
2075 {
2076 struct ixgbe_hw *hw = &sc->hw;
2077 struct ixgbe_hw_stats *stats = &sc->stats.pf;
2078 u32 missed_rx = 0, mpc, bprc, lxon, lxoff;
2079 u32 lxoffrxc;
2080 u64 total_missed_rx = 0, total;
2081
2082 stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2083 stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2084 stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2085 stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2086 for (int i = 0; i < nitems(stats->mpc); i++) {
2087 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2088 missed_rx += mpc;
2089 stats->mpc[i] += mpc;
2090 total_missed_rx += stats->mpc[i];
2091 }
2092 stats->mpctotal = total_missed_rx;
2093
2094 for (int i = 0; i < 16; i++) {
2095 stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2096 stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2097 stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2098 }
2099 stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2100 stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2101 stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2102
2103 /* Hardware workaround, gprc counts missed packets */
2104 stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2105 stats->gprc -= missed_rx;
2106
2107 if (hw->mac.type != ixgbe_mac_82598EB) {
2108 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) +
2109 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2110 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) +
2111 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2112 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) +
2113 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2114 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2115 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2116 stats->lxoffrxc += lxoffrxc;
2117 } else {
2118 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2119 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2120 stats->lxoffrxc += lxoffrxc;
2121 /* 82598 only has a counter in the high register */
2122 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2123 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2124 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2125 }
2126
2127 /*
2128 * For watchdog management we need to know if we have been paused
2129 * during the last interval, so capture that here.
2130 */
2131 if (lxoffrxc)
2132 sc->shared->isc_pause_frames = 1;
2133
2134 /*
2135 * Workaround: mprc hardware is incorrectly counting
2136 * broadcasts, so for now we subtract those.
2137 */
2138 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2139 stats->bprc += bprc;
2140 stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2141 if (hw->mac.type == ixgbe_mac_82598EB)
2142 stats->mprc -= bprc;
2143
2144 stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2145 stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2146 stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2147 stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2148 stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2149 stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2150
2151 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2152 stats->lxontxc += lxon;
2153 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2154 stats->lxofftxc += lxoff;
2155 total = (u64)lxon + lxoff;
2156
2157 stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2158 stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2159 stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2160 stats->gptc -= total;
2161 stats->mptc -= total;
2162 stats->ptc64 -= total;
2163 stats->gotc -= total * ETHER_MIN_LEN;
2164
2165 stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2166 stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2167 stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2168 stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2169 stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2170 stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2171 stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2172 stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2173 stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2174 stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2175 stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2176 stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2177 stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2178 stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2179 stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2180 stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2181 stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2182 stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2183 /* Only read FCOE on 82599 */
2184 if (hw->mac.type != ixgbe_mac_82598EB) {
2185 stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2186 stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2187 stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2188 stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2189 stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2190 }
2191
2192 /* TLPIC and RLPIC are clear-on-read. */
2193 if (sc->feat_cap & IXGBE_FEATURE_EEE) {
2194 stats->tlpic += IXGBE_READ_REG(hw, IXGBE_TLPIC);
2195 stats->rlpic += IXGBE_READ_REG(hw, IXGBE_RLPIC);
2196 }
2197
2198 /* Fill out the OS statistics structure */
2199 IXGBE_SET_IPACKETS(sc, stats->gprc);
2200 IXGBE_SET_OPACKETS(sc, stats->gptc);
2201 IXGBE_SET_IBYTES(sc, stats->gorc);
2202 IXGBE_SET_OBYTES(sc, stats->gotc);
2203 IXGBE_SET_IMCASTS(sc, stats->mprc);
2204 IXGBE_SET_OMCASTS(sc, stats->mptc);
2205 IXGBE_SET_COLLISIONS(sc, 0);
2206 IXGBE_SET_IQDROPS(sc, total_missed_rx);
2207
2208 /*
2209 * Aggregate following types of errors as RX errors:
2210 * - CRC error count,
2211 * - illegal byte error count,
2212 * - missed packets count,
2213 * - length error count,
2214 * - undersized packets count,
2215 * - fragmented packets count,
2216 * - oversized packets count,
2217 * - jabber count.
2218 */
2219 IXGBE_SET_IERRORS(sc, stats->crcerrs + stats->illerrc +
2220 stats->mpctotal + stats->rlec + stats->ruc + stats->rfc +
2221 stats->roc + stats->rjc);
2222 } /* ixgbe_update_stats_counters */
2223
2224 /************************************************************************
2225 * ixgbe_add_hw_stats
2226 *
2227 * Add sysctl variables, one per statistic, to the system.
2228 ************************************************************************/
2229 static void
ixgbe_add_hw_stats(struct ixgbe_softc * sc)2230 ixgbe_add_hw_stats(struct ixgbe_softc *sc)
2231 {
2232 device_t dev = iflib_get_dev(sc->ctx);
2233 struct ix_rx_queue *rx_que;
2234 struct ix_tx_queue *tx_que;
2235 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
2236 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
2237 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
2238 struct ixgbe_hw_stats *stats = &sc->stats.pf;
2239 struct sysctl_oid *stat_node, *queue_node;
2240 struct sysctl_oid_list *stat_list, *queue_list;
2241 int i;
2242
2243 #define QUEUE_NAME_LEN 32
2244 char namebuf[QUEUE_NAME_LEN];
2245
2246 /* Driver Statistics */
2247 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
2248 CTLFLAG_RD, &sc->dropped_pkts, "Driver dropped packets");
2249 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
2250 CTLFLAG_RD, &sc->link_irq, "Link MSI-X IRQ Handled");
2251
2252 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues;
2253 i++, tx_que++) {
2254 struct tx_ring *txr = &tx_que->txr;
2255 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i);
2256 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2257 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
2258 queue_list = SYSCTL_CHILDREN(queue_node);
2259
2260 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
2261 CTLTYPE_UINT | CTLFLAG_RD, txr, 0,
2262 ixgbe_sysctl_tdh_handler, "IU",
2263 "Transmit Descriptor Head");
2264 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
2265 CTLTYPE_UINT | CTLFLAG_RD, txr, 0,
2266 ixgbe_sysctl_tdt_handler, "IU",
2267 "Transmit Descriptor Tail");
2268 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx",
2269 CTLFLAG_RD, &txr->tso_tx, "TSO");
2270 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets",
2271 CTLFLAG_RD, &txr->total_packets,
2272 "Queue Packets Transmitted");
2273 }
2274
2275 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues;
2276 i++, rx_que++) {
2277 struct rx_ring *rxr = &rx_que->rxr;
2278 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i);
2279 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2280 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
2281 queue_list = SYSCTL_CHILDREN(queue_node);
2282
2283 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
2284 CTLTYPE_UINT | CTLFLAG_RW,
2285 &sc->rx_queues[i], 0,
2286 ixgbe_sysctl_interrupt_rate_handler, "IU",
2287 "Interrupt Rate");
2288 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs",
2289 CTLFLAG_RD, &(sc->rx_queues[i].irqs),
2290 "irqs on this queue");
2291 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
2292 CTLTYPE_UINT | CTLFLAG_RD, rxr, 0,
2293 ixgbe_sysctl_rdh_handler, "IU",
2294 "Receive Descriptor Head");
2295 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
2296 CTLTYPE_UINT | CTLFLAG_RD, rxr, 0,
2297 ixgbe_sysctl_rdt_handler, "IU",
2298 "Receive Descriptor Tail");
2299 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets",
2300 CTLFLAG_RD, &rxr->rx_packets, "Queue Packets Received");
2301 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes",
2302 CTLFLAG_RD, &rxr->rx_bytes, "Queue Bytes Received");
2303 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies",
2304 CTLFLAG_RD, &rxr->rx_copies, "Copied RX Frames");
2305 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_discarded",
2306 CTLFLAG_RD, &rxr->rx_discarded, "Discarded RX packets");
2307 }
2308
2309 /* MAC stats get their own sub node */
2310 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
2311 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MAC Statistics");
2312 stat_list = SYSCTL_CHILDREN(stat_node);
2313
2314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_errs",
2315 CTLFLAG_RD, &sc->ierrors, IXGBE_SYSCTL_DESC_RX_ERRS);
2316 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
2317 CTLFLAG_RD, &stats->crcerrs, "CRC Errors");
2318 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "ill_errs",
2319 CTLFLAG_RD, &stats->illerrc, "Illegal Byte Errors");
2320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "byte_errs",
2321 CTLFLAG_RD, &stats->errbc, "Byte Errors");
2322 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "short_discards",
2323 CTLFLAG_RD, &stats->mspdc, "MAC Short Packets Discarded");
2324 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "local_faults",
2325 CTLFLAG_RD, &stats->mlfc, "MAC Local Faults");
2326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "remote_faults",
2327 CTLFLAG_RD, &stats->mrfc, "MAC Remote Faults");
2328 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rec_len_errs",
2329 CTLFLAG_RD, &stats->rlec, "Receive Length Errors");
2330 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_missed_packets",
2331 CTLFLAG_RD, &stats->mpctotal, "RX Missed Packet Count");
2332
2333 /* Flow Control stats */
2334 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
2335 CTLFLAG_RD, &stats->lxontxc, "Link XON Transmitted");
2336 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
2337 CTLFLAG_RD, &stats->lxonrxc, "Link XON Received");
2338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
2339 CTLFLAG_RD, &stats->lxofftxc, "Link XOFF Transmitted");
2340 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
2341 CTLFLAG_RD, &stats->lxoffrxc, "Link XOFF Received");
2342
2343 /* Packet Reception Stats */
2344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_octets_rcvd",
2345 CTLFLAG_RD, &stats->tor, "Total Octets Received");
2346 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_rcvd",
2347 CTLFLAG_RD, &stats->gorc, "Good Octets Received");
2348 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_rcvd",
2349 CTLFLAG_RD, &stats->tpr, "Total Packets Received");
2350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_rcvd",
2351 CTLFLAG_RD, &stats->gprc, "Good Packets Received");
2352 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_rcvd",
2353 CTLFLAG_RD, &stats->mprc, "Multicast Packets Received");
2354 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_rcvd",
2355 CTLFLAG_RD, &stats->bprc, "Broadcast Packets Received");
2356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
2357 CTLFLAG_RD, &stats->prc64, "64 byte frames received ");
2358 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
2359 CTLFLAG_RD, &stats->prc127, "65-127 byte frames received");
2360 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
2361 CTLFLAG_RD, &stats->prc255, "128-255 byte frames received");
2362 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
2363 CTLFLAG_RD, &stats->prc511, "256-511 byte frames received");
2364 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
2365 CTLFLAG_RD, &stats->prc1023, "512-1023 byte frames received");
2366 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
2367 CTLFLAG_RD, &stats->prc1522, "1023-1522 byte frames received");
2368 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersized",
2369 CTLFLAG_RD, &stats->ruc, "Receive Undersized");
2370 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
2371 CTLFLAG_RD, &stats->rfc, "Fragmented Packets Received ");
2372 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversized",
2373 CTLFLAG_RD, &stats->roc, "Oversized Packets Received");
2374 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabberd",
2375 CTLFLAG_RD, &stats->rjc, "Received Jabber");
2376 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_rcvd",
2377 CTLFLAG_RD, &stats->mngprc, "Management Packets Received");
2378 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_drpd",
2379 CTLFLAG_RD, &stats->mngpdc, "Management Packets Dropped");
2380 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "checksum_errs",
2381 CTLFLAG_RD, &stats->xec, "Checksum Errors");
2382
2383 /* Packet Transmission Stats */
2384 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
2385 CTLFLAG_RD, &stats->gotc, "Good Octets Transmitted");
2386 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
2387 CTLFLAG_RD, &stats->tpt, "Total Packets Transmitted");
2388 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
2389 CTLFLAG_RD, &stats->gptc, "Good Packets Transmitted");
2390 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
2391 CTLFLAG_RD, &stats->bptc, "Broadcast Packets Transmitted");
2392 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
2393 CTLFLAG_RD, &stats->mptc, "Multicast Packets Transmitted");
2394 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_txd",
2395 CTLFLAG_RD, &stats->mngptc, "Management Packets Transmitted");
2396 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
2397 CTLFLAG_RD, &stats->ptc64, "64 byte frames transmitted ");
2398 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
2399 CTLFLAG_RD, &stats->ptc127, "65-127 byte frames transmitted");
2400 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
2401 CTLFLAG_RD, &stats->ptc255, "128-255 byte frames transmitted");
2402 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
2403 CTLFLAG_RD, &stats->ptc511, "256-511 byte frames transmitted");
2404 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
2405 CTLFLAG_RD, &stats->ptc1023, "512-1023 byte frames transmitted");
2406 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
2407 CTLFLAG_RD, &stats->ptc1522, "1024-1522 byte frames transmitted");
2408 } /* ixgbe_add_hw_stats */
2409
2410 /************************************************************************
2411 * ixgbe_sysctl_tdh_handler - Transmit Descriptor Head handler function
2412 *
2413 * Retrieves the TDH value from the hardware
2414 ************************************************************************/
2415 static int
ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS)2416 ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS)
2417 {
2418 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1);
2419 int error;
2420 unsigned int val;
2421
2422 if (!txr)
2423 return (0);
2424
2425
2426 if (atomic_load_acq_int(&txr->sc->recovery_mode))
2427 return (EPERM);
2428
2429 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDH(txr->me));
2430 error = sysctl_handle_int(oidp, &val, 0, req);
2431 if (error || !req->newptr)
2432 return error;
2433
2434 return (0);
2435 } /* ixgbe_sysctl_tdh_handler */
2436
2437 /************************************************************************
2438 * ixgbe_sysctl_tdt_handler - Transmit Descriptor Tail handler function
2439 *
2440 * Retrieves the TDT value from the hardware
2441 ************************************************************************/
2442 static int
ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS)2443 ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS)
2444 {
2445 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1);
2446 int error;
2447 unsigned int val;
2448
2449 if (!txr)
2450 return (0);
2451
2452 if (atomic_load_acq_int(&txr->sc->recovery_mode))
2453 return (EPERM);
2454
2455 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDT(txr->me));
2456 error = sysctl_handle_int(oidp, &val, 0, req);
2457 if (error || !req->newptr)
2458 return error;
2459
2460 return (0);
2461 } /* ixgbe_sysctl_tdt_handler */
2462
2463 /************************************************************************
2464 * ixgbe_sysctl_rdh_handler - Receive Descriptor Head handler function
2465 *
2466 * Retrieves the RDH value from the hardware
2467 ************************************************************************/
2468 static int
ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS)2469 ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS)
2470 {
2471 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1);
2472 int error;
2473 unsigned int val;
2474
2475 if (!rxr)
2476 return (0);
2477
2478 if (atomic_load_acq_int(&rxr->sc->recovery_mode))
2479 return (EPERM);
2480
2481 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDH(rxr->me));
2482 error = sysctl_handle_int(oidp, &val, 0, req);
2483 if (error || !req->newptr)
2484 return error;
2485
2486 return (0);
2487 } /* ixgbe_sysctl_rdh_handler */
2488
2489 /************************************************************************
2490 * ixgbe_sysctl_rdt_handler - Receive Descriptor Tail handler function
2491 *
2492 * Retrieves the RDT value from the hardware
2493 ************************************************************************/
2494 static int
ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS)2495 ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS)
2496 {
2497 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1);
2498 int error;
2499 unsigned int val;
2500
2501 if (!rxr)
2502 return (0);
2503
2504 if (atomic_load_acq_int(&rxr->sc->recovery_mode))
2505 return (EPERM);
2506
2507 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDT(rxr->me));
2508 error = sysctl_handle_int(oidp, &val, 0, req);
2509 if (error || !req->newptr)
2510 return error;
2511
2512 return (0);
2513 } /* ixgbe_sysctl_rdt_handler */
2514
2515 /************************************************************************
2516 * ixgbe_if_vlan_register
2517 *
2518 * Run via vlan config EVENT, it enables us to use the
2519 * HW Filter table since we can get the vlan id. This
2520 * just creates the entry in the soft version of the
2521 * VFTA, init will repopulate the real table.
2522 ************************************************************************/
2523 static void
ixgbe_if_vlan_register(if_ctx_t ctx,u16 vtag)2524 ixgbe_if_vlan_register(if_ctx_t ctx, u16 vtag)
2525 {
2526 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2527 bool present;
2528 u16 index;
2529 u32 mask;
2530
2531 index = (vtag >> 5) & 0x7F;
2532 mask = 1U << (vtag & 0x1F);
2533 present = (sc->shadow_vfta[index] & mask) != 0;
2534 sc->shadow_vfta[index] |= mask;
2535 if (!present)
2536 ++sc->num_vlans;
2537 #ifdef PCI_IOV
2538 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 &&
2539 sc->iov_vfta_valid && !sc->iov_vlan_promisc)
2540 (void)ixgbe_set_vfta(&sc->hw, vtag, sc->pool, true, true);
2541 #endif
2542 ixgbe_setup_vlan_hw_support(ctx);
2543 } /* ixgbe_if_vlan_register */
2544
2545 /************************************************************************
2546 * ixgbe_if_vlan_unregister
2547 *
2548 * Run via vlan unconfig EVENT, remove our entry in the soft vfta.
2549 ************************************************************************/
2550 static void
ixgbe_if_vlan_unregister(if_ctx_t ctx,u16 vtag)2551 ixgbe_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
2552 {
2553 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2554 bool present;
2555 u16 index;
2556 u32 mask;
2557
2558 index = (vtag >> 5) & 0x7F;
2559 mask = 1U << (vtag & 0x1F);
2560 present = (sc->shadow_vfta[index] & mask) != 0;
2561 sc->shadow_vfta[index] &= ~mask;
2562 if (present)
2563 --sc->num_vlans;
2564 #ifdef PCI_IOV
2565 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 &&
2566 sc->iov_vfta_valid && !sc->iov_vlan_promisc)
2567 (void)ixgbe_set_vfta(&sc->hw, vtag, sc->pool, false, true);
2568 #endif
2569 ixgbe_setup_vlan_hw_support(ctx);
2570 } /* ixgbe_if_vlan_unregister */
2571
2572 #ifdef PCI_IOV
2573 static bool
ixgbe_iov_pf_owns_vlan(const struct ixgbe_softc * sc,u16 vlan)2574 ixgbe_iov_pf_owns_vlan(const struct ixgbe_softc *sc, u16 vlan)
2575 {
2576
2577 return ((sc->shadow_vfta[vlan >> 5] &
2578 (1U << (vlan & 0x1f))) != 0);
2579 }
2580
2581 /*
2582 * start_hw clears both VFTA and VLVF. Reconstruct the shared tables from
2583 * PF and VF desired state after every reset or filtering-mode transition.
2584 * Allocate VF entries first so PF-only VLANs cannot exhaust VLVF.
2585 */
2586 static void
ixgbe_iov_vlan_rebuild(struct ixgbe_softc * sc,bool promisc)2587 ixgbe_iov_vlan_rebuild(struct ixgbe_softc *sc, bool promisc)
2588 {
2589 struct ixgbe_hw *hw;
2590 struct ixgbe_vf *vf;
2591 u32 vfta[IXGBE_VFTA_SIZE];
2592 u32 bits, vlan, vlvf;
2593 int bit, failures, i, word;
2594
2595 hw = &sc->hw;
2596 bcopy(sc->shadow_vfta, vfta, sizeof(vfta));
2597 (void)ixgbe_clear_vfta(hw);
2598 failures = 0;
2599 for (i = 0; i < sc->num_vfs; i++) {
2600 vf = &sc->vfs[i];
2601 if ((vf->flags & IXGBE_VF_ACTIVE) == 0)
2602 continue;
2603 if (vf->default_vlan == 0 &&
2604 ixgbe_set_vfta(hw, 0, vf->pool, true, false) !=
2605 IXGBE_SUCCESS)
2606 failures++;
2607 for (word = 0; word < IXGBE_VFTA_SIZE; word++) {
2608 bits = vf->vlans[word];
2609 while (bits != 0) {
2610 bit = ffs(bits) - 1;
2611 vlan = word * 32 + bit;
2612 if (ixgbe_set_vfta(hw, vlan, vf->pool, true,
2613 false) == IXGBE_SUCCESS)
2614 vfta[word] |= 1U << bit;
2615 else
2616 failures++;
2617 bits &= ~(1U << bit);
2618 }
2619 }
2620 }
2621 if (ixgbe_set_vfta(hw, 0, sc->pool, true, false) != IXGBE_SUCCESS)
2622 failures++;
2623
2624 /* Add the PF to shared entries, or every entry in promiscuous mode. */
2625 for (i = 1; i < IXGBE_VLVF_ENTRIES; i++) {
2626 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
2627 if ((vlvf & IXGBE_VLVF_VIEN) == 0)
2628 continue;
2629 vlan = vlvf & IXGBE_VLVF_VLANID_MASK;
2630 if (promisc || ixgbe_iov_pf_owns_vlan(sc, vlan))
2631 (void)ixgbe_set_vfta(hw, vlan, sc->pool, true, true);
2632 vfta[vlan >> 5] |= 1U << (vlan & 0x1f);
2633 }
2634 if (promisc)
2635 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2636 vfta[i] = UINT32_MAX;
2637 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2638 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), vfta[i]);
2639 if (failures != 0)
2640 device_printf(sc->dev,
2641 "VLAN pool restore failed for %d memberships\n", failures);
2642 }
2643
2644 static void
ixgbe_iov_vlan_sync(struct ixgbe_softc * sc,bool promisc)2645 ixgbe_iov_vlan_sync(struct ixgbe_softc *sc, bool promisc)
2646 {
2647
2648 if (sc->iov_vfta_valid && sc->iov_vlan_promisc == promisc)
2649 return;
2650 ixgbe_iov_vlan_rebuild(sc, promisc);
2651 sc->iov_vlan_promisc = promisc;
2652 sc->iov_vfta_valid = true;
2653 }
2654 #endif
2655
2656 /************************************************************************
2657 * ixgbe_setup_vlan_hw_support
2658 ************************************************************************/
2659 void
ixgbe_setup_vlan_hw_support(if_ctx_t ctx)2660 ixgbe_setup_vlan_hw_support(if_ctx_t ctx)
2661 {
2662 if_t ifp = iflib_get_ifp(ctx);
2663 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2664 struct ixgbe_hw *hw = &sc->hw;
2665 struct rx_ring *rxr;
2666 bool strip;
2667 int i;
2668 u32 ctrl;
2669
2670 strip = sc->num_vlans != 0 &&
2671 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0;
2672 for (i = 0; i < sc->num_rx_queues; i++) {
2673 rxr = &sc->rx_queues[i].rxr;
2674 /* On 82599 and newer VLAN stripping is per receive queue. */
2675 if (hw->mac.type != ixgbe_mac_82598EB) {
2676 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me));
2677 if (strip)
2678 ctrl |= IXGBE_RXDCTL_VME;
2679 else
2680 ctrl &= ~IXGBE_RXDCTL_VME;
2681 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl);
2682 }
2683 rxr->vtag_strip = strip;
2684 }
2685
2686 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2687 if (hw->mac.type == ixgbe_mac_82598EB) {
2688 if (strip)
2689 ctrl |= IXGBE_VLNCTRL_VME;
2690 else
2691 ctrl &= ~IXGBE_VLNCTRL_VME;
2692 }
2693
2694 /* Always admit priority-tagged frames. */
2695 sc->shadow_vfta[0] |= 1U;
2696
2697 #ifdef PCI_IOV
2698 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0) {
2699 /*
2700 * VFE must remain enabled to enforce per-pool VLAN ownership.
2701 */
2702 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2703 ctrl |= IXGBE_VLNCTRL_VFE;
2704 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2705 ixgbe_iov_vlan_sync(sc,
2706 (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0);
2707 return;
2708 }
2709 #endif
2710
2711 if (!strip ||
2712 (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) {
2713 ctrl |= IXGBE_VLNCTRL_CFIEN;
2714 ctrl &= ~IXGBE_VLNCTRL_VFE;
2715 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2716 return;
2717 }
2718
2719 /* A soft reset clears VFTA, so restore the PF's desired bitmap. */
2720 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2721 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), sc->shadow_vfta[i]);
2722 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2723 ctrl |= IXGBE_VLNCTRL_VFE;
2724 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2725 } /* ixgbe_setup_vlan_hw_support */
2726
2727 /************************************************************************
2728 * ixgbe_get_slot_info
2729 *
2730 * Get the width and transaction speed of
2731 * the slot this adapter is plugged into.
2732 ************************************************************************/
2733 static void
ixgbe_get_slot_info(struct ixgbe_softc * sc)2734 ixgbe_get_slot_info(struct ixgbe_softc *sc)
2735 {
2736 device_t dev = iflib_get_dev(sc->ctx);
2737 struct ixgbe_hw *hw = &sc->hw;
2738 int bus_info_valid = true;
2739 u32 offset;
2740 u16 link;
2741
2742 /* Some devices are behind an internal bridge */
2743 switch (hw->device_id) {
2744 case IXGBE_DEV_ID_82599_SFP_SF_QP:
2745 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
2746 goto get_parent_info;
2747 default:
2748 break;
2749 }
2750
2751 ixgbe_get_bus_info(hw);
2752
2753 /*
2754 * Some devices don't use PCI-E, but there is no need
2755 * to display "Unknown" for bus speed and width.
2756 */
2757 switch (hw->mac.type) {
2758 case ixgbe_mac_X550EM_x:
2759 case ixgbe_mac_X550EM_a:
2760 return;
2761 default:
2762 goto display;
2763 }
2764
2765 get_parent_info:
2766 /*
2767 * For the Quad port adapter we need to parse back
2768 * up the PCI tree to find the speed of the expansion
2769 * slot into which this adapter is plugged. A bit more work.
2770 */
2771 dev = device_get_parent(device_get_parent(dev));
2772 #ifdef IXGBE_DEBUG
2773 device_printf(dev, "parent pcib = %x,%x,%x\n", pci_get_bus(dev),
2774 pci_get_slot(dev), pci_get_function(dev));
2775 #endif
2776 dev = device_get_parent(device_get_parent(dev));
2777 #ifdef IXGBE_DEBUG
2778 device_printf(dev, "slot pcib = %x,%x,%x\n", pci_get_bus(dev),
2779 pci_get_slot(dev), pci_get_function(dev));
2780 #endif
2781 /* Now get the PCI Express Capabilities offset */
2782 if (pci_find_cap(dev, PCIY_EXPRESS, &offset)) {
2783 /*
2784 * Hmm...can't get PCI-Express capabilities.
2785 * Falling back to default method.
2786 */
2787 bus_info_valid = false;
2788 ixgbe_get_bus_info(hw);
2789 goto display;
2790 }
2791 /* ...and read the Link Status Register */
2792 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2);
2793 ixgbe_set_pci_config_data_generic(hw, link);
2794
2795 display:
2796 device_printf(dev, "PCI Express Bus: Speed %s Width %s\n",
2797 ((hw->bus.speed == ixgbe_bus_speed_16000) ? "16.0GT/s" :
2798 (hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" :
2799 (hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" :
2800 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" :
2801 "Unknown"),
2802 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "x8" :
2803 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "x4" :
2804 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "x1" :
2805 "Unknown"));
2806
2807 if (bus_info_valid) {
2808 if ((hw->device_id != IXGBE_DEV_ID_82599_SFP_SF_QP) &&
2809 ((hw->bus.width <= ixgbe_bus_width_pcie_x4) &&
2810 (hw->bus.speed == ixgbe_bus_speed_2500))) {
2811 device_printf(dev,
2812 "PCI-Express bandwidth available for this card"
2813 " is not sufficient for optimal performance.\n");
2814 device_printf(dev,
2815 "For optimal performance a x8 PCIE, or x4 PCIE"
2816 " Gen2 slot is required.\n");
2817 }
2818 if ((hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP) &&
2819 ((hw->bus.width <= ixgbe_bus_width_pcie_x8) &&
2820 (hw->bus.speed < ixgbe_bus_speed_8000))) {
2821 device_printf(dev,
2822 "PCI-Express bandwidth available for this card"
2823 " is not sufficient for optimal performance.\n");
2824 device_printf(dev,
2825 "For optimal performance a x8 PCIE Gen3 slot is"
2826 " required.\n");
2827 }
2828 } else
2829 device_printf(dev,
2830 "Unable to determine slot speed/width. The speed/width"
2831 " reported are that of the internal switch.\n");
2832
2833 return;
2834 } /* ixgbe_get_slot_info */
2835
2836 /************************************************************************
2837 * ixgbe_if_msix_intr_assign
2838 *
2839 * Setup MSI-X Interrupt resources and handlers
2840 ************************************************************************/
2841 static int
ixgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)2842 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
2843 {
2844 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2845 struct ix_rx_queue *rx_que = sc->rx_queues;
2846 struct ix_tx_queue *tx_que;
2847 int error, rid, vector = 0;
2848 char buf[16];
2849
2850 /* Admin Que is vector 0*/
2851 rid = vector + 1;
2852 for (int i = 0; i < sc->num_rx_queues; i++, vector++, rx_que++) {
2853 rid = vector + 1;
2854
2855 snprintf(buf, sizeof(buf), "rxq%d", i);
2856 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
2857 IFLIB_INTR_RXTX, ixgbe_msix_que, rx_que, rx_que->rxr.me,
2858 buf);
2859
2860 if (error) {
2861 device_printf(iflib_get_dev(ctx),
2862 "Failed to allocate que int %d err: %d",
2863 i,error);
2864 sc->num_rx_queues = i + 1;
2865 goto fail;
2866 }
2867
2868 rx_que->msix = vector;
2869 }
2870 for (int i = 0; i < sc->num_tx_queues; i++) {
2871 snprintf(buf, sizeof(buf), "txq%d", i);
2872 tx_que = &sc->tx_queues[i];
2873 tx_que->msix = i % sc->num_rx_queues;
2874 iflib_softirq_alloc_generic(ctx,
2875 &sc->rx_queues[tx_que->msix].que_irq,
2876 IFLIB_INTR_TX, tx_que, tx_que->txr.me, buf);
2877 }
2878 rid = vector + 1;
2879 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid,
2880 IFLIB_INTR_ADMIN, ixgbe_msix_link, sc, 0, "aq");
2881 if (error) {
2882 device_printf(iflib_get_dev(ctx),
2883 "Failed to register admin handler");
2884 return (error);
2885 }
2886
2887 sc->vector = vector;
2888
2889 return (0);
2890 fail:
2891 iflib_irq_free(ctx, &sc->irq);
2892 rx_que = sc->rx_queues;
2893 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++)
2894 iflib_irq_free(ctx, &rx_que->que_irq);
2895
2896 return (error);
2897 } /* ixgbe_if_msix_intr_assign */
2898
2899 static inline void
ixgbe_perform_aim(struct ixgbe_softc * sc,struct ix_rx_queue * que)2900 ixgbe_perform_aim(struct ixgbe_softc *sc, struct ix_rx_queue *que)
2901 {
2902 uint32_t newitr = 0;
2903 struct rx_ring *rxr = &que->rxr;
2904 /* FIXME struct tx_ring *txr = ... ->txr; */
2905
2906 /*
2907 * Do Adaptive Interrupt Moderation:
2908 * - Write out last calculated setting
2909 * - Calculate based on average size over
2910 * the last interval.
2911 */
2912 if (que->eitr_setting) {
2913 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix),
2914 que->eitr_setting);
2915 }
2916
2917 que->eitr_setting = 0;
2918 /* Idle, do nothing */
2919 if (rxr->bytes == 0) {
2920 /* FIXME && txr->bytes == 0 */
2921 return;
2922 }
2923
2924 if ((rxr->bytes) && (rxr->packets))
2925 newitr = rxr->bytes / rxr->packets;
2926 /* FIXME for transmit accounting
2927 * if ((txr->bytes) && (txr->packets))
2928 * newitr = txr->bytes/txr->packets;
2929 * if ((rxr->bytes) && (rxr->packets))
2930 * newitr = max(newitr, (rxr->bytes / rxr->packets));
2931 */
2932
2933 newitr += 24; /* account for hardware frame, crc */
2934 /* set an upper boundary */
2935 newitr = min(newitr, 3000);
2936
2937 /* Be nice to the mid range */
2938 if ((newitr > 300) && (newitr < 1200)) {
2939 newitr = (newitr / 3);
2940 } else {
2941 newitr = (newitr / 2);
2942 }
2943
2944 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
2945 newitr |= newitr << 16;
2946 } else {
2947 newitr |= IXGBE_EITR_CNT_WDIS;
2948 }
2949
2950 /* save for next interrupt */
2951 que->eitr_setting = newitr;
2952
2953 /* Reset state */
2954 /* FIXME txr->bytes = 0; */
2955 /* FIXME txr->packets = 0; */
2956 rxr->bytes = 0;
2957 rxr->packets = 0;
2958
2959 return;
2960 }
2961
2962 /*********************************************************************
2963 * ixgbe_msix_que - MSI-X Queue Interrupt Service routine
2964 **********************************************************************/
2965 static int
ixgbe_msix_que(void * arg)2966 ixgbe_msix_que(void *arg)
2967 {
2968 struct ix_rx_queue *que = arg;
2969 struct ixgbe_softc *sc = que->sc;
2970 if_t ifp = iflib_get_ifp(que->sc->ctx);
2971
2972 /* Protect against spurious interrupts */
2973 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2974 return (FILTER_HANDLED);
2975
2976 ixgbe_disable_queue(sc, que->msix);
2977 ++que->irqs;
2978
2979 /* Check for AIM */
2980 if (sc->enable_aim) {
2981 ixgbe_perform_aim(sc, que);
2982 }
2983
2984 return (FILTER_SCHEDULE_THREAD);
2985 } /* ixgbe_msix_que */
2986
2987 /************************************************************************
2988 * ixgbe_media_status - Media Ioctl callback
2989 *
2990 * Called whenever the user queries the status of
2991 * the interface using ifconfig.
2992 ************************************************************************/
2993 static void
ixgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2994 ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2995 {
2996 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2997 struct ixgbe_hw *hw = &sc->hw;
2998 int layer;
2999
3000 INIT_DEBUGOUT("ixgbe_if_media_status: begin");
3001
3002 ifmr->ifm_status = IFM_AVALID;
3003 ifmr->ifm_active = IFM_ETHER;
3004
3005 if (!sc->link_active)
3006 return;
3007
3008 ifmr->ifm_status |= IFM_ACTIVE;
3009 layer = sc->phy_layer;
3010
3011 if (layer & IXGBE_PHYSICAL_LAYERS_BASE_T_ALL)
3012 switch (sc->link_speed) {
3013 case IXGBE_LINK_SPEED_10GB_FULL:
3014 ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
3015 break;
3016 case IXGBE_LINK_SPEED_5GB_FULL:
3017 ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
3018 break;
3019 case IXGBE_LINK_SPEED_2_5GB_FULL:
3020 ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
3021 break;
3022 case IXGBE_LINK_SPEED_1GB_FULL:
3023 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
3024 break;
3025 case IXGBE_LINK_SPEED_100_FULL:
3026 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
3027 break;
3028 case IXGBE_LINK_SPEED_10_FULL:
3029 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
3030 break;
3031 }
3032 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU ||
3033 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA)
3034 switch (sc->link_speed) {
3035 case IXGBE_LINK_SPEED_10GB_FULL:
3036 ifmr->ifm_active |= IFM_10G_TWINAX | IFM_FDX;
3037 break;
3038 case IXGBE_LINK_SPEED_1GB_FULL:
3039 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX;
3040 break;
3041 }
3042 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR)
3043 switch (sc->link_speed) {
3044 case IXGBE_LINK_SPEED_10GB_FULL:
3045 ifmr->ifm_active |= IFM_10G_LR | IFM_FDX;
3046 break;
3047 case IXGBE_LINK_SPEED_1GB_FULL:
3048 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX;
3049 break;
3050 }
3051 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_BX &&
3052 sc->link_speed == IXGBE_LINK_SPEED_10GB_FULL)
3053 ifmr->ifm_active |= IFM_10G_BX | IFM_FDX;
3054 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LRM)
3055 switch (sc->link_speed) {
3056 case IXGBE_LINK_SPEED_10GB_FULL:
3057 ifmr->ifm_active |= IFM_10G_LRM | IFM_FDX;
3058 break;
3059 case IXGBE_LINK_SPEED_1GB_FULL:
3060 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX;
3061 break;
3062 }
3063 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR ||
3064 layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX)
3065 switch (sc->link_speed) {
3066 case IXGBE_LINK_SPEED_10GB_FULL:
3067 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX;
3068 break;
3069 case IXGBE_LINK_SPEED_1GB_FULL:
3070 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
3071 break;
3072 }
3073 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4)
3074 switch (sc->link_speed) {
3075 case IXGBE_LINK_SPEED_10GB_FULL:
3076 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX;
3077 break;
3078 }
3079 /*
3080 * XXX: These need to use the proper media types once
3081 * they're added.
3082 */
3083 #ifndef IFM_ETH_XTYPE
3084 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR)
3085 switch (sc->link_speed) {
3086 case IXGBE_LINK_SPEED_10GB_FULL:
3087 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX;
3088 break;
3089 case IXGBE_LINK_SPEED_2_5GB_FULL:
3090 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
3091 break;
3092 case IXGBE_LINK_SPEED_1GB_FULL:
3093 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX;
3094 break;
3095 }
3096 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 ||
3097 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX ||
3098 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX)
3099 switch (sc->link_speed) {
3100 case IXGBE_LINK_SPEED_10GB_FULL:
3101 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX;
3102 break;
3103 case IXGBE_LINK_SPEED_2_5GB_FULL:
3104 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
3105 break;
3106 case IXGBE_LINK_SPEED_1GB_FULL:
3107 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX;
3108 break;
3109 }
3110 #else
3111 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR)
3112 switch (sc->link_speed) {
3113 case IXGBE_LINK_SPEED_10GB_FULL:
3114 ifmr->ifm_active |= IFM_10G_KR | IFM_FDX;
3115 break;
3116 case IXGBE_LINK_SPEED_2_5GB_FULL:
3117 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX;
3118 break;
3119 case IXGBE_LINK_SPEED_1GB_FULL:
3120 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX;
3121 break;
3122 }
3123 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 ||
3124 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX ||
3125 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX)
3126 switch (sc->link_speed) {
3127 case IXGBE_LINK_SPEED_10GB_FULL:
3128 ifmr->ifm_active |= IFM_10G_KX4 | IFM_FDX;
3129 break;
3130 case IXGBE_LINK_SPEED_2_5GB_FULL:
3131 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX;
3132 break;
3133 case IXGBE_LINK_SPEED_1GB_FULL:
3134 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX;
3135 break;
3136 }
3137 #endif
3138
3139 /* If nothing is recognized... */
3140 if (IFM_SUBTYPE(ifmr->ifm_active) == 0)
3141 ifmr->ifm_active |= IFM_UNKNOWN;
3142
3143 /* Display current flow control setting used on link */
3144 if (hw->fc.current_mode == ixgbe_fc_rx_pause ||
3145 hw->fc.current_mode == ixgbe_fc_full)
3146 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3147 if (hw->fc.current_mode == ixgbe_fc_tx_pause ||
3148 hw->fc.current_mode == ixgbe_fc_full)
3149 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3150 } /* ixgbe_media_status */
3151
3152 /************************************************************************
3153 * ixgbe_media_change - Media Ioctl callback
3154 *
3155 * Called when the user changes speed/duplex using
3156 * media/mediopt option with ifconfig.
3157 ************************************************************************/
3158 static int
ixgbe_if_media_change(if_ctx_t ctx)3159 ixgbe_if_media_change(if_ctx_t ctx)
3160 {
3161 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3162 struct ifmedia *ifm = iflib_get_media(ctx);
3163 struct ixgbe_hw *hw = &sc->hw;
3164 ixgbe_link_speed speed = 0;
3165
3166 INIT_DEBUGOUT("ixgbe_if_media_change: begin");
3167
3168 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3169 return (EINVAL);
3170
3171 if (hw->phy.media_type == ixgbe_media_type_backplane)
3172 return (EPERM);
3173
3174 /*
3175 * We don't actually need to check against the supported
3176 * media types of the adapter; ifmedia will take care of
3177 * that for us.
3178 */
3179 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3180 case IFM_AUTO:
3181 case IFM_10G_T:
3182 speed |= IXGBE_LINK_SPEED_100_FULL;
3183 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3184 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3185 break;
3186 case IFM_10G_BX:
3187 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3188 break;
3189 case IFM_10G_LRM:
3190 case IFM_10G_LR:
3191 #ifndef IFM_ETH_XTYPE
3192 case IFM_10G_SR: /* KR, too */
3193 case IFM_10G_CX4: /* KX4 */
3194 #else
3195 case IFM_10G_KR:
3196 case IFM_10G_KX4:
3197 #endif
3198 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3199 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3200 break;
3201 #ifndef IFM_ETH_XTYPE
3202 case IFM_1000_CX: /* KX */
3203 #else
3204 case IFM_1000_KX:
3205 #endif
3206 case IFM_1000_LX:
3207 case IFM_1000_SX:
3208 case IFM_1000_BX:
3209 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3210 break;
3211 case IFM_1000_T:
3212 speed |= IXGBE_LINK_SPEED_100_FULL;
3213 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3214 break;
3215 case IFM_10G_TWINAX:
3216 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3217 break;
3218 case IFM_5000_T:
3219 speed |= IXGBE_LINK_SPEED_5GB_FULL;
3220 break;
3221 case IFM_2500_T:
3222 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
3223 break;
3224 case IFM_100_TX:
3225 speed |= IXGBE_LINK_SPEED_100_FULL;
3226 break;
3227 case IFM_10_T:
3228 speed |= IXGBE_LINK_SPEED_10_FULL;
3229 break;
3230 default:
3231 goto invalid;
3232 }
3233
3234 hw->mac.autotry_restart = true;
3235 hw->mac.ops.setup_link(hw, speed, true);
3236 sc->advertise =
3237 ((speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) |
3238 ((speed & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) |
3239 ((speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) |
3240 ((speed & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) |
3241 ((speed & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) |
3242 ((speed & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0);
3243
3244 return (0);
3245
3246 invalid:
3247 device_printf(iflib_get_dev(ctx), "Invalid media type!\n");
3248
3249 return (EINVAL);
3250 } /* ixgbe_if_media_change */
3251
3252 /************************************************************************
3253 * ixgbe_set_promisc
3254 ************************************************************************/
3255 static int
ixgbe_if_promisc_set(if_ctx_t ctx,int flags)3256 ixgbe_if_promisc_set(if_ctx_t ctx, int flags)
3257 {
3258 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3259 if_t ifp = iflib_get_ifp(ctx);
3260 u32 rctl;
3261 int mcnt = 0;
3262
3263 rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
3264 rctl &= (~IXGBE_FCTRL_UPE);
3265 if (if_getflags(ifp) & IFF_ALLMULTI)
3266 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
3267 else {
3268 mcnt = min(if_llmaddr_count(ifp),
3269 MAX_NUM_MULTICAST_ADDRESSES);
3270 }
3271 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
3272 rctl &= (~IXGBE_FCTRL_MPE);
3273 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl);
3274
3275 if (if_getflags(ifp) & IFF_PROMISC) {
3276 rctl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3277 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl);
3278 } else if (if_getflags(ifp) & IFF_ALLMULTI) {
3279 rctl |= IXGBE_FCTRL_MPE;
3280 rctl &= ~IXGBE_FCTRL_UPE;
3281 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl);
3282 }
3283 return (0);
3284 } /* ixgbe_if_promisc_set */
3285
3286 /************************************************************************
3287 * ixgbe_handle_ecc - Defer recovery from an ECC interrupt
3288 ************************************************************************/
3289 static bool
ixgbe_handle_ecc(struct ixgbe_softc * sc,u32 eicr)3290 ixgbe_handle_ecc(struct ixgbe_softc *sc, u32 eicr)
3291 {
3292 struct ixgbe_hw *hw = &sc->hw;
3293
3294 if ((eicr & IXGBE_EICR_ECC) == 0)
3295 return (false);
3296
3297 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_ECC);
3298 if (!atomic_cmpset_int(&sc->ecc_reset_pending, 0, 1))
3299 return (false);
3300
3301 device_printf(sc->dev, "Received ECC Err, initiating reset\n");
3302 return (true);
3303 }
3304
3305 /************************************************************************
3306 * ixgbe_msix_link - Link status change ISR (MSI/MSI-X)
3307 ************************************************************************/
3308 static int
ixgbe_msix_link(void * arg)3309 ixgbe_msix_link(void *arg)
3310 {
3311 struct ixgbe_softc *sc = arg;
3312 struct ixgbe_hw *hw = &sc->hw;
3313 u32 eicr, eicr_mask;
3314 s32 retval;
3315
3316 ++sc->link_irq;
3317
3318 /* Pause other interrupts */
3319 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER);
3320
3321 /* First get the cause */
3322 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3323 /* Be sure the queue bits are not cleared */
3324 eicr &= ~IXGBE_EICR_RTX_QUEUE;
3325 /* Clear interrupt with write */
3326 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3327
3328 /* Link status change */
3329 if (eicr & IXGBE_EICR_LSC) {
3330 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
3331 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_LSC);
3332 }
3333
3334 if (eicr & IXGBE_EICR_FW_EVENT) {
3335 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FW_EVENT);
3336 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_FWEVENT);
3337 }
3338
3339 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
3340 if ((sc->feat_en & IXGBE_FEATURE_FDIR) &&
3341 (eicr & IXGBE_EICR_FLOW_DIR)) {
3342 /* This is probably overkill :) */
3343 if (atomic_cmpset_int(&sc->fdir_reinit, 0, 1)) {
3344 /* Disable the interrupt */
3345 IXGBE_WRITE_REG(hw, IXGBE_EIMC,
3346 IXGBE_EICR_FLOW_DIR);
3347 atomic_set_32(&sc->task_requests,
3348 IXGBE_REQUEST_TASK_FDIR);
3349 }
3350 }
3351 if (ixgbe_handle_ecc(sc, eicr))
3352 atomic_set_32(&sc->task_requests,
3353 IXGBE_REQUEST_TASK_RESET);
3354
3355 /* Check for over temp condition */
3356 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) {
3357 switch (sc->hw.mac.type) {
3358 case ixgbe_mac_X550EM_a:
3359 if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a))
3360 break;
3361 IXGBE_WRITE_REG(hw, IXGBE_EIMC,
3362 IXGBE_EICR_GPI_SDP0_X550EM_a);
3363 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3364 IXGBE_EICR_GPI_SDP0_X550EM_a);
3365 retval = hw->phy.ops.check_overtemp(hw);
3366 if (retval != IXGBE_ERR_OVERTEMP)
3367 break;
3368 device_printf(iflib_get_dev(sc->ctx),
3369 "\nCRITICAL: OVER TEMP!!"
3370 " PHY IS SHUT DOWN!!\n");
3371 device_printf(iflib_get_dev(sc->ctx),
3372 "System shutdown required!\n");
3373 break;
3374 default:
3375 if (!(eicr & IXGBE_EICR_TS))
3376 break;
3377 retval = hw->phy.ops.check_overtemp(hw);
3378 if (retval != IXGBE_ERR_OVERTEMP)
3379 break;
3380 device_printf(iflib_get_dev(sc->ctx),
3381 "\nCRITICAL: OVER TEMP!!"
3382 " PHY IS SHUT DOWN!!\n");
3383 device_printf(iflib_get_dev(sc->ctx),
3384 "System shutdown required!\n");
3385 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3386 IXGBE_EICR_TS);
3387 break;
3388 }
3389 }
3390
3391 /* Check for VF message */
3392 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) &&
3393 (eicr & IXGBE_EICR_MAILBOX)) {
3394 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MBX);
3395 }
3396 }
3397
3398 /*
3399 * On E610, the firmware handles PHY configuration, so
3400 * there is no need to perform any SFP-specific tasks.
3401 */
3402 if (hw->mac.type != ixgbe_mac_E610 && ixgbe_is_sfp(hw)) {
3403 /* Pluggable optics-related interrupt */
3404 if (hw->mac.type >= ixgbe_mac_X540)
3405 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
3406 else
3407 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw);
3408
3409 if (eicr & eicr_mask) {
3410 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
3411 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MOD);
3412 }
3413
3414 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3415 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) {
3416 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3417 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
3418 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MSF);
3419 }
3420 }
3421
3422 /* Check for fan failure */
3423 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) {
3424 ixgbe_check_fan_failure(sc, eicr, true);
3425 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3426 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
3427 }
3428
3429 /* External PHY interrupt */
3430 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&
3431 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3432 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540);
3433 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_PHY);
3434 }
3435
3436 return (atomic_load_acq_32(&sc->task_requests) != 0) ?
3437 FILTER_SCHEDULE_THREAD : FILTER_HANDLED;
3438 } /* ixgbe_msix_link */
3439
3440 /************************************************************************
3441 * ixgbe_sysctl_interrupt_rate_handler
3442 ************************************************************************/
3443 static int
ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)3444 ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)
3445 {
3446 struct ix_rx_queue *que = ((struct ix_rx_queue *)oidp->oid_arg1);
3447 int error;
3448 unsigned int reg, usec, rate;
3449
3450 if (atomic_load_acq_int(&que->sc->recovery_mode))
3451 return (EPERM);
3452
3453 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix));
3454 usec = ((reg & 0x0FF8) >> 3);
3455 if (usec > 0)
3456 rate = 500000 / usec;
3457 else
3458 rate = 0;
3459 error = sysctl_handle_int(oidp, &rate, 0, req);
3460 if (error || !req->newptr)
3461 return error;
3462 reg &= ~0xfff; /* default, no limitation */
3463 ixgbe_max_interrupt_rate = 0;
3464 if (rate > 0 && rate < 500000) {
3465 if (rate < 1000)
3466 rate = 1000;
3467 ixgbe_max_interrupt_rate = rate;
3468 reg |= ((4000000/rate) & 0xff8);
3469 }
3470 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg);
3471
3472 return (0);
3473 } /* ixgbe_sysctl_interrupt_rate_handler */
3474
3475 /************************************************************************
3476 * ixgbe_debug_dump_print_cluster
3477 ************************************************************************/
3478 static u8
ixgbe_debug_dump_print_cluster(struct ixgbe_softc * sc,struct sbuf * sbuf,u8 cluster_id)3479 ixgbe_debug_dump_print_cluster(struct ixgbe_softc *sc, struct sbuf *sbuf,
3480 u8 cluster_id)
3481 {
3482 u16 data_buf_size = IXGBE_ACI_MAX_BUFFER_SIZE;
3483 device_t dev = sc->dev;
3484 struct ixgbe_hw *hw = &sc->hw;
3485 const u8 reserved_buf[8] = {};
3486 int max_aci_calls = 1000;
3487 int error, counter = 0;
3488 u8 *data_buf;
3489
3490 /* Input parameters / loop variables */
3491 u16 table_id = 0;
3492 u32 offset = 0;
3493
3494 /* Data returned from ACI command */
3495 u16 ret_buf_size = 0;
3496 u16 ret_next_cluster = 0;
3497 u16 ret_next_table = 0;
3498 u32 ret_next_index = 0;
3499
3500 data_buf = (u8 *)malloc(data_buf_size, M_IXGBE, M_NOWAIT | M_ZERO);
3501 if (!data_buf)
3502 return (0);
3503
3504 DEBUGOUT2("%s: dumping cluster id (relative) %d\n",
3505 __func__, cluster_id);
3506
3507 do {
3508 DEBUGOUT3("table_id 0x%04x offset 0x%08x buf_size %d\n",
3509 table_id, offset, data_buf_size);
3510
3511 error = ixgbe_aci_get_internal_data(hw, cluster_id, table_id,
3512 offset, data_buf, data_buf_size, &ret_buf_size,
3513 &ret_next_cluster, &ret_next_table, &ret_next_index);
3514 if (error) {
3515 device_printf(dev,
3516 "%s: Failed to get internal FW/HW data, error: %d, "
3517 "last aci status: %d\n",
3518 __func__, error, hw->aci.last_status);
3519 break;
3520 }
3521
3522 DEBUGOUT3("ret_table_id 0x%04x ret_offset 0x%08x "
3523 "ret_buf_size %d\n",
3524 ret_next_table, ret_next_index, ret_buf_size);
3525
3526 /* Print cluster id */
3527 u32 print_cluster_id = (u32)cluster_id;
3528 sbuf_bcat(sbuf, &print_cluster_id, sizeof(print_cluster_id));
3529 /* Print table id */
3530 u32 print_table_id = (u32)table_id;
3531 sbuf_bcat(sbuf, &print_table_id, sizeof(print_table_id));
3532 /* Print table length */
3533 u32 print_table_length = (u32)ret_buf_size;
3534 sbuf_bcat(sbuf, &print_table_length,
3535 sizeof(print_table_length));
3536 /* Print current offset */
3537 u32 print_curr_offset = offset;
3538 sbuf_bcat(sbuf, &print_curr_offset, sizeof(print_curr_offset));
3539 /* Print reserved bytes */
3540 sbuf_bcat(sbuf, reserved_buf, sizeof(reserved_buf));
3541 /* Print data */
3542 sbuf_bcat(sbuf, data_buf, ret_buf_size);
3543
3544 /* Prepare for the next loop spin */
3545 memset(data_buf, 0, data_buf_size);
3546
3547 bool last_index = (ret_next_index == 0xffffffff);
3548 bool last_table = ((ret_next_table == 0xff ||
3549 ret_next_table == 0xffff) &&
3550 last_index);
3551
3552 if (last_table) {
3553 /* End of the cluster */
3554 DEBUGOUT1("End of the cluster ID %d\n", cluster_id);
3555 break;
3556 } else if (last_index) {
3557 /* End of the table */
3558 table_id = ret_next_table;
3559 offset = 0;
3560 } else {
3561 /* More data left in the table */
3562 offset = ret_next_index;
3563 }
3564 } while (++counter < max_aci_calls);
3565
3566 if (counter >= max_aci_calls)
3567 device_printf(dev, "Exceeded nr of ACI calls for cluster %d\n",
3568 cluster_id);
3569
3570 free(data_buf, M_IXGBE);
3571
3572 return (++cluster_id);
3573 } /* ixgbe_print_debug_dump_cluster */
3574
3575 /************************************************************************
3576 * ixgbe_sysctl_debug_dump_set_clusters
3577 *
3578 * Sets the cluster to dump from FW when Debug Dump requested.
3579 ************************************************************************/
3580 static int
ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS)3581 ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS)
3582 {
3583 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
3584 u32 clusters = sc->debug_dump_cluster_mask;
3585 device_t dev = sc->dev;
3586 int error;
3587
3588 error = sysctl_handle_32(oidp, &clusters, 0, req);
3589 if ((error) || !req->newptr)
3590 return (error);
3591
3592 if (clusters & ~(IXGBE_DBG_DUMP_VALID_CLUSTERS_MASK)) {
3593 device_printf(dev,
3594 "%s: Unrecognized parameter: %u\n",
3595 __func__, clusters);
3596 sc->debug_dump_cluster_mask =
3597 IXGBE_ACI_DBG_DUMP_CLUSTER_ID_INVALID;
3598 return (EINVAL);
3599 }
3600
3601 sc->debug_dump_cluster_mask = clusters;
3602
3603 return (0);
3604 } /* ixgbe_sysctl_debug_dump_set_clusters */
3605
3606 /************************************************************************
3607 * ixgbe_sysctl_dump_debug_dump
3608 ************************************************************************/
3609 static int
ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS)3610 ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS)
3611 {
3612 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
3613 device_t dev = sc->dev;
3614 struct sbuf *sbuf;
3615 int error = 0;
3616
3617 UNREFERENCED_PARAMETER(arg2);
3618
3619 if (!sc->do_debug_dump) {
3620 if (req->oldptr == NULL && req->newptr == NULL) {
3621 error = SYSCTL_OUT(req, 0, 0);
3622 return (error);
3623 }
3624
3625 char input_buf[2] = "";
3626 error = sysctl_handle_string(oidp, input_buf,
3627 sizeof(input_buf), req);
3628 if ((error) || (req->newptr == NULL))
3629 return (error);
3630
3631 if (input_buf[0] == '1') {
3632 if (sc->debug_dump_cluster_mask ==
3633 IXGBE_ACI_DBG_DUMP_CLUSTER_ID_INVALID) {
3634 device_printf(dev,
3635 "Debug Dump failed because an invalid "
3636 "cluster was specified.\n");
3637 return (EINVAL);
3638 }
3639
3640 sc->do_debug_dump = true;
3641 return (0);
3642 }
3643
3644 return (EINVAL);
3645 }
3646
3647 /* Caller just wants the upper bound for size */
3648 if (req->oldptr == NULL && req->newptr == NULL) {
3649 size_t est_output_len = IXGBE_DBG_DUMP_BASE_SIZE;
3650 if (sc->debug_dump_cluster_mask & 0x2)
3651 est_output_len += IXGBE_DBG_DUMP_BASE_SIZE;
3652 error = SYSCTL_OUT(req, 0, est_output_len);
3653 return (error);
3654 }
3655
3656 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
3657 sbuf_clear_flags(sbuf, SBUF_INCLUDENUL);
3658
3659 DEBUGOUT("FW Debug Dump running...\n");
3660
3661 if (sc->debug_dump_cluster_mask) {
3662 for (u8 id = 0; id <= IXGBE_ACI_DBG_DUMP_CLUSTER_ID_MAX; id++) {
3663 if (sc->debug_dump_cluster_mask & BIT(id)) {
3664 DEBUGOUT1("Dumping cluster ID %u...\n", id);
3665 ixgbe_debug_dump_print_cluster(sc, sbuf, id);
3666 }
3667 }
3668 } else {
3669 u8 next_cluster_id = 0;
3670 do {
3671 DEBUGOUT1("Dumping cluster ID %u...\n",
3672 next_cluster_id);
3673 next_cluster_id = ixgbe_debug_dump_print_cluster(sc,
3674 sbuf, next_cluster_id);
3675 } while (next_cluster_id != 0 &&
3676 next_cluster_id <= IXGBE_ACI_DBG_DUMP_CLUSTER_ID_MAX);
3677 }
3678
3679 sbuf_finish(sbuf);
3680 sbuf_delete(sbuf);
3681
3682 sc->do_debug_dump = false;
3683
3684 return (error);
3685 } /* ixgbe_sysctl_dump_debug_dump */
3686
3687 /************************************************************************
3688 * ixgbe_add_debug_dump_sysctls
3689 ************************************************************************/
3690 static void
ixgbe_add_debug_dump_sysctls(struct ixgbe_softc * sc)3691 ixgbe_add_debug_dump_sysctls(struct ixgbe_softc *sc)
3692 {
3693 struct sysctl_oid_list *debug_list, *dump_list;
3694 struct sysctl_oid *dump_node;
3695 struct sysctl_ctx_list *ctx;
3696 device_t dev = sc->dev;
3697
3698 ctx = device_get_sysctl_ctx(dev);
3699 debug_list = SYSCTL_CHILDREN(sc->debug_sysctls);
3700
3701 dump_node = SYSCTL_ADD_NODE(ctx, debug_list, OID_AUTO, "dump",
3702 CTLFLAG_RD, NULL, "Internal FW/HW Dump");
3703 dump_list = SYSCTL_CHILDREN(dump_node);
3704
3705 SYSCTL_ADD_PROC(ctx, dump_list, OID_AUTO, "clusters",
3706 CTLTYPE_U32 | CTLFLAG_RW, sc, 0,
3707 ixgbe_sysctl_debug_dump_set_clusters, "SU",
3708 IXGBE_SYSCTL_DESC_DEBUG_DUMP_SET_CLUSTER);
3709
3710 SYSCTL_ADD_PROC(ctx, dump_list, OID_AUTO, "dump",
3711 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
3712 ixgbe_sysctl_dump_debug_dump, "",
3713 IXGBE_SYSCTL_DESC_DUMP_DEBUG_DUMP);
3714 } /* ixgbe_add_debug_dump_sysctls */
3715
3716 static void
ixgbe_add_debug_sysctls(struct ixgbe_softc * sc)3717 ixgbe_add_debug_sysctls(struct ixgbe_softc *sc)
3718 {
3719 struct sysctl_oid_list *ctx_list;
3720 struct sysctl_ctx_list *ctx;
3721 device_t dev = sc->dev;
3722
3723 ctx = device_get_sysctl_ctx(dev);
3724 ctx_list = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
3725
3726 sc->debug_sysctls = SYSCTL_ADD_NODE(ctx, ctx_list, OID_AUTO, "debug",
3727 CTLFLAG_RD, NULL, "Debug Sysctls");
3728
3729 if (sc->feat_en & IXGBE_FEATURE_DBG_DUMP)
3730 ixgbe_add_debug_dump_sysctls(sc);
3731
3732 if (sc->feat_en & IXGBE_FEATURE_FW_LOGGING)
3733 ixgbe_add_fw_logging_tunables(sc, sc->debug_sysctls);
3734 } /* ixgbe_add_debug_sysctls */
3735
3736 /************************************************************************
3737 * ixgbe_add_device_sysctls
3738 ************************************************************************/
3739 static void
ixgbe_add_device_sysctls(if_ctx_t ctx)3740 ixgbe_add_device_sysctls(if_ctx_t ctx)
3741 {
3742 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3743 device_t dev = iflib_get_dev(ctx);
3744 struct ixgbe_hw *hw = &sc->hw;
3745 struct sysctl_oid_list *child;
3746 struct sysctl_ctx_list *ctx_list;
3747
3748 ctx_list = device_get_sysctl_ctx(dev);
3749 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
3750
3751 /* Sysctls for all devices */
3752 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc",
3753 CTLTYPE_INT | CTLFLAG_RW,
3754 sc, 0, ixgbe_sysctl_flowcntl, "I",
3755 IXGBE_SYSCTL_DESC_SET_FC);
3756
3757 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "advertise_speed",
3758 CTLTYPE_INT | CTLFLAG_RW,
3759 sc, 0, ixgbe_sysctl_advertise, "I",
3760 IXGBE_SYSCTL_DESC_ADV_SPEED);
3761 if (hw->mac.type == ixgbe_mac_82599EB ||
3762 hw->mac.type == ixgbe_mac_X540) {
3763 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3764 "iov_dma_abort_events", CTLFLAG_RD,
3765 &sc->iov_dma_abort_events, 0,
3766 "VF invalid-DMA events");
3767 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3768 "iov_dma_abort_flr_failures", CTLFLAG_RD,
3769 &sc->iov_dma_abort_flr_failures, 0,
3770 "Failed VF reset attempts after invalid-DMA events");
3771 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3772 "iov_dma_abort_quarantines", CTLFLAG_RD,
3773 &sc->iov_dma_abort_quarantines, 0,
3774 "VFs quarantined after repeated invalid-DMA events");
3775 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3776 "iov_quarantined_vfs", CTLFLAG_RD,
3777 &sc->iov_quarantined_vfs, 0,
3778 "Bitmap of quarantined VF pools");
3779 }
3780
3781 sc->enable_aim = ixgbe_enable_aim;
3782 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", CTLFLAG_RW,
3783 &sc->enable_aim, 0, "Interrupt Moderation");
3784
3785 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
3786 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
3787 ixgbe_sysctl_print_fw_version, "A", "Prints FW/NVM Versions");
3788
3789 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
3790 "tso_tcp_flags_mask_first_segment",
3791 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
3792 sc, 0, ixgbe_sysctl_tso_tcp_flags_mask, "IU",
3793 "TSO TCP flags mask for first segment");
3794
3795 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
3796 "tso_tcp_flags_mask_middle_segment",
3797 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
3798 sc, 1, ixgbe_sysctl_tso_tcp_flags_mask, "IU",
3799 "TSO TCP flags mask for middle segment");
3800
3801 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
3802 "tso_tcp_flags_mask_last_segment",
3803 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
3804 sc, 2, ixgbe_sysctl_tso_tcp_flags_mask, "IU",
3805 "TSO TCP flags mask for last segment");
3806
3807 #ifdef IXGBE_DEBUG
3808 /* testing sysctls (for all devices) */
3809 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "power_state",
3810 CTLTYPE_INT | CTLFLAG_RW,
3811 sc, 0, ixgbe_sysctl_power_state,
3812 "I", "PCI Power State");
3813
3814 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "print_rss_config",
3815 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
3816 ixgbe_sysctl_print_rss_config, "A", "Prints RSS Configuration");
3817 #endif
3818 /* for X550 series devices */
3819 if (hw->mac.type >= ixgbe_mac_X550)
3820 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac",
3821 CTLTYPE_U16 | CTLFLAG_RW,
3822 sc, 0, ixgbe_sysctl_dmac,
3823 "I", "DMA Coalesce");
3824
3825 /* for X552/X557-AT devices */
3826 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
3827 struct sysctl_oid *phy_node;
3828 struct sysctl_oid_list *phy_list;
3829
3830 phy_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "phy",
3831 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3832 "External PHY sysctls");
3833 phy_list = SYSCTL_CHILDREN(phy_node);
3834
3835 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, "temp",
3836 CTLTYPE_U16 | CTLFLAG_RD,
3837 sc, 0, ixgbe_sysctl_phy_temp,
3838 "I", "Current External PHY Temperature (Celsius)");
3839
3840 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO,
3841 "overtemp_occurred",
3842 CTLTYPE_U16 | CTLFLAG_RD, sc, 0,
3843 ixgbe_sysctl_phy_overtemp_occurred, "I",
3844 "External PHY High Temperature Event Occurred");
3845 }
3846
3847 if (sc->feat_cap & IXGBE_FEATURE_EEE) {
3848 struct sysctl_oid *eee_node;
3849 struct sysctl_oid_list *eee_list;
3850
3851 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_state",
3852 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
3853 ixgbe_sysctl_eee_state, "I", "EEE Power Save State");
3854
3855 eee_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "eee",
3856 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3857 "Energy Efficient Ethernet statistics");
3858 eee_list = SYSCTL_CHILDREN(eee_node);
3859 SYSCTL_ADD_UQUAD(ctx_list, eee_list, OID_AUTO, "tx_lpi_count",
3860 CTLFLAG_RD, &sc->stats.pf.tlpic, "TX LPI event count");
3861 SYSCTL_ADD_UQUAD(ctx_list, eee_list, OID_AUTO, "rx_lpi_count",
3862 CTLFLAG_RD, &sc->stats.pf.rlpic, "RX LPI event count");
3863 }
3864
3865 ixgbe_add_debug_sysctls(sc);
3866 } /* ixgbe_add_device_sysctls */
3867
3868 /************************************************************************
3869 * ixgbe_allocate_pci_resources
3870 ************************************************************************/
3871 static int
ixgbe_allocate_pci_resources(if_ctx_t ctx)3872 ixgbe_allocate_pci_resources(if_ctx_t ctx)
3873 {
3874 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3875 device_t dev = iflib_get_dev(ctx);
3876 int rid;
3877
3878 rid = PCIR_BAR(0);
3879 sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3880 RF_ACTIVE);
3881
3882 if (!(sc->pci_mem)) {
3883 device_printf(dev,
3884 "Unable to allocate bus resource: memory\n");
3885 return (ENXIO);
3886 }
3887
3888 /* Save bus_space values for READ/WRITE_REG macros */
3889 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->pci_mem);
3890 sc->osdep.mem_bus_space_handle =
3891 rman_get_bushandle(sc->pci_mem);
3892 /* Set hw values for shared code */
3893 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
3894
3895 return (0);
3896 } /* ixgbe_allocate_pci_resources */
3897
3898 /************************************************************************
3899 * ixgbe_detach - Device removal routine
3900 *
3901 * Called when the driver is being removed.
3902 * Stops the adapter and deallocates all the resources
3903 * that were allocated for driver operation.
3904 *
3905 * return 0 on success, positive on failure
3906 ************************************************************************/
3907 static int
ixgbe_if_detach(if_ctx_t ctx)3908 ixgbe_if_detach(if_ctx_t ctx)
3909 {
3910 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3911 u32 ctrl_ext;
3912
3913 INIT_DEBUGOUT("ixgbe_detach: begin");
3914
3915 sc->iov_recovery_stop = true;
3916
3917 ixgbe_setup_low_power_mode(ctx, false);
3918
3919 /* let hardware know driver is unloading */
3920 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
3921 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD;
3922 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
3923
3924 callout_drain(&sc->fw_mode_timer);
3925
3926 if (sc->hw.mac.type == ixgbe_mac_E610) {
3927 ixgbe_disable_lse(sc);
3928 ixgbe_shutdown_aci(&sc->hw);
3929 }
3930
3931 ixgbe_free_pci_resources(ctx);
3932
3933 free(sc->mta, M_IXGBE);
3934
3935 return (0);
3936 } /* ixgbe_if_detach */
3937
3938 static void
ixgbe_prepare_wakeup(if_ctx_t ctx,bool arm_wake)3939 ixgbe_prepare_wakeup(if_ctx_t ctx, bool arm_wake)
3940 {
3941 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3942 struct ixgbe_hw *hw = &sc->hw;
3943 if_t ifp = iflib_get_ifp(ctx);
3944 int enabled;
3945 u32 wufc;
3946
3947 enabled = arm_wake ?
3948 if_getcapenable(ifp) & if_getcapabilities(ifp) & IFCAP_WOL : 0;
3949 wufc = 0;
3950 if ((enabled & IFCAP_WOL_MAGIC) != 0)
3951 wufc |= IXGBE_WUFC_MAG;
3952 if ((enabled & IFCAP_WOL_UCAST) != 0)
3953 wufc |= IXGBE_WUFC_EX;
3954 if ((enabled & IFCAP_WOL_MCAST) != 0)
3955 wufc |= IXGBE_WUFC_MC;
3956 sc->wol_filters = wufc;
3957 hw->wol_enabled = wufc != 0;
3958
3959 /* X550EM 10GBASE-T requires PHY reset suppression during the stop. */
3960 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T &&
3961 hw->phy.ops.enter_lplu != NULL)
3962 hw->phy.reset_disable = true;
3963 }
3964
3965 static u_int
ixgbe_wakeup_mta_apply(void * arg,struct sockaddr_dl * sdl,u_int idx __unused)3966 ixgbe_wakeup_mta_apply(void *arg, struct sockaddr_dl *sdl, u_int idx __unused)
3967 {
3968 struct ixgbe_hw *hw = arg;
3969
3970 ixgbe_set_mta(hw, LLADDR(sdl));
3971 return (1);
3972 }
3973
3974 /* Restore multicast hashes needed by directed and multicast-magic wake. */
3975 static void
ixgbe_configure_wakeup_mta(if_ctx_t ctx)3976 ixgbe_configure_wakeup_mta(if_ctx_t ctx)
3977 {
3978 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3979 struct ixgbe_hw *hw = &sc->hw;
3980 u_int i, mcnt;
3981
3982 bzero(hw->mac.mta_shadow, sizeof(hw->mac.mta_shadow));
3983 hw->addr_ctrl.mta_in_use = 0;
3984 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx),
3985 ixgbe_wakeup_mta_apply, hw);
3986 hw->addr_ctrl.num_mc_addrs = mcnt;
3987 for (i = 0; i < hw->mac.mcft_size; i++)
3988 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
3989 hw->mac.mta_shadow[i]);
3990 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3991 (hw->addr_ctrl.mta_in_use != 0 ? IXGBE_MCSTCTRL_MFE : 0) |
3992 hw->mac.mc_filter_type);
3993 }
3994
3995 /************************************************************************
3996 * ixgbe_setup_low_power_mode - LPLU/WoL preparation
3997 *
3998 * Prepare the adapter/port for LPLU and/or WoL
3999 ************************************************************************/
4000 static int
ixgbe_setup_low_power_mode(if_ctx_t ctx,bool arm_wake)4001 ixgbe_setup_low_power_mode(if_ctx_t ctx, bool arm_wake)
4002 {
4003 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4004 struct ixgbe_hw *hw = &sc->hw;
4005 device_t dev = iflib_get_dev(ctx);
4006 u32 fctrl, grc, wufc;
4007 s32 error = 0;
4008
4009 /* Snapshot wake policy before the terminal stop clears hardware state. */
4010 ixgbe_prepare_wakeup(ctx, arm_wake);
4011 wufc = sc->wol_filters;
4012 ixgbe_if_stop(ctx);
4013
4014 /* Limit power management flow to X550EM baseT */
4015 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T &&
4016 hw->phy.ops.enter_lplu) {
4017 /* X550EM baseT adapters need a special LPLU flow. */
4018 error = hw->phy.ops.enter_lplu(hw);
4019 if (error)
4020 device_printf(dev, "Error entering LPLU: %d\n",
4021 error);
4022 hw->phy.reset_disable = false;
4023 error = 0;
4024 }
4025
4026 /* Disable the 82599 link only when actually entering D3. */
4027 if (hw->mac.type == ixgbe_mac_82599EB)
4028 ixgbe_stop_mac_link_on_d3_82599(hw);
4029
4030 /*
4031 * Make ifconfig's ACPI policy authoritative. All supported families,
4032 * including E610, implement the standard filters in WUFC; leaving the
4033 * NVM-selected APM path enabled would permit an unrequested magic wake.
4034 */
4035 if (hw->mac.type != ixgbe_mac_82598EB) {
4036 grc = IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw));
4037 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw),
4038 grc & ~IXGBE_GRC_APME);
4039 }
4040 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4041 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4042 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff);
4043 pci_clear_pme(dev);
4044 if (wufc != 0) {
4045 bcopy(if_getlladdr(iflib_get_ifp(ctx)), hw->mac.addr,
4046 IXGBE_ETH_LENGTH_OF_ADDRESS);
4047 error = ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool,
4048 IXGBE_RAH_AV);
4049 if (error != IXGBE_SUCCESS) {
4050 device_printf(dev,
4051 "Could not restore unicast wake address: %d\n", error);
4052 sc->wol_filters = 0;
4053 hw->wol_enabled = false;
4054 goto no_wake;
4055 }
4056
4057 /* 82599 SFP+ ports need the laser for an optical wake packet. */
4058 ixgbe_enable_tx_laser(hw);
4059
4060 /* Rebuild address filtering erased by the terminal reset. */
4061 ixgbe_configure_wakeup_mta(ctx);
4062 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4063 fctrl |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_MPE;
4064 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4065
4066 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4067 IXGBE_WRITE_REG(hw, IXGBE_WUC,
4068 IXGBE_WUC_WKEN | IXGBE_WUC_PME_EN);
4069 pci_enable_pme(dev);
4070 return (0);
4071 }
4072
4073 no_wake:
4074 ixgbe_set_phy_power(hw, false);
4075 return (error == IXGBE_SUCCESS ? 0 : EIO);
4076 } /* ixgbe_setup_low_power_mode */
4077
4078 /************************************************************************
4079 * ixgbe_shutdown - Shutdown entry point
4080 ************************************************************************/
4081 static int
ixgbe_if_shutdown(if_ctx_t ctx)4082 ixgbe_if_shutdown(if_ctx_t ctx)
4083 {
4084 int error = 0;
4085
4086 INIT_DEBUGOUT("ixgbe_shutdown: begin");
4087
4088 error = ixgbe_setup_low_power_mode(ctx, true);
4089 if (error != 0)
4090 device_printf(iflib_get_dev(ctx),
4091 "Wake configuration failed during shutdown: %d\n", error);
4092 return (0);
4093 } /* ixgbe_if_shutdown */
4094
4095 /************************************************************************
4096 * ixgbe_suspend
4097 *
4098 * From D0 to D3
4099 ************************************************************************/
4100 static int
ixgbe_if_suspend(if_ctx_t ctx)4101 ixgbe_if_suspend(if_ctx_t ctx)
4102 {
4103 int error = 0;
4104
4105 INIT_DEBUGOUT("ixgbe_suspend: begin");
4106
4107 error = ixgbe_setup_low_power_mode(ctx, true);
4108
4109 return (error);
4110 } /* ixgbe_if_suspend */
4111
4112 /************************************************************************
4113 * ixgbe_resume
4114 *
4115 * From D3 to D0
4116 ************************************************************************/
4117 static int
ixgbe_if_resume(if_ctx_t ctx)4118 ixgbe_if_resume(if_ctx_t ctx)
4119 {
4120 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4121 device_t dev = iflib_get_dev(ctx);
4122 if_t ifp = iflib_get_ifp(ctx);
4123 struct ixgbe_hw *hw = &sc->hw;
4124 u32 wus;
4125
4126 INIT_DEBUGOUT("ixgbe_resume: begin");
4127
4128 /* Read & clear WUS register */
4129 wus = IXGBE_READ_REG(hw, IXGBE_WUS);
4130 if (wus)
4131 device_printf(dev, "Woken up by (WUS): %#010x\n",
4132 wus);
4133 /* Remove every device wake source before clearing PCI PME. */
4134 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4135 if (hw->mac.type != ixgbe_mac_82598EB)
4136 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw),
4137 IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) &
4138 ~IXGBE_GRC_APME);
4139 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4140 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff);
4141 pci_clear_pme(dev);
4142 hw->wol_enabled = false;
4143 sc->wol_filters = 0;
4144
4145 /*
4146 * Required after D3->D0 transition;
4147 * will re-advertise all previous advertised speeds
4148 */
4149 if (if_getflags(ifp) & IFF_UP)
4150 ixgbe_if_init(ctx);
4151
4152 return (0);
4153 } /* ixgbe_if_resume */
4154
4155 /************************************************************************
4156 * ixgbe_if_mtu_set - Ioctl mtu entry point
4157 *
4158 * Return 0 on success, EINVAL on failure
4159 ************************************************************************/
4160 static int
ixgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)4161 ixgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
4162 {
4163 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4164 int error = 0;
4165
4166 IOCTL_DEBUGOUT("ioctl: SIOCIFMTU (Set Interface MTU)");
4167
4168 if (mtu > IXGBE_MAX_MTU) {
4169 error = EINVAL;
4170 } else {
4171 sc->max_frame_size = mtu + IXGBE_MTU_HDR;
4172 }
4173
4174 return error;
4175 } /* ixgbe_if_mtu_set */
4176
4177 /************************************************************************
4178 * ixgbe_if_crcstrip_set
4179 ************************************************************************/
4180 static void
ixgbe_if_crcstrip_set(if_ctx_t ctx,int onoff,int crcstrip)4181 ixgbe_if_crcstrip_set(if_ctx_t ctx, int onoff, int crcstrip)
4182 {
4183 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4184 struct ixgbe_hw *hw = &sc->hw;
4185 /* crc stripping is set in two places:
4186 * IXGBE_HLREG0 (modified on init_locked and hw reset)
4187 * IXGBE_RDRXCTL (set by the original driver in
4188 * ixgbe_setup_hw_rsc() called in init_locked.
4189 * We disable the setting when netmap is compiled in).
4190 * We update the values here, but also in ixgbe.c because
4191 * init_locked sometimes is called outside our control.
4192 */
4193 uint32_t hl, rxc;
4194
4195 hl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4196 rxc = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4197 #ifdef NETMAP
4198 if (netmap_verbose)
4199 D("%s read HLREG 0x%x rxc 0x%x",
4200 onoff ? "enter" : "exit", hl, rxc);
4201 #endif
4202 /* hw requirements ... */
4203 rxc &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4204 rxc |= IXGBE_RDRXCTL_RSCACKC;
4205 if (onoff && !crcstrip) {
4206 /* keep the crc. Fast rx */
4207 hl &= ~IXGBE_HLREG0_RXCRCSTRP;
4208 rxc &= ~IXGBE_RDRXCTL_CRCSTRIP;
4209 } else {
4210 /* reset default mode */
4211 hl |= IXGBE_HLREG0_RXCRCSTRP;
4212 rxc |= IXGBE_RDRXCTL_CRCSTRIP;
4213 }
4214 #ifdef NETMAP
4215 if (netmap_verbose)
4216 D("%s write HLREG 0x%x rxc 0x%x",
4217 onoff ? "enter" : "exit", hl, rxc);
4218 #endif
4219 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hl);
4220 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rxc);
4221 } /* ixgbe_if_crcstrip_set */
4222
4223 /*********************************************************************
4224 * ixgbe_if_init - Init entry point
4225 *
4226 * Used in two ways: It is used by the stack as an init
4227 * entry point in network interface structure. It is also
4228 * used by the driver as a hw/sw initialization routine to
4229 * get to a consistent state.
4230 *
4231 * Return 0 on success, positive on failure
4232 **********************************************************************/
4233 void
ixgbe_if_init(if_ctx_t ctx)4234 ixgbe_if_init(if_ctx_t ctx)
4235 {
4236 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4237 if_t ifp = iflib_get_ifp(ctx);
4238 device_t dev = iflib_get_dev(ctx);
4239 struct ixgbe_hw *hw = &sc->hw;
4240 struct ix_rx_queue *rx_que;
4241 struct ix_tx_queue *tx_que;
4242 u32 txdctl, mhadd;
4243 u32 rxdctl, rxctrl;
4244 u32 ctrl_ext;
4245
4246 int i, j, err;
4247
4248 INIT_DEBUGOUT("ixgbe_if_init: begin");
4249 if (atomic_load_acq_int(&sc->recovery_mode)) {
4250 iflib_init_failed(ctx);
4251 return;
4252 }
4253 /* Leave an overheated adapter stopped until an operator retries. */
4254 if (sc->overtemp_shutdown_pending) {
4255 sc->overtemp_shutdown_pending = false;
4256 iflib_init_failed(ctx);
4257 return;
4258 }
4259
4260 /* Preserve the largest frame requested by the PF or an active VF. */
4261 sc->max_frame_size = if_getmtu(ifp) + IXGBE_MTU_HDR;
4262 ixgbe_recalculate_max_frame(sc);
4263
4264 /* Queue indices may change with IOV mode */
4265 ixgbe_align_all_queue_indices(sc);
4266
4267 /* reprogram the RAR[0] in case user changed it. */
4268 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, IXGBE_RAH_AV);
4269
4270 /* Get the latest mac address, User can use a LAA */
4271 bcopy(if_getlladdr(ifp), hw->mac.addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
4272 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 1);
4273 hw->addr_ctrl.rar_used_count = 1;
4274
4275 ixgbe_init_hw(hw);
4276 sc->iov_mta_valid = false;
4277 sc->iov_vfta_valid = false;
4278
4279 ixgbe_initialize_iov(sc);
4280
4281 ixgbe_initialize_transmit_units(ctx);
4282
4283 /* Setup Multicast table */
4284 ixgbe_if_multi_set(ctx);
4285
4286 /* Determine the correct mbuf pool, based on frame size */
4287 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
4288
4289 /* Configure RX settings */
4290 ixgbe_initialize_receive_units(ctx);
4291
4292 /*
4293 * Initialize the deferred administrative request mask.
4294 */
4295 atomic_store_rel_32(&sc->task_requests, 0);
4296
4297 /* Enable SDP & MSI-X interrupts based on adapter */
4298 ixgbe_config_gpie(sc);
4299
4300 /* Set MTU size */
4301 if (sc->max_frame_size > ETHER_MAX_LEN) {
4302 /* aka IXGBE_MAXFRS on 82599 and newer */
4303 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4304 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4305 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT;
4306 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4307 }
4308
4309 /* Now enable all the queues */
4310 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues;
4311 i++, tx_que++) {
4312 struct tx_ring *txr = &tx_que->txr;
4313
4314 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me));
4315 txdctl &= ~IXGBE_TXDCTL_THRESH_MASK;
4316 txdctl |= IXGBE_TXDCTL_ENABLE | IXGBE_TXDCTL_THRESH_DEFAULT;
4317 /*
4318 * When the internal queue falls below PTHRESH (32),
4319 * start prefetching as long as there are at least
4320 * HTHRESH (1) buffers ready. Leave WTHRESH at zero
4321 * so that writeback follows iflib's sparse RS bits.
4322 * Prefetching enables tx line rate even with 1 queue.
4323 */
4324 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl);
4325 }
4326
4327 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues;
4328 i++, rx_que++) {
4329 struct rx_ring *rxr = &rx_que->rxr;
4330
4331 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me));
4332 if (hw->mac.type == ixgbe_mac_82598EB) {
4333 /*
4334 * PTHRESH = 21
4335 * HTHRESH = 4
4336 * WTHRESH = 8
4337 */
4338 rxdctl &= ~0x3FFFFF;
4339 rxdctl |= 0x080420;
4340 }
4341 rxdctl |= IXGBE_RXDCTL_ENABLE;
4342 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), rxdctl);
4343 for (j = 0; j < 10; j++) {
4344 if (IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)) &
4345 IXGBE_RXDCTL_ENABLE)
4346 break;
4347 else
4348 msec_delay(1);
4349 }
4350 wmb();
4351 }
4352
4353 /* Enable Receive engine */
4354 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4355 if (hw->mac.type == ixgbe_mac_82598EB)
4356 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4357 rxctrl |= IXGBE_RXCTRL_RXEN;
4358 ixgbe_enable_rx_dma(hw, rxctrl);
4359
4360 /* Set up MSI/MSI-X routing */
4361 if (ixgbe_enable_msix) {
4362 ixgbe_configure_ivars(sc);
4363 /* Set up auto-mask */
4364 if (hw->mac.type == ixgbe_mac_82598EB)
4365 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4366 else {
4367 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4368 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4369 }
4370 } else { /* Simple settings for Legacy/MSI */
4371 ixgbe_set_ivar(sc, 0, 0, 0);
4372 ixgbe_set_ivar(sc, 0, 0, 1);
4373 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4374 }
4375
4376 ixgbe_init_fdir(sc);
4377
4378 /*
4379 * Check on any SFP devices that
4380 * need to be kick-started
4381 */
4382 if (hw->phy.type == ixgbe_phy_none) {
4383 err = hw->phy.ops.identify(hw);
4384 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4385 device_printf(dev,
4386 "Unsupported SFP+ module type was detected.\n");
4387 return;
4388 }
4389 }
4390
4391 /* Set moderation on the Link interrupt */
4392 IXGBE_WRITE_REG(hw, IXGBE_EITR(sc->vector), IXGBE_LINK_ITR);
4393
4394 /* Enable power to the phy. */
4395 ixgbe_set_phy_power(hw, true);
4396
4397 /* Config/Enable Link */
4398 ixgbe_config_link(ctx);
4399
4400 /* Hardware Packet Buffer & Flow Control setup */
4401 ixgbe_config_delay_values(sc);
4402
4403 /* Initialize the FC settings */
4404 ixgbe_start_hw(hw);
4405
4406 /* Set up VLAN support and filter */
4407 ixgbe_setup_vlan_hw_support(ctx);
4408
4409 /* Setup DMA Coalescing */
4410 ixgbe_config_dmac(sc);
4411
4412 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
4413 ixgbe_enable_mdd(hw);
4414 ixgbe_activate_vfs(sc);
4415 }
4416
4417 /* And now turn on interrupts */
4418 ixgbe_if_enable_intr(ctx);
4419
4420 /* Enable the use of the MBX by the VF's */
4421 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
4422 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4423 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4424 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4425 }
4426
4427 } /* ixgbe_init_locked */
4428
4429 /************************************************************************
4430 * ixgbe_set_ivar
4431 *
4432 * Setup the correct IVAR register for a particular MSI-X interrupt
4433 * (yes this is all very magic and confusing :)
4434 * - entry is the register array entry
4435 * - vector is the MSI-X vector for this queue
4436 * - type is RX/TX/MISC
4437 ************************************************************************/
4438 static void
ixgbe_set_ivar(struct ixgbe_softc * sc,u8 entry,u8 vector,s8 type)4439 ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type)
4440 {
4441 struct ixgbe_hw *hw = &sc->hw;
4442 u32 ivar, index;
4443
4444 vector |= IXGBE_IVAR_ALLOC_VAL;
4445
4446 switch (hw->mac.type) {
4447 case ixgbe_mac_82598EB:
4448 if (type == -1)
4449 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4450 else
4451 entry += (type * 64);
4452 index = (entry >> 2) & 0x1F;
4453 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4454 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4455 ivar |= (vector << (8 * (entry & 0x3)));
4456 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar);
4457 break;
4458 case ixgbe_mac_82599EB:
4459 case ixgbe_mac_X540:
4460 case ixgbe_mac_X550:
4461 case ixgbe_mac_X550EM_x:
4462 case ixgbe_mac_X550EM_a:
4463 case ixgbe_mac_E610:
4464 if (type == -1) { /* MISC IVAR */
4465 index = (entry & 1) * 8;
4466 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4467 ivar &= ~(0xFF << index);
4468 ivar |= (vector << index);
4469 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4470 } else { /* RX/TX IVARS */
4471 index = (16 * (entry & 1)) + (8 * type);
4472 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4473 ivar &= ~(0xFF << index);
4474 ivar |= (vector << index);
4475 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4476 }
4477 default:
4478 break;
4479 }
4480 } /* ixgbe_set_ivar */
4481
4482 /************************************************************************
4483 * ixgbe_configure_ivars
4484 ************************************************************************/
4485 static void
ixgbe_configure_ivars(struct ixgbe_softc * sc)4486 ixgbe_configure_ivars(struct ixgbe_softc *sc)
4487 {
4488 struct ix_rx_queue *rx_que = sc->rx_queues;
4489 struct ix_tx_queue *tx_que = sc->tx_queues;
4490 u32 newitr;
4491
4492 if (ixgbe_max_interrupt_rate > 0)
4493 newitr = (4000000 / ixgbe_max_interrupt_rate) & 0x0FF8;
4494 else {
4495 /*
4496 * Disable DMA coalescing if interrupt moderation is
4497 * disabled.
4498 */
4499 sc->dmac = 0;
4500 newitr = 0;
4501 }
4502
4503 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) {
4504 struct rx_ring *rxr = &rx_que->rxr;
4505
4506 /* First the RX queue entry */
4507 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0);
4508
4509 /* Set an Initial EITR value */
4510 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr);
4511 }
4512 for (int i = 0; i < sc->num_tx_queues; i++, tx_que++) {
4513 struct tx_ring *txr = &tx_que->txr;
4514
4515 /* ... and the TX */
4516 ixgbe_set_ivar(sc, txr->me, tx_que->msix, 1);
4517 }
4518 /* For the Link interrupt */
4519 ixgbe_set_ivar(sc, 1, sc->vector, -1);
4520 } /* ixgbe_configure_ivars */
4521
4522 /************************************************************************
4523 * ixgbe_config_gpie
4524 ************************************************************************/
4525 static void
ixgbe_config_gpie(struct ixgbe_softc * sc)4526 ixgbe_config_gpie(struct ixgbe_softc *sc)
4527 {
4528 struct ixgbe_hw *hw = &sc->hw;
4529 u32 gpie;
4530
4531 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4532
4533 if (sc->intr_type == IFLIB_INTR_MSIX) {
4534 /* Enable Enhanced MSI-X mode */
4535 gpie |= IXGBE_GPIE_MSIX_MODE |
4536 IXGBE_GPIE_EIAME |
4537 IXGBE_GPIE_PBA_SUPPORT |
4538 IXGBE_GPIE_OCD;
4539 }
4540
4541 /* Fan Failure Interrupt */
4542 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL)
4543 gpie |= IXGBE_SDP1_GPIEN;
4544
4545 /* Thermal Sensor Interrupt */
4546 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR)
4547 gpie |= IXGBE_SDP0_GPIEN_X540;
4548
4549 /* Link detection */
4550 switch (hw->mac.type) {
4551 case ixgbe_mac_82599EB:
4552 gpie |= IXGBE_SDP1_GPIEN | IXGBE_SDP2_GPIEN;
4553 break;
4554 case ixgbe_mac_X550EM_x:
4555 case ixgbe_mac_X550EM_a:
4556 gpie |= IXGBE_SDP0_GPIEN_X540;
4557 break;
4558 default:
4559 break;
4560 }
4561
4562 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4563
4564 } /* ixgbe_config_gpie */
4565
4566 /************************************************************************
4567 * ixgbe_config_delay_values
4568 *
4569 * Requires sc->max_frame_size to be set.
4570 ************************************************************************/
4571 static void
ixgbe_config_delay_values(struct ixgbe_softc * sc)4572 ixgbe_config_delay_values(struct ixgbe_softc *sc)
4573 {
4574 struct ixgbe_hw *hw = &sc->hw;
4575 u32 rxpb, frame, size, tmp;
4576
4577 frame = sc->max_frame_size;
4578
4579 /* Calculate High Water */
4580 switch (hw->mac.type) {
4581 case ixgbe_mac_X540:
4582 case ixgbe_mac_X550:
4583 case ixgbe_mac_X550EM_x:
4584 case ixgbe_mac_X550EM_a:
4585 tmp = IXGBE_DV_X540(frame, frame);
4586 break;
4587 default:
4588 tmp = IXGBE_DV(frame, frame);
4589 break;
4590 }
4591 size = IXGBE_BT2KB(tmp);
4592 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10;
4593 hw->fc.high_water[0] = rxpb - size;
4594
4595 /* Now calculate Low Water */
4596 switch (hw->mac.type) {
4597 case ixgbe_mac_X540:
4598 case ixgbe_mac_X550:
4599 case ixgbe_mac_X550EM_x:
4600 case ixgbe_mac_X550EM_a:
4601 tmp = IXGBE_LOW_DV_X540(frame);
4602 break;
4603 default:
4604 tmp = IXGBE_LOW_DV(frame);
4605 break;
4606 }
4607 hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
4608
4609 hw->fc.pause_time = IXGBE_FC_PAUSE;
4610 hw->fc.send_xon = true;
4611 } /* ixgbe_config_delay_values */
4612
4613 /************************************************************************
4614 * ixgbe_set_multi - Multicast Update
4615 *
4616 * Called whenever multicast address list is updated.
4617 ************************************************************************/
4618 static u_int
ixgbe_mc_filter_apply(void * arg,struct sockaddr_dl * sdl,u_int idx)4619 ixgbe_mc_filter_apply(void *arg, struct sockaddr_dl *sdl, u_int idx)
4620 {
4621 struct ixgbe_softc *sc = arg;
4622 struct ixgbe_mc_addr *mta = sc->mta;
4623
4624 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
4625 return (0);
4626 bcopy(LLADDR(sdl), mta[idx].addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
4627 mta[idx].vmdq = sc->pool;
4628
4629 return (1);
4630 } /* ixgbe_mc_filter_apply */
4631
4632 #ifdef PCI_IOV
4633 /*
4634 * The MTA is shared by the PF and every VF. Rebuild it from all owners
4635 * because an individual bit cannot be cleared safely when hashes collide.
4636 */
4637 u_int
ixgbe_iov_rebuild_mta(struct ixgbe_softc * sc)4638 ixgbe_iov_rebuild_mta(struct ixgbe_softc *sc)
4639 {
4640 struct ixgbe_hw *hw;
4641 struct ixgbe_mc_addr *mta;
4642 struct ixgbe_vf *vf;
4643 u32 old_mta[IXGBE_MAX_MTA];
4644 u32 hash;
4645 u_int i, mcnt;
4646 int vf_index;
4647
4648 hw = &sc->hw;
4649 mta = sc->mta;
4650 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES);
4651 mcnt = if_foreach_llmaddr(iflib_get_ifp(sc->ctx),
4652 ixgbe_mc_filter_apply, sc);
4653
4654 bcopy(hw->mac.mta_shadow, old_mta, sizeof(old_mta));
4655 bzero(hw->mac.mta_shadow, sizeof(hw->mac.mta_shadow));
4656 hw->addr_ctrl.num_mc_addrs = mcnt;
4657 hw->addr_ctrl.mta_in_use = 0;
4658
4659 for (i = 0; i < mcnt; i++)
4660 ixgbe_set_mta(hw, mta[i].addr);
4661
4662 for (vf_index = 0; vf_index < sc->num_vfs; vf_index++) {
4663 vf = &sc->vfs[vf_index];
4664 if (!(vf->flags & IXGBE_VF_ACTIVE))
4665 continue;
4666
4667 for (i = 0; i < vf->num_mc_hashes; i++) {
4668 hash = vf->mc_hash[i] & 0xfff;
4669 hw->mac.mta_shadow[(hash >> 5) &
4670 (hw->mac.mcft_size - 1)] |=
4671 1U << (hash & 0x1f);
4672 hw->addr_ctrl.mta_in_use++;
4673 }
4674 }
4675
4676 for (i = 0; i < hw->mac.mcft_size; i++) {
4677 if (sc->iov_mta_valid &&
4678 old_mta[i] == hw->mac.mta_shadow[i])
4679 continue;
4680 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
4681 hw->mac.mta_shadow[i]);
4682 }
4683 sc->iov_mta_valid = true;
4684
4685 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4686 (hw->addr_ctrl.mta_in_use != 0 ? IXGBE_MCSTCTRL_MFE : 0) |
4687 hw->mac.mc_filter_type);
4688
4689 return (mcnt);
4690 }
4691 #endif
4692
4693 static void
ixgbe_if_multi_set(if_ctx_t ctx)4694 ixgbe_if_multi_set(if_ctx_t ctx)
4695 {
4696 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4697 struct ixgbe_mc_addr *mta;
4698 if_t ifp = iflib_get_ifp(ctx);
4699 u8 *update_ptr;
4700 u32 fctrl;
4701 u_int mcnt;
4702
4703 IOCTL_DEBUGOUT("ixgbe_if_multi_set: begin");
4704
4705 #ifdef PCI_IOV
4706 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
4707 mcnt = ixgbe_iov_rebuild_mta(sc);
4708 } else
4709 #endif
4710 {
4711 mta = sc->mta;
4712 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES);
4713
4714 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx),
4715 ixgbe_mc_filter_apply, sc);
4716
4717 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) {
4718 update_ptr = (u8 *)mta;
4719 ixgbe_update_mc_addr_list(&sc->hw, update_ptr, mcnt,
4720 ixgbe_mc_array_itr, true);
4721 }
4722 }
4723
4724 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
4725
4726 if (if_getflags(ifp) & IFF_PROMISC)
4727 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4728 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
4729 if_getflags(ifp) & IFF_ALLMULTI) {
4730 fctrl |= IXGBE_FCTRL_MPE;
4731 fctrl &= ~IXGBE_FCTRL_UPE;
4732 } else
4733 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4734
4735 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl);
4736 } /* ixgbe_if_multi_set */
4737
4738 /************************************************************************
4739 * ixgbe_mc_array_itr
4740 *
4741 * An iterator function needed by the multicast shared code.
4742 * It feeds the shared code routine the addresses in the
4743 * array of ixgbe_set_multi() one by one.
4744 ************************************************************************/
4745 static u8 *
ixgbe_mc_array_itr(struct ixgbe_hw * hw,u8 ** update_ptr,u32 * vmdq)4746 ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq)
4747 {
4748 struct ixgbe_mc_addr *mta;
4749
4750 mta = (struct ixgbe_mc_addr *)*update_ptr;
4751 *vmdq = mta->vmdq;
4752
4753 *update_ptr = (u8*)(mta + 1);
4754
4755 return (mta->addr);
4756 } /* ixgbe_mc_array_itr */
4757
4758 /************************************************************************
4759 * ixgbe_local_timer - Timer routine
4760 *
4761 * Checks for link status, updates statistics,
4762 * and runs the watchdog check.
4763 ************************************************************************/
4764 static void
ixgbe_if_timer(if_ctx_t ctx,uint16_t qid)4765 ixgbe_if_timer(if_ctx_t ctx, uint16_t qid)
4766 {
4767 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4768
4769 if (qid != 0)
4770 return;
4771
4772 /* Check for pluggable optics */
4773 if (sc->sfp_probe)
4774 if (!ixgbe_sfp_probe(ctx))
4775 return; /* Nothing to do */
4776
4777 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0);
4778
4779 /* Fire off the adminq task */
4780 iflib_admin_intr_deferred(ctx);
4781
4782 } /* ixgbe_if_timer */
4783
4784 /************************************************************************
4785 * ixgbe_fw_mode_timer - FW mode timer routine
4786 ************************************************************************/
4787 static void
ixgbe_fw_mode_timer(void * arg)4788 ixgbe_fw_mode_timer(void *arg)
4789 {
4790 struct ixgbe_softc *sc = arg;
4791 struct ixgbe_hw *hw = &sc->hw;
4792
4793 if (ixgbe_fw_recovery_mode(hw)) {
4794 if (atomic_cmpset_acq_int(&sc->recovery_mode, 0, 1)) {
4795 /* Firmware error detected, entering recovery mode */
4796 device_printf(sc->dev,
4797 "Firmware recovery mode detected. Limiting"
4798 " functionality. Refer to the Intel(R) Ethernet"
4799 " Adapters and Devices User Guide for details on"
4800 " firmware recovery mode.\n");
4801
4802 /* Stop and publish the failure from the iflib taskqueue. */
4803 iflib_request_reset_if_up(sc->ctx);
4804 iflib_admin_intr_deferred(sc->ctx);
4805 }
4806 } else if (atomic_cmpset_acq_int(&sc->recovery_mode, 1, 0)) {
4807 /* Reinitialize an interface which was up when recovery began. */
4808 iflib_request_reset_if_up(sc->ctx);
4809 iflib_admin_intr_deferred(sc->ctx);
4810 }
4811
4812
4813 callout_reset(&sc->fw_mode_timer, hz,
4814 ixgbe_fw_mode_timer, sc);
4815 } /* ixgbe_fw_mode_timer */
4816
4817 /************************************************************************
4818 * ixgbe_sfp_probe
4819 *
4820 * Determine if a port had optics inserted.
4821 ************************************************************************/
4822 static bool
ixgbe_sfp_probe(if_ctx_t ctx)4823 ixgbe_sfp_probe(if_ctx_t ctx)
4824 {
4825 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4826 struct ixgbe_hw *hw = &sc->hw;
4827 device_t dev = iflib_get_dev(ctx);
4828 bool result = false;
4829
4830 if ((hw->phy.type == ixgbe_phy_nl) &&
4831 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4832 s32 ret = hw->phy.ops.identify_sfp(hw);
4833 if (ret)
4834 goto out;
4835 ret = hw->phy.ops.reset(hw);
4836 sc->sfp_probe = false;
4837 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4838 device_printf(dev,
4839 "Unsupported SFP+ module detected!");
4840 device_printf(dev,
4841 "Reload driver with supported module.\n");
4842 goto out;
4843 } else
4844 device_printf(dev, "SFP+ module detected!\n");
4845 /* We now have supported optics */
4846 result = true;
4847 }
4848 out:
4849
4850 return (result);
4851 } /* ixgbe_sfp_probe */
4852
4853 /************************************************************************
4854 * ixgbe_handle_mod - Tasklet for SFP module interrupts
4855 ************************************************************************/
4856 static bool
ixgbe_handle_mod(void * context)4857 ixgbe_handle_mod(void *context)
4858 {
4859 if_ctx_t ctx = context;
4860 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4861 struct ixgbe_hw *hw = &sc->hw;
4862 device_t dev = iflib_get_dev(ctx);
4863 u32 err, cage_full = 0;
4864
4865 if (sc->hw.need_crosstalk_fix) {
4866 switch (hw->mac.type) {
4867 case ixgbe_mac_82599EB:
4868 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4869 IXGBE_ESDP_SDP2;
4870 break;
4871 case ixgbe_mac_X550EM_x:
4872 case ixgbe_mac_X550EM_a:
4873 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4874 IXGBE_ESDP_SDP0;
4875 break;
4876 default:
4877 break;
4878 }
4879
4880 if (!cage_full)
4881 goto handle_mod_out;
4882 }
4883
4884 err = hw->phy.ops.identify_sfp(hw);
4885 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4886 device_printf(dev,
4887 "Unsupported SFP+ module type was detected.\n");
4888 goto handle_mod_out;
4889 }
4890
4891 if (hw->mac.type == ixgbe_mac_82598EB)
4892 err = hw->phy.ops.reset(hw);
4893 else
4894 err = hw->mac.ops.setup_sfp(hw);
4895
4896 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4897 device_printf(dev,
4898 "Setup failure - unsupported SFP+ module type.\n");
4899 goto handle_mod_out;
4900 }
4901 return (true);
4902
4903 handle_mod_out:
4904 return (false);
4905 } /* ixgbe_handle_mod */
4906
4907
4908 /************************************************************************
4909 * ixgbe_handle_msf - Tasklet for MSF (multispeed fiber) interrupts
4910 ************************************************************************/
4911 static void
ixgbe_handle_msf(void * context)4912 ixgbe_handle_msf(void *context)
4913 {
4914 if_ctx_t ctx = context;
4915 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4916 struct ixgbe_hw *hw = &sc->hw;
4917 u32 autoneg;
4918 bool negotiate;
4919
4920 /* get_supported_phy_layer will call hw->phy.ops.identify_sfp() */
4921 sc->phy_layer = ixgbe_get_supported_physical_layer(hw);
4922
4923 autoneg = hw->phy.autoneg_advertised;
4924 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4925 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate);
4926 if (hw->mac.ops.setup_link)
4927 hw->mac.ops.setup_link(hw, autoneg, true);
4928
4929 /* Adjust media types shown in ifconfig */
4930 ifmedia_removeall(sc->media);
4931 ixgbe_add_media_types(sc->ctx);
4932 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
4933 } /* ixgbe_handle_msf */
4934
4935 /************************************************************************
4936 * ixgbe_handle_phy - Tasklet for external PHY interrupts
4937 ************************************************************************/
4938 static void
ixgbe_handle_phy(void * context)4939 ixgbe_handle_phy(void *context)
4940 {
4941 if_ctx_t ctx = context;
4942 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4943 struct ixgbe_hw *hw = &sc->hw;
4944 int error;
4945
4946 error = hw->phy.ops.handle_lasi(hw);
4947 if (error == IXGBE_ERR_OVERTEMP)
4948 device_printf(sc->dev,
4949 "CRITICAL: EXTERNAL PHY OVER TEMP!!"
4950 " PHY will downshift to lower power state!\n");
4951 else if (error)
4952 device_printf(sc->dev,
4953 "Error handling LASI interrupt: %d\n", error);
4954 } /* ixgbe_handle_phy */
4955
4956 /************************************************************************
4957 * ixgbe_enable_lse - enable link status events
4958 *
4959 * Sets mask and enables link status events
4960 ************************************************************************/
ixgbe_enable_lse(struct ixgbe_softc * sc)4961 s32 ixgbe_enable_lse(struct ixgbe_softc *sc)
4962 {
4963 s32 error;
4964
4965 u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN |
4966 IXGBE_ACI_LINK_EVENT_MEDIA_NA |
4967 IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL |
4968 IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL));
4969
4970 error = ixgbe_configure_lse(&sc->hw, TRUE, mask);
4971 if (error)
4972 return (error);
4973
4974 sc->lse_mask = mask;
4975 return (IXGBE_SUCCESS);
4976 } /* ixgbe_enable_lse */
4977
4978 /************************************************************************
4979 * ixgbe_disable_lse - disable link status events
4980 ************************************************************************/
ixgbe_disable_lse(struct ixgbe_softc * sc)4981 s32 ixgbe_disable_lse(struct ixgbe_softc *sc)
4982 {
4983 s32 error;
4984
4985 error = ixgbe_configure_lse(&sc->hw, false, sc->lse_mask);
4986 if (error)
4987 return (error);
4988
4989 sc->lse_mask = 0;
4990 return (IXGBE_SUCCESS);
4991 } /* ixgbe_disable_lse */
4992
4993 /************************************************************************
4994 * ixgbe_handle_fw_event - Tasklet for MSI-X Link Status Event interrupts
4995 ************************************************************************/
4996 static u32
ixgbe_handle_fw_event(void * context)4997 ixgbe_handle_fw_event(void *context)
4998 {
4999 if_ctx_t ctx = context;
5000 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5001 struct ixgbe_hw *hw = &sc->hw;
5002 struct ixgbe_aci_event event;
5003 bool pending = false;
5004 s32 error;
5005 u32 requests = 0;
5006
5007 event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE;
5008 event.msg_buf = malloc(event.buf_len, M_IXGBE, M_ZERO | M_NOWAIT);
5009 if (!event.msg_buf) {
5010 device_printf(sc->dev, "Can not allocate buffer for "
5011 "event message\n");
5012 return (0);
5013 }
5014
5015 do {
5016 error = ixgbe_aci_get_event(hw, &event, &pending);
5017 if (error) {
5018 device_printf(sc->dev, "Error getting event from "
5019 "FW:%d\n", error);
5020 break;
5021 }
5022
5023 switch (le16toh(event.desc.opcode)) {
5024 case ixgbe_aci_opc_get_link_status:
5025 requests |= IXGBE_REQUEST_TASK_LSC;
5026 break;
5027
5028 case ixgbe_aci_opc_fw_logs_event:
5029 ixgbe_fwlog_event_dump(&sc->hw, &event.desc, event.msg_buf);
5030 break;
5031
5032 case ixgbe_aci_opc_temp_tca_event:
5033 if (!sc->overtemp_shutdown_pending) {
5034 sc->overtemp_shutdown_pending = true;
5035 requests |= IXGBE_REQUEST_TASK_RESET;
5036 device_printf(sc->dev,
5037 "CRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n");
5038 device_printf(sc->dev,
5039 "System shutdown required!\n");
5040 }
5041 break;
5042
5043 default:
5044 device_printf(sc->dev,
5045 "Unknown FW event captured, opcode=0x%04X\n",
5046 le16toh(event.desc.opcode));
5047 break;
5048 }
5049 } while (pending);
5050
5051 free(event.msg_buf, M_IXGBE);
5052 return (requests);
5053 } /* ixgbe_handle_fw_event */
5054
5055 /************************************************************************
5056 * ixgbe_if_stop - Stop the hardware
5057 *
5058 * Disables all traffic on the adapter by issuing a
5059 * global reset on the MAC and deallocates TX/RX buffers.
5060 ************************************************************************/
5061 static void
ixgbe_if_stop(if_ctx_t ctx)5062 ixgbe_if_stop(if_ctx_t ctx)
5063 {
5064 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5065 struct ixgbe_hw *hw = &sc->hw;
5066
5067 INIT_DEBUGOUT("ixgbe_if_stop: begin\n");
5068
5069 ixgbe_led_restore(sc);
5070 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
5071 ixgbe_disable_mdd(hw);
5072 ixgbe_quiesce_vfs(sc);
5073 }
5074 ixgbe_reset_hw(hw);
5075 atomic_store_rel_int(&sc->ecc_reset_pending, 0);
5076 hw->adapter_stopped = false;
5077 ixgbe_stop_adapter(hw);
5078 /* Turn off the laser - noop with no optics */
5079 ixgbe_disable_tx_laser(hw);
5080
5081 /* Update the stack */
5082 sc->link_up = false;
5083 if (sc->link_active) {
5084 if (bootverbose)
5085 device_printf(sc->dev, "Link is Down\n");
5086 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
5087 sc->link_active = false;
5088 }
5089
5090 /* reprogram the RAR[0] in case user changed it. */
5091 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV);
5092
5093 return;
5094 } /* ixgbe_if_stop */
5095
5096 /*
5097 * Identify the physical port while retaining the NVM-selected LED mode.
5098 * E610 exposes identification through firmware rather than LEDCTL.
5099 */
5100 static void
ixgbe_if_led_func(if_ctx_t ctx,int onoff)5101 ixgbe_if_led_func(if_ctx_t ctx, int onoff)
5102 {
5103 struct ixgbe_softc *sc;
5104 struct ixgbe_hw *hw;
5105
5106 sc = iflib_get_softc(ctx);
5107 hw = &sc->hw;
5108 if (!onoff) {
5109 ixgbe_led_restore(sc);
5110 return;
5111 }
5112 if (sc->led_active)
5113 return;
5114
5115 if (hw->mac.type == ixgbe_mac_E610) {
5116 if (ixgbe_aci_set_port_id_led(hw, false) == IXGBE_SUCCESS)
5117 sc->led_active = true;
5118 return;
5119 }
5120
5121 sc->ledctl_default = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
5122 if (ixgbe_led_on(hw, hw->mac.led_link_act) == IXGBE_SUCCESS)
5123 sc->led_active = true;
5124 }
5125
5126 static void
ixgbe_led_restore(struct ixgbe_softc * sc)5127 ixgbe_led_restore(struct ixgbe_softc *sc)
5128 {
5129 struct ixgbe_hw *hw;
5130
5131 if (!sc->led_active)
5132 return;
5133
5134 hw = &sc->hw;
5135 if (hw->mac.type == ixgbe_mac_E610) {
5136 (void)ixgbe_aci_set_port_id_led(hw, true);
5137 } else {
5138 /* Clear any PHY manual override before restoring LEDCTL. */
5139 (void)ixgbe_led_off(hw, hw->mac.led_link_act);
5140 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, sc->ledctl_default);
5141 IXGBE_WRITE_FLUSH(hw);
5142 }
5143 sc->led_active = false;
5144 }
5145
5146 /************************************************************************
5147 * ixgbe_link_speed_to_str - Convert link speed to string
5148 *
5149 * Helper function to convert link speed constants to human-readable
5150 * string representations in conventional Gbps or Mbps.
5151 ************************************************************************/
5152 static const char *
ixgbe_link_speed_to_str(u32 link_speed)5153 ixgbe_link_speed_to_str(u32 link_speed)
5154 {
5155 switch (link_speed) {
5156 case IXGBE_LINK_SPEED_10GB_FULL:
5157 return "10 Gbps";
5158 case IXGBE_LINK_SPEED_5GB_FULL:
5159 return "5 Gbps";
5160 case IXGBE_LINK_SPEED_2_5GB_FULL:
5161 return "2.5 Gbps";
5162 case IXGBE_LINK_SPEED_1GB_FULL:
5163 return "1 Gbps";
5164 case IXGBE_LINK_SPEED_100_FULL:
5165 return "100 Mbps";
5166 case IXGBE_LINK_SPEED_10_FULL:
5167 return "10 Mbps";
5168 default:
5169 return "Unknown";
5170 }
5171 } /* ixgbe_link_speed_to_str */
5172
5173 /************************************************************************
5174 * ixgbe_update_link_status - Update OS on link state
5175 *
5176 * Process deferred administrative requests and update the OS link state.
5177 ************************************************************************/
5178 static void
ixgbe_if_update_admin_status(if_ctx_t ctx)5179 ixgbe_if_update_admin_status(if_ctx_t ctx)
5180 {
5181 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5182 device_t dev = iflib_get_dev(ctx);
5183 u32 requests;
5184 u_int pass;
5185 bool check_link = false;
5186
5187 /*
5188 * The interrupt filter and other producers can run concurrently with
5189 * this task. Claim each batch atomically so a request posted while the
5190 * task is running remains pending for this or the next invocation.
5191 *
5192 * MOD and firmware events can produce dependent requests. Fold those
5193 * into the claimed batch so link state is sampled after any link setup.
5194 */
5195 if ((if_getdrvflags(iflib_get_ifp(ctx)) & IFF_DRV_RUNNING) != 0 &&
5196 (sc->iov_mbx_cleanup_pending || ixgbe_mbx_pending(sc)))
5197 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MBX);
5198 for (pass = 0; pass < IXGBE_ADMIN_TASK_BUDGET; pass++) {
5199 requests = atomic_readandclear_32(&sc->task_requests);
5200 if (requests == 0)
5201 break;
5202 if (requests & IXGBE_REQUEST_TASK_FWEVENT)
5203 requests |= ixgbe_handle_fw_event(ctx);
5204 if (requests & IXGBE_REQUEST_TASK_MOD) {
5205 if (ixgbe_handle_mod(ctx))
5206 requests |= IXGBE_REQUEST_TASK_MSF;
5207 else
5208 requests &= ~IXGBE_REQUEST_TASK_MSF;
5209 }
5210 if (requests & IXGBE_REQUEST_TASK_MSF)
5211 ixgbe_handle_msf(ctx);
5212 /* A reset request can re-enable VF traffic; skip it while stopped. */
5213 if ((requests & IXGBE_REQUEST_TASK_MBX) != 0 &&
5214 (if_getdrvflags(iflib_get_ifp(ctx)) & IFF_DRV_RUNNING) != 0)
5215 ixgbe_handle_mbx(ctx);
5216 if (requests & IXGBE_REQUEST_TASK_FDIR)
5217 ixgbe_reinit_fdir(ctx);
5218 if (requests & IXGBE_REQUEST_TASK_PHY)
5219 ixgbe_handle_phy(ctx);
5220 if (requests & IXGBE_REQUEST_TASK_LSC)
5221 check_link = true;
5222 if (requests & IXGBE_REQUEST_TASK_RESET) {
5223 /* Re-enter the admin task so it observes IFC_DO_RESET. */
5224 iflib_request_reset(ctx);
5225 iflib_admin_intr_deferred(ctx);
5226 }
5227 }
5228
5229 /* Do not let a continuous producer monopolize the admin taskqueue. */
5230 if (atomic_load_acq_32(&sc->task_requests) != 0)
5231 iflib_admin_intr_deferred(ctx);
5232
5233 if (check_link)
5234 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up,
5235 false);
5236
5237 if (sc->link_up) {
5238 if (sc->link_active == false) {
5239 if (bootverbose)
5240 device_printf(dev,
5241 "Link is up %s Full Duplex\n",
5242 ixgbe_link_speed_to_str(sc->link_speed));
5243 sc->link_active = true;
5244
5245 /* If link speed is <= 1Gbps and EEE is enabled,
5246 * log info.
5247 */
5248 if (sc->hw.mac.type == ixgbe_mac_E610 &&
5249 (sc->feat_en & IXGBE_FEATURE_EEE) &&
5250 sc->link_speed <= IXGBE_LINK_SPEED_1GB_FULL) {
5251 device_printf(sc->dev,
5252 "Energy Efficient Ethernet (EEE) feature "
5253 "is not supported on link speeds equal to "
5254 "or below 1Gbps. EEE is supported on "
5255 "speeds above 1Gbps.\n");
5256 }
5257
5258 /* Update any Flow Control changes */
5259 ixgbe_fc_enable(&sc->hw);
5260 /* Update DMA coalescing config */
5261 ixgbe_config_dmac(sc);
5262 iflib_link_state_change(ctx, LINK_STATE_UP,
5263 ixgbe_link_speed_to_baudrate(sc->link_speed));
5264
5265 if (sc->feat_en & IXGBE_FEATURE_SRIOV)
5266 ixgbe_ping_all_vfs(sc);
5267 }
5268 } else { /* Link down */
5269 if (sc->link_active == true) {
5270 if (bootverbose)
5271 device_printf(dev, "Link is Down\n");
5272 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
5273 sc->link_active = false;
5274 if (sc->feat_en & IXGBE_FEATURE_SRIOV)
5275 ixgbe_ping_all_vfs(sc);
5276 }
5277 }
5278
5279 ixgbe_schedule_iov_recovery(sc);
5280
5281 ixgbe_update_stats_counters(sc);
5282 } /* ixgbe_if_update_admin_status */
5283
5284 /************************************************************************
5285 * ixgbe_config_dmac - Configure DMA Coalescing
5286 ************************************************************************/
5287 static void
ixgbe_config_dmac(struct ixgbe_softc * sc)5288 ixgbe_config_dmac(struct ixgbe_softc *sc)
5289 {
5290 struct ixgbe_hw *hw = &sc->hw;
5291 struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config;
5292
5293 if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config)
5294 return;
5295
5296 if (dcfg->watchdog_timer ^ sc->dmac ||
5297 dcfg->link_speed ^ sc->link_speed) {
5298 dcfg->watchdog_timer = sc->dmac;
5299 dcfg->fcoe_en = false;
5300 dcfg->link_speed = sc->link_speed;
5301 dcfg->num_tcs = 1;
5302
5303 INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n",
5304 dcfg->watchdog_timer, dcfg->link_speed);
5305
5306 hw->mac.ops.dmac_config(hw);
5307 }
5308 } /* ixgbe_config_dmac */
5309
5310 /************************************************************************
5311 * ixgbe_if_enable_intr
5312 ************************************************************************/
5313 void
ixgbe_if_enable_intr(if_ctx_t ctx)5314 ixgbe_if_enable_intr(if_ctx_t ctx)
5315 {
5316 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5317 struct ixgbe_hw *hw = &sc->hw;
5318 struct ix_rx_queue *que = sc->rx_queues;
5319 u32 mask, fwsm;
5320
5321 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
5322
5323 switch (sc->hw.mac.type) {
5324 case ixgbe_mac_82599EB:
5325 mask |= IXGBE_EIMS_ECC;
5326 /* Temperature sensor on some scs */
5327 mask |= IXGBE_EIMS_GPI_SDP0;
5328 /* SFP+ (RX_LOS_N & MOD_ABS_N) */
5329 mask |= IXGBE_EIMS_GPI_SDP1;
5330 mask |= IXGBE_EIMS_GPI_SDP2;
5331 break;
5332 case ixgbe_mac_X540:
5333 /* Detect if Thermal Sensor is enabled */
5334 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5335 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5336 mask |= IXGBE_EIMS_TS;
5337 mask |= IXGBE_EIMS_ECC;
5338 break;
5339 case ixgbe_mac_X550:
5340 /* MAC thermal sensor is automatically enabled */
5341 mask |= IXGBE_EIMS_TS;
5342 mask |= IXGBE_EIMS_ECC;
5343 break;
5344 case ixgbe_mac_X550EM_x:
5345 case ixgbe_mac_X550EM_a:
5346 /* Some devices use SDP0 for important information */
5347 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
5348 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
5349 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N ||
5350 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T)
5351 mask |= IXGBE_EIMS_GPI_SDP0_BY_MAC(hw);
5352 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
5353 mask |= IXGBE_EICR_GPI_SDP0_X540;
5354 mask |= IXGBE_EIMS_ECC;
5355 break;
5356 case ixgbe_mac_E610:
5357 mask |= IXGBE_EIMS_FW_EVENT;
5358 break;
5359 default:
5360 break;
5361 }
5362
5363 /* Enable Fan Failure detection */
5364 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL)
5365 mask |= IXGBE_EIMS_GPI_SDP1;
5366 /* Enable SR-IOV */
5367 if (sc->feat_en & IXGBE_FEATURE_SRIOV)
5368 mask |= IXGBE_EIMS_MAILBOX;
5369 /* Enable Flow Director */
5370 if (sc->feat_en & IXGBE_FEATURE_FDIR)
5371 mask |= IXGBE_EIMS_FLOW_DIR;
5372 if (atomic_load_acq_int(&sc->ecc_reset_pending))
5373 mask &= ~IXGBE_EIMS_ECC;
5374
5375 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
5376
5377 /* With MSI-X we use auto clear */
5378 if (sc->intr_type == IFLIB_INTR_MSIX) {
5379 mask = IXGBE_EIMS_ENABLE_MASK;
5380 /* Don't autoclear Link */
5381 mask &= ~IXGBE_EIMS_OTHER;
5382 mask &= ~IXGBE_EIMS_LSC;
5383 mask &= ~IXGBE_EIMS_FW_EVENT;
5384 if (sc->feat_cap & IXGBE_FEATURE_SRIOV)
5385 mask &= ~IXGBE_EIMS_MAILBOX;
5386 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5387 }
5388
5389 /*
5390 * Now enable all queues, this is done separately to
5391 * allow for handling the extended (beyond 32) MSI-X
5392 * vectors that can be used by 82599
5393 */
5394 for (int i = 0; i < sc->num_rx_queues; i++, que++)
5395 ixgbe_enable_queue(sc, que->msix);
5396
5397 IXGBE_WRITE_FLUSH(hw);
5398
5399 } /* ixgbe_if_enable_intr */
5400
5401 /************************************************************************
5402 * ixgbe_if_disable_intr
5403 ************************************************************************/
5404 static void
ixgbe_if_disable_intr(if_ctx_t ctx)5405 ixgbe_if_disable_intr(if_ctx_t ctx)
5406 {
5407 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5408
5409 if (sc->intr_type == IFLIB_INTR_MSIX)
5410 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0);
5411 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
5412 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0);
5413 } else {
5414 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000);
5415 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0);
5416 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0);
5417 }
5418 IXGBE_WRITE_FLUSH(&sc->hw);
5419
5420 } /* ixgbe_if_disable_intr */
5421
5422 /************************************************************************
5423 * ixgbe_link_intr_enable
5424 ************************************************************************/
5425 static void
ixgbe_link_intr_enable(if_ctx_t ctx)5426 ixgbe_link_intr_enable(if_ctx_t ctx)
5427 {
5428 struct ixgbe_hw *hw =
5429 &((struct ixgbe_softc *)iflib_get_softc(ctx))->hw;
5430
5431 /* Re-enable other interrupts */
5432 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
5433 } /* ixgbe_link_intr_enable */
5434
5435 /************************************************************************
5436 * ixgbe_if_rx_queue_intr_enable
5437 ************************************************************************/
5438 static int
ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t rxqid)5439 ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
5440 {
5441 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5442 struct ix_rx_queue *que = &sc->rx_queues[rxqid];
5443
5444 ixgbe_enable_queue(sc, que->msix);
5445
5446 return (0);
5447 } /* ixgbe_if_rx_queue_intr_enable */
5448
5449 /************************************************************************
5450 * ixgbe_enable_queue
5451 ************************************************************************/
5452 static void
ixgbe_enable_queue(struct ixgbe_softc * sc,u32 vector)5453 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector)
5454 {
5455 struct ixgbe_hw *hw = &sc->hw;
5456 u64 queue = 1ULL << vector;
5457 u32 mask;
5458
5459 if (hw->mac.type == ixgbe_mac_82598EB) {
5460 mask = (IXGBE_EIMS_RTX_QUEUE & queue);
5461 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
5462 } else {
5463 mask = (queue & 0xFFFFFFFF);
5464 if (mask)
5465 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5466 mask = (queue >> 32);
5467 if (mask)
5468 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5469 }
5470 } /* ixgbe_enable_queue */
5471
5472 /************************************************************************
5473 * ixgbe_disable_queue
5474 ************************************************************************/
5475 static void
ixgbe_disable_queue(struct ixgbe_softc * sc,u32 vector)5476 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector)
5477 {
5478 struct ixgbe_hw *hw = &sc->hw;
5479 u64 queue = 1ULL << vector;
5480 u32 mask;
5481
5482 if (hw->mac.type == ixgbe_mac_82598EB) {
5483 mask = (IXGBE_EIMS_RTX_QUEUE & queue);
5484 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
5485 } else {
5486 mask = (queue & 0xFFFFFFFF);
5487 if (mask)
5488 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
5489 mask = (queue >> 32);
5490 if (mask)
5491 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
5492 }
5493 } /* ixgbe_disable_queue */
5494
5495 /************************************************************************
5496 * ixgbe_intr - Legacy Interrupt Service Routine
5497 ************************************************************************/
5498 int
ixgbe_intr(void * arg)5499 ixgbe_intr(void *arg)
5500 {
5501 struct ixgbe_softc *sc = arg;
5502 struct ix_rx_queue *que = sc->rx_queues;
5503 struct ixgbe_hw *hw = &sc->hw;
5504 if_ctx_t ctx = sc->ctx;
5505 u32 eicr, eicr_mask, requests;
5506
5507 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
5508 requests = 0;
5509
5510 ++que->irqs;
5511 if (eicr == 0) {
5512 ixgbe_if_enable_intr(ctx);
5513 return (FILTER_HANDLED);
5514 }
5515
5516 /* Check for fan failure */
5517 if ((sc->feat_en & IXGBE_FEATURE_FAN_FAIL) &&
5518 (eicr & IXGBE_EICR_GPI_SDP1)) {
5519 device_printf(sc->dev,
5520 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n");
5521 IXGBE_WRITE_REG(hw, IXGBE_EIMS,
5522 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
5523 }
5524
5525 /* Link status change */
5526 if (eicr & IXGBE_EICR_LSC) {
5527 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
5528 requests |= IXGBE_REQUEST_TASK_LSC;
5529 }
5530
5531 if (ixgbe_is_sfp(hw)) {
5532 /* Pluggable optics-related interrupt */
5533 if (hw->mac.type >= ixgbe_mac_X540)
5534 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
5535 else
5536 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw);
5537
5538 if (eicr & eicr_mask) {
5539 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
5540 requests |= IXGBE_REQUEST_TASK_MOD;
5541 }
5542
5543 if ((hw->mac.type == ixgbe_mac_82599EB) &&
5544 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) {
5545 IXGBE_WRITE_REG(hw, IXGBE_EICR,
5546 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
5547 requests |= IXGBE_REQUEST_TASK_MSF;
5548 }
5549 }
5550
5551 /* External PHY interrupt */
5552 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&
5553 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
5554 requests |= IXGBE_REQUEST_TASK_PHY;
5555 }
5556 if (hw->mac.type != ixgbe_mac_82598EB &&
5557 ixgbe_handle_ecc(sc, eicr))
5558 requests |= IXGBE_REQUEST_TASK_RESET;
5559 if (requests != 0) {
5560 atomic_set_32(&sc->task_requests, requests);
5561 iflib_admin_intr_deferred(ctx);
5562 }
5563
5564 return (FILTER_SCHEDULE_THREAD);
5565 } /* ixgbe_intr */
5566
5567 /************************************************************************
5568 * ixgbe_free_pci_resources
5569 ************************************************************************/
5570 static void
ixgbe_free_pci_resources(if_ctx_t ctx)5571 ixgbe_free_pci_resources(if_ctx_t ctx)
5572 {
5573 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5574 struct ix_rx_queue *que = sc->rx_queues;
5575 device_t dev = iflib_get_dev(ctx);
5576
5577 /* Release all MSI-X queue resources */
5578 if (sc->intr_type == IFLIB_INTR_MSIX)
5579 iflib_irq_free(ctx, &sc->irq);
5580
5581 if (que != NULL) {
5582 for (int i = 0; i < sc->num_rx_queues; i++, que++) {
5583 iflib_irq_free(ctx, &que->que_irq);
5584 }
5585 }
5586
5587 if (sc->pci_mem != NULL)
5588 bus_release_resource(dev, SYS_RES_MEMORY,
5589 rman_get_rid(sc->pci_mem), sc->pci_mem);
5590 } /* ixgbe_free_pci_resources */
5591
5592 /************************************************************************
5593 * ixgbe_sysctl_flowcntl
5594 *
5595 * SYSCTL wrapper around setting Flow Control
5596 ************************************************************************/
5597 static int
ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS)5598 ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS)
5599 {
5600 struct ixgbe_softc *sc;
5601 struct sx *ctx_lock;
5602 int error, fc;
5603
5604 sc = (struct ixgbe_softc *)arg1;
5605 fc = sc->hw.fc.requested_mode;
5606
5607 error = sysctl_handle_int(oidp, &fc, 0, req);
5608 if ((error) || (req->newptr == NULL))
5609 return (error);
5610
5611 /* Serialize the live register update with the administrative task. */
5612 ctx_lock = iflib_ctx_lock_get(sc->ctx);
5613 sx_xlock(ctx_lock);
5614 if (fc == sc->hw.fc.requested_mode)
5615 error = 0;
5616 else
5617 error = ixgbe_set_flowcntl(sc, fc);
5618 sx_xunlock(ctx_lock);
5619 return (error);
5620 } /* ixgbe_sysctl_flowcntl */
5621
5622 /************************************************************************
5623 * ixgbe_set_flowcntl - Set flow control
5624 *
5625 * Flow control values:
5626 * 0 - off
5627 * 1 - rx pause
5628 * 2 - tx pause
5629 * 3 - full
5630 ************************************************************************/
5631 static int
ixgbe_set_flowcntl(struct ixgbe_softc * sc,int fc)5632 ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc)
5633 {
5634 bool enable_drop, mdd_active;
5635
5636 switch (fc) {
5637 case ixgbe_fc_rx_pause:
5638 case ixgbe_fc_tx_pause:
5639 case ixgbe_fc_full:
5640 enable_drop = false;
5641 break;
5642 case ixgbe_fc_none:
5643 enable_drop = true;
5644 break;
5645 default:
5646 return (EINVAL);
5647 }
5648
5649 /* Updating SRRCTL on a live queue is itself an MDD violation. */
5650 mdd_active = sc->num_rx_queues > 1 &&
5651 (sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 &&
5652 (if_getdrvflags(iflib_get_ifp(sc->ctx)) & IFF_DRV_RUNNING) != 0;
5653 if (mdd_active)
5654 ixgbe_disable_mdd(&sc->hw);
5655 if (sc->num_rx_queues > 1) {
5656 if (enable_drop)
5657 ixgbe_enable_rx_drop(sc);
5658 else
5659 ixgbe_disable_rx_drop(sc);
5660 }
5661 if (mdd_active) {
5662 ixgbe_enable_mdd(&sc->hw);
5663 /* Service an event whose interrupt edge was lost while masked. */
5664 if (ixgbe_mbx_pending(sc)) {
5665 atomic_set_32(&sc->task_requests,
5666 IXGBE_REQUEST_TASK_MBX);
5667 iflib_admin_intr_deferred(sc->ctx);
5668 }
5669 }
5670
5671 sc->hw.fc.requested_mode = fc;
5672
5673 /* Don't autoneg if forcing a value */
5674 sc->hw.fc.disable_fc_autoneg = true;
5675 ixgbe_fc_enable(&sc->hw);
5676
5677 return (0);
5678 } /* ixgbe_set_flowcntl */
5679
5680 /************************************************************************
5681 * ixgbe_enable_rx_drop
5682 *
5683 * Enable the hardware to drop packets when the buffer is
5684 * full. This is useful with multiqueue, so that no single
5685 * queue being full stalls the entire RX engine. We only
5686 * enable this when Multiqueue is enabled AND Flow Control
5687 * is disabled.
5688 ************************************************************************/
5689 static void
ixgbe_enable_rx_drop(struct ixgbe_softc * sc)5690 ixgbe_enable_rx_drop(struct ixgbe_softc *sc)
5691 {
5692 struct ixgbe_hw *hw = &sc->hw;
5693 struct rx_ring *rxr;
5694 u32 srrctl;
5695
5696 for (int i = 0; i < sc->num_rx_queues; i++) {
5697 rxr = &sc->rx_queues[i].rxr;
5698 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me));
5699 srrctl |= IXGBE_SRRCTL_DROP_EN;
5700 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl);
5701 }
5702
5703 } /* ixgbe_enable_rx_drop */
5704
5705 /************************************************************************
5706 * ixgbe_disable_rx_drop
5707 ************************************************************************/
5708 static void
ixgbe_disable_rx_drop(struct ixgbe_softc * sc)5709 ixgbe_disable_rx_drop(struct ixgbe_softc *sc)
5710 {
5711 struct ixgbe_hw *hw = &sc->hw;
5712 struct rx_ring *rxr;
5713 u32 srrctl;
5714
5715 for (int i = 0; i < sc->num_rx_queues; i++) {
5716 rxr = &sc->rx_queues[i].rxr;
5717 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me));
5718 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
5719 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl);
5720 }
5721
5722 } /* ixgbe_disable_rx_drop */
5723
5724 /************************************************************************
5725 * ixgbe_sysctl_advertise
5726 *
5727 * SYSCTL wrapper around setting advertised speed
5728 ************************************************************************/
5729 static int
ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS)5730 ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS)
5731 {
5732 struct ixgbe_softc *sc;
5733 int error, advertise;
5734
5735 sc = (struct ixgbe_softc *)arg1;
5736 if (atomic_load_acq_int(&sc->recovery_mode))
5737 return (EPERM);
5738
5739 advertise = sc->advertise;
5740
5741 error = sysctl_handle_int(oidp, &advertise, 0, req);
5742 if ((error) || (req->newptr == NULL))
5743 return (error);
5744
5745 return ixgbe_set_advertise(sc, advertise);
5746 } /* ixgbe_sysctl_advertise */
5747
5748 /************************************************************************
5749 * ixgbe_set_advertise - Control advertised link speed
5750 *
5751 * Flags:
5752 * 0x1 - advertise 100 Mb
5753 * 0x2 - advertise 1G
5754 * 0x4 - advertise 10G
5755 * 0x8 - advertise 10 Mb (yes, Mb)
5756 * 0x10 - advertise 2.5G (disabled by default)
5757 * 0x20 - advertise 5G (disabled by default)
5758 *
5759 ************************************************************************/
5760 static int
ixgbe_set_advertise(struct ixgbe_softc * sc,int advertise)5761 ixgbe_set_advertise(struct ixgbe_softc *sc, int advertise)
5762 {
5763 device_t dev = iflib_get_dev(sc->ctx);
5764 struct ixgbe_hw *hw;
5765 ixgbe_link_speed speed = 0;
5766 ixgbe_link_speed link_caps = 0;
5767 s32 err = IXGBE_NOT_IMPLEMENTED;
5768 bool negotiate = false;
5769
5770 /* Checks to validate new value */
5771 if (sc->advertise == advertise) /* no change */
5772 return (0);
5773
5774 hw = &sc->hw;
5775
5776 /* No speed changes for backplane media */
5777 if (hw->phy.media_type == ixgbe_media_type_backplane)
5778 return (ENODEV);
5779
5780 if (!((hw->phy.media_type == ixgbe_media_type_copper) ||
5781 (hw->phy.multispeed_fiber))) {
5782 device_printf(dev,
5783 "Advertised speed can only be set on copper or multispeed"
5784 " fiber media types.\n");
5785 return (EINVAL);
5786 }
5787
5788 if (advertise < 0x1 || advertise > 0x3F) {
5789 device_printf(dev,
5790 "Invalid advertised speed; valid modes are 0x1 through"
5791 " 0x3F\n");
5792 return (EINVAL);
5793 }
5794
5795 if (hw->mac.ops.get_link_capabilities) {
5796 err = hw->mac.ops.get_link_capabilities(hw, &link_caps,
5797 &negotiate);
5798 if (err != IXGBE_SUCCESS) {
5799 device_printf(dev,
5800 "Unable to determine supported advertise speeds"
5801 "\n");
5802 return (ENODEV);
5803 }
5804 }
5805
5806 /* Set new value and report new advertised mode */
5807 if (advertise & 0x1) {
5808 if (!(link_caps & IXGBE_LINK_SPEED_100_FULL)) {
5809 device_printf(dev,
5810 "Interface does not support 100Mb advertised"
5811 " speed\n");
5812 return (EINVAL);
5813 }
5814 speed |= IXGBE_LINK_SPEED_100_FULL;
5815 }
5816 if (advertise & 0x2) {
5817 if (!(link_caps & IXGBE_LINK_SPEED_1GB_FULL)) {
5818 device_printf(dev,
5819 "Interface does not support 1Gb advertised speed"
5820 "\n");
5821 return (EINVAL);
5822 }
5823 speed |= IXGBE_LINK_SPEED_1GB_FULL;
5824 }
5825 if (advertise & 0x4) {
5826 if (!(link_caps & IXGBE_LINK_SPEED_10GB_FULL)) {
5827 device_printf(dev,
5828 "Interface does not support 10Gb advertised speed"
5829 "\n");
5830 return (EINVAL);
5831 }
5832 speed |= IXGBE_LINK_SPEED_10GB_FULL;
5833 }
5834 if (advertise & 0x8) {
5835 if (!(link_caps & IXGBE_LINK_SPEED_10_FULL)) {
5836 device_printf(dev,
5837 "Interface does not support 10Mb advertised speed"
5838 "\n");
5839 return (EINVAL);
5840 }
5841 speed |= IXGBE_LINK_SPEED_10_FULL;
5842 }
5843 if (advertise & 0x10) {
5844 if (!(link_caps & IXGBE_LINK_SPEED_2_5GB_FULL)) {
5845 device_printf(dev,
5846 "Interface does not support 2.5G advertised speed"
5847 "\n");
5848 return (EINVAL);
5849 }
5850 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
5851 }
5852 if (advertise & 0x20) {
5853 if (!(link_caps & IXGBE_LINK_SPEED_5GB_FULL)) {
5854 device_printf(dev,
5855 "Interface does not support 5G advertised speed"
5856 "\n");
5857 return (EINVAL);
5858 }
5859 speed |= IXGBE_LINK_SPEED_5GB_FULL;
5860 }
5861
5862 hw->mac.autotry_restart = true;
5863 hw->mac.ops.setup_link(hw, speed, true);
5864 sc->advertise = advertise;
5865
5866 return (0);
5867 } /* ixgbe_set_advertise */
5868
5869 /************************************************************************
5870 * ixgbe_get_default_advertise - Get default advertised speed settings
5871 *
5872 * Formatted for sysctl usage.
5873 * Flags:
5874 * 0x1 - advertise 100 Mb
5875 * 0x2 - advertise 1G
5876 * 0x4 - advertise 10G
5877 * 0x8 - advertise 10 Mb (yes, Mb)
5878 * 0x10 - advertise 2.5G (disabled by default)
5879 * 0x20 - advertise 5G (disabled by default)
5880 ************************************************************************/
5881 static int
ixgbe_get_default_advertise(struct ixgbe_softc * sc)5882 ixgbe_get_default_advertise(struct ixgbe_softc *sc)
5883 {
5884 struct ixgbe_hw *hw = &sc->hw;
5885 int speed;
5886 ixgbe_link_speed link_caps = 0;
5887 s32 err;
5888 bool negotiate = false;
5889
5890 /*
5891 * Advertised speed means nothing unless it's copper or
5892 * multi-speed fiber
5893 */
5894 if (!(hw->phy.media_type == ixgbe_media_type_copper) &&
5895 !(hw->phy.multispeed_fiber))
5896 return (0);
5897
5898 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, &negotiate);
5899 if (err != IXGBE_SUCCESS)
5900 return (0);
5901
5902 if (hw->mac.type == ixgbe_mac_X550) {
5903 /*
5904 * 2.5G and 5G autonegotiation speeds on X550
5905 * are disabled by default due to reported
5906 * interoperability issues with some switches.
5907 */
5908 link_caps &= ~(IXGBE_LINK_SPEED_2_5GB_FULL |
5909 IXGBE_LINK_SPEED_5GB_FULL);
5910 }
5911
5912 speed =
5913 ((link_caps & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) |
5914 ((link_caps & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) |
5915 ((link_caps & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) |
5916 ((link_caps & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) |
5917 ((link_caps & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) |
5918 ((link_caps & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0);
5919
5920 return speed;
5921 } /* ixgbe_get_default_advertise */
5922
5923 /************************************************************************
5924 * ixgbe_sysctl_dmac - Manage DMA Coalescing
5925 *
5926 * Control values:
5927 * 0/1 - off / on (use default value of 1000)
5928 *
5929 * Legal timer values are:
5930 * 50,100,250,500,1000,2000,5000,10000
5931 *
5932 * Turning off interrupt moderation will also turn this off.
5933 ************************************************************************/
5934 static int
ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS)5935 ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS)
5936 {
5937 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
5938 if_t ifp = iflib_get_ifp(sc->ctx);
5939 int error;
5940 u16 newval;
5941
5942 newval = sc->dmac;
5943 error = sysctl_handle_16(oidp, &newval, 0, req);
5944 if ((error) || (req->newptr == NULL))
5945 return (error);
5946
5947 switch (newval) {
5948 case 0:
5949 /* Disabled */
5950 sc->dmac = 0;
5951 break;
5952 case 1:
5953 /* Enable and use default */
5954 sc->dmac = 1000;
5955 break;
5956 case 50:
5957 case 100:
5958 case 250:
5959 case 500:
5960 case 1000:
5961 case 2000:
5962 case 5000:
5963 case 10000:
5964 /* Legal values - allow */
5965 sc->dmac = newval;
5966 break;
5967 default:
5968 /* Do nothing, illegal value */
5969 return (EINVAL);
5970 }
5971
5972 /* Re-initialize hardware if it's already running */
5973 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5974 if_init(ifp, ifp);
5975
5976 return (0);
5977 } /* ixgbe_sysctl_dmac */
5978
5979 #ifdef IXGBE_DEBUG
5980 /************************************************************************
5981 * ixgbe_sysctl_power_state
5982 *
5983 * Sysctl to test power states
5984 * Values:
5985 * 0 - set device to D0
5986 * 3 - set device to D3
5987 * (none) - get current device power state
5988 ************************************************************************/
5989 static int
ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS)5990 ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS)
5991 {
5992 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
5993 device_t dev = sc->dev;
5994 int curr_ps, new_ps, error = 0;
5995
5996 curr_ps = new_ps = pci_get_powerstate(dev);
5997
5998 error = sysctl_handle_int(oidp, &new_ps, 0, req);
5999 if ((error) || (req->newptr == NULL))
6000 return (error);
6001
6002 if (new_ps == curr_ps)
6003 return (0);
6004
6005 if (new_ps == 3 && curr_ps == 0)
6006 error = DEVICE_SUSPEND(dev);
6007 else if (new_ps == 0 && curr_ps == 3)
6008 error = DEVICE_RESUME(dev);
6009 else
6010 return (EINVAL);
6011
6012 device_printf(dev, "New state: %d\n", pci_get_powerstate(dev));
6013
6014 return (error);
6015 } /* ixgbe_sysctl_power_state */
6016 #endif
6017
6018 #ifdef IXGBE_DEBUG
6019 /************************************************************************
6020 * ixgbe_sysctl_print_rss_config
6021 ************************************************************************/
6022 static int
ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS)6023 ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS)
6024 {
6025 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6026 struct ixgbe_hw *hw = &sc->hw;
6027 device_t dev = sc->dev;
6028 struct sbuf *buf;
6029 int error = 0, reta_size;
6030 u32 reg;
6031
6032 if (atomic_load_acq_int(&sc->recovery_mode))
6033 return (EPERM);
6034
6035 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6036 if (!buf) {
6037 device_printf(dev, "Could not allocate sbuf for output.\n");
6038 return (ENOMEM);
6039 }
6040
6041 // TODO: use sbufs to make a string to print out
6042 /* Set multiplier for RETA setup and table size based on MAC */
6043 switch (sc->hw.mac.type) {
6044 case ixgbe_mac_X550:
6045 case ixgbe_mac_X550EM_x:
6046 case ixgbe_mac_X550EM_a:
6047 reta_size = 128;
6048 break;
6049 default:
6050 reta_size = 32;
6051 break;
6052 }
6053
6054 /* Print out the redirection table */
6055 sbuf_cat(buf, "\n");
6056 for (int i = 0; i < reta_size; i++) {
6057 if (i < 32) {
6058 reg = IXGBE_READ_REG(hw, IXGBE_RETA(i));
6059 sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg);
6060 } else {
6061 reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32));
6062 sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg);
6063 }
6064 }
6065
6066 // TODO: print more config
6067
6068 error = sbuf_finish(buf);
6069 if (error)
6070 device_printf(dev, "Error finishing sbuf: %d\n", error);
6071
6072 sbuf_delete(buf);
6073
6074 return (0);
6075 } /* ixgbe_sysctl_print_rss_config */
6076 #endif /* IXGBE_DEBUG */
6077
6078 /************************************************************************
6079 * ixgbe_sysctl_phy_temp - Retrieve temperature of PHY
6080 *
6081 * For X552/X557-AT devices using an external PHY
6082 ************************************************************************/
6083 static int
ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS)6084 ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS)
6085 {
6086 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6087 struct ixgbe_hw *hw = &sc->hw;
6088 u16 reg;
6089
6090 if (atomic_load_acq_int(&sc->recovery_mode))
6091 return (EPERM);
6092
6093 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) {
6094 device_printf(iflib_get_dev(sc->ctx),
6095 "Device has no supported external thermal sensor.\n");
6096 return (ENODEV);
6097 }
6098
6099 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP,
6100 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) {
6101 device_printf(iflib_get_dev(sc->ctx),
6102 "Error reading from PHY's current temperature register"
6103 "\n");
6104 return (EAGAIN);
6105 }
6106
6107 /* Shift temp for output */
6108 reg = reg >> 8;
6109
6110 return (sysctl_handle_16(oidp, NULL, reg, req));
6111 } /* ixgbe_sysctl_phy_temp */
6112
6113 /************************************************************************
6114 * ixgbe_sysctl_phy_overtemp_occurred
6115 *
6116 * Reports (directly from the PHY) whether the current PHY
6117 * temperature is over the overtemp threshold.
6118 ************************************************************************/
6119 static int
ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS)6120 ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS)
6121 {
6122 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6123 struct ixgbe_hw *hw = &sc->hw;
6124 u16 reg;
6125
6126 if (atomic_load_acq_int(&sc->recovery_mode))
6127 return (EPERM);
6128
6129 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) {
6130 device_printf(iflib_get_dev(sc->ctx),
6131 "Device has no supported external thermal sensor.\n");
6132 return (ENODEV);
6133 }
6134
6135 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS,
6136 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) {
6137 device_printf(iflib_get_dev(sc->ctx),
6138 "Error reading from PHY's temperature status register\n");
6139 return (EAGAIN);
6140 }
6141
6142 /* Get occurrence bit */
6143 reg = !!(reg & 0x4000);
6144
6145 return (sysctl_handle_16(oidp, 0, reg, req));
6146 } /* ixgbe_sysctl_phy_overtemp_occurred */
6147
6148 /************************************************************************
6149 * ixgbe_sysctl_eee_state
6150 *
6151 * Sysctl to set EEE power saving feature
6152 * Values:
6153 * 0 - disable EEE
6154 * 1 - enable EEE
6155 * (none) - get current device EEE state
6156 ************************************************************************/
6157 static int
ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS)6158 ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS)
6159 {
6160 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6161 device_t dev = sc->dev;
6162 if_t ifp = iflib_get_ifp(sc->ctx);
6163 int curr_eee, new_eee, error = 0;
6164 s32 retval;
6165
6166 if (atomic_load_acq_int(&sc->recovery_mode))
6167 return (EPERM);
6168
6169 curr_eee = new_eee = !!(sc->feat_en & IXGBE_FEATURE_EEE);
6170
6171 error = sysctl_handle_int(oidp, &new_eee, 0, req);
6172 if ((error) || (req->newptr == NULL))
6173 return (error);
6174
6175 /* Nothing to do */
6176 if (new_eee == curr_eee)
6177 return (0);
6178
6179 /* Not supported */
6180 if (!(sc->feat_cap & IXGBE_FEATURE_EEE))
6181 return (EINVAL);
6182
6183 /* Bounds checking */
6184 if ((new_eee < 0) || (new_eee > 1))
6185 return (EINVAL);
6186
6187 /* If link speed is <= 1Gbps and EEE is being enabled, log info */
6188 if (sc->hw.mac.type == ixgbe_mac_E610 &&
6189 new_eee &&
6190 sc->link_speed <= IXGBE_LINK_SPEED_1GB_FULL) {
6191 device_printf(dev,
6192 "Energy Efficient Ethernet (EEE) feature is not "
6193 "supported on link speeds equal to or below 1Gbps. "
6194 "EEE is supported on speeds above 1Gbps.\n");
6195 return (EINVAL);
6196 }
6197
6198 retval = ixgbe_setup_eee(&sc->hw, new_eee);
6199 if (retval) {
6200 device_printf(dev, "Error in EEE setup: 0x%08X\n", retval);
6201 return (EINVAL);
6202 }
6203
6204 /* Restart auto-neg */
6205 if_init(ifp, ifp);
6206
6207 device_printf(dev, "New EEE state: %d\n", new_eee);
6208
6209 /* Cache new value */
6210 if (new_eee)
6211 sc->feat_en |= IXGBE_FEATURE_EEE;
6212 else
6213 sc->feat_en &= ~IXGBE_FEATURE_EEE;
6214
6215 return (error);
6216 } /* ixgbe_sysctl_eee_state */
6217
6218 static int
ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)6219 ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)
6220 {
6221 struct ixgbe_softc *sc;
6222 u32 reg, val, shift;
6223 int error, mask;
6224
6225 sc = oidp->oid_arg1;
6226 switch (oidp->oid_arg2) {
6227 case 0:
6228 reg = IXGBE_DTXTCPFLGL;
6229 shift = 0;
6230 break;
6231 case 1:
6232 reg = IXGBE_DTXTCPFLGL;
6233 shift = 16;
6234 break;
6235 case 2:
6236 reg = IXGBE_DTXTCPFLGH;
6237 shift = 0;
6238 break;
6239 default:
6240 return (EINVAL);
6241 break;
6242 }
6243 val = IXGBE_READ_REG(&sc->hw, reg);
6244 mask = (val >> shift) & 0xfff;
6245 error = sysctl_handle_int(oidp, &mask, 0, req);
6246 if (error != 0 || req->newptr == NULL)
6247 return (error);
6248 if (mask < 0 || mask > 0xfff)
6249 return (EINVAL);
6250 val = (val & ~(0xfff << shift)) | (mask << shift);
6251 IXGBE_WRITE_REG(&sc->hw, reg, val);
6252 return (0);
6253 }
6254
6255 /************************************************************************
6256 * ixgbe_init_device_features
6257 ************************************************************************/
6258 static void
ixgbe_init_device_features(struct ixgbe_softc * sc)6259 ixgbe_init_device_features(struct ixgbe_softc *sc)
6260 {
6261 s32 error;
6262
6263 sc->feat_cap = IXGBE_FEATURE_NETMAP |
6264 IXGBE_FEATURE_RSS |
6265 IXGBE_FEATURE_MSI |
6266 IXGBE_FEATURE_MSIX |
6267 IXGBE_FEATURE_LEGACY_IRQ;
6268
6269 /* Set capabilities first... */
6270 switch (sc->hw.mac.type) {
6271 case ixgbe_mac_82598EB:
6272 if (sc->hw.device_id == IXGBE_DEV_ID_82598AT)
6273 sc->feat_cap |= IXGBE_FEATURE_FAN_FAIL;
6274 break;
6275 case ixgbe_mac_X540:
6276 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6277 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6278 if ((sc->hw.device_id == IXGBE_DEV_ID_X540_BYPASS) &&
6279 (sc->hw.bus.func == 0))
6280 sc->feat_cap |= IXGBE_FEATURE_BYPASS;
6281 break;
6282 case ixgbe_mac_X550:
6283 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6284 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR;
6285 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6286 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6287 break;
6288 case ixgbe_mac_X550EM_x:
6289 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6290 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6291 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6292 if (sc->hw.device_id == IXGBE_DEV_ID_X550EM_X_KR)
6293 sc->feat_cap |= IXGBE_FEATURE_EEE;
6294 break;
6295 case ixgbe_mac_X550EM_a:
6296 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6297 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6298 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6299 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ;
6300 if ((sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
6301 (sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
6302 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR;
6303 sc->feat_cap |= IXGBE_FEATURE_EEE;
6304 }
6305 break;
6306 case ixgbe_mac_82599EB:
6307 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6308 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6309 if ((sc->hw.device_id == IXGBE_DEV_ID_82599_BYPASS) &&
6310 (sc->hw.bus.func == 0))
6311 sc->feat_cap |= IXGBE_FEATURE_BYPASS;
6312 if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP)
6313 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ;
6314 break;
6315 case ixgbe_mac_E610:
6316 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6317 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6318 sc->feat_cap |= IXGBE_FEATURE_DBG_DUMP;
6319 sc->feat_cap |= IXGBE_FEATURE_FW_LOGGING;
6320 error = ixgbe_get_caps(&sc->hw);
6321 if (error == 0 && sc->hw.func_caps.common_cap.eee_support != 0)
6322 sc->feat_cap |= IXGBE_FEATURE_EEE;
6323 break;
6324 default:
6325 break;
6326 }
6327
6328 /* Enabled by default... */
6329 /* Fan failure detection */
6330 if (sc->feat_cap & IXGBE_FEATURE_FAN_FAIL)
6331 sc->feat_en |= IXGBE_FEATURE_FAN_FAIL;
6332 /* Netmap */
6333 if (sc->feat_cap & IXGBE_FEATURE_NETMAP)
6334 sc->feat_en |= IXGBE_FEATURE_NETMAP;
6335 /* EEE */
6336 if (sc->feat_cap & IXGBE_FEATURE_EEE)
6337 sc->feat_en |= IXGBE_FEATURE_EEE;
6338 /* Thermal Sensor */
6339 if (sc->feat_cap & IXGBE_FEATURE_TEMP_SENSOR)
6340 sc->feat_en |= IXGBE_FEATURE_TEMP_SENSOR;
6341 /* Recovery mode */
6342 if (sc->feat_cap & IXGBE_FEATURE_RECOVERY_MODE)
6343 sc->feat_en |= IXGBE_FEATURE_RECOVERY_MODE;
6344 /* FW Debug Dump */
6345 if (sc->feat_cap & IXGBE_FEATURE_DBG_DUMP)
6346 sc->feat_en |= IXGBE_FEATURE_DBG_DUMP;
6347 /* FW Logging */
6348 if (sc->feat_cap & IXGBE_FEATURE_FW_LOGGING)
6349 sc->feat_en |= IXGBE_FEATURE_FW_LOGGING;
6350
6351 /* Enabled via global sysctl... */
6352 /* Flow Director */
6353 if (ixgbe_enable_fdir) {
6354 if (sc->feat_cap & IXGBE_FEATURE_FDIR)
6355 sc->feat_en |= IXGBE_FEATURE_FDIR;
6356 else
6357 device_printf(sc->dev,
6358 "Device does not support Flow Director."
6359 " Leaving disabled.");
6360 }
6361 /*
6362 * Message Signal Interrupts - Extended (MSI-X)
6363 * Normal MSI is only enabled if MSI-X calls fail.
6364 */
6365 if (!ixgbe_enable_msix)
6366 sc->feat_cap &= ~IXGBE_FEATURE_MSIX;
6367 /* Receive-Side Scaling (RSS) */
6368 if ((sc->feat_cap & IXGBE_FEATURE_RSS) && ixgbe_enable_rss)
6369 sc->feat_en |= IXGBE_FEATURE_RSS;
6370
6371 /* Disable features with unmet dependencies... */
6372 /* No MSI-X */
6373 if (!(sc->feat_cap & IXGBE_FEATURE_MSIX)) {
6374 sc->feat_cap &= ~IXGBE_FEATURE_RSS;
6375 sc->feat_cap &= ~IXGBE_FEATURE_SRIOV;
6376 sc->feat_en &= ~IXGBE_FEATURE_RSS;
6377 sc->feat_en &= ~IXGBE_FEATURE_SRIOV;
6378 }
6379 } /* ixgbe_init_device_features */
6380
6381 /************************************************************************
6382 * ixgbe_check_fan_failure
6383 ************************************************************************/
6384 static void
ixgbe_check_fan_failure(struct ixgbe_softc * sc,u32 reg,bool in_interrupt)6385 ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt)
6386 {
6387 u32 mask;
6388
6389 mask = (in_interrupt) ? IXGBE_EICR_GPI_SDP1_BY_MAC(&sc->hw) :
6390 IXGBE_ESDP_SDP1;
6391
6392 if (reg & mask)
6393 device_printf(sc->dev,
6394 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n");
6395 } /* ixgbe_check_fan_failure */
6396
6397 /************************************************************************
6398 * ixgbe_sbuf_fw_version
6399 ************************************************************************/
6400 static void
ixgbe_sbuf_fw_version(struct ixgbe_hw * hw,struct sbuf * buf)6401 ixgbe_sbuf_fw_version(struct ixgbe_hw *hw, struct sbuf *buf)
6402 {
6403 struct ixgbe_nvm_version nvm_ver = {0};
6404 const char *space = "";
6405
6406 ixgbe_get_nvm_version(hw, &nvm_ver); /* NVM version */
6407 ixgbe_get_oem_prod_version(hw, &nvm_ver); /* OEM's NVM version */
6408 ixgbe_get_etk_id(hw, &nvm_ver); /* eTrack a build ID in Intel's SCM */
6409 ixgbe_get_orom_version(hw, &nvm_ver); /* Option ROM */
6410
6411 /* FW version */
6412 if ((nvm_ver.phy_fw_maj == 0x0 &&
6413 nvm_ver.phy_fw_min == 0x0 &&
6414 nvm_ver.phy_fw_id == 0x0) ||
6415 (nvm_ver.phy_fw_maj == 0xF &&
6416 nvm_ver.phy_fw_min == 0xFF &&
6417 nvm_ver.phy_fw_id == 0xF)) {
6418 /* If major, minor and id numbers are set to 0,
6419 * reading FW version is unsupported. If major number
6420 * is set to 0xF, minor is set to 0xFF and id is set
6421 * to 0xF, this means that number read is invalid. */
6422 } else
6423 sbuf_printf(buf, "fw %d.%d.%d ",
6424 nvm_ver.phy_fw_maj, nvm_ver.phy_fw_min,
6425 nvm_ver.phy_fw_id);
6426
6427 /* NVM version */
6428 if ((nvm_ver.nvm_major == 0x0 &&
6429 nvm_ver.nvm_minor == 0x0 &&
6430 nvm_ver.nvm_id == 0x0) ||
6431 (nvm_ver.nvm_major == 0xF &&
6432 nvm_ver.nvm_minor == 0xFF &&
6433 nvm_ver.nvm_id == 0xF)) {
6434 /* If major, minor and id numbers are set to 0,
6435 * reading NVM version is unsupported. If major number
6436 * is set to 0xF, minor is set to 0xFF and id is set
6437 * to 0xF, this means that number read is invalid. */
6438 } else
6439 sbuf_printf(buf, "nvm %x.%02x.%x ",
6440 nvm_ver.nvm_major, nvm_ver.nvm_minor, nvm_ver.nvm_id);
6441
6442 if (nvm_ver.oem_valid) {
6443 sbuf_printf(buf, "NVM OEM V%d.%d R%d", nvm_ver.oem_major,
6444 nvm_ver.oem_minor, nvm_ver.oem_release);
6445 space = " ";
6446 }
6447
6448 if (nvm_ver.or_valid) {
6449 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
6450 space, nvm_ver.or_major, nvm_ver.or_build,
6451 nvm_ver.or_patch);
6452 space = " ";
6453 }
6454
6455 if (nvm_ver.etk_id != ((NVM_VER_INVALID << NVM_ETK_SHIFT) |
6456 NVM_VER_INVALID | 0xFFFFFFFF)) {
6457 sbuf_printf(buf, "%seTrack 0x%08x", space, nvm_ver.etk_id);
6458 }
6459 } /* ixgbe_sbuf_fw_version */
6460
6461 /************************************************************************
6462 * ixgbe_print_fw_version
6463 ************************************************************************/
6464 static void
ixgbe_print_fw_version(if_ctx_t ctx)6465 ixgbe_print_fw_version(if_ctx_t ctx)
6466 {
6467 struct ixgbe_softc *sc = iflib_get_softc(ctx);
6468 struct ixgbe_hw *hw = &sc->hw;
6469 device_t dev = sc->dev;
6470 struct sbuf *buf;
6471 int error = 0;
6472
6473 buf = sbuf_new_auto();
6474 if (!buf) {
6475 device_printf(dev, "Could not allocate sbuf for output.\n");
6476 return;
6477 }
6478
6479 ixgbe_sbuf_fw_version(hw, buf);
6480
6481 error = sbuf_finish(buf);
6482 if (error)
6483 device_printf(dev, "Error finishing sbuf: %d\n", error);
6484 else if (sbuf_len(buf))
6485 device_printf(dev, "%s\n", sbuf_data(buf));
6486
6487 sbuf_delete(buf);
6488 } /* ixgbe_print_fw_version */
6489
6490 /************************************************************************
6491 * ixgbe_sysctl_print_fw_version
6492 ************************************************************************/
6493 static int
ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)6494 ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
6495 {
6496 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6497 struct ixgbe_hw *hw = &sc->hw;
6498 device_t dev = sc->dev;
6499 struct sbuf *buf;
6500 int error = 0;
6501
6502 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6503 if (!buf) {
6504 device_printf(dev, "Could not allocate sbuf for output.\n");
6505 return (ENOMEM);
6506 }
6507
6508 ixgbe_sbuf_fw_version(hw, buf);
6509
6510 error = sbuf_finish(buf);
6511 if (error)
6512 device_printf(dev, "Error finishing sbuf: %d\n", error);
6513
6514 sbuf_delete(buf);
6515
6516 return (0);
6517 } /* ixgbe_sysctl_print_fw_version */
6518