1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6#include <dt-bindings/clock/imx8ulp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/imx8ulp-power.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8ulp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpiod; 22 gpio1 = &gpioe; 23 gpio2 = &gpiof; 24 mmc0 = &usdhc0; 25 mmc1 = &usdhc1; 26 mmc2 = &usdhc2; 27 serial0 = &lpuart4; 28 serial1 = &lpuart5; 29 serial2 = &lpuart6; 30 serial3 = &lpuart7; 31 spi0 = &lpspi4; 32 spi1 = &lpspi5; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 A35_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 next-level-cache = <&A35_L2>; 45 cpu-idle-states = <&cpu_sleep>; 46 }; 47 48 A35_1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35"; 51 reg = <0x0 0x1>; 52 enable-method = "psci"; 53 next-level-cache = <&A35_L2>; 54 cpu-idle-states = <&cpu_sleep>; 55 }; 56 57 A35_L2: l2-cache0 { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 }; 62 63 idle-states { 64 entry-method = "psci"; 65 66 cpu_sleep: cpu-sleep { 67 compatible = "arm,idle-state"; 68 arm,psci-suspend-param = <0x0>; 69 local-timer-stop; 70 entry-latency-us = <1000>; 71 exit-latency-us = <700>; 72 min-residency-us = <2700>; 73 }; 74 }; 75 }; 76 77 gic: interrupt-controller@2d400000 { 78 compatible = "arm,gic-v3"; 79 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ 80 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 81 #interrupt-cells = <3>; 82 interrupt-controller; 83 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 84 }; 85 86 pmu { 87 compatible = "arm,cortex-a35-pmu"; 88 interrupt-parent = <&gic>; 89 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 90 interrupt-affinity = <&A35_0>, <&A35_1>; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0"; 95 method = "smc"; 96 }; 97 98 thermal-zones { 99 cpu-thermal { 100 polling-delay-passive = <250>; 101 polling-delay = <2000>; 102 thermal-sensors = <&scmi_sensor 0>; 103 104 trips { 105 cpu_alert0: trip0 { 106 temperature = <85000>; 107 hysteresis = <2000>; 108 type = "passive"; 109 }; 110 111 cpu_crit0: trip1 { 112 temperature = <95000>; 113 hysteresis = <2000>; 114 type = "critical"; 115 }; 116 }; 117 }; 118 }; 119 120 timer { 121 compatible = "arm,armv8-timer"; 122 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 123 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 124 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 125 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 126 }; 127 128 frosc: clock-frosc { 129 compatible = "fixed-clock"; 130 clock-frequency = <192000000>; 131 clock-output-names = "frosc"; 132 #clock-cells = <0>; 133 }; 134 135 lposc: clock-lposc { 136 compatible = "fixed-clock"; 137 clock-frequency = <1000000>; 138 clock-output-names = "lposc"; 139 #clock-cells = <0>; 140 }; 141 142 rosc: clock-rosc { 143 compatible = "fixed-clock"; 144 clock-frequency = <32768>; 145 clock-output-names = "rosc"; 146 #clock-cells = <0>; 147 }; 148 149 sosc: clock-sosc { 150 compatible = "fixed-clock"; 151 clock-frequency = <24000000>; 152 clock-output-names = "sosc"; 153 #clock-cells = <0>; 154 }; 155 156 sram@2201f000 { 157 compatible = "mmio-sram"; 158 reg = <0x0 0x2201f000 0x0 0x1000>; 159 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0 0x0 0x2201f000 0x1000>; 163 164 scmi_buf: scmi-sram-section@0 { 165 compatible = "arm,scmi-shmem"; 166 reg = <0x0 0x400>; 167 }; 168 }; 169 170 firmware { 171 scmi { 172 compatible = "arm,scmi-smc"; 173 arm,smc-id = <0xc20000fe>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 shmem = <&scmi_buf>; 177 178 scmi_devpd: protocol@11 { 179 reg = <0x11>; 180 #power-domain-cells = <1>; 181 }; 182 183 scmi_sensor: protocol@15 { 184 reg = <0x15>; 185 #thermal-sensor-cells = <1>; 186 }; 187 }; 188 }; 189 190 cm33: remoteproc-cm33 { 191 compatible = "fsl,imx8ulp-cm33"; 192 status = "disabled"; 193 }; 194 195 soc: soc@0 { 196 compatible = "simple-bus"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges = <0x0 0x0 0x0 0x40000000>, 200 <0x60000000 0x0 0x60000000 0x1000000>; 201 202 s4muap: mailbox@27020000 { 203 compatible = "fsl,imx8ulp-mu-s4"; 204 reg = <0x27020000 0x10000>; 205 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 206 #mbox-cells = <2>; 207 }; 208 209 per_bridge3: bus@29000000 { 210 compatible = "simple-bus"; 211 reg = <0x29000000 0x800000>; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 ranges; 215 216 edma1: dma-controller@29010000 { 217 compatible = "fsl,imx8ulp-edma"; 218 reg = <0x29010000 0x210000>; 219 #dma-cells = <3>; 220 dma-channels = <32>; 221 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, 254 <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, 255 <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, 256 <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, 257 <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, 258 <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, 259 <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, 260 <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, 261 <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, 262 <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, 263 <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, 264 <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, 265 <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, 266 <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, 267 <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, 268 <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, 269 <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; 270 clock-names = "dma", "ch00","ch01", "ch02", "ch03", 271 "ch04", "ch05", "ch06", "ch07", 272 "ch08", "ch09", "ch10", "ch11", 273 "ch12", "ch13", "ch14", "ch15", 274 "ch16", "ch17", "ch18", "ch19", 275 "ch20", "ch21", "ch22", "ch23", 276 "ch24", "ch25", "ch26", "ch27", 277 "ch28", "ch29", "ch30", "ch31"; 278 }; 279 280 mu: mailbox@29220000 { 281 compatible = "fsl,imx8ulp-mu"; 282 reg = <0x29220000 0x10000>; 283 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 284 #mbox-cells = <2>; 285 status = "disabled"; 286 }; 287 288 mu3: mailbox@29230000 { 289 compatible = "fsl,imx8ulp-mu"; 290 reg = <0x29230000 0x10000>; 291 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; 293 #mbox-cells = <2>; 294 status = "disabled"; 295 }; 296 297 wdog3: watchdog@292a0000 { 298 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; 299 reg = <0x292a0000 0x10000>; 300 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 302 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 303 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; 304 timeout-sec = <40>; 305 }; 306 307 cgc1: clock-controller@292c0000 { 308 compatible = "fsl,imx8ulp-cgc1"; 309 reg = <0x292c0000 0x10000>; 310 #clock-cells = <1>; 311 }; 312 313 pcc3: clock-controller@292d0000 { 314 compatible = "fsl,imx8ulp-pcc3"; 315 reg = <0x292d0000 0x10000>; 316 #clock-cells = <1>; 317 #reset-cells = <1>; 318 }; 319 320 crypto: crypto@292e0000 { 321 compatible = "fsl,sec-v4.0"; 322 reg = <0x292e0000 0x10000>; 323 ranges = <0 0x292e0000 0x10000>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 327 sec_jr0: jr@1000 { 328 compatible = "fsl,sec-v4.0-job-ring"; 329 reg = <0x1000 0x1000>; 330 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 331 }; 332 333 sec_jr1: jr@2000 { 334 compatible = "fsl,sec-v4.0-job-ring"; 335 reg = <0x2000 0x1000>; 336 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 337 }; 338 339 sec_jr2: jr@3000 { 340 compatible = "fsl,sec-v4.0-job-ring"; 341 reg = <0x3000 0x1000>; 342 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 343 }; 344 345 sec_jr3: jr@4000 { 346 compatible = "fsl,sec-v4.0-job-ring"; 347 reg = <0x4000 0x1000>; 348 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 349 }; 350 }; 351 352 tpm5: tpm@29340000 { 353 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; 354 reg = <0x29340000 0x1000>; 355 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&pcc3 IMX8ULP_CLK_TPM5>, 357 <&pcc3 IMX8ULP_CLK_TPM5>; 358 clock-names = "ipg", "per"; 359 status = "disabled"; 360 }; 361 362 lpi2c4: i2c@29370000 { 363 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 364 reg = <0x29370000 0x10000>; 365 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, 367 <&pcc3 IMX8ULP_CLK_LPI2C4>; 368 clock-names = "per", "ipg"; 369 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; 370 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 371 assigned-clock-rates = <48000000>; 372 status = "disabled"; 373 }; 374 375 lpi2c5: i2c@29380000 { 376 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 377 reg = <0x29380000 0x10000>; 378 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, 380 <&pcc3 IMX8ULP_CLK_LPI2C5>; 381 clock-names = "per", "ipg"; 382 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; 383 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 384 assigned-clock-rates = <48000000>; 385 status = "disabled"; 386 }; 387 388 lpuart4: serial@29390000 { 389 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 390 reg = <0x29390000 0x1000>; 391 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; 393 clock-names = "ipg"; 394 status = "disabled"; 395 }; 396 397 lpuart5: serial@293a0000 { 398 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 399 reg = <0x293a0000 0x1000>; 400 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; 402 clock-names = "ipg"; 403 status = "disabled"; 404 }; 405 406 lpspi4: spi@293b0000 { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 410 reg = <0x293b0000 0x10000>; 411 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, 413 <&pcc3 IMX8ULP_CLK_LPSPI4>; 414 clock-names = "per", "ipg"; 415 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; 416 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 417 assigned-clock-rates = <48000000>; 418 status = "disabled"; 419 }; 420 421 lpspi5: spi@293c0000 { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 425 reg = <0x293c0000 0x10000>; 426 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, 428 <&pcc3 IMX8ULP_CLK_LPSPI5>; 429 clock-names = "per", "ipg"; 430 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; 431 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 432 assigned-clock-rates = <48000000>; 433 status = "disabled"; 434 }; 435 }; 436 437 per_bridge4: bus@29800000 { 438 compatible = "simple-bus"; 439 reg = <0x29800000 0x800000>; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 ranges; 443 444 pcc4: clock-controller@29800000 { 445 compatible = "fsl,imx8ulp-pcc4"; 446 reg = <0x29800000 0x10000>; 447 #clock-cells = <1>; 448 #reset-cells = <1>; 449 }; 450 451 flexspi2: spi@29810000 { 452 compatible = "nxp,imx8ulp-fspi"; 453 reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; 454 reg-names = "fspi_base", "fspi_mmap"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, 459 <&pcc4 IMX8ULP_CLK_FLEXSPI2>; 460 clock-names = "fspi_en", "fspi"; 461 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>; 462 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 463 status = "disabled"; 464 }; 465 466 lpi2c6: i2c@29840000 { 467 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 468 reg = <0x29840000 0x10000>; 469 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, 471 <&pcc4 IMX8ULP_CLK_LPI2C6>; 472 clock-names = "per", "ipg"; 473 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; 474 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 475 assigned-clock-rates = <48000000>; 476 status = "disabled"; 477 }; 478 479 lpi2c7: i2c@29850000 { 480 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 481 reg = <0x29850000 0x10000>; 482 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, 484 <&pcc4 IMX8ULP_CLK_LPI2C7>; 485 clock-names = "per", "ipg"; 486 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; 487 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 488 assigned-clock-rates = <48000000>; 489 status = "disabled"; 490 }; 491 492 lpuart6: serial@29860000 { 493 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 494 reg = <0x29860000 0x1000>; 495 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; 497 clock-names = "ipg"; 498 status = "disabled"; 499 }; 500 501 lpuart7: serial@29870000 { 502 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 503 reg = <0x29870000 0x1000>; 504 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; 506 clock-names = "ipg"; 507 status = "disabled"; 508 }; 509 510 sai4: sai@29880000 { 511 compatible = "fsl,imx8ulp-sai"; 512 reg = <0x29880000 0x10000>; 513 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, 515 <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 516 <&cgc1 IMX8ULP_CLK_DUMMY>; 517 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 518 dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; 519 dma-names = "rx", "tx"; 520 #sound-dai-cells = <0>; 521 fsl,dataline = <0 0x03 0x03>; 522 status = "disabled"; 523 }; 524 525 sai5: sai@29890000 { 526 compatible = "fsl,imx8ulp-sai"; 527 reg = <0x29890000 0x10000>; 528 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, 530 <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 531 <&cgc1 IMX8ULP_CLK_DUMMY>; 532 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 533 dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; 534 dma-names = "rx", "tx"; 535 #sound-dai-cells = <0>; 536 fsl,dataline = <0 0x0f 0x0f>; 537 status = "disabled"; 538 }; 539 540 iomuxc1: pinctrl@298c0000 { 541 compatible = "fsl,imx8ulp-iomuxc1"; 542 reg = <0x298c0000 0x10000>; 543 }; 544 545 usdhc0: mmc@298d0000 { 546 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 547 reg = <0x298d0000 0x10000>; 548 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 550 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, 551 <&pcc4 IMX8ULP_CLK_USDHC0>; 552 clock-names = "ipg", "ahb", "per"; 553 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 554 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, 555 <&pcc4 IMX8ULP_CLK_USDHC0>; 556 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; 557 assigned-clock-rates = <389283840>, <389283840>; 558 fsl,tuning-start-tap = <20>; 559 fsl,tuning-step = <2>; 560 bus-width = <4>; 561 status = "disabled"; 562 }; 563 564 usdhc1: mmc@298e0000 { 565 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 566 reg = <0x298e0000 0x10000>; 567 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 569 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 570 <&pcc4 IMX8ULP_CLK_USDHC1>; 571 clock-names = "ipg", "ahb", "per"; 572 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 573 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 574 <&pcc4 IMX8ULP_CLK_USDHC1>; 575 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 576 assigned-clock-rates = <194641920>, <194641920>; 577 fsl,tuning-start-tap = <20>; 578 fsl,tuning-step = <2>; 579 bus-width = <4>; 580 status = "disabled"; 581 }; 582 583 usdhc2: mmc@298f0000 { 584 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 585 reg = <0x298f0000 0x10000>; 586 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 588 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 589 <&pcc4 IMX8ULP_CLK_USDHC2>; 590 clock-names = "ipg", "ahb", "per"; 591 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 592 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 593 <&pcc4 IMX8ULP_CLK_USDHC2>; 594 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 595 assigned-clock-rates = <194641920>, <194641920>; 596 fsl,tuning-start-tap = <20>; 597 fsl,tuning-step = <2>; 598 bus-width = <4>; 599 status = "disabled"; 600 }; 601 602 usbotg1: usb@29900000 { 603 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; 604 reg = <0x29900000 0x200>; 605 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&pcc4 IMX8ULP_CLK_USB0>; 607 power-domains = <&scmi_devpd IMX8ULP_PD_USB0>; 608 phys = <&usbphy1>; 609 fsl,usbmisc = <&usbmisc1 0>; 610 ahb-burst-config = <0x0>; 611 tx-burst-size-dword = <0x8>; 612 rx-burst-size-dword = <0x8>; 613 status = "disabled"; 614 }; 615 616 usbmisc1: usbmisc@29900200 { 617 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", 618 "fsl,imx6q-usbmisc"; 619 reg = <0x29900200 0x200>; 620 #index-cells = <1>; 621 status = "disabled"; 622 }; 623 624 usbphy1: usb-phy@29910000 { 625 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; 626 reg = <0x29910000 0x10000>; 627 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; 629 #phy-cells = <0>; 630 status = "disabled"; 631 }; 632 633 usbotg2: usb@29920000 { 634 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; 635 reg = <0x29920000 0x200>; 636 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&pcc4 IMX8ULP_CLK_USB1>; 638 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 639 phys = <&usbphy2>; 640 fsl,usbmisc = <&usbmisc2 0>; 641 ahb-burst-config = <0x0>; 642 tx-burst-size-dword = <0x8>; 643 rx-burst-size-dword = <0x8>; 644 status = "disabled"; 645 }; 646 647 usbmisc2: usbmisc@29920200 { 648 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", 649 "fsl,imx6q-usbmisc"; 650 reg = <0x29920200 0x200>; 651 #index-cells = <1>; 652 status = "disabled"; 653 }; 654 655 usbphy2: usb-phy@29930000 { 656 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; 657 reg = <0x29930000 0x10000>; 658 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; 660 #phy-cells = <0>; 661 status = "disabled"; 662 }; 663 664 fec: ethernet@29950000 { 665 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; 666 reg = <0x29950000 0x10000>; 667 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 668 interrupt-names = "int0"; 669 fsl,num-tx-queues = <1>; 670 fsl,num-rx-queues = <1>; 671 status = "disabled"; 672 }; 673 }; 674 675 gpioe: gpio@2d000000 { 676 compatible = "fsl,imx8ulp-gpio"; 677 reg = <0x2d000000 0x1000>; 678 gpio-controller; 679 #gpio-cells = <2>; 680 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, 685 <&pcc4 IMX8ULP_CLK_PCTLE>; 686 clock-names = "gpio", "port"; 687 gpio-ranges = <&iomuxc1 0 32 24>; 688 ngpios = <24>; 689 }; 690 691 gpiof: gpio@2d010000 { 692 compatible = "fsl,imx8ulp-gpio"; 693 reg = <0x2d010000 0x1000>; 694 gpio-controller; 695 #gpio-cells = <2>; 696 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, 701 <&pcc4 IMX8ULP_CLK_PCTLF>; 702 clock-names = "gpio", "port"; 703 gpio-ranges = <&iomuxc1 0 64 32>; 704 ngpios = <32>; 705 }; 706 707 per_bridge5: bus@2d800000 { 708 compatible = "simple-bus"; 709 reg = <0x2d800000 0x800000>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 ranges; 713 714 edma2: dma-controller@2d800000 { 715 compatible = "fsl,imx8ulp-edma"; 716 reg = <0x2d800000 0x210000>; 717 #dma-cells = <3>; 718 dma-channels = <32>; 719 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, 752 <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, 753 <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, 754 <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, 755 <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, 756 <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, 757 <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, 758 <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, 759 <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, 760 <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, 761 <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, 762 <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, 763 <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, 764 <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, 765 <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, 766 <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, 767 <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; 768 clock-names = "dma", "ch00","ch01", "ch02", "ch03", 769 "ch04", "ch05", "ch06", "ch07", 770 "ch08", "ch09", "ch10", "ch11", 771 "ch12", "ch13", "ch14", "ch15", 772 "ch16", "ch17", "ch18", "ch19", 773 "ch20", "ch21", "ch22", "ch23", 774 "ch24", "ch25", "ch26", "ch27", 775 "ch28", "ch29", "ch30", "ch31"; 776 }; 777 778 sim_lpav: clock-controller@2da50000 { 779 compatible = "fsl,imx8ulp-sim-lpav"; 780 reg = <0x2da50000 0x10000>; 781 clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, 782 <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, 783 <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; 784 clock-names = "bus", "core", "plat"; 785 #clock-cells = <1>; 786 #reset-cells = <1>; 787 788 sim_lpav_mux: mux-controller { 789 compatible = "reg-mux"; 790 #mux-control-cells = <1>; 791 mux-reg-masks = <0x8 0x00000200>; 792 }; 793 }; 794 795 cgc2: clock-controller@2da60000 { 796 compatible = "fsl,imx8ulp-cgc2"; 797 reg = <0x2da60000 0x10000>; 798 #clock-cells = <1>; 799 }; 800 801 pcc5: clock-controller@2da70000 { 802 compatible = "fsl,imx8ulp-pcc5"; 803 reg = <0x2da70000 0x10000>; 804 #clock-cells = <1>; 805 #reset-cells = <1>; 806 }; 807 808 sai6: sai@2da90000 { 809 compatible = "fsl,imx8ulp-sai"; 810 reg = <0x2da90000 0x10000>; 811 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, 813 <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 814 <&cgc1 IMX8ULP_CLK_DUMMY>; 815 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 816 dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; 817 dma-names = "rx", "tx"; 818 #sound-dai-cells = <0>; 819 fsl,dataline = <0 0x0f 0x0f>; 820 status = "disabled"; 821 }; 822 823 sai7: sai@2daa0000 { 824 compatible = "fsl,imx8ulp-sai"; 825 reg = <0x2daa0000 0x10000>; 826 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, 828 <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 829 <&cgc1 IMX8ULP_CLK_DUMMY>; 830 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 831 dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; 832 dma-names = "rx", "tx"; 833 #sound-dai-cells = <0>; 834 fsl,dataline = <0 0x0f 0x0f>; 835 status = "disabled"; 836 }; 837 838 spdif: spdif@2dab0000 { 839 compatible = "fsl,imx8ulp-spdif"; 840 reg = <0x2dab0000 0x10000>; 841 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ 843 <&sosc>, /* 0, extal */ 844 <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ 845 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ 846 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ 847 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ 848 <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ 849 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ 850 <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ 851 <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ 852 clock-names = "core", "rxtx0", 853 "rxtx1", "rxtx2", 854 "rxtx3", "rxtx4", 855 "rxtx5", "rxtx6", 856 "rxtx7", "spba"; 857 dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; 858 dma-names = "rx", "tx"; 859 status = "disabled"; 860 }; 861 }; 862 863 gpiod: gpio@2e200000 { 864 compatible = "fsl,imx8ulp-gpio"; 865 reg = <0x2e200000 0x1000>; 866 gpio-controller; 867 #gpio-cells = <2>; 868 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, 873 <&pcc5 IMX8ULP_CLK_RGPIOD>; 874 clock-names = "gpio", "port"; 875 gpio-ranges = <&iomuxc1 0 0 24>; 876 ngpios = <24>; 877 }; 878 }; 879}; 880