1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Dominik Haller <d.haller@phytec.de> 5 * 6 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-j721s2.dtsi" 14 15/ { 16 compatible = "phytec,am68-phycore-som", "ti,j721s2"; 17 model = "PHYTEC phyCORE-AM68x"; 18 19 aliases { 20 ethernet1 = &main_cpsw_port1; 21 mmc0 = &main_sdhci0; 22 rtc0 = &i2c_som_rtc; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 /* 4GB RAM */ 28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 29 <0x00000008 0x80000000 0x00000000 0x80000000>; 30 bootph-all; 31 }; 32 33 reserved_memory: reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 /* global cma region */ 39 linux,cma { 40 compatible = "shared-dma-pool"; 41 reusable; 42 size = <0x00 0x20000000>; 43 linux,cma-default; 44 }; 45 46 secure_ddr: optee@9e800000 { 47 reg = <0x00 0x9e800000 0x00 0x01800000>; 48 alignment = <0x1000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core0_memory_region: memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 }; 64 65 vdd_sd_dv: regulator-sd { 66 /* Output of TLV71033 */ 67 compatible = "regulator-gpio"; 68 regulator-name = "VDD_SD_DV"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&vdd_sd_dv_pins_default>; 71 regulator-min-microvolt = <1800000>; 72 regulator-max-microvolt = <3300000>; 73 regulator-boot-on; 74 gpios = <&main_gpio0 1 GPIO_ACTIVE_HIGH>; 75 states = <3300000 0x0>, 76 <1800000 0x1>; 77 }; 78}; 79 80&main_pmx0 { 81 main_cpsw_mdio_pins_default: main-cpsw-mdio-default-pins { 82 pinctrl-single,pins = < 83 J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ 84 J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ 85 >; 86 }; 87 88 main_i2c0_pins_default: main-i2c0-default-pins { 89 pinctrl-single,pins = < 90 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ 91 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ 92 >; 93 }; 94 95 rgmii1_pins_default: rgmii1-default-pins { 96 pinctrl-single,pins = < 97 J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ 98 J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ 99 J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ 100 J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ 101 J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ 102 J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ 103 J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ 104 J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ 105 J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ 106 J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ 107 J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ 108 J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ 109 >; 110 }; 111 112 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 113 pinctrl-single,pins = < 114 J721S2_IOPAD(0x004, PIN_OUTPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ 115 >; 116 }; 117}; 118 119&wkup_pmx0 { 120 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 121 pinctrl-single,pins = < 122 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 123 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 124 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 125 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 126 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ 127 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ 128 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ 129 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ 130 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ 131 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ 132 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ 133 >; 134 bootph-all; 135 }; 136}; 137 138&wkup_pmx1 { 139 pmic_irq_pins_default: pmic-irq-default-pins { 140 pinctrl-single,pins = < 141 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 142 >; 143 }; 144}; 145 146&wkup_pmx2 { 147 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 148 pinctrl-single,pins = < 149 J721S2_WKUP_IOPAD(0x098, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SCL */ 150 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */ 151 >; 152 bootph-all; 153 }; 154}; 155 156&main_cpsw { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&rgmii1_pins_default>; 159 status = "okay"; 160}; 161 162&main_cpsw_mdio { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&main_cpsw_mdio_pins_default>; 165 status = "okay"; 166 167 phy1: ethernet-phy@0 { 168 reg = <0>; 169 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 170 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 171 ti,min-output-impedance; 172 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 173 }; 174}; 175 176&main_cpsw_port1 { 177 phy-handle = <&phy1>; 178 phy-mode = "rgmii-id"; 179 status = "okay"; 180}; 181 182&main_i2c0 { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&main_i2c0_pins_default>; 185 186 temperature-sensor@48 { 187 compatible = "ti,tmp102"; 188 reg = <0x48>; 189 }; 190 191 temperature-sensor@49 { 192 compatible = "ti,tmp102"; 193 reg = <0x49>; 194 }; 195 196 i2c_som_rtc: rtc@52 { 197 compatible = "microcrystal,rv3028"; 198 reg = <0x52>; 199 }; 200}; 201 202&main_gpio0 { 203 status = "okay"; 204}; 205 206/* eMMC */ 207&main_sdhci0 { 208 non-removable; 209 ti,driver-strength-ohm = <50>; 210 bootph-all; 211 status = "okay"; 212}; 213 214/* SD card */ 215&main_sdhci1 { 216 vqmmc-supply = <&vdd_sd_dv>; 217 bootph-all; 218}; 219 220&ospi0 { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 223 status = "okay"; 224 225 serial_flash: flash@0 { 226 compatible = "jedec,spi-nor"; 227 reg = <0x0>; 228 spi-tx-bus-width = <8>; 229 spi-rx-bus-width = <8>; 230 spi-max-frequency = <25000000>; 231 cdns,tshsl-ns = <60>; 232 cdns,tsd2d-ns = <60>; 233 cdns,tchsh-ns = <60>; 234 cdns,tslch-ns = <60>; 235 cdns,read-delay = <2>; 236 bootph-all; 237 }; 238}; 239 240&wkup_gpio0 { 241 status = "okay"; 242}; 243 244&wkup_i2c0 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&wkup_i2c0_pins_default>; 247 clock-frequency = <400000>; 248 status = "okay"; 249 250 vdd_cpu_avs: regulator@40 { 251 compatible = "ti,tps62873"; 252 reg = <0x40>; 253 regulator-name = "VDD_CPU_AVS"; 254 regulator-min-microvolt = <600000>; 255 regulator-max-microvolt = <900000>; 256 regulator-boot-on; 257 regulator-always-on; 258 bootph-pre-ram; 259 }; 260 261 pmic: pmic@48 { 262 compatible = "ti,tps6594-q1"; 263 reg = <0x48>; 264 system-power-controller; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pmic_irq_pins_default>; 267 interrupt-parent = <&wkup_gpio0>; 268 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 269 gpio-controller; 270 #gpio-cells = <2>; 271 buck12-supply = <&vcc_3v3>; 272 buck3-supply = <&vcc_3v3>; 273 buck4-supply = <&vcc_3v3>; 274 buck5-supply = <&vcc_3v3>; 275 ldo1-supply = <&vcc_3v3>; 276 ldo2-supply = <&vcc_3v3>; 277 ldo3-supply = <&vcc_3v3>; 278 ldo4-supply = <&vcc_3v3>; 279 ti,primary-pmic; 280 281 regulators { 282 bucka12: buck12 { 283 regulator-name = "VDD_DDR_1V1"; 284 regulator-min-microvolt = <1100000>; 285 regulator-max-microvolt = <1100000>; 286 regulator-boot-on; 287 regulator-always-on; 288 bootph-all; 289 }; 290 291 bucka3: buck3 { 292 regulator-name = "VDD_RAM_0V85"; 293 regulator-min-microvolt = <850000>; 294 regulator-max-microvolt = <850000>; 295 regulator-boot-on; 296 regulator-always-on; 297 bootph-all; 298 }; 299 300 bucka4: buck4 { 301 regulator-name = "VDD_IO_1V8"; 302 regulator-min-microvolt = <1800000>; 303 regulator-max-microvolt = <1800000>; 304 regulator-boot-on; 305 regulator-always-on; 306 bootph-all; 307 }; 308 309 bucka5: buck5 { 310 regulator-name = "VDD_MCU_0V85"; 311 regulator-min-microvolt = <850000>; 312 regulator-max-microvolt = <850000>; 313 regulator-boot-on; 314 regulator-always-on; 315 bootph-all; 316 }; 317 318 ldoa1: ldo1 { 319 regulator-name = "VDD_MCUIO_1V8"; 320 regulator-min-microvolt = <1800000>; 321 regulator-max-microvolt = <1800000>; 322 regulator-boot-on; 323 regulator-always-on; 324 bootph-all; 325 }; 326 327 ldoa2: ldo2 { 328 regulator-name = "VDD_MCUIO_3V3"; 329 regulator-min-microvolt = <3300000>; 330 regulator-max-microvolt = <3300000>; 331 regulator-boot-on; 332 regulator-always-on; 333 bootph-all; 334 }; 335 336 ldoa3: ldo3 { 337 regulator-name = "VDDA_DLL_0V8"; 338 regulator-min-microvolt = <800000>; 339 regulator-max-microvolt = <800000>; 340 regulator-boot-on; 341 regulator-always-on; 342 bootph-all; 343 }; 344 345 ldoa4: ldo4 { 346 regulator-name = "VDDA_MCU_1V8"; 347 regulator-min-microvolt = <1800000>; 348 regulator-max-microvolt = <1800000>; 349 regulator-boot-on; 350 regulator-always-on; 351 bootph-all; 352 }; 353 }; 354 }; 355 356 eeprom@50 { 357 compatible = "atmel,24c32"; 358 reg = <0x50>; 359 pagesize = <32>; 360 bootph-all; 361 }; 362 363 som_eeprom_opt: eeprom@51 { 364 compatible = "atmel,24c32"; 365 reg = <0x51>; 366 pagesize = <32>; 367 }; 368}; 369 370#include "k3-j721s2-ti-ipc-firmware.dtsi" 371