1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
30 */
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/rman.h>
39 #include <sys/smp.h>
40 #include <sys/socket.h>
41 #include <sys/sysctl.h>
42 #include <sys/systm.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <dev/mii/mii.h>
48 #include <dev/mii/miivar.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52
53 #include "xgbe.h"
54 #include "xgbe-common.h"
55
56 #include "miibus_if.h"
57 #include "ifdi_if.h"
58 #include "opt_inet.h"
59 #include "opt_inet6.h"
60 #include "opt_rss.h"
61
62 #include <net/rss_config.h>
63 #ifdef RSS
64 #include <netinet/in_rss.h>
65 #endif
66
67 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
68
69 extern struct if_txrx axgbe_txrx;
70 static int axgbe_sph_enable;
71
72 /* Function prototypes */
73 static void *axgbe_register(device_t);
74 static int axgbe_if_attach_pre(if_ctx_t);
75 static int axgbe_if_attach_post(if_ctx_t);
76 static int axgbe_if_detach(if_ctx_t);
77 static void axgbe_if_stop(if_ctx_t);
78 static void axgbe_if_init(if_ctx_t);
79
80 /* Queue related routines */
81 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
82 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
83 static int axgbe_alloc_channels(if_ctx_t);
84 static void axgbe_free_channels(struct axgbe_if_softc *);
85 static void axgbe_if_queues_free(if_ctx_t);
86 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
87 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
88
89 /* Interrupt related routines */
90 static void axgbe_if_disable_intr(if_ctx_t);
91 static void axgbe_if_enable_intr(if_ctx_t);
92 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
93 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
94
95 /* Init and Iflib routines */
96 static int axgbe_pci_init(struct xgbe_prv_data *);
97 static void axgbe_pci_stop(if_ctx_t);
98 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
99 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
100 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
101 static void axgbe_if_update_admin_status(if_ctx_t);
102 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
103 static int axgbe_if_media_change(if_ctx_t);
104 static int axgbe_if_promisc_set(if_ctx_t, int);
105 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
106 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
107 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
108 #if __FreeBSD_version >= 1300000
109 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
110 #endif
111 static void axgbe_set_counts(if_ctx_t);
112 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
113 static void axgbe_initialize_rss_mapping(struct xgbe_prv_data *);
114
115 /* MII interface registered functions */
116 static int axgbe_miibus_readreg(device_t, int, int);
117 static int axgbe_miibus_writereg(device_t, int, int, int);
118 static void axgbe_miibus_statchg(device_t);
119
120 /* ISR routines */
121 static int axgbe_dev_isr(void *);
122 static void axgbe_ecc_isr(void *);
123 static void axgbe_i2c_isr(void *);
124 static void axgbe_an_isr(void *);
125 static int axgbe_msix_que(void *);
126
127 /* Timer routines */
128 static void xgbe_service(void *, int);
129 static void xgbe_service_timer(void *);
130 static void xgbe_init_timers(struct xgbe_prv_data *);
131 static void xgbe_stop_timers(struct xgbe_prv_data *);
132
133 /* Dump routines */
134 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
135
136 /*
137 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
138 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
139 * table.
140 */
141 static struct resource_spec axgbe_pci_mac_spec[] = {
142 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
143 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
144 { -1, 0 }
145 };
146
147 static const pci_vendor_info_t axgbe_vendor_info_array[] =
148 {
149 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
150 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
151 PVID_END
152 };
153
154 static struct xgbe_version_data xgbe_v2a = {
155 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
156 .xpcs_access = XGBE_XPCS_ACCESS_V2,
157 .mmc_64bit = 1,
158 .tx_max_fifo_size = 229376,
159 .rx_max_fifo_size = 229376,
160 .tx_tstamp_workaround = 1,
161 .ecc_support = 1,
162 .i2c_support = 1,
163 .irq_reissue_support = 1,
164 .tx_desc_prefetch = 5,
165 .rx_desc_prefetch = 5,
166 .an_cdr_workaround = 1,
167 };
168
169 static struct xgbe_version_data xgbe_v2b = {
170 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
171 .xpcs_access = XGBE_XPCS_ACCESS_V2,
172 .mmc_64bit = 1,
173 .tx_max_fifo_size = 65536,
174 .rx_max_fifo_size = 65536,
175 .tx_tstamp_workaround = 1,
176 .ecc_support = 1,
177 .i2c_support = 1,
178 .irq_reissue_support = 1,
179 .tx_desc_prefetch = 5,
180 .rx_desc_prefetch = 5,
181 .an_cdr_workaround = 1,
182 };
183
184 /* Device Interface */
185 static device_method_t ax_methods[] = {
186 DEVMETHOD(device_register, axgbe_register),
187 DEVMETHOD(device_probe, iflib_device_probe),
188 DEVMETHOD(device_attach, iflib_device_attach),
189 DEVMETHOD(device_detach, iflib_device_detach),
190 DEVMETHOD(device_shutdown, iflib_device_shutdown),
191 DEVMETHOD(device_suspend, iflib_device_suspend),
192 DEVMETHOD(device_resume, iflib_device_resume),
193
194 /* MII interface */
195 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
196 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
197 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
198
199 DEVMETHOD_END
200 };
201
202 static driver_t ax_driver = {
203 "ax", ax_methods, sizeof(struct axgbe_if_softc),
204 };
205
206 DRIVER_MODULE(axp, pci, ax_driver, 0, 0);
207 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0);
208 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
209
210 MODULE_DEPEND(ax, pci, 1, 1, 1);
211 MODULE_DEPEND(ax, ether, 1, 1, 1);
212 MODULE_DEPEND(ax, iflib, 1, 1, 1);
213 MODULE_DEPEND(ax, miibus, 1, 1, 1);
214
215 /* Iflib Interface */
216 static device_method_t axgbe_if_methods[] = {
217 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
218 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
219 DEVMETHOD(ifdi_detach, axgbe_if_detach),
220 DEVMETHOD(ifdi_init, axgbe_if_init),
221 DEVMETHOD(ifdi_stop, axgbe_if_stop),
222 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
223 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
224 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
225 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
226 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
227 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
228 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
229 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
230 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
231 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
232 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
233 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
234 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
235 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
236 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
237 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
238 #if __FreeBSD_version >= 1300000
239 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
240 #endif
241 DEVMETHOD_END
242 };
243
244 static driver_t axgbe_if_driver = {
245 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
246 };
247
248 /* Iflib Shared Context */
249 static struct if_shared_ctx axgbe_sctx_init = {
250 .isc_magic = IFLIB_MAGIC,
251 .isc_driver = &axgbe_if_driver,
252 .isc_q_align = PAGE_SIZE,
253 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
254 .isc_tx_maxsegsize = PAGE_SIZE,
255 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
256 .isc_tso_maxsegsize = PAGE_SIZE,
257 .isc_rx_maxsize = MJUM9BYTES,
258 .isc_rx_maxsegsize = MJUM9BYTES,
259 .isc_rx_nsegments = 1,
260 .isc_admin_intrcnt = 4,
261
262 .isc_vendor_info = axgbe_vendor_info_array,
263 .isc_driver_version = XGBE_DRV_VERSION,
264
265 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
266 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
267 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
268
269 .isc_ntxqs = 1,
270 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
271 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
272 };
273
274 static void *
axgbe_register(device_t dev)275 axgbe_register(device_t dev)
276 {
277 int axgbe_nfl;
278 int axgbe_nrxqs;
279 int error, i;
280 char *value = NULL;
281
282 value = kern_getenv("dev.ax.sph_enable");
283 if (value) {
284 axgbe_sph_enable = strtol(value, NULL, 10);
285 freeenv(value);
286 } else {
287 /*
288 * No tunable found, generate one with default values
289 * Note: only a reboot will reveal the new kenv
290 */
291 error = kern_setenv("dev.ax.sph_enable", "0");
292 if (error) {
293 printf("Error setting tunable, using default driver values\n");
294 }
295 axgbe_sph_enable = 0;
296 }
297
298 if (!axgbe_sph_enable) {
299 axgbe_nfl = 1;
300 axgbe_nrxqs = 1;
301 } else {
302 axgbe_nfl = 2;
303 axgbe_nrxqs = 2;
304 }
305
306 axgbe_sctx_init.isc_nfl = axgbe_nfl;
307 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
308
309 for (i = 0 ; i < axgbe_nrxqs ; i++) {
310 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
311 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
312 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
313 }
314
315 return (&axgbe_sctx_init);
316 }
317
318 /* MII Interface Functions */
319 static int
axgbe_miibus_readreg(device_t dev,int phy,int reg)320 axgbe_miibus_readreg(device_t dev, int phy, int reg)
321 {
322 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
323 struct xgbe_prv_data *pdata = &sc->pdata;
324 int val;
325
326 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
327
328 val = xgbe_phy_mii_read(pdata, phy, reg);
329
330 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
331 return (val & 0xFFFF);
332 }
333
334 static int
axgbe_miibus_writereg(device_t dev,int phy,int reg,int val)335 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
336 {
337 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
338 struct xgbe_prv_data *pdata = &sc->pdata;
339
340 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
341
342 xgbe_phy_mii_write(pdata, phy, reg, val);
343
344 return(0);
345 }
346
347 static void
axgbe_miibus_statchg(device_t dev)348 axgbe_miibus_statchg(device_t dev)
349 {
350 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
351 struct xgbe_prv_data *pdata = &sc->pdata;
352 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
353 if_t ifp = pdata->netdev;
354 int bmsr;
355
356 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
357 pdata->phy_link);
358
359 if (mii == NULL || ifp == NULL ||
360 !iflib_is_running(sc->ctx))
361 return;
362
363 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
364 (IFM_ACTIVE | IFM_AVALID)) {
365
366 switch (IFM_SUBTYPE(mii->mii_media_active)) {
367 case IFM_10_T:
368 case IFM_100_TX:
369 pdata->phy.link = 1;
370 break;
371 case IFM_1000_T:
372 case IFM_1000_SX:
373 case IFM_2500_SX:
374 pdata->phy.link = 1;
375 break;
376 default:
377 pdata->phy.link = 0;
378 break;
379 }
380 } else
381 pdata->phy_link = 0;
382
383 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
384 if (bmsr & BMSR_ANEG) {
385
386 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
387
388 /* Raise AN Interrupt */
389 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
390 XGBE_AN_CL73_INT_MASK);
391 }
392 }
393
394 static int
axgbe_if_attach_pre(if_ctx_t ctx)395 axgbe_if_attach_pre(if_ctx_t ctx)
396 {
397 struct axgbe_if_softc *sc;
398 struct xgbe_prv_data *pdata;
399 struct resource *mac_res[2];
400 if_softc_ctx_t scctx;
401 if_shared_ctx_t sctx;
402 device_t dev;
403 device_t rdev;
404 unsigned int ma_lo, ma_hi;
405 unsigned int reg;
406 int ret;
407
408 sc = iflib_get_softc(ctx);
409 sc->pdata.dev = dev = iflib_get_dev(ctx);
410 sc->sctx = sctx = iflib_get_sctx(ctx);
411 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
412 sc->media = iflib_get_media(ctx);
413 sc->ctx = ctx;
414 sc->link_status = LINK_STATE_DOWN;
415 pdata = &sc->pdata;
416 pdata->netdev = iflib_get_ifp(ctx);
417
418 spin_lock_init(&pdata->xpcs_lock);
419
420 /* Initialize locks */
421 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
422 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
423
424 /* Allocate VLAN bitmap */
425 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
426 pdata->num_active_vlans = 0;
427
428 /* Get the version data */
429 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
430 if (pci_get_device(dev) == 0x1458)
431 sc->pdata.vdata = &xgbe_v2a;
432 else if (pci_get_device(dev) == 0x1459)
433 sc->pdata.vdata = &xgbe_v2b;
434
435 /* PCI setup */
436 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
437 axgbe_error("Unable to allocate bus resources\n");
438 ret = ENXIO;
439 goto free_vlans;
440 }
441
442 sc->pdata.xgmac_res = mac_res[0];
443 sc->pdata.xpcs_res = mac_res[1];
444
445 /*
446 * Set the PCS indirect addressing definition registers.
447 * A newer version of the hardware is using the same PCI ids
448 * for the network device but has altered register definitions
449 * for determining the window settings for the indirect PCS access.
450 * This code checks hardware usage and uses the register values
451 * accordingly.
452 */
453 rdev = pci_find_dbsf(0, 0, 0, 0);
454 if (rdev && pci_get_device(rdev) == 0x15d0
455 && pci_get_vendor(rdev) == 0x1022) {
456 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
457 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
458 } else {
459 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
460 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
461 }
462
463 /* Configure the PCS indirect addressing support */
464 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
465 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
466 pdata->xpcs_window <<= 6;
467 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
468 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
469 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
470 DBGPR("xpcs window def : %#010x\n",
471 pdata->xpcs_window_def_reg);
472 DBGPR("xpcs window sel : %#010x\n",
473 pdata->xpcs_window_sel_reg);
474 DBGPR("xpcs window : %#010x\n",
475 pdata->xpcs_window);
476 DBGPR("xpcs window size : %#010x\n",
477 pdata->xpcs_window_size);
478 DBGPR("xpcs window mask : %#010x\n",
479 pdata->xpcs_window_mask);
480
481 /* Enable all interrupts in the hardware */
482 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
483
484 /* Retrieve the MAC address */
485 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
486 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
487 pdata->mac_addr[0] = ma_lo & 0xff;
488 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
489 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
490 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
491 pdata->mac_addr[4] = ma_hi & 0xff;
492 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
493 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
494 axgbe_error("Invalid mac address\n");
495 ret = EINVAL;
496 goto release_bus_resource;
497 }
498 iflib_set_mac(ctx, pdata->mac_addr);
499
500 /* Clock settings */
501 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
502 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
503
504 /* Set the DMA coherency values */
505 pdata->coherent = 1;
506 pdata->arcr = XGBE_DMA_PCI_ARCR;
507 pdata->awcr = XGBE_DMA_PCI_AWCR;
508 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
509
510 /* Read the port property registers */
511 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
512 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
513 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
514 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
515 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
516 DBGPR("port property 0 = %#010x\n", pdata->pp0);
517 DBGPR("port property 1 = %#010x\n", pdata->pp1);
518 DBGPR("port property 2 = %#010x\n", pdata->pp2);
519 DBGPR("port property 3 = %#010x\n", pdata->pp3);
520 DBGPR("port property 4 = %#010x\n", pdata->pp4);
521
522 /* Set the maximum channels and queues */
523 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
524 MAX_TX_DMA);
525 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
526 MAX_RX_DMA);
527 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
528 MAX_TX_QUEUES);
529 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
530 MAX_RX_QUEUES);
531 DBGPR("max tx/rx channel count = %u/%u\n",
532 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
533 DBGPR("max tx/rx hw queue count = %u/%u\n",
534 pdata->tx_max_q_count, pdata->rx_max_q_count);
535
536 axgbe_set_counts(ctx);
537
538 /* Set the maximum fifo amounts */
539 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
540 TX_FIFO_SIZE);
541 pdata->tx_max_fifo_size *= 16384;
542 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
543 pdata->vdata->tx_max_fifo_size);
544 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
545 RX_FIFO_SIZE);
546 pdata->rx_max_fifo_size *= 16384;
547 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
548 pdata->vdata->rx_max_fifo_size);
549 DBGPR("max tx/rx max fifo size = %u/%u\n",
550 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
551
552 /* Initialize IFLIB if_softc_ctx_t */
553 axgbe_init_iflib_softc_ctx(sc);
554
555 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
556
557 /* create the workqueue */
558 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
559 taskqueue_thread_enqueue, &pdata->dev_workqueue);
560 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
561 "axgbe dev taskq");
562 if (ret) {
563 axgbe_error("Unable to start taskqueue\n");
564 ret = ENOMEM;
565 goto free_task_queue;
566 }
567
568 /* Init timers */
569 xgbe_init_timers(pdata);
570
571 return (0);
572
573 free_task_queue:
574 taskqueue_free(pdata->dev_workqueue);
575
576 release_bus_resource:
577 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
578
579 free_vlans:
580 free(pdata->active_vlans, M_AXGBE);
581 pdata->active_vlans = NULL;
582 mtx_destroy(&pdata->xpcs_lock);
583 mtx_destroy(&pdata->rss_mutex);
584 mtx_destroy(&pdata->mdio_mutex);
585
586 return (ret);
587 } /* axgbe_if_attach_pre */
588
589 static void
xgbe_init_all_fptrs(struct xgbe_prv_data * pdata)590 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
591 {
592 xgbe_init_function_ptrs_dev(&pdata->hw_if);
593 xgbe_init_function_ptrs_phy(&pdata->phy_if);
594 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
595 xgbe_init_function_ptrs_desc(&pdata->desc_if);
596
597 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
598 }
599
600 static void
axgbe_set_counts(if_ctx_t ctx)601 axgbe_set_counts(if_ctx_t ctx)
602 {
603 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
604 struct xgbe_prv_data *pdata = &sc->pdata;
605 cpuset_t lcpus;
606
607 /* Set all function pointers */
608 xgbe_init_all_fptrs(pdata);
609
610 /* Populate the hardware features */
611 xgbe_get_all_hw_features(pdata);
612
613 if (!pdata->tx_max_channel_count)
614 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
615 if (!pdata->rx_max_channel_count)
616 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
617
618 if (!pdata->tx_max_q_count)
619 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
620 if (!pdata->rx_max_q_count)
621 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
622
623 /*
624 * Calculate the number of Tx and Rx rings to be created
625 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
626 * the number of Tx queues to the number of Tx channels
627 * enabled
628 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
629 * number of Rx queues or maximum allowed
630 */
631
632 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
633 axgbe_error("Unable to fetch CPU list\n");
634 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
635 }
636
637 DBGPR("ncpu %d intrcpu %d\n", mp_ncpus, CPU_COUNT(&lcpus));
638
639 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
640 pdata->tx_ring_count = min(pdata->tx_ring_count,
641 pdata->tx_max_channel_count);
642 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
643
644 pdata->tx_q_count = pdata->tx_ring_count;
645
646 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
647 pdata->rx_ring_count = min(pdata->rx_ring_count,
648 pdata->rx_max_channel_count);
649
650 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
651
652 DBGPR("TX/RX max channel count = %u/%u\n",
653 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
654 DBGPR("TX/RX max queue count = %u/%u\n",
655 pdata->tx_max_q_count, pdata->rx_max_q_count);
656 DBGPR("TX/RX DMA ring count = %u/%u\n",
657 pdata->tx_ring_count, pdata->rx_ring_count);
658 DBGPR("TX/RX hardware queue count = %u/%u\n",
659 pdata->tx_q_count, pdata->rx_q_count);
660 } /* axgbe_set_counts */
661
662 static void
axgbe_init_iflib_softc_ctx(struct axgbe_if_softc * sc)663 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
664 {
665 struct xgbe_prv_data *pdata = &sc->pdata;
666 if_softc_ctx_t scctx = sc->scctx;
667 if_shared_ctx_t sctx = sc->sctx;
668 int i;
669
670 scctx->isc_nrxqsets = pdata->rx_q_count;
671 scctx->isc_ntxqsets = pdata->tx_q_count;
672 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
673 scctx->isc_tx_nsegments = 32;
674
675 for (i = 0; i < sctx->isc_ntxqs; i++) {
676 scctx->isc_txqsizes[i] =
677 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
678 128);
679 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
680 }
681
682 for (i = 0; i < sctx->isc_nrxqs; i++) {
683 scctx->isc_rxqsizes[i] =
684 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
685 128);
686 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
687 }
688
689 scctx->isc_tx_tso_segments_max = 32;
690 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
691 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
692
693 /*
694 * Set capabilities
695 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
696 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
697 * IFCAP_HWCSUM) is set
698 */
699 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
700 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
701 CSUM_TSO);
702 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
703 IFCAP_JUMBO_MTU |
704 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
705 IFCAP_VLAN_HWCSUM |
706 IFCAP_TSO | IFCAP_VLAN_HWTSO);
707 scctx->isc_capabilities = scctx->isc_capenable;
708
709 /*
710 * Set rss_table_size alone when adding RSS support. rss_table_mask
711 * will be set by IFLIB based on rss_table_size
712 */
713 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
714
715 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
716 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
717
718 scctx->isc_txrx = &axgbe_txrx;
719 }
720
721 static void
axgbe_initialize_rss_mapping(struct xgbe_prv_data * pdata)722 axgbe_initialize_rss_mapping(struct xgbe_prv_data *pdata)
723 {
724 int i;
725
726 #ifdef RSS
727 int qid;
728 uint32_t rss_hash_config = 0;
729 #endif
730
731 /* Get RSS key independently of software RSS queue placement. */
732 _Static_assert(sizeof(pdata->rss_key) == RSS_KEYSIZE,
733 "RSS key size mismatch");
734 rss_getkey((uint8_t *)&pdata->rss_key);
735
736 #ifdef RSS
737 rss_hash_config = rss_gethashconfig();
738
739 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
740 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
741 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
742 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
743 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
744 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
745 #else
746 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
747 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
748 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
749 #endif
750
751 /* Setup RSS lookup table */
752 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) {
753 #ifdef RSS
754 qid = rss_get_indirection_to_bucket(i) % pdata->rx_ring_count;
755 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
756 #else
757 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
758 i % pdata->rx_ring_count);
759 #endif
760 }
761
762 }
763
764 static int
axgbe_alloc_channels(if_ctx_t ctx)765 axgbe_alloc_channels(if_ctx_t ctx)
766 {
767 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
768 struct xgbe_prv_data *pdata = &sc->pdata;
769 struct xgbe_channel *channel;
770 int i, j, count;
771
772 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
773 pdata->rx_ring_count);
774
775 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
776 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
777
778 /* Allocate channel memory */
779 for (i = 0; i < count ; i++) {
780 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
781 M_AXGBE, M_NOWAIT | M_ZERO);
782
783 if (channel == NULL) {
784 for (j = 0; j < i; j++) {
785 free(pdata->channel[j], M_AXGBE);
786 pdata->channel[j] = NULL;
787 }
788 return (ENOMEM);
789 }
790
791 pdata->channel[i] = channel;
792 }
793
794 pdata->total_channel_count = count;
795 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
796
797 for (i = 0; i < count; i++) {
798
799 channel = pdata->channel[i];
800 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
801
802 channel->pdata = pdata;
803 channel->queue_index = i;
804 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
805 bus_space_subregion(channel->dma_tag,
806 rman_get_bushandle(pdata->xgmac_res),
807 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
808 &channel->dma_handle);
809 channel->tx_ring = NULL;
810 channel->rx_ring = NULL;
811 }
812
813 return (0);
814 } /* axgbe_alloc_channels */
815
816 static void
axgbe_free_channels(struct axgbe_if_softc * sc)817 axgbe_free_channels(struct axgbe_if_softc *sc)
818 {
819 struct xgbe_prv_data *pdata = &sc->pdata;
820 int i;
821
822 for (i = 0; i < pdata->total_channel_count ; i++) {
823 free(pdata->channel[i], M_AXGBE);
824 pdata->channel[i] = NULL;
825 }
826
827 pdata->total_channel_count = 0;
828 pdata->channel_count = 0;
829 }
830
831 static void
xgbe_service(void * ctx,int pending)832 xgbe_service(void *ctx, int pending)
833 {
834 struct xgbe_prv_data *pdata = ctx;
835 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
836 bool prev_state = false;
837
838 /* Get previous link status */
839 prev_state = pdata->phy.link;
840
841 pdata->phy_if.phy_status(pdata);
842
843 if (prev_state != pdata->phy.link) {
844 pdata->phy_link = pdata->phy.link;
845 axgbe_if_update_admin_status(sc->ctx);
846 }
847
848 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
849 }
850
851 static void
xgbe_service_timer(void * data)852 xgbe_service_timer(void *data)
853 {
854 struct xgbe_prv_data *pdata = data;
855
856 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
857 }
858
859 static void
xgbe_init_timers(struct xgbe_prv_data * pdata)860 xgbe_init_timers(struct xgbe_prv_data *pdata)
861 {
862 callout_init(&pdata->service_timer, 1);
863 }
864
865 static void
xgbe_start_timers(struct xgbe_prv_data * pdata)866 xgbe_start_timers(struct xgbe_prv_data *pdata)
867 {
868 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
869 }
870
871 static void
xgbe_stop_timers(struct xgbe_prv_data * pdata)872 xgbe_stop_timers(struct xgbe_prv_data *pdata)
873 {
874 callout_drain(&pdata->service_timer);
875 callout_stop(&pdata->service_timer);
876 }
877
878 static void
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)879 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
880 {
881 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
882
883 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
884 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
885 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
886 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
887 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
888 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
889 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
890 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
891 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
892 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
893 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
894 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
895 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
896 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
897 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
898 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
899 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
900 MDIO_AN_ADVERTISE,
901 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
902 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
903 MDIO_AN_ADVERTISE + 1,
904 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
905 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
906 MDIO_AN_ADVERTISE + 2,
907 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
908 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
909 MDIO_AN_COMP_STAT,
910 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
911
912 axgbe_printf(1, "\n************************************************\n");
913 }
914
915 static void
xgbe_dump_prop_registers(struct xgbe_prv_data * pdata)916 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
917 {
918 int i;
919
920 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
921
922 for (i = 0 ; i < 38 ; i++) {
923 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
924 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
925 (XP_PROP_0 + (i * 4))));
926 }
927 }
928
929 static void
xgbe_dump_dma_registers(struct xgbe_prv_data * pdata,int ch)930 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
931 {
932 struct xgbe_channel *channel;
933 int i;
934
935 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
936
937 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
938 XGMAC_IOREAD(pdata, DMA_MR));
939 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
940 XGMAC_IOREAD(pdata, DMA_SBMR));
941 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
942 XGMAC_IOREAD(pdata, DMA_ISR));
943 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
944 XGMAC_IOREAD(pdata, DMA_AXIARCR));
945 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
946 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
947 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
948 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
949 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
950 XGMAC_IOREAD(pdata, DMA_DSR0));
951 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
952 XGMAC_IOREAD(pdata, DMA_DSR1));
953 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
954 XGMAC_IOREAD(pdata, DMA_DSR2));
955 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
956 XGMAC_IOREAD(pdata, DMA_DSR3));
957 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
958 XGMAC_IOREAD(pdata, DMA_DSR4));
959 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
960 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
961 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
962 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
963
964 for (i = 0 ; i < 8 ; i++ ) {
965
966 if (ch >= 0) {
967 if (i != ch)
968 continue;
969 }
970
971 channel = pdata->channel[i];
972
973 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
974
975 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
976 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
977 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
978 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
979 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
980 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
981 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
982 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
983 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
984 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
985 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
986 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
987 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
988 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
989 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
990 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
991 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
992 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
993 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
994 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
995 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
996 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
997 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
998 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
999 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
1000 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
1001 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
1002 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
1003 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
1004 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
1005 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
1006 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
1007 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
1008 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
1009 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
1010 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
1011 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
1012 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
1013 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
1014 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
1015 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
1016 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
1017 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
1018 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
1019 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
1020 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
1021 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
1022 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
1023 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
1024 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
1025 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
1026 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
1027 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
1028 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
1029 }
1030 }
1031
1032 static void
xgbe_dump_mtl_registers(struct xgbe_prv_data * pdata)1033 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
1034 {
1035 int i;
1036
1037 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
1038
1039 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
1040 XGMAC_IOREAD(pdata, MTL_OMR));
1041 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
1042 XGMAC_IOREAD(pdata, MTL_FDCR));
1043 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
1044 XGMAC_IOREAD(pdata, MTL_FDSR));
1045 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
1046 XGMAC_IOREAD(pdata, MTL_FDDR));
1047 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
1048 XGMAC_IOREAD(pdata, MTL_ISR));
1049 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
1050 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
1051 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
1052 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1053 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
1054 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1055 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
1056 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1057 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
1058 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1059
1060 for (i = 0 ; i < 8 ; i++ ) {
1061
1062 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1063
1064 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1065 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1066 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1067 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1068 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1069 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1070 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1071 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1072 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1073 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1074 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1075 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1076
1077 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1078 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1079 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1080 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1081 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1082 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1083 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1084 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1085 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1086 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1087 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1088 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1089 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1090 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1091 }
1092 }
1093
1094 static void
xgbe_dump_mac_registers(struct xgbe_prv_data * pdata)1095 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1096 {
1097 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1098
1099 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1100 XGMAC_IOREAD(pdata, MAC_TCR));
1101 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1102 XGMAC_IOREAD(pdata, MAC_RCR));
1103 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1104 XGMAC_IOREAD(pdata, MAC_PFR));
1105 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1106 XGMAC_IOREAD(pdata, MAC_WTR));
1107 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1108 XGMAC_IOREAD(pdata, MAC_HTR0));
1109 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1110 XGMAC_IOREAD(pdata, MAC_HTR1));
1111 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1112 XGMAC_IOREAD(pdata, MAC_HTR2));
1113 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1114 XGMAC_IOREAD(pdata, MAC_HTR3));
1115 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1116 XGMAC_IOREAD(pdata, MAC_HTR4));
1117 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1118 XGMAC_IOREAD(pdata, MAC_HTR5));
1119 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1120 XGMAC_IOREAD(pdata, MAC_HTR6));
1121 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1122 XGMAC_IOREAD(pdata, MAC_HTR7));
1123 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1124 XGMAC_IOREAD(pdata, MAC_VLANTR));
1125 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1126 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1127 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1128 XGMAC_IOREAD(pdata, MAC_VLANIR));
1129 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1130 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1131 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1132 XGMAC_IOREAD(pdata, MAC_RETMR));
1133 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1134 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1135 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1136 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1137 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1138 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1139 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1140 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1141 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1142 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1143 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1144 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1145 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1146 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1147 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1148 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1149 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1150 XGMAC_IOREAD(pdata, MAC_RFCR));
1151 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1152 XGMAC_IOREAD(pdata, MAC_RQC0R));
1153 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1154 XGMAC_IOREAD(pdata, MAC_RQC1R));
1155 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1156 XGMAC_IOREAD(pdata, MAC_RQC2R));
1157 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1158 XGMAC_IOREAD(pdata, MAC_RQC3R));
1159 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1160 XGMAC_IOREAD(pdata, MAC_ISR));
1161 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1162 XGMAC_IOREAD(pdata, MAC_IER));
1163 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1164 XGMAC_IOREAD(pdata, MAC_RTSR));
1165 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1166 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1167 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1168 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1169 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1170 XGMAC_IOREAD(pdata, MAC_LPICSR));
1171 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1172 XGMAC_IOREAD(pdata, MAC_LPITCR));
1173 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1174 XGMAC_IOREAD(pdata, MAC_TIR));
1175 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1176 XGMAC_IOREAD(pdata, MAC_VR));
1177 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1178 XGMAC_IOREAD(pdata, MAC_DR));
1179 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1180 XGMAC_IOREAD(pdata, MAC_HWF0R));
1181 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1182 XGMAC_IOREAD(pdata, MAC_HWF1R));
1183 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1184 XGMAC_IOREAD(pdata, MAC_HWF2R));
1185 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1186 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1187 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1188 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1189 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1190 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1191 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1192 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1193 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1194 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1195 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1196 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1197 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1198 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1199 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1200 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1201 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1202 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1203 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1204 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1205 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1206 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1207 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1208 XGMAC_IOREAD(pdata, MAC_RSSCR));
1209 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1210 XGMAC_IOREAD(pdata, MAC_RSSDR));
1211 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1212 XGMAC_IOREAD(pdata, MAC_RSSAR));
1213 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1214 XGMAC_IOREAD(pdata, MAC_TSCR));
1215 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1216 XGMAC_IOREAD(pdata, MAC_SSIR));
1217 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1218 XGMAC_IOREAD(pdata, MAC_STSR));
1219 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1220 XGMAC_IOREAD(pdata, MAC_STNR));
1221 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1222 XGMAC_IOREAD(pdata, MAC_STSUR));
1223 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1224 XGMAC_IOREAD(pdata, MAC_STNUR));
1225 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1226 XGMAC_IOREAD(pdata, MAC_TSAR));
1227 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1228 XGMAC_IOREAD(pdata, MAC_TSSR));
1229 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1230 XGMAC_IOREAD(pdata, MAC_TXSNR));
1231 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1232 XGMAC_IOREAD(pdata, MAC_TXSSR));
1233 }
1234
1235 static void
xgbe_dump_rmon_counters(struct xgbe_prv_data * pdata)1236 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1237 {
1238 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1239
1240 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1241
1242 pdata->hw_if.read_mmc_stats(pdata);
1243
1244 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1245 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1246 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1247 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1248 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1249 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1250 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1251 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1252 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1253 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1254 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1255 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1256 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1257 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1258 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1259 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1260 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1261 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1262 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1263 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1264 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1265 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1266 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1267 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1268 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1269 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1270 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1271 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1272 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1273 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1274 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1275 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1276 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1277 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1278 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1279 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1280 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1281 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1282 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1283 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1284 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1285 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1286 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1287 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1288 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1289 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1290 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1291 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1292 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1293 MMC_RXRUNTERROR, stats->rxrunterror);
1294 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1295 MMC_RXJABBERERROR, stats->rxjabbererror);
1296 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1297 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1298 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1299 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1300 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1301 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1302 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1303 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1304 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1305 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1306 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1307 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1308 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1309 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1310 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1311 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1312 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1313 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1314 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1315 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1316 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1317 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1318 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1319 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1320 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1321 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1322 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1323 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1324 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1325 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1326 }
1327
1328 void
xgbe_dump_i2c_registers(struct xgbe_prv_data * pdata)1329 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1330 {
1331 axgbe_printf(1, "*************** I2C Registers **************\n");
1332 axgbe_printf(1, " IC_CON : %010x\n",
1333 XI2C_IOREAD(pdata, 0x00));
1334 axgbe_printf(1, " IC_TAR : %010x\n",
1335 XI2C_IOREAD(pdata, 0x04));
1336 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1337 XI2C_IOREAD(pdata, 0x0c));
1338 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1339 XI2C_IOREAD(pdata, 0x2c));
1340 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1341 XI2C_IOREAD(pdata, 0x30));
1342 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1343 XI2C_IOREAD(pdata, 0x34));
1344 axgbe_printf(1, " IC_RX_TL : %010x\n",
1345 XI2C_IOREAD(pdata, 0x38));
1346 axgbe_printf(1, " IC_TX_TL : %010x\n",
1347 XI2C_IOREAD(pdata, 0x3c));
1348 axgbe_printf(1, " IC_ENABLE : %010x\n",
1349 XI2C_IOREAD(pdata, 0x6c));
1350 axgbe_printf(1, " IC_STATUS : %010x\n",
1351 XI2C_IOREAD(pdata, 0x70));
1352 axgbe_printf(1, " IC_TXFLR : %010x\n",
1353 XI2C_IOREAD(pdata, 0x74));
1354 axgbe_printf(1, " IC_RXFLR : %010x\n",
1355 XI2C_IOREAD(pdata, 0x78));
1356 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1357 XI2C_IOREAD(pdata, 0x9c));
1358 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1359 XI2C_IOREAD(pdata, 0xf4));
1360 }
1361
1362 static void
xgbe_dump_active_vlans(struct xgbe_prv_data * pdata)1363 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1364 {
1365 int i;
1366
1367 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1368 if (i && (i%8 == 0))
1369 axgbe_printf(1, "\n");
1370 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1371 }
1372 axgbe_printf(1, "\n");
1373 }
1374
1375 static void
xgbe_default_config(struct xgbe_prv_data * pdata)1376 xgbe_default_config(struct xgbe_prv_data *pdata)
1377 {
1378 pdata->blen = DMA_SBMR_BLEN_64;
1379 pdata->pbl = DMA_PBL_128;
1380 pdata->aal = 1;
1381 pdata->rd_osr_limit = 8;
1382 pdata->wr_osr_limit = 8;
1383 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1384 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1385 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1386 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1387 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1388 pdata->pause_autoneg = 1;
1389 pdata->phy_speed = SPEED_UNKNOWN;
1390 pdata->power_down = 0;
1391 pdata->enable_rss = 1;
1392 }
1393
1394 static int
axgbe_if_attach_post(if_ctx_t ctx)1395 axgbe_if_attach_post(if_ctx_t ctx)
1396 {
1397 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1398 struct xgbe_prv_data *pdata = &sc->pdata;
1399 if_t ifp = pdata->netdev;
1400 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1401 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1402 if_softc_ctx_t scctx = sc->scctx;
1403 int ret;
1404
1405 /* set split header support based on tunable */
1406 pdata->sph_enable = axgbe_sph_enable;
1407
1408 /* Initialize ECC timestamps */
1409 pdata->tx_sec_period = ticks;
1410 pdata->tx_ded_period = ticks;
1411 pdata->rx_sec_period = ticks;
1412 pdata->rx_ded_period = ticks;
1413 pdata->desc_sec_period = ticks;
1414 pdata->desc_ded_period = ticks;
1415
1416 /* Reset the hardware */
1417 ret = hw_if->exit(&sc->pdata);
1418 if (ret)
1419 axgbe_error("%s: exit error %d\n", __func__, ret);
1420
1421 axgbe_sysctl_init(pdata);
1422
1423 /* Configure the defaults */
1424 xgbe_default_config(pdata);
1425
1426 /* Set default max values if not provided */
1427 if (!pdata->tx_max_fifo_size)
1428 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1429 if (!pdata->rx_max_fifo_size)
1430 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1431
1432 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1433 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1434
1435 /* Set and validate the number of descriptors for a ring */
1436 MPASS(powerof2(XGBE_TX_DESC_CNT));
1437 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1438 MPASS(powerof2(XGBE_RX_DESC_CNT));
1439 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1440
1441 /* Adjust the number of queues based on interrupts assigned */
1442 if (pdata->channel_irq_count) {
1443 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1444 pdata->channel_irq_count);
1445 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1446 pdata->channel_irq_count);
1447
1448 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1449 pdata->tx_ring_count, pdata->tx_q_count,
1450 pdata->rx_ring_count, pdata->rx_q_count);
1451 }
1452
1453 /* Set channel count based on interrupts assigned */
1454 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1455 scctx->isc_nrxqsets);
1456 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1457
1458 axgbe_initialize_rss_mapping(pdata);
1459
1460 /* Initialize the PHY device */
1461 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1462 phy_if->phy_init(pdata);
1463
1464 /* Set the coalescing */
1465 xgbe_init_rx_coalesce(&sc->pdata);
1466 xgbe_init_tx_coalesce(&sc->pdata);
1467
1468 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1469 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1470 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1471 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1472 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1473 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1474 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1475 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1476 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1477 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1478 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1479 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1480 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1481
1482 /* Initialize the phy */
1483 pdata->phy_link = -1;
1484 pdata->phy_speed = SPEED_UNKNOWN;
1485 ret = phy_if->phy_reset(pdata);
1486 if (ret)
1487 return (ret);
1488
1489 /* Calculate the Rx buffer size before allocating rings */
1490 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1491 pdata->rx_buf_size = ret;
1492 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1493
1494 /*
1495 * Mark the device down until it is initialized, which happens
1496 * when the device is accessed first (for configuring the iface,
1497 * eg: setting IP)
1498 */
1499 set_bit(XGBE_DOWN, &pdata->dev_state);
1500
1501 DBGPR("mtu %d\n", if_getmtu(ifp));
1502 scctx->isc_max_frame_size = if_getmtu(ifp) + 18;
1503 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1504
1505 ret = axgbe_pci_init(pdata);
1506 return (ret < 0 ? -ret : ret);
1507 } /* axgbe_if_attach_post */
1508
1509 static void
xgbe_free_intr(struct xgbe_prv_data * pdata,struct resource * res,void * tag,int rid)1510 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1511 int rid)
1512 {
1513 if (tag)
1514 bus_teardown_intr(pdata->dev, res, tag);
1515
1516 if (res)
1517 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1518 }
1519
1520 static void
axgbe_interrupts_free(if_ctx_t ctx)1521 axgbe_interrupts_free(if_ctx_t ctx)
1522 {
1523 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1524 struct xgbe_prv_data *pdata = &sc->pdata;
1525 if_softc_ctx_t scctx = sc->scctx;
1526 struct xgbe_channel *channel;
1527 struct if_irq irq;
1528 int i;
1529
1530 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1531
1532 /* Free dev_irq */
1533 iflib_irq_free(ctx, &pdata->dev_irq);
1534
1535 /* Free ecc_irq */
1536 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1537 pdata->ecc_rid);
1538
1539 /* Free i2c_irq */
1540 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1541 pdata->i2c_rid);
1542
1543 /* Free an_irq */
1544 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1545 pdata->an_rid);
1546
1547 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1548
1549 channel = pdata->channel[i];
1550 if (channel == NULL)
1551 continue;
1552 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1553 irq.ii_res = channel->dma_irq_res;
1554 irq.ii_tag = channel->dma_irq_tag;
1555 iflib_irq_free(ctx, &irq);
1556 }
1557 }
1558
1559 static int
axgbe_if_detach(if_ctx_t ctx)1560 axgbe_if_detach(if_ctx_t ctx)
1561 {
1562 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1563 struct xgbe_prv_data *pdata = &sc->pdata;
1564 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1565 struct resource *mac_res[2];
1566
1567 mac_res[0] = pdata->xgmac_res;
1568 mac_res[1] = pdata->xpcs_res;
1569
1570 if (pdata->phy_data != NULL) {
1571 phy_if->phy_stop(pdata);
1572 phy_if->phy_exit(pdata);
1573 pdata->phy_data = NULL;
1574 }
1575
1576 /* Free Interrupts */
1577 axgbe_interrupts_free(ctx);
1578
1579 /* Free workqueues */
1580 taskqueue_free(pdata->dev_workqueue);
1581 pdata->dev_workqueue = NULL;
1582
1583 /* Release bus resources */
1584 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1585
1586 /* Free VLAN bitmap */
1587 free(pdata->active_vlans, M_AXGBE);
1588 pdata->active_vlans = NULL;
1589
1590 axgbe_sysctl_exit(pdata);
1591 pdata->sys_op = NULL;
1592 mtx_destroy(&pdata->xpcs_lock);
1593 mtx_destroy(&pdata->rss_mutex);
1594 mtx_destroy(&pdata->mdio_mutex);
1595
1596 return (0);
1597 } /* axgbe_if_detach */
1598
1599 static int
axgbe_pci_init(struct xgbe_prv_data * pdata)1600 axgbe_pci_init(struct xgbe_prv_data *pdata)
1601 {
1602 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1603 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1604 int ret, reset_ret;
1605
1606 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1607 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1608 return (0);
1609 }
1610
1611 ret = hw_if->init(pdata);
1612 if (ret != 0) {
1613 axgbe_error("%s: hardware init error %d\n", __func__, ret);
1614 goto fail;
1615 }
1616
1617 ret = phy_if->phy_start(pdata);
1618 if (ret != 0) {
1619 axgbe_error("%s: phy start error %d\n", __func__, ret);
1620 goto fail;
1621 }
1622
1623 hw_if->enable_tx(pdata);
1624 hw_if->enable_rx(pdata);
1625
1626 xgbe_start_timers(pdata);
1627
1628 clear_bit(XGBE_DOWN, &pdata->dev_state);
1629
1630 xgbe_dump_phy_registers(pdata);
1631 xgbe_dump_prop_registers(pdata);
1632 xgbe_dump_dma_registers(pdata, -1);
1633 xgbe_dump_mtl_registers(pdata);
1634 xgbe_dump_mac_registers(pdata);
1635 xgbe_dump_rmon_counters(pdata);
1636 return (0);
1637
1638 fail:
1639 reset_ret = hw_if->exit(pdata);
1640 if (reset_ret != 0)
1641 axgbe_error("%s: cleanup reset error %d\n", __func__, reset_ret);
1642 return (ret);
1643 }
1644
1645 static void
axgbe_if_init(if_ctx_t ctx)1646 axgbe_if_init(if_ctx_t ctx)
1647 {
1648 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1649 struct xgbe_prv_data *pdata = &sc->pdata;
1650
1651 if (axgbe_pci_init(pdata) != 0)
1652 iflib_init_failed(ctx);
1653 }
1654
1655 static void
axgbe_pci_stop(if_ctx_t ctx)1656 axgbe_pci_stop(if_ctx_t ctx)
1657 {
1658 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1659 struct xgbe_prv_data *pdata = &sc->pdata;
1660 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1661 int ret;
1662
1663 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1664 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1665 return;
1666 }
1667
1668 xgbe_stop_timers(pdata);
1669 taskqueue_drain_all(pdata->dev_workqueue);
1670
1671 hw_if->disable_tx(pdata);
1672 hw_if->disable_rx(pdata);
1673
1674 ret = hw_if->exit(pdata);
1675 if (ret)
1676 axgbe_error("%s: exit error %d\n", __func__, ret);
1677
1678 set_bit(XGBE_DOWN, &pdata->dev_state);
1679 }
1680
1681 static void
axgbe_if_stop(if_ctx_t ctx)1682 axgbe_if_stop(if_ctx_t ctx)
1683 {
1684 axgbe_pci_stop(ctx);
1685 }
1686
1687 static void
axgbe_if_disable_intr(if_ctx_t ctx)1688 axgbe_if_disable_intr(if_ctx_t ctx)
1689 {
1690 /* TODO - implement */
1691 }
1692
1693 static void
axgbe_if_enable_intr(if_ctx_t ctx)1694 axgbe_if_enable_intr(if_ctx_t ctx)
1695 {
1696 /* TODO - implement */
1697 }
1698
1699 static int
axgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int ntxqs,int ntxqsets)1700 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1701 int ntxqsets)
1702 {
1703 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1704 struct xgbe_prv_data *pdata = &sc->pdata;
1705 if_softc_ctx_t scctx = sc->scctx;
1706 struct xgbe_channel *channel;
1707 struct xgbe_ring *tx_ring;
1708 int i, j;
1709
1710 MPASS(scctx->isc_ntxqsets > 0);
1711 MPASS(scctx->isc_ntxqsets == ntxqsets);
1712 MPASS(ntxqs == 1);
1713
1714 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1715 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1716 if (axgbe_alloc_channels(ctx) != 0) {
1717 axgbe_error("Unable to allocate channel memory\n");
1718 return (ENOMEM);
1719 }
1720
1721 for (i = 0 ; i < ntxqsets; i++) {
1722
1723 channel = pdata->channel[i];
1724
1725 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1726 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1727
1728 if (tx_ring == NULL) {
1729 axgbe_error("Unable to allocate TX ring memory\n");
1730 goto tx_ring_fail;
1731 }
1732
1733 channel->tx_ring = tx_ring;
1734
1735 for (j = 0; j < ntxqs; j++, tx_ring++) {
1736 tx_ring->rdata =
1737 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1738 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1739 if (tx_ring->rdata == NULL) {
1740 axgbe_error("Unable to allocate TX ring data\n");
1741 goto tx_ring_fail;
1742 }
1743
1744 /* Get the virtual & physical address of hw queues */
1745 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1746 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1747 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1748 spin_lock_init(&tx_ring->lock);
1749 }
1750 }
1751
1752 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1753
1754 return (0);
1755
1756 tx_ring_fail:
1757 axgbe_if_queues_free(ctx);
1758 return (ENOMEM);
1759
1760 } /* axgbe_if_tx_queues_alloc */
1761
1762 static int
axgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int nrxqs,int nrxqsets)1763 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1764 int nrxqsets)
1765 {
1766 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1767 struct xgbe_prv_data *pdata = &sc->pdata;
1768 if_softc_ctx_t scctx = sc->scctx;
1769 struct xgbe_channel *channel;
1770 struct xgbe_ring *rx_ring;
1771 int i, j;
1772
1773 MPASS(scctx->isc_nrxqsets > 0);
1774 MPASS(scctx->isc_nrxqsets == nrxqsets);
1775 if (!pdata->sph_enable) {
1776 MPASS(nrxqs == 1);
1777 } else {
1778 MPASS(nrxqs == 2);
1779 }
1780
1781 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1782 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1783
1784 for (i = 0 ; i < nrxqsets; i++) {
1785
1786 channel = pdata->channel[i];
1787
1788 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1789 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1790
1791 if (rx_ring == NULL) {
1792 axgbe_error("Unable to allocate RX ring memory\n");
1793 goto rx_ring_fail;
1794 }
1795
1796 channel->rx_ring = rx_ring;
1797
1798 for (j = 0; j < nrxqs; j++, rx_ring++) {
1799 rx_ring->rdata =
1800 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1801 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1802 if (rx_ring->rdata == NULL) {
1803 axgbe_error("Unable to allocate RX ring data\n");
1804 goto rx_ring_fail;
1805 }
1806
1807 /* Get the virtual and physical address of the hw queues */
1808 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1809 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1810 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1811 spin_lock_init(&rx_ring->lock);
1812 }
1813 }
1814
1815 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1816
1817 return (0);
1818
1819 rx_ring_fail:
1820 axgbe_if_queues_free(ctx);
1821 return (ENOMEM);
1822
1823 } /* axgbe_if_rx_queues_alloc */
1824
1825 static void
axgbe_if_queues_free(if_ctx_t ctx)1826 axgbe_if_queues_free(if_ctx_t ctx)
1827 {
1828 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1829 struct xgbe_prv_data *pdata = &sc->pdata;
1830 if_softc_ctx_t scctx = sc->scctx;
1831 if_shared_ctx_t sctx = sc->sctx;
1832 struct xgbe_channel *channel;
1833 struct xgbe_ring *tx_ring;
1834 struct xgbe_ring *rx_ring;
1835 int i, j;
1836
1837 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1838
1839 channel = pdata->channel[i];
1840 if (channel == NULL || channel->tx_ring == NULL)
1841 continue;
1842
1843 tx_ring = channel->tx_ring;
1844 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1845 if (tx_ring && tx_ring->rdata)
1846 free(tx_ring->rdata, M_AXGBE);
1847 }
1848 free(channel->tx_ring, M_AXGBE);
1849 channel->tx_ring = NULL;
1850 }
1851
1852 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1853
1854 channel = pdata->channel[i];
1855 if (channel == NULL || channel->rx_ring == NULL)
1856 continue;
1857
1858 rx_ring = channel->rx_ring;
1859 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1860 if (rx_ring && rx_ring->rdata)
1861 free(rx_ring->rdata, M_AXGBE);
1862 }
1863 free(channel->rx_ring, M_AXGBE);
1864 channel->rx_ring = NULL;
1865 }
1866
1867 axgbe_free_channels(sc);
1868 } /* axgbe_if_queues_free */
1869
1870 static void
axgbe_if_vlan_register(if_ctx_t ctx,uint16_t vtag)1871 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1872 {
1873 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1874 struct xgbe_prv_data *pdata = &sc->pdata;
1875 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1876
1877 if (!bit_test(pdata->active_vlans, vtag)) {
1878 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1879
1880 bit_set(pdata->active_vlans, vtag);
1881 hw_if->update_vlan_hash_table(pdata);
1882 pdata->num_active_vlans++;
1883
1884 axgbe_printf(1, "Total active vlans: %d\n",
1885 pdata->num_active_vlans);
1886 } else
1887 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1888
1889 xgbe_dump_active_vlans(pdata);
1890 }
1891
1892 static void
axgbe_if_vlan_unregister(if_ctx_t ctx,uint16_t vtag)1893 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1894 {
1895 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1896 struct xgbe_prv_data *pdata = &sc->pdata;
1897 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1898
1899 if (pdata->num_active_vlans == 0) {
1900 axgbe_printf(1, "No active VLANs to unregister\n");
1901 return;
1902 }
1903
1904 if (bit_test(pdata->active_vlans, vtag)){
1905 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1906
1907 bit_clear(pdata->active_vlans, vtag);
1908 hw_if->update_vlan_hash_table(pdata);
1909 pdata->num_active_vlans--;
1910
1911 axgbe_printf(1, "Total active vlans: %d\n",
1912 pdata->num_active_vlans);
1913 } else
1914 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1915
1916 xgbe_dump_active_vlans(pdata);
1917 }
1918
1919 #if __FreeBSD_version >= 1300000
1920 static bool
axgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1921 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1922 {
1923 switch (event) {
1924 case IFLIB_RESTART_VLAN_CONFIG:
1925 default:
1926 return (true);
1927 }
1928 }
1929 #endif
1930
1931 static int
axgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)1932 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1933 {
1934 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1935 struct xgbe_prv_data *pdata = &sc->pdata;
1936 if_softc_ctx_t scctx = sc->scctx;
1937 struct xgbe_channel *channel;
1938 struct if_irq irq;
1939 int i, error, rid = 0, flags;
1940 char buf[16];
1941
1942 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1943
1944 pdata->isr_as_tasklet = 1;
1945
1946 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1947 pdata->irq_count = 1;
1948 pdata->channel_irq_count = 1;
1949 return (0);
1950 }
1951
1952 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1953 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1954
1955 flags = RF_ACTIVE;
1956
1957 /* DEV INTR SETUP */
1958 rid++;
1959 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1960 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1961 if (error) {
1962 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1963 rid, "dev_irq");
1964 return (error);
1965 }
1966
1967 /* ECC INTR SETUP */
1968 rid++;
1969 pdata->ecc_rid = rid;
1970 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1971 &rid, flags);
1972 if (!pdata->ecc_irq_res) {
1973 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1974 rid, "ecc_irq");
1975 return (ENOMEM);
1976 }
1977
1978 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1979 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1980 if (error) {
1981 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1982 rid, "ecc_irq", error);
1983 return (error);
1984 }
1985
1986 /* I2C INTR SETUP */
1987 rid++;
1988 pdata->i2c_rid = rid;
1989 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1990 &rid, flags);
1991 if (!pdata->i2c_irq_res) {
1992 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1993 rid, "i2c_irq");
1994 return (ENOMEM);
1995 }
1996
1997 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1998 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1999 if (error) {
2000 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2001 rid, "i2c_irq", error);
2002 return (error);
2003 }
2004
2005 /* AN INTR SETUP */
2006 rid++;
2007 pdata->an_rid = rid;
2008 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
2009 &rid, flags);
2010 if (!pdata->an_irq_res) {
2011 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
2012 rid, "an_irq");
2013 return (ENOMEM);
2014 }
2015
2016 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
2017 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
2018 if (error) {
2019 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2020 rid, "an_irq", error);
2021 return (error);
2022 }
2023
2024 pdata->per_channel_irq = 1;
2025 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
2026 rid++;
2027 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
2028
2029 channel = pdata->channel[i];
2030
2031 snprintf(buf, sizeof(buf), "rxq%d", i);
2032 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
2033 axgbe_msix_que, channel, channel->queue_index, buf);
2034
2035 if (error) {
2036 axgbe_error("Failed to allocated que int %d err: %d\n",
2037 i, error);
2038 return (error);
2039 }
2040
2041 channel->dma_irq_rid = rid;
2042 channel->dma_irq_res = irq.ii_res;
2043 channel->dma_irq_tag = irq.ii_tag;
2044 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2045 __func__, scctx->isc_nrxqsets, i, rid);
2046 }
2047 pdata->irq_count = msix;
2048 pdata->channel_irq_count = scctx->isc_nrxqsets;
2049
2050 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2051
2052 channel = pdata->channel[i];
2053
2054 snprintf(buf, sizeof(buf), "txq%d", i);
2055 irq.ii_res = channel->dma_irq_res;
2056 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2057 channel->queue_index, buf);
2058 }
2059
2060 return (0);
2061 } /* axgbe_if_msix_intr_assign */
2062
2063 static int
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2064 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2065 {
2066 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2067 enum xgbe_int int_id;
2068
2069 if (channel->tx_ring && channel->rx_ring)
2070 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2071 else if (channel->tx_ring)
2072 int_id = XGMAC_INT_DMA_CH_SR_TI;
2073 else if (channel->rx_ring)
2074 int_id = XGMAC_INT_DMA_CH_SR_RI;
2075 else
2076 return (-1);
2077
2078 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2079 __func__, channel->queue_index, int_id);
2080 return (hw_if->enable_int(channel, int_id));
2081 }
2082
2083 static void
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2084 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2085 {
2086 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2087 enum xgbe_int int_id;
2088
2089 if (channel->tx_ring && channel->rx_ring)
2090 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2091 else if (channel->tx_ring)
2092 int_id = XGMAC_INT_DMA_CH_SR_TI;
2093 else if (channel->rx_ring)
2094 int_id = XGMAC_INT_DMA_CH_SR_RI;
2095 else
2096 return;
2097
2098 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2099 __func__, channel->queue_index, int_id);
2100 hw_if->disable_int(channel, int_id);
2101 }
2102
2103 static void
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)2104 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2105 {
2106 unsigned int i;
2107
2108 for (i = 0; i < pdata->channel_count; i++)
2109 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2110 }
2111
2112 static int
axgbe_msix_que(void * arg)2113 axgbe_msix_que(void *arg)
2114 {
2115 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2116 struct xgbe_prv_data *pdata = channel->pdata;
2117 unsigned int dma_status;
2118
2119 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2120 __func__, channel->queue_index,
2121 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2122 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2123 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2124 XGMAC_IOREAD(pdata, DMA_ISR),
2125 XGMAC_IOREAD(pdata, MAC_ISR));
2126
2127 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2128
2129 /* Disable Tx and Rx channel interrupts */
2130 xgbe_disable_rx_tx_int(pdata, channel);
2131
2132 /* Clear the interrupts */
2133 dma_status = 0;
2134 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2135 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2136 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2137
2138 return (FILTER_SCHEDULE_THREAD);
2139 }
2140
2141 static int
axgbe_dev_isr(void * arg)2142 axgbe_dev_isr(void *arg)
2143 {
2144 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2145 struct xgbe_prv_data *pdata = &sc->pdata;
2146 struct xgbe_channel *channel;
2147 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2148 unsigned int i, dma_isr, dma_ch_isr;
2149 unsigned int mac_isr, mac_mdioisr;
2150 int ret = FILTER_HANDLED;
2151
2152 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2153 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2154
2155 if (!dma_isr)
2156 return (FILTER_HANDLED);
2157
2158 for (i = 0; i < pdata->channel_count; i++) {
2159
2160 if (!(dma_isr & (1 << i)))
2161 continue;
2162
2163 channel = pdata->channel[i];
2164
2165 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2166 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2167 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2168 DMA_CH_DSR));
2169
2170 /*
2171 * The TI or RI interrupt bits may still be set even if using
2172 * per channel DMA interrupts. Check to be sure those are not
2173 * enabled before using the private data napi structure.
2174 */
2175 if (!pdata->per_channel_irq &&
2176 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2177 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2178
2179 /* Disable Tx and Rx interrupts */
2180 xgbe_disable_rx_tx_ints(pdata);
2181 } else {
2182
2183 /*
2184 * Don't clear Rx/Tx status if doing per channel DMA
2185 * interrupts, these will be cleared by the ISR for
2186 * per channel DMA interrupts
2187 */
2188 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2189 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2190 }
2191
2192 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2193 pdata->ext_stats.rx_buffer_unavailable++;
2194
2195 /* Restart the device on a Fatal Bus Error */
2196 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2197 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2198 __func__, dma_ch_isr);
2199
2200 /* Clear all interrupt signals */
2201 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2202
2203 ret = FILTER_SCHEDULE_THREAD;
2204 }
2205
2206 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2207
2208 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2209 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2210
2211 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2212 hw_if->tx_mmc_int(pdata);
2213
2214 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2215 hw_if->rx_mmc_int(pdata);
2216
2217 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2218 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2219
2220 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2221 SNGLCOMPINT))
2222 wakeup_one(pdata);
2223 }
2224
2225 }
2226
2227 return (ret);
2228 } /* axgbe_dev_isr */
2229
2230 static void
axgbe_i2c_isr(void * arg)2231 axgbe_i2c_isr(void *arg)
2232 {
2233 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2234
2235 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2236 }
2237
2238 static void
axgbe_ecc_isr(void * arg)2239 axgbe_ecc_isr(void *arg)
2240 {
2241 /* TODO - implement */
2242 }
2243
2244 static void
axgbe_an_isr(void * arg)2245 axgbe_an_isr(void *arg)
2246 {
2247 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2248
2249 sc->pdata.phy_if.an_isr(&sc->pdata);
2250 }
2251
2252 static int
axgbe_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2253 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2254 {
2255 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2256 struct xgbe_prv_data *pdata = &sc->pdata;
2257 int ret;
2258
2259 if (qid < pdata->tx_q_count) {
2260 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2261 if (ret) {
2262 axgbe_error("Enable TX INT failed\n");
2263 return (ret);
2264 }
2265 } else
2266 axgbe_error("Queue ID exceed channel count\n");
2267
2268 return (0);
2269 }
2270
2271 static int
axgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2272 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2273 {
2274 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2275 struct xgbe_prv_data *pdata = &sc->pdata;
2276 int ret;
2277
2278 if (qid < pdata->rx_q_count) {
2279 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2280 if (ret) {
2281 axgbe_error("Enable RX INT failed\n");
2282 return (ret);
2283 }
2284 } else
2285 axgbe_error("Queue ID exceed channel count\n");
2286
2287 return (0);
2288 }
2289
2290 static void
axgbe_if_update_admin_status(if_ctx_t ctx)2291 axgbe_if_update_admin_status(if_ctx_t ctx)
2292 {
2293 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2294 struct xgbe_prv_data *pdata = &sc->pdata;
2295
2296 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2297 pdata->phy_link, sc->link_status, pdata->phy.speed);
2298
2299 if (pdata->phy_link < 0)
2300 return;
2301
2302 if (pdata->phy_link) {
2303 if (sc->link_status == LINK_STATE_DOWN) {
2304 sc->link_status = LINK_STATE_UP;
2305 if (pdata->phy.speed & SPEED_10000)
2306 iflib_link_state_change(ctx, LINK_STATE_UP,
2307 IF_Gbps(10));
2308 else if (pdata->phy.speed & SPEED_2500)
2309 iflib_link_state_change(ctx, LINK_STATE_UP,
2310 IF_Gbps(2.5));
2311 else if (pdata->phy.speed & SPEED_1000)
2312 iflib_link_state_change(ctx, LINK_STATE_UP,
2313 IF_Gbps(1));
2314 else if (pdata->phy.speed & SPEED_100)
2315 iflib_link_state_change(ctx, LINK_STATE_UP,
2316 IF_Mbps(100));
2317 else if (pdata->phy.speed & SPEED_10)
2318 iflib_link_state_change(ctx, LINK_STATE_UP,
2319 IF_Mbps(10));
2320 }
2321 } else {
2322 if (sc->link_status == LINK_STATE_UP) {
2323 sc->link_status = LINK_STATE_DOWN;
2324 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2325 }
2326 }
2327 }
2328
2329 static int
axgbe_if_media_change(if_ctx_t ctx)2330 axgbe_if_media_change(if_ctx_t ctx)
2331 {
2332 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2333 struct ifmedia *ifm = iflib_get_media(ctx);
2334
2335 sx_xlock(&sc->pdata.an_mutex);
2336 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2337 return (EINVAL);
2338
2339 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2340 case IFM_10G_KR:
2341 sc->pdata.phy.speed = SPEED_10000;
2342 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2343 break;
2344 case IFM_2500_KX:
2345 sc->pdata.phy.speed = SPEED_2500;
2346 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2347 break;
2348 case IFM_1000_KX:
2349 sc->pdata.phy.speed = SPEED_1000;
2350 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2351 break;
2352 case IFM_100_TX:
2353 sc->pdata.phy.speed = SPEED_100;
2354 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2355 break;
2356 case IFM_AUTO:
2357 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2358 break;
2359 }
2360 sx_xunlock(&sc->pdata.an_mutex);
2361
2362 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2363 }
2364
2365 static int
axgbe_if_promisc_set(if_ctx_t ctx,int flags)2366 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2367 {
2368 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2369 struct xgbe_prv_data *pdata = &sc->pdata;
2370
2371 axgbe_printf(1, "%s: MAC_PFR 0x%x if_flags 0x%x\n",
2372 __func__, XGMAC_IOREAD(pdata, MAC_PFR), flags);
2373
2374 if (flags & IFF_PROMISC) {
2375
2376 axgbe_printf(1, "Requested to enter promisc mode\n");
2377
2378 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2379 axgbe_printf(1, "Already in promisc mode\n");
2380 return (0);
2381 }
2382
2383 axgbe_printf(1, "Entering promisc mode\n");
2384 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2385 /* Disable VLAN filtering */
2386 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2387 } else {
2388
2389 axgbe_printf(1, "Requested to leave promisc mode\n");
2390
2391 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2392 axgbe_printf(1, "Already not in promisc mode\n");
2393 return (0);
2394 }
2395
2396 axgbe_printf(1, "Leaving promisc mode\n");
2397 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2398 /* Enable VLAN filtering */
2399 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2400 }
2401
2402 return (0);
2403 }
2404
2405 static uint64_t
axgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)2406 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2407 {
2408 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2409 if_t ifp = iflib_get_ifp(ctx);
2410 struct xgbe_prv_data *pdata = &sc->pdata;
2411 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2412
2413 pdata->hw_if.read_mmc_stats(pdata);
2414
2415 switch(cnt) {
2416 case IFCOUNTER_IPACKETS:
2417 return (pstats->rxframecount_gb);
2418 case IFCOUNTER_IERRORS:
2419 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2420 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2421 case IFCOUNTER_OPACKETS:
2422 return (pstats->txframecount_gb);
2423 case IFCOUNTER_OERRORS:
2424 return (if_get_counter_default(ifp, cnt) +
2425 pstats->txframecount_gb - pstats->txframecount_g);
2426 case IFCOUNTER_IBYTES:
2427 return (pstats->rxoctetcount_gb);
2428 case IFCOUNTER_OBYTES:
2429 return (pstats->txoctetcount_gb);
2430 default:
2431 return (if_get_counter_default(ifp, cnt));
2432 }
2433 }
2434
2435 static int
axgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)2436 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2437 {
2438 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2439 struct xgbe_prv_data *pdata = &sc->pdata;
2440 int ret;
2441
2442 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2443 return (EINVAL);
2444
2445 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2446 pdata->rx_buf_size = ret;
2447 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2448
2449 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2450 return (0);
2451 }
2452
2453 static void
axgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2454 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2455 {
2456 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2457 struct xgbe_prv_data *pdata = &sc->pdata;
2458
2459 ifmr->ifm_status = IFM_AVALID;
2460 if (!sc->pdata.phy.link)
2461 return;
2462
2463 ifmr->ifm_active = IFM_ETHER;
2464 ifmr->ifm_status |= IFM_ACTIVE;
2465
2466 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2467 pdata->phy_if.phy_impl.cur_mode(pdata));
2468 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2469
2470 ifmr->ifm_active |= IFM_FDX;
2471 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2472 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2473 }
2474