1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * (1) Redistributions of source code must retain the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer. 12 * 13 * (2) Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * (3)The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _AQ_RING_H_ 36 #define _AQ_RING_H_ 37 38 #include "aq_hw.h" 39 40 #define REFILL_THRESHOLD 128 41 42 43 typedef volatile struct { 44 uint32_t rss_type:4; 45 uint32_t pkt_type:8; 46 uint32_t rdm_err:1; 47 uint32_t rsvd:6; 48 uint32_t rx_cntl:2; 49 uint32_t sph:1; 50 uint32_t hdr_len:10; 51 uint32_t rss_hash; 52 uint16_t dd:1; 53 uint16_t eop:1; 54 uint16_t rx_stat:4; 55 uint16_t rx_estat:6; 56 uint16_t rsc_cnt:4; 57 uint16_t pkt_len; 58 uint16_t next_desp; 59 uint16_t vlan; 60 } __attribute__((__packed__)) aq_rx_wb_t; 61 62 typedef volatile struct { 63 union { 64 /* HW RX descriptor */ 65 struct __packed { 66 uint64_t buf_addr; 67 uint64_t hdr_addr; 68 } read; 69 70 /* HW RX descriptor writeback */ 71 aq_rx_wb_t wb; 72 }; 73 } __attribute__((__packed__)) aq_rx_desc_t; 74 75 /* Hardware tx descriptor */ 76 typedef volatile struct { 77 uint64_t buf_addr; 78 79 union { 80 struct { 81 uint32_t type:3; 82 uint32_t :1; 83 uint32_t len:16; 84 uint32_t dd:1; 85 uint32_t eop:1; 86 uint32_t cmd:8; 87 uint32_t :14; 88 uint32_t ct_idx:1; 89 uint32_t ct_en:1; 90 uint32_t pay_len:18; 91 } __attribute__((__packed__)); 92 uint64_t flags; 93 }; 94 } __attribute__((__packed__)) aq_tx_desc_t; 95 96 enum aq_tx_desc_type { 97 tx_desc_type_desc = 1, 98 tx_desc_type_ctx = 2, 99 }; 100 101 enum aq_tx_desc_cmd { 102 tx_desc_cmd_vlan = 1, 103 tx_desc_cmd_fcs = 2, 104 tx_desc_cmd_ipv4 = 4, 105 tx_desc_cmd_l4cs = 8, 106 tx_desc_cmd_lso = 0x10, 107 tx_desc_cmd_wb = 0x20, 108 }; 109 110 /* Hardware tx context descriptor */ 111 typedef volatile union { 112 struct __packed { 113 uint64_t flags1; 114 uint64_t flags2; 115 }; 116 117 struct __packed { 118 uint64_t :40; 119 uint32_t tun_len:8; 120 uint32_t out_len:16; 121 uint32_t type:3; 122 uint32_t idx:1; 123 uint32_t vlan_tag:16; 124 uint32_t cmd:4; 125 uint32_t l2_len:7; 126 uint32_t l3_len:9; 127 uint32_t l4_len:8; 128 uint32_t mss_len:16; 129 }; 130 } __attribute__((__packed__)) aq_txc_desc_t; 131 132 struct aq_ring_stats { 133 uint64_t rx_pkts; 134 uint64_t rx_bytes; 135 uint64_t jumbo_pkts; 136 uint64_t rx_err; 137 uint64_t irq; 138 139 uint64_t tx_pkts; 140 uint64_t tx_bytes; 141 uint64_t tx_drops; 142 uint64_t tx_queue_full; 143 }; 144 145 struct aq_dev; 146 147 struct aq_ring { 148 struct aq_dev *dev; 149 int index; 150 151 struct if_irq irq; 152 int msix; 153 /* RX */ 154 qidx_t rx_size; 155 int rx_max_frame_size; 156 void *rx_desc_area_ptr; 157 aq_rx_desc_t *rx_descs; 158 uint64_t rx_descs_phys; 159 160 /* TX */ 161 int tx_head, tx_tail; 162 qidx_t tx_size; 163 void *tx_desc_area_ptr; 164 aq_tx_desc_t *tx_descs; 165 uint64_t tx_descs_phys; 166 167 struct aq_ring_stats stats; 168 }; 169 170 int aq_ring_rx_init(struct aq_hw *hw, struct aq_ring *ring); 171 int aq_ring_tx_init(struct aq_hw *hw, struct aq_ring *ring); 172 173 int aq_ring_tx_start(struct aq_hw *hw, struct aq_ring *ring); 174 int aq_ring_tx_stop(struct aq_hw *hw, struct aq_ring *ring); 175 int aq_ring_rx_start(struct aq_hw *hw, struct aq_ring *ring); 176 int aq_ring_rx_stop(struct aq_hw *hw, struct aq_ring *ring); 177 178 int aq_ring_tx_tail_update(struct aq_hw *hw, struct aq_ring *ring, uint32_t tail); 179 180 181 extern struct if_txrx aq_txrx; 182 int aq_intr(void *arg); 183 184 #endif /* _AQ_RING_H_ */ 185