1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * UCSI driver for Cypress CCGx Type-C controller
4 *
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
7 *
8 * Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
9 */
10 #include <linux/acpi.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/usb/typec_dp.h>
20
21 #include <linux/unaligned.h>
22 #include "ucsi.h"
23
24 enum enum_fw_mode {
25 BOOT, /* bootloader */
26 FW1, /* FW partition-1 (contains secondary fw) */
27 FW2, /* FW partition-2 (contains primary fw) */
28 FW_INVALID,
29 };
30
31 #define CCGX_RAB_DEVICE_MODE 0x0000
32 #define CCGX_RAB_INTR_REG 0x0006
33 #define DEV_INT BIT(0)
34 #define PORT0_INT BIT(1)
35 #define PORT1_INT BIT(2)
36 #define UCSI_READ_INT BIT(7)
37 #define CCGX_RAB_JUMP_TO_BOOT 0x0007
38 #define TO_BOOT 'J'
39 #define TO_ALT_FW 'A'
40 #define CCGX_RAB_RESET_REQ 0x0008
41 #define RESET_SIG 'R'
42 #define CMD_RESET_I2C 0x0
43 #define CMD_RESET_DEV 0x1
44 #define CCGX_RAB_ENTER_FLASHING 0x000A
45 #define FLASH_ENTER_SIG 'P'
46 #define CCGX_RAB_VALIDATE_FW 0x000B
47 #define CCGX_RAB_FLASH_ROW_RW 0x000C
48 #define FLASH_SIG 'F'
49 #define FLASH_RD_CMD 0x0
50 #define FLASH_WR_CMD 0x1
51 #define FLASH_FWCT1_WR_CMD 0x2
52 #define FLASH_FWCT2_WR_CMD 0x3
53 #define FLASH_FWCT_SIG_WR_CMD 0x4
54 #define CCGX_RAB_READ_ALL_VER 0x0010
55 #define CCGX_RAB_READ_FW2_VER 0x0020
56 #define CCGX_RAB_UCSI_CONTROL 0x0039
57 #define CCGX_RAB_UCSI_CONTROL_START BIT(0)
58 #define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
59 #define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
60 #define REG_FLASH_RW_MEM 0x0200
61 #define DEV_REG_IDX CCGX_RAB_DEVICE_MODE
62 #define CCGX_RAB_PDPORT_ENABLE 0x002C
63 #define PDPORT_1 BIT(0)
64 #define PDPORT_2 BIT(1)
65 #define CCGX_RAB_RESPONSE 0x007E
66 #define ASYNC_EVENT BIT(7)
67
68 /* CCGx events & async msg codes */
69 #define RESET_COMPLETE 0x80
70 #define EVENT_INDEX RESET_COMPLETE
71 #define PORT_CONNECT_DET 0x84
72 #define PORT_DISCONNECT_DET 0x85
73 #define ROLE_SWAP_COMPELETE 0x87
74
75 /* ccg firmware */
76 #define CYACD_LINE_SIZE 527
77 #define CCG4_ROW_SIZE 256
78 #define FW1_METADATA_ROW 0x1FF
79 #define FW2_METADATA_ROW 0x1FE
80 #define FW_CFG_TABLE_SIG_SIZE 256
81
82 static int secondary_fw_min_ver = 41;
83
84 enum enum_flash_mode {
85 SECONDARY_BL, /* update secondary using bootloader */
86 PRIMARY, /* update primary using secondary */
87 SECONDARY, /* update secondary using primary */
88 FLASH_NOT_NEEDED, /* update not required */
89 FLASH_INVALID,
90 };
91
92 static const char * const ccg_fw_names[] = {
93 "ccg_boot.cyacd",
94 "ccg_primary.cyacd",
95 "ccg_secondary.cyacd"
96 };
97
98 struct ccg_dev_info {
99 #define CCG_DEVINFO_FWMODE_SHIFT (0)
100 #define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
101 #define CCG_DEVINFO_PDPORTS_SHIFT (2)
102 #define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
103 u8 mode;
104 u8 bl_mode;
105 __le16 silicon_id;
106 __le16 bl_last_row;
107 } __packed;
108
109 struct version_format {
110 __le16 build;
111 u8 patch;
112 u8 ver;
113 #define CCG_VERSION_PATCH(x) ((x) << 16)
114 #define CCG_VERSION(x) ((x) << 24)
115 #define CCG_VERSION_MIN_SHIFT (0)
116 #define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
117 #define CCG_VERSION_MAJ_SHIFT (4)
118 #define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
119 } __packed;
120
121 /*
122 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
123 * of missing interrupt when a device is connected for runtime resume
124 */
125 #define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v')
126 #define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
127
128 /* Firmware for Tegra doesn't support UCSI ALT command, built
129 * for NVIDIA has known issue of reporting wrong capability info
130 */
131 #define CCG_FW_BUILD_NVIDIA_TEGRA (('g' << 8) | 'n')
132
133 /* Altmode offset for NVIDIA Function Test Board (FTB) */
134 #define NVIDIA_FTB_DP_OFFSET (2)
135 #define NVIDIA_FTB_DBG_OFFSET (3)
136
137 struct version_info {
138 struct version_format base;
139 struct version_format app;
140 };
141
142 struct fw_config_table {
143 u32 identity;
144 u16 table_size;
145 u8 fwct_version;
146 u8 is_key_change;
147 u8 guid[16];
148 struct version_format base;
149 struct version_format app;
150 u8 primary_fw_digest[32];
151 u32 key_exp_length;
152 u8 key_modulus[256];
153 u8 key_exp[4];
154 };
155
156 /* CCGx response codes */
157 enum ccg_resp_code {
158 CMD_NO_RESP = 0x00,
159 CMD_SUCCESS = 0x02,
160 FLASH_DATA_AVAILABLE = 0x03,
161 CMD_INVALID = 0x05,
162 FLASH_UPDATE_FAIL = 0x07,
163 INVALID_FW = 0x08,
164 INVALID_ARG = 0x09,
165 CMD_NOT_SUPPORT = 0x0A,
166 TRANSACTION_FAIL = 0x0C,
167 PD_CMD_FAIL = 0x0D,
168 UNDEF_ERROR = 0x0F,
169 INVALID_RESP = 0x10,
170 };
171
172 #define CCG_EVENT_MAX (EVENT_INDEX + 43)
173
174 struct ccg_cmd {
175 u16 reg;
176 u32 data;
177 int len;
178 u32 delay; /* ms delay for cmd timeout */
179 };
180
181 struct ccg_resp {
182 u8 code;
183 u8 length;
184 };
185
186 struct ucsi_ccg_altmode {
187 u16 svid;
188 u32 mid;
189 u8 linked_idx;
190 u8 active_idx;
191 #define UCSI_MULTI_DP_INDEX (0xff)
192 bool checked;
193 } __packed;
194
195 #define CCGX_MESSAGE_IN_MAX 4
196 struct op_region {
197 __le32 cci;
198 __le32 message_in[CCGX_MESSAGE_IN_MAX];
199 };
200
201 struct ucsi_ccg {
202 struct device *dev;
203 struct ucsi *ucsi;
204 struct i2c_client *client;
205
206 struct ccg_dev_info info;
207 /* version info for boot, primary and secondary */
208 struct version_info version[FW2 + 1];
209 u32 fw_version;
210 /* CCG HPI communication flags */
211 unsigned long flags;
212 #define RESET_PENDING 0
213 #define DEV_CMD_PENDING 1
214 struct ccg_resp dev_resp;
215 u8 cmd_resp;
216 int port_num;
217 int irq;
218 struct work_struct work;
219 struct mutex lock; /* to sync between user and driver thread */
220
221 /* fw build with vendor information */
222 u16 fw_build;
223 struct work_struct pm_work;
224
225 u64 last_cmd_sent;
226 bool has_multiple_dp;
227 struct ucsi_ccg_altmode orig[UCSI_MAX_ALTMODES];
228 struct ucsi_ccg_altmode updated[UCSI_MAX_ALTMODES];
229
230 /*
231 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
232 * will be updated in ISR
233 */
234 spinlock_t op_lock;
235 struct op_region op_data;
236 };
237
ccg_read(struct ucsi_ccg * uc,u16 rab,u8 * data,u32 len)238 static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
239 {
240 struct i2c_client *client = uc->client;
241 const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
242 unsigned char buf[2];
243 struct i2c_msg msgs[] = {
244 {
245 .addr = client->addr,
246 .flags = 0x0,
247 .len = sizeof(buf),
248 .buf = buf,
249 },
250 {
251 .addr = client->addr,
252 .flags = I2C_M_RD,
253 .buf = data,
254 },
255 };
256 u32 rlen, rem_len = len, max_read_len = len;
257 int status;
258
259 /* check any max_read_len limitation on i2c adapter */
260 if (quirks && quirks->max_read_len)
261 max_read_len = quirks->max_read_len;
262
263 pm_runtime_get_sync(uc->dev);
264 while (rem_len > 0) {
265 msgs[1].buf = &data[len - rem_len];
266 rlen = min_t(u16, rem_len, max_read_len);
267 msgs[1].len = rlen;
268 put_unaligned_le16(rab, buf);
269 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
270 if (status < 0) {
271 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
272 pm_runtime_put_sync(uc->dev);
273 return status;
274 }
275 rab += rlen;
276 rem_len -= rlen;
277 }
278
279 pm_runtime_put_sync(uc->dev);
280 return 0;
281 }
282
ccg_write(struct ucsi_ccg * uc,u16 rab,const u8 * data,u32 len)283 static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
284 {
285 struct i2c_client *client = uc->client;
286 unsigned char *buf;
287 struct i2c_msg msgs[] = {
288 {
289 .addr = client->addr,
290 .flags = 0x0,
291 }
292 };
293 int status;
294
295 buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
296 if (!buf)
297 return -ENOMEM;
298
299 put_unaligned_le16(rab, buf);
300 memcpy(buf + sizeof(rab), data, len);
301
302 msgs[0].len = len + sizeof(rab);
303 msgs[0].buf = buf;
304
305 pm_runtime_get_sync(uc->dev);
306 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
307 if (status < 0) {
308 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
309 pm_runtime_put_sync(uc->dev);
310 kfree(buf);
311 return status;
312 }
313
314 pm_runtime_put_sync(uc->dev);
315 kfree(buf);
316 return 0;
317 }
318
ccg_op_region_update(struct ucsi_ccg * uc,u32 cci)319 static int ccg_op_region_update(struct ucsi_ccg *uc, u32 cci)
320 {
321 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_MESSAGE_IN);
322 struct op_region *data = &uc->op_data;
323 unsigned char *buf;
324 size_t size = sizeof(data->message_in);
325
326 buf = kzalloc(size, GFP_ATOMIC);
327 if (!buf)
328 return -ENOMEM;
329 if (UCSI_CCI_LENGTH(cci)) {
330 int ret = ccg_read(uc, reg, (void *)buf, size);
331
332 if (ret) {
333 kfree(buf);
334 return ret;
335 }
336 }
337
338 spin_lock(&uc->op_lock);
339 data->cci = cpu_to_le32(cci);
340 if (UCSI_CCI_LENGTH(cci))
341 memcpy(&data->message_in, buf, size);
342 spin_unlock(&uc->op_lock);
343 kfree(buf);
344 return 0;
345 }
346
ucsi_ccg_init(struct ucsi_ccg * uc)347 static int ucsi_ccg_init(struct ucsi_ccg *uc)
348 {
349 unsigned int count = 10;
350 u8 data;
351 int status;
352
353 spin_lock_init(&uc->op_lock);
354
355 data = CCGX_RAB_UCSI_CONTROL_STOP;
356 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
357 if (status < 0)
358 return status;
359
360 data = CCGX_RAB_UCSI_CONTROL_START;
361 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
362 if (status < 0)
363 return status;
364
365 /*
366 * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
367 * register write will push response which must be cleared.
368 */
369 do {
370 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
371 if (status < 0)
372 return status;
373
374 if (!(data & DEV_INT))
375 return 0;
376
377 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
378 if (status < 0)
379 return status;
380
381 usleep_range(10000, 11000);
382 } while (--count);
383
384 return -ETIMEDOUT;
385 }
386
ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg * uc,u8 * data)387 static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data)
388 {
389 u8 cam, new_cam;
390
391 cam = data[0];
392 new_cam = uc->orig[cam].linked_idx;
393 uc->updated[new_cam].active_idx = cam;
394 data[0] = new_cam;
395 }
396
ucsi_ccg_update_altmodes(struct ucsi * ucsi,struct ucsi_altmode * orig,struct ucsi_altmode * updated)397 static bool ucsi_ccg_update_altmodes(struct ucsi *ucsi,
398 struct ucsi_altmode *orig,
399 struct ucsi_altmode *updated)
400 {
401 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
402 struct ucsi_ccg_altmode *alt, *new_alt;
403 int i, j, k = 0;
404 bool found = false;
405
406 alt = uc->orig;
407 new_alt = uc->updated;
408 memset(uc->updated, 0, sizeof(uc->updated));
409
410 /*
411 * Copy original connector altmodes to new structure.
412 * We need this before second loop since second loop
413 * checks for duplicate altmodes.
414 */
415 for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
416 alt[i].svid = orig[i].svid;
417 alt[i].mid = orig[i].mid;
418 if (!alt[i].svid)
419 break;
420 }
421
422 for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
423 if (!alt[i].svid)
424 break;
425
426 /* already checked and considered */
427 if (alt[i].checked)
428 continue;
429
430 if (!DP_CONF_GET_PIN_ASSIGN(alt[i].mid)) {
431 /* Found Non DP altmode */
432 new_alt[k].svid = alt[i].svid;
433 new_alt[k].mid |= alt[i].mid;
434 new_alt[k].linked_idx = i;
435 alt[i].linked_idx = k;
436 updated[k].svid = new_alt[k].svid;
437 updated[k].mid = new_alt[k].mid;
438 k++;
439 continue;
440 }
441
442 for (j = i + 1; j < UCSI_MAX_ALTMODES; j++) {
443 if (alt[i].svid != alt[j].svid ||
444 !DP_CONF_GET_PIN_ASSIGN(alt[j].mid)) {
445 continue;
446 } else {
447 /* Found duplicate DP mode */
448 new_alt[k].svid = alt[i].svid;
449 new_alt[k].mid |= alt[i].mid | alt[j].mid;
450 new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX;
451 alt[i].linked_idx = k;
452 alt[j].linked_idx = k;
453 alt[j].checked = true;
454 found = true;
455 }
456 }
457 if (found) {
458 uc->has_multiple_dp = true;
459 } else {
460 /* Didn't find any duplicate DP altmode */
461 new_alt[k].svid = alt[i].svid;
462 new_alt[k].mid |= alt[i].mid;
463 new_alt[k].linked_idx = i;
464 alt[i].linked_idx = k;
465 }
466 updated[k].svid = new_alt[k].svid;
467 updated[k].mid = new_alt[k].mid;
468 k++;
469 }
470 return found;
471 }
472
ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg * uc,struct ucsi_connector * con,u64 * cmd)473 static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc,
474 struct ucsi_connector *con,
475 u64 *cmd)
476 {
477 struct ucsi_ccg_altmode *new_port, *port;
478 struct typec_altmode *alt = NULL;
479 u8 new_cam, cam, pin;
480 bool enter_new_mode;
481 int i, j, k = 0xff;
482
483 port = uc->orig;
484 new_cam = UCSI_SET_NEW_CAM_GET_AM(*cmd);
485 if (new_cam >= ARRAY_SIZE(uc->updated))
486 return;
487 new_port = &uc->updated[new_cam];
488 cam = new_port->linked_idx;
489 enter_new_mode = UCSI_SET_NEW_CAM_ENTER(*cmd);
490
491 /*
492 * If CAM is UCSI_MULTI_DP_INDEX then this is DP altmode
493 * with multiple DP mode. Find out CAM for best pin assignment
494 * among all DP mode. Priorite pin E->D->C after making sure
495 * the partner supports that pin.
496 */
497 if (cam == UCSI_MULTI_DP_INDEX) {
498 if (enter_new_mode) {
499 for (i = 0; con->partner_altmode[i]; i++) {
500 alt = con->partner_altmode[i];
501 if (alt->svid == new_port->svid)
502 break;
503 }
504 /*
505 * alt will always be non NULL since this is
506 * UCSI_SET_NEW_CAM command and so there will be
507 * at least one con->partner_altmode[i] with svid
508 * matching with new_port->svid.
509 */
510 for (j = 0; port[j].svid; j++) {
511 pin = DP_CONF_GET_PIN_ASSIGN(port[j].mid);
512 if (alt && port[j].svid == alt->svid &&
513 (pin & DP_CONF_GET_PIN_ASSIGN(alt->vdo))) {
514 /* prioritize pin E->D->C */
515 if (k == 0xff || (k != 0xff && pin >
516 DP_CONF_GET_PIN_ASSIGN(port[k].mid))
517 ) {
518 k = j;
519 }
520 }
521 }
522 cam = k;
523 new_port->active_idx = cam;
524 } else {
525 cam = new_port->active_idx;
526 }
527 }
528 *cmd &= ~UCSI_SET_NEW_CAM_AM_MASK;
529 *cmd |= UCSI_SET_NEW_CAM_SET_AM(cam);
530 }
531
532 /*
533 * Change the order of vdo values of NVIDIA test device FTB
534 * (Function Test Board) which reports altmode list with vdo=0x3
535 * first and then vdo=0x. Current logic to assign mode value is
536 * based on order in altmode list and it causes a mismatch of CON
537 * and SOP altmodes since NVIDIA GPU connector has order of vdo=0x1
538 * first and then vdo=0x3
539 */
ucsi_ccg_nvidia_altmode(struct ucsi_ccg * uc,struct ucsi_altmode * alt)540 static void ucsi_ccg_nvidia_altmode(struct ucsi_ccg *uc,
541 struct ucsi_altmode *alt)
542 {
543 switch (UCSI_ALTMODE_OFFSET(uc->last_cmd_sent)) {
544 case NVIDIA_FTB_DP_OFFSET:
545 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DBG_VDO)
546 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DP_VDO |
547 DP_CAP_DP_SIGNALLING(0) | DP_CAP_USB |
548 DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_E));
549 break;
550 case NVIDIA_FTB_DBG_OFFSET:
551 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DP_VDO)
552 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DBG_VDO;
553 break;
554 default:
555 break;
556 }
557 }
558
ucsi_ccg_read_version(struct ucsi * ucsi,u16 * version)559 static int ucsi_ccg_read_version(struct ucsi *ucsi, u16 *version)
560 {
561 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
562 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_VERSION);
563
564 return ccg_read(uc, reg, (u8 *)version, sizeof(*version));
565 }
566
ucsi_ccg_read_cci(struct ucsi * ucsi,u32 * cci)567 static int ucsi_ccg_read_cci(struct ucsi *ucsi, u32 *cci)
568 {
569 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
570
571 spin_lock(&uc->op_lock);
572 *cci = uc->op_data.cci;
573 spin_unlock(&uc->op_lock);
574
575 return 0;
576 }
577
ucsi_ccg_read_message_in(struct ucsi * ucsi,void * val,size_t val_len)578 static int ucsi_ccg_read_message_in(struct ucsi *ucsi, void *val, size_t val_len)
579 {
580 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
581 struct ucsi_capability *cap;
582 struct ucsi_altmode *alt;
583
584 spin_lock(&uc->op_lock);
585 memcpy(val, uc->op_data.message_in, val_len);
586 spin_unlock(&uc->op_lock);
587
588 switch (UCSI_COMMAND(uc->last_cmd_sent)) {
589 case UCSI_GET_CURRENT_CAM:
590 if (uc->has_multiple_dp)
591 ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)val);
592 break;
593 case UCSI_GET_ALTERNATE_MODES:
594 if (UCSI_ALTMODE_RECIPIENT(uc->last_cmd_sent) ==
595 UCSI_RECIPIENT_SOP) {
596 alt = val;
597 if (alt[0].svid == USB_TYPEC_NVIDIA_VLINK_SID)
598 ucsi_ccg_nvidia_altmode(uc, alt);
599 }
600 break;
601 case UCSI_GET_CAPABILITY:
602 if (uc->fw_build == CCG_FW_BUILD_NVIDIA_TEGRA) {
603 cap = val;
604 cap->features &= ~UCSI_CAP_ALT_MODE_DETAILS;
605 }
606 break;
607 default:
608 break;
609 }
610 uc->last_cmd_sent = 0;
611
612 return 0;
613 }
614
ucsi_ccg_async_control(struct ucsi * ucsi,u64 command)615 static int ucsi_ccg_async_control(struct ucsi *ucsi, u64 command)
616 {
617 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
618 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CONTROL);
619
620 /*
621 * UCSI may read CCI instantly after async_control,
622 * clear CCI to avoid caller getting wrong data before we get CCI from ISR
623 */
624 spin_lock(&uc->op_lock);
625 uc->op_data.cci = 0;
626 spin_unlock(&uc->op_lock);
627
628 return ccg_write(uc, reg, (u8 *)&command, sizeof(command));
629 }
630
ucsi_ccg_sync_control(struct ucsi * ucsi,u64 command)631 static int ucsi_ccg_sync_control(struct ucsi *ucsi, u64 command)
632 {
633 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
634 struct ucsi_connector *con;
635 int con_index;
636 int ret;
637
638 mutex_lock(&uc->lock);
639 pm_runtime_get_sync(uc->dev);
640
641 uc->last_cmd_sent = command;
642
643 if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_SET_NEW_CAM &&
644 uc->has_multiple_dp) {
645 con_index = (uc->last_cmd_sent >> 16) &
646 UCSI_CMD_CONNECTOR_MASK;
647 if (con_index == 0) {
648 ret = -EINVAL;
649 goto err_put;
650 }
651 con = &uc->ucsi->connector[con_index - 1];
652 ucsi_ccg_update_set_new_cam_cmd(uc, con, &command);
653 }
654
655 ret = ucsi_sync_control_common(ucsi, command);
656
657 err_put:
658 pm_runtime_put_sync(uc->dev);
659 mutex_unlock(&uc->lock);
660
661 return ret;
662 }
663
664 static const struct ucsi_operations ucsi_ccg_ops = {
665 .read_version = ucsi_ccg_read_version,
666 .read_cci = ucsi_ccg_read_cci,
667 .poll_cci = ucsi_ccg_read_cci,
668 .read_message_in = ucsi_ccg_read_message_in,
669 .sync_control = ucsi_ccg_sync_control,
670 .async_control = ucsi_ccg_async_control,
671 .update_altmodes = ucsi_ccg_update_altmodes
672 };
673
ccg_irq_handler(int irq,void * data)674 static irqreturn_t ccg_irq_handler(int irq, void *data)
675 {
676 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI);
677 struct ucsi_ccg *uc = data;
678 u8 intr_reg;
679 u32 cci = 0;
680 int ret = 0;
681
682 ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
683 if (ret)
684 return ret;
685
686 if (!intr_reg)
687 return IRQ_HANDLED;
688 else if (!(intr_reg & UCSI_READ_INT))
689 goto err_clear_irq;
690
691 ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
692 if (ret)
693 goto err_clear_irq;
694
695 /*
696 * As per CCGx UCSI interface guide, copy CCI and MESSAGE_IN
697 * to the OpRegion before clear the UCSI interrupt
698 */
699 ret = ccg_op_region_update(uc, cci);
700 if (ret)
701 goto err_clear_irq;
702
703 err_clear_irq:
704 ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
705
706 if (!ret)
707 ucsi_notify_common(uc->ucsi, cci);
708
709 return IRQ_HANDLED;
710 }
711
ccg_request_irq(struct ucsi_ccg * uc)712 static int ccg_request_irq(struct ucsi_ccg *uc)
713 {
714 unsigned long flags = IRQF_ONESHOT;
715
716 if (!dev_fwnode(uc->dev))
717 flags |= IRQF_TRIGGER_HIGH;
718
719 return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc);
720 }
721
ccg_pm_workaround_work(struct work_struct * pm_work)722 static void ccg_pm_workaround_work(struct work_struct *pm_work)
723 {
724 ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work));
725 }
726
get_fw_info(struct ucsi_ccg * uc)727 static int get_fw_info(struct ucsi_ccg *uc)
728 {
729 int err;
730
731 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
732 sizeof(uc->version));
733 if (err < 0)
734 return err;
735
736 uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
737 CCG_VERSION_PATCH(uc->version[FW2].app.patch);
738
739 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
740 sizeof(uc->info));
741 if (err < 0)
742 return err;
743
744 return 0;
745 }
746
invalid_async_evt(int code)747 static inline bool invalid_async_evt(int code)
748 {
749 return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);
750 }
751
ccg_process_response(struct ucsi_ccg * uc)752 static void ccg_process_response(struct ucsi_ccg *uc)
753 {
754 struct device *dev = uc->dev;
755
756 if (uc->dev_resp.code & ASYNC_EVENT) {
757 if (uc->dev_resp.code == RESET_COMPLETE) {
758 if (test_bit(RESET_PENDING, &uc->flags))
759 uc->cmd_resp = uc->dev_resp.code;
760 get_fw_info(uc);
761 }
762 if (invalid_async_evt(uc->dev_resp.code))
763 dev_err(dev, "invalid async evt %d\n",
764 uc->dev_resp.code);
765 } else {
766 if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
767 uc->cmd_resp = uc->dev_resp.code;
768 clear_bit(DEV_CMD_PENDING, &uc->flags);
769 } else {
770 dev_err(dev, "dev resp 0x%04x but no cmd pending\n",
771 uc->dev_resp.code);
772 }
773 }
774 }
775
ccg_read_response(struct ucsi_ccg * uc)776 static int ccg_read_response(struct ucsi_ccg *uc)
777 {
778 unsigned long target = jiffies + msecs_to_jiffies(1000);
779 struct device *dev = uc->dev;
780 u8 intval;
781 int status;
782
783 /* wait for interrupt status to get updated */
784 do {
785 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
786 sizeof(intval));
787 if (status < 0)
788 return status;
789
790 if (intval & DEV_INT)
791 break;
792 usleep_range(500, 600);
793 } while (time_is_after_jiffies(target));
794
795 if (time_is_before_jiffies(target)) {
796 dev_err(dev, "response timeout error\n");
797 return -ETIME;
798 }
799
800 status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
801 sizeof(uc->dev_resp));
802 if (status < 0)
803 return status;
804
805 status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
806 if (status < 0)
807 return status;
808
809 return 0;
810 }
811
812 /* Caller must hold uc->lock */
ccg_send_command(struct ucsi_ccg * uc,struct ccg_cmd * cmd)813 static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
814 {
815 struct device *dev = uc->dev;
816 int ret;
817
818 switch (cmd->reg & 0xF000) {
819 case DEV_REG_IDX:
820 set_bit(DEV_CMD_PENDING, &uc->flags);
821 break;
822 default:
823 dev_err(dev, "invalid cmd register\n");
824 break;
825 }
826
827 ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
828 if (ret < 0)
829 return ret;
830
831 msleep(cmd->delay);
832
833 ret = ccg_read_response(uc);
834 if (ret < 0) {
835 dev_err(dev, "response read error\n");
836 switch (cmd->reg & 0xF000) {
837 case DEV_REG_IDX:
838 clear_bit(DEV_CMD_PENDING, &uc->flags);
839 break;
840 default:
841 dev_err(dev, "invalid cmd register\n");
842 break;
843 }
844 return -EIO;
845 }
846 ccg_process_response(uc);
847
848 return uc->cmd_resp;
849 }
850
ccg_cmd_enter_flashing(struct ucsi_ccg * uc)851 static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
852 {
853 struct ccg_cmd cmd;
854 int ret;
855
856 cmd.reg = CCGX_RAB_ENTER_FLASHING;
857 cmd.data = FLASH_ENTER_SIG;
858 cmd.len = 1;
859 cmd.delay = 50;
860
861 mutex_lock(&uc->lock);
862
863 ret = ccg_send_command(uc, &cmd);
864
865 mutex_unlock(&uc->lock);
866
867 if (ret != CMD_SUCCESS) {
868 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
869 return ret;
870 }
871
872 return 0;
873 }
874
ccg_cmd_reset(struct ucsi_ccg * uc)875 static int ccg_cmd_reset(struct ucsi_ccg *uc)
876 {
877 struct ccg_cmd cmd;
878 u8 *p;
879 int ret;
880
881 p = (u8 *)&cmd.data;
882 cmd.reg = CCGX_RAB_RESET_REQ;
883 p[0] = RESET_SIG;
884 p[1] = CMD_RESET_DEV;
885 cmd.len = 2;
886 cmd.delay = 5000;
887
888 mutex_lock(&uc->lock);
889
890 set_bit(RESET_PENDING, &uc->flags);
891
892 ret = ccg_send_command(uc, &cmd);
893 if (ret != RESET_COMPLETE)
894 goto err_clear_flag;
895
896 ret = 0;
897
898 err_clear_flag:
899 clear_bit(RESET_PENDING, &uc->flags);
900
901 mutex_unlock(&uc->lock);
902
903 return ret;
904 }
905
ccg_cmd_port_control(struct ucsi_ccg * uc,bool enable)906 static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
907 {
908 struct ccg_cmd cmd;
909 int ret;
910
911 cmd.reg = CCGX_RAB_PDPORT_ENABLE;
912 if (enable)
913 cmd.data = (uc->port_num == 1) ?
914 PDPORT_1 : (PDPORT_1 | PDPORT_2);
915 else
916 cmd.data = 0x0;
917 cmd.len = 1;
918 cmd.delay = 10;
919
920 mutex_lock(&uc->lock);
921
922 ret = ccg_send_command(uc, &cmd);
923
924 mutex_unlock(&uc->lock);
925
926 if (ret != CMD_SUCCESS) {
927 dev_err(uc->dev, "port control failed ret=%d\n", ret);
928 return ret;
929 }
930 return 0;
931 }
932
ccg_cmd_jump_boot_mode(struct ucsi_ccg * uc,int bl_mode)933 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
934 {
935 struct ccg_cmd cmd;
936 int ret;
937
938 cmd.reg = CCGX_RAB_JUMP_TO_BOOT;
939
940 if (bl_mode)
941 cmd.data = TO_BOOT;
942 else
943 cmd.data = TO_ALT_FW;
944
945 cmd.len = 1;
946 cmd.delay = 100;
947
948 mutex_lock(&uc->lock);
949
950 set_bit(RESET_PENDING, &uc->flags);
951
952 ret = ccg_send_command(uc, &cmd);
953 if (ret != RESET_COMPLETE)
954 goto err_clear_flag;
955
956 ret = 0;
957
958 err_clear_flag:
959 clear_bit(RESET_PENDING, &uc->flags);
960
961 mutex_unlock(&uc->lock);
962
963 return ret;
964 }
965
966 static int
ccg_cmd_write_flash_row(struct ucsi_ccg * uc,u16 row,const void * data,u8 fcmd)967 ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
968 const void *data, u8 fcmd)
969 {
970 struct i2c_client *client = uc->client;
971 struct ccg_cmd cmd;
972 u8 buf[CCG4_ROW_SIZE + 2];
973 u8 *p;
974 int ret;
975
976 /* Copy the data into the flash read/write memory. */
977 put_unaligned_le16(REG_FLASH_RW_MEM, buf);
978
979 memcpy(buf + 2, data, CCG4_ROW_SIZE);
980
981 mutex_lock(&uc->lock);
982
983 ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2);
984 if (ret != CCG4_ROW_SIZE + 2) {
985 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
986 mutex_unlock(&uc->lock);
987 return ret < 0 ? ret : -EIO;
988 }
989
990 /* Use the FLASH_ROW_READ_WRITE register to trigger */
991 /* writing of data to the desired flash row */
992 p = (u8 *)&cmd.data;
993 cmd.reg = CCGX_RAB_FLASH_ROW_RW;
994 p[0] = FLASH_SIG;
995 p[1] = fcmd;
996 put_unaligned_le16(row, &p[2]);
997 cmd.len = 4;
998 cmd.delay = 50;
999 if (fcmd == FLASH_FWCT_SIG_WR_CMD)
1000 cmd.delay += 400;
1001 if (row == 510)
1002 cmd.delay += 220;
1003 ret = ccg_send_command(uc, &cmd);
1004
1005 mutex_unlock(&uc->lock);
1006
1007 if (ret != CMD_SUCCESS) {
1008 dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
1009 return ret;
1010 }
1011
1012 return 0;
1013 }
1014
ccg_cmd_validate_fw(struct ucsi_ccg * uc,unsigned int fwid)1015 static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
1016 {
1017 struct ccg_cmd cmd;
1018 int ret;
1019
1020 cmd.reg = CCGX_RAB_VALIDATE_FW;
1021 cmd.data = fwid;
1022 cmd.len = 1;
1023 cmd.delay = 500;
1024
1025 mutex_lock(&uc->lock);
1026
1027 ret = ccg_send_command(uc, &cmd);
1028
1029 mutex_unlock(&uc->lock);
1030
1031 if (ret != CMD_SUCCESS)
1032 return ret;
1033
1034 return 0;
1035 }
1036
ccg_check_vendor_version(struct ucsi_ccg * uc,struct version_format * app,struct fw_config_table * fw_cfg)1037 static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
1038 struct version_format *app,
1039 struct fw_config_table *fw_cfg)
1040 {
1041 struct device *dev = uc->dev;
1042
1043 /* Check if the fw build is for supported vendors */
1044 if (le16_to_cpu(app->build) != uc->fw_build) {
1045 dev_info(dev, "current fw is not from supported vendor\n");
1046 return false;
1047 }
1048
1049 /* Check if the new fw build is for supported vendors */
1050 if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
1051 dev_info(dev, "new fw is not from supported vendor\n");
1052 return false;
1053 }
1054 return true;
1055 }
1056
ccg_check_fw_version(struct ucsi_ccg * uc,const char * fw_name,struct version_format * app)1057 static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
1058 struct version_format *app)
1059 {
1060 const struct firmware *fw = NULL;
1061 struct device *dev = uc->dev;
1062 struct fw_config_table fw_cfg;
1063 u32 cur_version, new_version;
1064 bool is_later = false;
1065
1066 if (request_firmware(&fw, fw_name, dev) != 0) {
1067 dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name);
1068 return false;
1069 }
1070
1071 /*
1072 * check if signed fw
1073 * last part of fw image is fw cfg table and signature
1074 */
1075 if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE)
1076 goto out_release_firmware;
1077
1078 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1079 sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg));
1080
1081 if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
1082 dev_info(dev, "not a signed image\n");
1083 goto out_release_firmware;
1084 }
1085
1086 /* compare input version with FWCT version */
1087 cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) |
1088 CCG_VERSION(app->ver);
1089
1090 new_version = le16_to_cpu(fw_cfg.app.build) |
1091 CCG_VERSION_PATCH(fw_cfg.app.patch) |
1092 CCG_VERSION(fw_cfg.app.ver);
1093
1094 if (!ccg_check_vendor_version(uc, app, &fw_cfg))
1095 goto out_release_firmware;
1096
1097 if (new_version > cur_version)
1098 is_later = true;
1099
1100 out_release_firmware:
1101 release_firmware(fw);
1102 return is_later;
1103 }
1104
ccg_fw_update_needed(struct ucsi_ccg * uc,enum enum_flash_mode * mode)1105 static int ccg_fw_update_needed(struct ucsi_ccg *uc,
1106 enum enum_flash_mode *mode)
1107 {
1108 struct device *dev = uc->dev;
1109 int err;
1110 struct version_info version[3];
1111
1112 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
1113 sizeof(uc->info));
1114 if (err) {
1115 dev_err(dev, "read device mode failed\n");
1116 return err;
1117 }
1118
1119 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
1120 sizeof(version));
1121 if (err) {
1122 dev_err(dev, "read device mode failed\n");
1123 return err;
1124 }
1125
1126 if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0",
1127 sizeof(struct version_info)) == 0) {
1128 dev_info(dev, "secondary fw is not flashed\n");
1129 *mode = SECONDARY_BL;
1130 } else if (le16_to_cpu(version[FW1].base.build) <
1131 secondary_fw_min_ver) {
1132 dev_info(dev, "secondary fw version is too low (< %d)\n",
1133 secondary_fw_min_ver);
1134 *mode = SECONDARY;
1135 } else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0",
1136 sizeof(struct version_info)) == 0) {
1137 dev_info(dev, "primary fw is not flashed\n");
1138 *mode = PRIMARY;
1139 } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
1140 &version[FW2].app)) {
1141 dev_info(dev, "found primary fw with later version\n");
1142 *mode = PRIMARY;
1143 } else {
1144 dev_info(dev, "secondary and primary fw are the latest\n");
1145 *mode = FLASH_NOT_NEEDED;
1146 }
1147 return 0;
1148 }
1149
do_flash(struct ucsi_ccg * uc,enum enum_flash_mode mode)1150 static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
1151 {
1152 struct device *dev = uc->dev;
1153 const struct firmware *fw = NULL;
1154 const char *p, *s;
1155 const char *eof;
1156 int err, row, len, line_sz, line_cnt = 0;
1157 unsigned long start_time = jiffies;
1158 struct fw_config_table fw_cfg;
1159 u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];
1160 u8 *wr_buf;
1161
1162 err = request_firmware(&fw, ccg_fw_names[mode], dev);
1163 if (err) {
1164 dev_err(dev, "request %s failed err=%d\n",
1165 ccg_fw_names[mode], err);
1166 return err;
1167 }
1168
1169 if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
1170 CCG_DEVINFO_FWMODE_SHIFT) == FW2) {
1171 err = ccg_cmd_port_control(uc, false);
1172 if (err < 0)
1173 goto release_fw;
1174 err = ccg_cmd_jump_boot_mode(uc, 0);
1175 if (err < 0)
1176 goto release_fw;
1177 }
1178
1179 eof = fw->data + fw->size;
1180
1181 /*
1182 * check if signed fw
1183 * last part of fw image is fw cfg table and signature
1184 */
1185 if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))
1186 goto not_signed_fw;
1187
1188 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1189 sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));
1190
1191 if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
1192 dev_info(dev, "not a signed image\n");
1193 goto not_signed_fw;
1194 }
1195 eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);
1196
1197 memcpy((uint8_t *)&fw_cfg_sig,
1198 fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));
1199
1200 /* flash fw config table and signature first */
1201 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
1202 FLASH_FWCT1_WR_CMD);
1203 if (err)
1204 goto release_fw;
1205
1206 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
1207 FLASH_FWCT2_WR_CMD);
1208 if (err)
1209 goto release_fw;
1210
1211 err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
1212 FLASH_FWCT_SIG_WR_CMD);
1213 if (err)
1214 goto release_fw;
1215
1216 not_signed_fw:
1217 wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);
1218 if (!wr_buf) {
1219 err = -ENOMEM;
1220 goto release_fw;
1221 }
1222
1223 err = ccg_cmd_enter_flashing(uc);
1224 if (err)
1225 goto release_mem;
1226
1227 /*****************************************************************
1228 * CCG firmware image (.cyacd) file line format
1229 *
1230 * :00rrrrllll[dd....]cc/r/n
1231 *
1232 * :00 header
1233 * rrrr is row number to flash (4 char)
1234 * llll is data len to flash (4 char)
1235 * dd is a data field represents one byte of data (512 char)
1236 * cc is checksum (2 char)
1237 * \r\n newline
1238 *
1239 * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527
1240 *
1241 *****************************************************************/
1242
1243 p = strnchr(fw->data, fw->size, ':');
1244 while (p < eof) {
1245 s = strnchr(p + 1, eof - p - 1, ':');
1246
1247 if (!s)
1248 s = eof;
1249
1250 line_sz = s - p;
1251
1252 if (line_sz != CYACD_LINE_SIZE) {
1253 dev_err(dev, "Bad FW format line_sz=%d\n", line_sz);
1254 err = -EINVAL;
1255 goto release_mem;
1256 }
1257
1258 if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {
1259 err = -EINVAL;
1260 goto release_mem;
1261 }
1262
1263 row = get_unaligned_be16(wr_buf);
1264 len = get_unaligned_be16(&wr_buf[2]);
1265
1266 if (len != CCG4_ROW_SIZE) {
1267 err = -EINVAL;
1268 goto release_mem;
1269 }
1270
1271 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
1272 FLASH_WR_CMD);
1273 if (err)
1274 goto release_mem;
1275
1276 line_cnt++;
1277 p = s;
1278 }
1279
1280 dev_info(dev, "total %d row flashed. time: %dms\n",
1281 line_cnt, jiffies_to_msecs(jiffies - start_time));
1282
1283 err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1);
1284 if (err)
1285 dev_err(dev, "%s validation failed err=%d\n",
1286 (mode == PRIMARY) ? "FW2" : "FW1", err);
1287 else
1288 dev_info(dev, "%s validated\n",
1289 (mode == PRIMARY) ? "FW2" : "FW1");
1290
1291 err = ccg_cmd_port_control(uc, false);
1292 if (err < 0)
1293 goto release_mem;
1294
1295 err = ccg_cmd_reset(uc);
1296 if (err < 0)
1297 goto release_mem;
1298
1299 err = ccg_cmd_port_control(uc, true);
1300 if (err < 0)
1301 goto release_mem;
1302
1303 release_mem:
1304 kfree(wr_buf);
1305
1306 release_fw:
1307 release_firmware(fw);
1308 return err;
1309 }
1310
1311 /*******************************************************************************
1312 * CCG4 has two copies of the firmware in addition to the bootloader.
1313 * If the device is running FW1, FW2 can be updated with the new version.
1314 * Dual firmware mode allows the CCG device to stay in a PD contract and support
1315 * USB PD and Type-C functionality while a firmware update is in progress.
1316 ******************************************************************************/
ccg_fw_update(struct ucsi_ccg * uc,enum enum_flash_mode flash_mode)1317 static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
1318 {
1319 int err = 0;
1320
1321 while (flash_mode != FLASH_NOT_NEEDED) {
1322 err = do_flash(uc, flash_mode);
1323 if (err < 0)
1324 return err;
1325 err = ccg_fw_update_needed(uc, &flash_mode);
1326 if (err < 0)
1327 return err;
1328 }
1329 dev_info(uc->dev, "CCG FW update successful\n");
1330
1331 return err;
1332 }
1333
ccg_restart(struct ucsi_ccg * uc)1334 static int ccg_restart(struct ucsi_ccg *uc)
1335 {
1336 struct device *dev = uc->dev;
1337 int status;
1338
1339 status = ucsi_ccg_init(uc);
1340 if (status < 0) {
1341 dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status);
1342 return status;
1343 }
1344
1345 status = ccg_request_irq(uc);
1346 if (status < 0) {
1347 dev_err(dev, "request_threaded_irq failed - %d\n", status);
1348 return status;
1349 }
1350
1351 status = ucsi_register(uc->ucsi);
1352 if (status) {
1353 dev_err(uc->dev, "failed to register the interface\n");
1354 return status;
1355 }
1356
1357 pm_runtime_enable(uc->dev);
1358 return 0;
1359 }
1360
ccg_update_firmware(struct work_struct * work)1361 static void ccg_update_firmware(struct work_struct *work)
1362 {
1363 struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
1364 enum enum_flash_mode flash_mode;
1365 int status;
1366
1367 status = ccg_fw_update_needed(uc, &flash_mode);
1368 if (status < 0)
1369 return;
1370
1371 if (flash_mode != FLASH_NOT_NEEDED) {
1372 ucsi_unregister(uc->ucsi);
1373 pm_runtime_disable(uc->dev);
1374 free_irq(uc->irq, uc);
1375
1376 ccg_fw_update(uc, flash_mode);
1377 ccg_restart(uc);
1378 }
1379 }
1380
do_flash_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1381 static ssize_t do_flash_store(struct device *dev,
1382 struct device_attribute *attr,
1383 const char *buf, size_t n)
1384 {
1385 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1386 bool flash;
1387
1388 if (kstrtobool(buf, &flash))
1389 return -EINVAL;
1390
1391 if (!flash)
1392 return n;
1393
1394 if (uc->fw_build == 0x0) {
1395 dev_err(dev, "fail to flash FW due to missing FW build info\n");
1396 return -EINVAL;
1397 }
1398
1399 schedule_work(&uc->work);
1400 return n;
1401 }
1402
1403 static DEVICE_ATTR_WO(do_flash);
1404
1405 static struct attribute *ucsi_ccg_attrs[] = {
1406 &dev_attr_do_flash.attr,
1407 NULL,
1408 };
1409 ATTRIBUTE_GROUPS(ucsi_ccg);
1410
ucsi_ccg_probe(struct i2c_client * client)1411 static int ucsi_ccg_probe(struct i2c_client *client)
1412 {
1413 struct device *dev = &client->dev;
1414 struct ucsi_ccg *uc;
1415 const char *fw_name;
1416 int status;
1417
1418 uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
1419 if (!uc)
1420 return -ENOMEM;
1421
1422 uc->dev = dev;
1423 uc->client = client;
1424 uc->irq = client->irq;
1425 mutex_init(&uc->lock);
1426 INIT_WORK(&uc->work, ccg_update_firmware);
1427 INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
1428
1429 /* Only fail FW flashing when FW build information is not provided */
1430 status = device_property_read_string(dev, "firmware-name", &fw_name);
1431 if (!status) {
1432 if (!strcmp(fw_name, "nvidia,jetson-agx-xavier"))
1433 uc->fw_build = CCG_FW_BUILD_NVIDIA_TEGRA;
1434 else if (!strcmp(fw_name, "nvidia,gpu"))
1435 uc->fw_build = CCG_FW_BUILD_NVIDIA;
1436 }
1437
1438 if (!uc->fw_build)
1439 dev_err(uc->dev, "failed to get FW build information\n");
1440
1441 /* reset ccg device and initialize ucsi */
1442 status = ucsi_ccg_init(uc);
1443 if (status < 0) {
1444 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
1445 return status;
1446 }
1447
1448 status = get_fw_info(uc);
1449 if (status < 0) {
1450 dev_err(uc->dev, "get_fw_info failed - %d\n", status);
1451 return status;
1452 }
1453
1454 uc->port_num = 1;
1455
1456 if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
1457 uc->port_num++;
1458
1459 uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
1460 if (IS_ERR(uc->ucsi))
1461 return PTR_ERR(uc->ucsi);
1462
1463 ucsi_set_drvdata(uc->ucsi, uc);
1464
1465 status = ccg_request_irq(uc);
1466 if (status < 0) {
1467 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
1468 goto out_ucsi_destroy;
1469 }
1470
1471 status = ucsi_register(uc->ucsi);
1472 if (status)
1473 goto out_free_irq;
1474
1475 i2c_set_clientdata(client, uc);
1476
1477 pm_runtime_set_active(uc->dev);
1478 pm_runtime_enable(uc->dev);
1479 pm_runtime_use_autosuspend(uc->dev);
1480 pm_runtime_set_autosuspend_delay(uc->dev, 5000);
1481 pm_runtime_idle(uc->dev);
1482
1483 return 0;
1484
1485 out_free_irq:
1486 free_irq(uc->irq, uc);
1487 out_ucsi_destroy:
1488 ucsi_destroy(uc->ucsi);
1489
1490 return status;
1491 }
1492
ucsi_ccg_remove(struct i2c_client * client)1493 static void ucsi_ccg_remove(struct i2c_client *client)
1494 {
1495 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1496
1497 cancel_work_sync(&uc->pm_work);
1498 cancel_work_sync(&uc->work);
1499 pm_runtime_disable(uc->dev);
1500 ucsi_unregister(uc->ucsi);
1501 ucsi_destroy(uc->ucsi);
1502 free_irq(uc->irq, uc);
1503 }
1504
1505 static const struct of_device_id ucsi_ccg_of_match_table[] = {
1506 { .compatible = "cypress,cypd4226", },
1507 { /* sentinel */ }
1508 };
1509 MODULE_DEVICE_TABLE(of, ucsi_ccg_of_match_table);
1510
1511 static const struct i2c_device_id ucsi_ccg_device_id[] = {
1512 { "ccgx-ucsi" },
1513 {}
1514 };
1515 MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
1516
1517 static const struct acpi_device_id amd_i2c_ucsi_match[] = {
1518 {"AMDI0042"},
1519 {}
1520 };
1521 MODULE_DEVICE_TABLE(acpi, amd_i2c_ucsi_match);
1522
ucsi_ccg_resume(struct device * dev)1523 static int ucsi_ccg_resume(struct device *dev)
1524 {
1525 struct i2c_client *client = to_i2c_client(dev);
1526 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1527
1528 return ucsi_resume(uc->ucsi);
1529 }
1530
ucsi_ccg_runtime_suspend(struct device * dev)1531 static int ucsi_ccg_runtime_suspend(struct device *dev)
1532 {
1533 return 0;
1534 }
1535
ucsi_ccg_runtime_resume(struct device * dev)1536 static int ucsi_ccg_runtime_resume(struct device *dev)
1537 {
1538 struct i2c_client *client = to_i2c_client(dev);
1539 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1540
1541 /*
1542 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
1543 * of missing interrupt when a device is connected for runtime resume.
1544 * Schedule a work to call ISR as a workaround.
1545 */
1546 if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
1547 uc->fw_version <= CCG_OLD_FW_VERSION)
1548 schedule_work(&uc->pm_work);
1549
1550 return 0;
1551 }
1552
1553 static const struct dev_pm_ops ucsi_ccg_pm = {
1554 .resume = ucsi_ccg_resume,
1555 .runtime_suspend = ucsi_ccg_runtime_suspend,
1556 .runtime_resume = ucsi_ccg_runtime_resume,
1557 };
1558
1559 static struct i2c_driver ucsi_ccg_driver = {
1560 .driver = {
1561 .name = "ucsi_ccg",
1562 .pm = &ucsi_ccg_pm,
1563 .dev_groups = ucsi_ccg_groups,
1564 .acpi_match_table = amd_i2c_ucsi_match,
1565 .of_match_table = ucsi_ccg_of_match_table,
1566 },
1567 .probe = ucsi_ccg_probe,
1568 .remove = ucsi_ccg_remove,
1569 .id_table = ucsi_ccg_device_id,
1570 };
1571
1572 module_i2c_driver(ucsi_ccg_driver);
1573
1574 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
1575 MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
1576 MODULE_LICENSE("GPL v2");
1577