1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RZ/V2H System controller (SYS) driver
4 *
5 * Copyright (C) 2025 Renesas Electronics Corp.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/device.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13
14 #include "rz-sysc.h"
15
16 /* Register Offsets */
17 #define SYS_LSI_MODE 0x300
18 /*
19 * BOOTPLLCA[1:0]
20 * [0,0] => 1.1GHZ
21 * [0,1] => 1.5GHZ
22 * [1,0] => 1.6GHZ
23 * [1,1] => 1.7GHZ
24 */
25 #define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
26 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
27
28 #define SYS_LSI_PRR 0x308
29 #define SYS_LSI_PRR_GPU_DIS BIT(0)
30 #define SYS_LSI_PRR_ISP_DIS BIT(4)
31
32 #define SYS_LSI_OTPTSU0TRMVAL0 0x320
33 #define SYS_LSI_OTPTSU0TRMVAL1 0x324
34 #define SYS_LSI_OTPTSU1TRMVAL0 0x330
35 #define SYS_LSI_OTPTSU1TRMVAL1 0x334
36 #define SYS_GBETH0_CFG 0xf00
37 #define SYS_GBETH1_CFG 0xf04
38 #define SYS_PCIE_INTX_CH0 0x1000
39 #define SYS_PCIE_MSI1_CH0 0x1004
40 #define SYS_PCIE_MSI2_CH0 0x1008
41 #define SYS_PCIE_MSI3_CH0 0x100c
42 #define SYS_PCIE_MSI4_CH0 0x1010
43 #define SYS_PCIE_MSI5_CH0 0x1014
44 #define SYS_PCIE_PME_CH0 0x1018
45 #define SYS_PCIE_ACK_CH0 0x101c
46 #define SYS_PCIE_MISC_CH0 0x1020
47 #define SYS_PCIE_MODE_CH0 0x1024
48 #define SYS_PCIE_INTX_CH1 0x1030
49 #define SYS_PCIE_MSI1_CH1 0x1034
50 #define SYS_PCIE_MSI2_CH1 0x1038
51 #define SYS_PCIE_MSI3_CH1 0x103c
52 #define SYS_PCIE_MSI4_CH1 0x1040
53 #define SYS_PCIE_MSI5_CH1 0x1044
54 #define SYS_PCIE_PME_CH1 0x1048
55 #define SYS_PCIE_ACK_CH1 0x104c
56 #define SYS_PCIE_MISC_CH1 0x1050
57 #define SYS_PCIE_MODE_CH1 0x1054
58 #define SYS_PCIE_MODE 0x1060
59 #define SYS_ADC_CFG 0x1600
60
rzv2h_sys_print_id(struct device * dev,void __iomem * sysc_base,struct soc_device_attribute * soc_dev_attr)61 static void rzv2h_sys_print_id(struct device *dev,
62 void __iomem *sysc_base,
63 struct soc_device_attribute *soc_dev_attr)
64 {
65 bool gpu_enabled, isp_enabled;
66 u32 prr_val, mode_val;
67
68 prr_val = readl(sysc_base + SYS_LSI_PRR);
69 mode_val = readl(sysc_base + SYS_LSI_MODE);
70
71 /* Check GPU and ISP configuration */
72 gpu_enabled = !(prr_val & SYS_LSI_PRR_GPU_DIS);
73 isp_enabled = !(prr_val & SYS_LSI_PRR_ISP_DIS);
74
75 dev_info(dev, "Detected Renesas %s %s Rev %s%s%s\n",
76 soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision,
77 gpu_enabled ? " with GE3D (Mali-G31)" : "",
78 isp_enabled ? " with ISP (Mali-C55)" : "");
79
80 /* Check CA55 PLL configuration */
81 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
82 dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
83 }
84
85 static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initconst = {
86 .family = "RZ/V2H",
87 .id = 0x847a447,
88 .devid_offset = 0x304,
89 .revision_mask = GENMASK(31, 28),
90 .specific_id_mask = GENMASK(27, 0),
91 .print_id = rzv2h_sys_print_id,
92 };
93
rzv2h_regmap_readable_reg(struct device * dev,unsigned int reg)94 static bool rzv2h_regmap_readable_reg(struct device *dev, unsigned int reg)
95 {
96 switch (reg) {
97 case SYS_LSI_OTPTSU0TRMVAL0:
98 case SYS_LSI_OTPTSU0TRMVAL1:
99 case SYS_LSI_OTPTSU1TRMVAL0:
100 case SYS_LSI_OTPTSU1TRMVAL1:
101 case SYS_GBETH0_CFG:
102 case SYS_GBETH1_CFG:
103 case SYS_PCIE_INTX_CH0:
104 case SYS_PCIE_MSI1_CH0:
105 case SYS_PCIE_MSI2_CH0:
106 case SYS_PCIE_MSI3_CH0:
107 case SYS_PCIE_MSI4_CH0:
108 case SYS_PCIE_MSI5_CH0:
109 case SYS_PCIE_PME_CH0:
110 case SYS_PCIE_ACK_CH0:
111 case SYS_PCIE_MISC_CH0:
112 case SYS_PCIE_MODE_CH0:
113 case SYS_PCIE_INTX_CH1:
114 case SYS_PCIE_MSI1_CH1:
115 case SYS_PCIE_MSI2_CH1:
116 case SYS_PCIE_MSI3_CH1:
117 case SYS_PCIE_MSI4_CH1:
118 case SYS_PCIE_MSI5_CH1:
119 case SYS_PCIE_PME_CH1:
120 case SYS_PCIE_ACK_CH1:
121 case SYS_PCIE_MISC_CH1:
122 case SYS_PCIE_MODE_CH1:
123 case SYS_PCIE_MODE:
124 case SYS_ADC_CFG:
125 return true;
126 default:
127 return false;
128 }
129 }
130
rzv2h_regmap_writeable_reg(struct device * dev,unsigned int reg)131 static bool rzv2h_regmap_writeable_reg(struct device *dev, unsigned int reg)
132 {
133 switch (reg) {
134 case SYS_GBETH0_CFG:
135 case SYS_GBETH1_CFG:
136 case SYS_PCIE_INTX_CH0:
137 case SYS_PCIE_MSI1_CH0:
138 case SYS_PCIE_MSI2_CH0:
139 case SYS_PCIE_MSI3_CH0:
140 case SYS_PCIE_MSI4_CH0:
141 case SYS_PCIE_MSI5_CH0:
142 case SYS_PCIE_PME_CH0:
143 case SYS_PCIE_ACK_CH0:
144 case SYS_PCIE_MISC_CH0:
145 case SYS_PCIE_MODE_CH0:
146 case SYS_PCIE_INTX_CH1:
147 case SYS_PCIE_MSI1_CH1:
148 case SYS_PCIE_MSI2_CH1:
149 case SYS_PCIE_MSI3_CH1:
150 case SYS_PCIE_MSI4_CH1:
151 case SYS_PCIE_MSI5_CH1:
152 case SYS_PCIE_PME_CH1:
153 case SYS_PCIE_ACK_CH1:
154 case SYS_PCIE_MISC_CH1:
155 case SYS_PCIE_MODE_CH1:
156 case SYS_PCIE_MODE:
157 case SYS_ADC_CFG:
158 return true;
159 default:
160 return false;
161 }
162 }
163
164 const struct rz_sysc_init_data rzv2h_sys_init_data = {
165 .soc_id_init_data = &rzv2h_sys_soc_id_init_data,
166 .readable_reg = rzv2h_regmap_readable_reg,
167 .writeable_reg = rzv2h_regmap_writeable_reg,
168 .max_register = 0x170c,
169 };
170