1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clocks = <&clk IMX8MN_CLK_ARM>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&A53_L2>; 74 operating-points-v2 = <&a53_opp_table>; 75 nvmem-cells = <&cpu_speed_grade>; 76 nvmem-cell-names = "speed_grade"; 77 cpu-idle-states = <&cpu_pd_wait>; 78 #cooling-cells = <2>; 79 }; 80 81 A53_1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x1>; 85 clocks = <&clk IMX8MN_CLK_ARM>; 86 enable-method = "psci"; 87 i-cache-size = <0x8000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&A53_L2>; 94 operating-points-v2 = <&a53_opp_table>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 #cooling-cells = <2>; 97 }; 98 99 A53_2: cpu@2 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x2>; 103 clocks = <&clk IMX8MN_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 operating-points-v2 = <&a53_opp_table>; 113 cpu-idle-states = <&cpu_pd_wait>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x3>; 121 clocks = <&clk IMX8MN_CLK_ARM>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 cpu-idle-states = <&cpu_pd_wait>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_L2: l2-cache0 { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 cache-size = <0x80000>; 140 cache-line-size = <64>; 141 cache-sets = <512>; 142 }; 143 }; 144 145 a53_opp_table: opp-table { 146 compatible = "operating-points-v2"; 147 opp-shared; 148 149 opp-1200000000 { 150 opp-hz = /bits/ 64 <1200000000>; 151 opp-microvolt = <850000>; 152 opp-supported-hw = <0xb00>, <0x7>; 153 clock-latency-ns = <150000>; 154 opp-suspend; 155 }; 156 157 opp-1400000000 { 158 opp-hz = /bits/ 64 <1400000000>; 159 opp-microvolt = <950000>; 160 opp-supported-hw = <0x300>, <0x7>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1500000000 { 166 opp-hz = /bits/ 64 <1500000000>; 167 opp-microvolt = <1000000>; 168 opp-supported-hw = <0x100>, <0x3>; 169 clock-latency-ns = <150000>; 170 opp-suspend; 171 }; 172 }; 173 174 osc_32k: clock-osc-32k { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <32768>; 178 clock-output-names = "osc_32k"; 179 }; 180 181 osc_24m: clock-osc-24m { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <24000000>; 185 clock-output-names = "osc_24m"; 186 }; 187 188 clk_ext1: clock-ext1 { 189 compatible = "fixed-clock"; 190 #clock-cells = <0>; 191 clock-frequency = <133000000>; 192 clock-output-names = "clk_ext1"; 193 }; 194 195 clk_ext2: clock-ext2 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <133000000>; 199 clock-output-names = "clk_ext2"; 200 }; 201 202 clk_ext3: clock-ext3 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <133000000>; 206 clock-output-names = "clk_ext3"; 207 }; 208 209 clk_ext4: clock-ext4 { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <133000000>; 213 clock-output-names = "clk_ext4"; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 psci { 222 compatible = "arm,psci-1.0"; 223 method = "smc"; 224 }; 225 226 thermal-zones { 227 cpu-thermal { 228 polling-delay-passive = <250>; 229 polling-delay = <2000>; 230 thermal-sensors = <&tmu>; 231 trips { 232 cpu_alert0: trip0 { 233 temperature = <85000>; 234 hysteresis = <2000>; 235 type = "passive"; 236 }; 237 238 cpu_crit0: trip1 { 239 temperature = <95000>; 240 hysteresis = <2000>; 241 type = "critical"; 242 }; 243 }; 244 245 cooling-maps { 246 map0 { 247 trip = <&cpu_alert0>; 248 cooling-device = 249 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 250 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 253 }; 254 }; 255 }; 256 }; 257 258 timer { 259 compatible = "arm,armv8-timer"; 260 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 261 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 262 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 263 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 264 clock-frequency = <8000000>; 265 arm,no-tick-in-suspend; 266 }; 267 268 soc: soc@0 { 269 compatible = "fsl,imx8mn-soc", "simple-bus"; 270 #address-cells = <1>; 271 #size-cells = <1>; 272 ranges = <0x0 0x0 0x0 0x3e000000>; 273 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 274 nvmem-cells = <&imx8mn_uid>; 275 nvmem-cell-names = "soc_unique_id"; 276 277 aips1: bus@30000000 { 278 compatible = "fsl,aips-bus", "simple-bus"; 279 reg = <0x30000000 0x400000>; 280 #address-cells = <1>; 281 #size-cells = <1>; 282 ranges; 283 284 spba2: spba-bus@30000000 { 285 compatible = "fsl,spba-bus", "simple-bus"; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 reg = <0x30000000 0x100000>; 289 ranges; 290 291 sai2: sai@30020000 { 292 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 293 reg = <0x30020000 0x10000>; 294 #sound-dai-cells = <0>; 295 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 297 <&clk IMX8MN_CLK_DUMMY>, 298 <&clk IMX8MN_CLK_SAI2_ROOT>, 299 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 300 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 301 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 302 dma-names = "rx", "tx"; 303 status = "disabled"; 304 }; 305 306 sai3: sai@30030000 { 307 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 308 reg = <0x30030000 0x10000>; 309 #sound-dai-cells = <0>; 310 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 312 <&clk IMX8MN_CLK_DUMMY>, 313 <&clk IMX8MN_CLK_SAI3_ROOT>, 314 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 315 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 316 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 317 dma-names = "rx", "tx"; 318 status = "disabled"; 319 }; 320 321 sai5: sai@30050000 { 322 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 323 reg = <0x30050000 0x10000>; 324 #sound-dai-cells = <0>; 325 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 327 <&clk IMX8MN_CLK_DUMMY>, 328 <&clk IMX8MN_CLK_SAI5_ROOT>, 329 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 330 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 331 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 332 dma-names = "rx", "tx"; 333 fsl,shared-interrupt; 334 fsl,dataline = <0 0xf 0xf>; 335 status = "disabled"; 336 }; 337 338 sai6: sai@30060000 { 339 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 340 reg = <0x30060000 0x10000>; 341 #sound-dai-cells = <0>; 342 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 344 <&clk IMX8MN_CLK_DUMMY>, 345 <&clk IMX8MN_CLK_SAI6_ROOT>, 346 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 347 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 349 dma-names = "rx", "tx"; 350 status = "disabled"; 351 }; 352 353 micfil: audio-controller@30080000 { 354 compatible = "fsl,imx8mm-micfil"; 355 reg = <0x30080000 0x10000>; 356 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 361 <&clk IMX8MN_CLK_PDM_ROOT>, 362 <&clk IMX8MN_AUDIO_PLL1_OUT>, 363 <&clk IMX8MN_AUDIO_PLL2_OUT>, 364 <&clk IMX8MN_CLK_EXT3>; 365 clock-names = "ipg_clk", "ipg_clk_app", 366 "pll8k", "pll11k", "clkext3"; 367 dmas = <&sdma2 24 25 0x80000000>; 368 dma-names = "rx"; 369 #sound-dai-cells = <0>; 370 status = "disabled"; 371 }; 372 373 spdif1: spdif@30090000 { 374 compatible = "fsl,imx35-spdif"; 375 reg = <0x30090000 0x10000>; 376 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 378 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 379 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 380 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 382 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 383 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 386 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 387 clock-names = "core", "rxtx0", 388 "rxtx1", "rxtx2", 389 "rxtx3", "rxtx4", 390 "rxtx5", "rxtx6", 391 "rxtx7", "spba"; 392 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 393 dma-names = "rx", "tx"; 394 status = "disabled"; 395 }; 396 397 sai7: sai@300b0000 { 398 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 399 reg = <0x300b0000 0x10000>; 400 #sound-dai-cells = <0>; 401 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 403 <&clk IMX8MN_CLK_DUMMY>, 404 <&clk IMX8MN_CLK_SAI7_ROOT>, 405 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 406 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 407 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 408 dma-names = "rx", "tx"; 409 status = "disabled"; 410 }; 411 412 easrc: easrc@300c0000 { 413 compatible = "fsl,imx8mn-easrc"; 414 reg = <0x300c0000 0x10000>; 415 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 417 clock-names = "mem"; 418 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 419 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 420 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 421 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 422 dma-names = "ctx0_rx", "ctx0_tx", 423 "ctx1_rx", "ctx1_tx", 424 "ctx2_rx", "ctx2_tx", 425 "ctx3_rx", "ctx3_tx"; 426 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 427 fsl,asrc-rate = <8000>; 428 fsl,asrc-format = <2>; 429 status = "disabled"; 430 }; 431 }; 432 433 gpio1: gpio@30200000 { 434 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 435 reg = <0x30200000 0x10000>; 436 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 gpio-ranges = <&iomuxc 0 10 30>; 444 }; 445 446 gpio2: gpio@30210000 { 447 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 448 reg = <0x30210000 0x10000>; 449 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 gpio-ranges = <&iomuxc 0 40 21>; 457 }; 458 459 gpio3: gpio@30220000 { 460 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 461 reg = <0x30220000 0x10000>; 462 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 gpio-ranges = <&iomuxc 0 61 26>; 470 }; 471 472 gpio4: gpio@30230000 { 473 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 474 reg = <0x30230000 0x10000>; 475 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 478 gpio-controller; 479 #gpio-cells = <2>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 gpio-ranges = <&iomuxc 21 108 11>; 483 }; 484 485 gpio5: gpio@30240000 { 486 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 487 reg = <0x30240000 0x10000>; 488 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 gpio-ranges = <&iomuxc 0 119 30>; 496 }; 497 498 tmu: tmu@30260000 { 499 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 500 reg = <0x30260000 0x10000>; 501 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 502 nvmem-cells = <&tmu_calib>; 503 nvmem-cell-names = "calib"; 504 #thermal-sensor-cells = <0>; 505 }; 506 507 wdog1: watchdog@30280000 { 508 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 509 reg = <0x30280000 0x10000>; 510 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 512 status = "disabled"; 513 }; 514 515 wdog2: watchdog@30290000 { 516 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 517 reg = <0x30290000 0x10000>; 518 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 520 status = "disabled"; 521 }; 522 523 wdog3: watchdog@302a0000 { 524 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 525 reg = <0x302a0000 0x10000>; 526 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 528 status = "disabled"; 529 }; 530 531 sdma3: dma-controller@302b0000 { 532 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 533 reg = <0x302b0000 0x10000>; 534 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 536 <&clk IMX8MN_CLK_SDMA3_ROOT>; 537 clock-names = "ipg", "ahb"; 538 #dma-cells = <3>; 539 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 540 }; 541 542 sdma2: dma-controller@302c0000 { 543 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 544 reg = <0x302c0000 0x10000>; 545 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 547 <&clk IMX8MN_CLK_SDMA2_ROOT>; 548 clock-names = "ipg", "ahb"; 549 #dma-cells = <3>; 550 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 551 }; 552 553 iomuxc: pinctrl@30330000 { 554 compatible = "fsl,imx8mn-iomuxc"; 555 reg = <0x30330000 0x10000>; 556 }; 557 558 gpr: syscon@30340000 { 559 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 560 reg = <0x30340000 0x10000>; 561 }; 562 563 ocotp: efuse@30350000 { 564 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 565 reg = <0x30350000 0x10000>; 566 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 570 /* 571 * The register address below maps to the MX8M 572 * Fusemap Description Table entries this way. 573 * Assuming 574 * reg = <ADDR SIZE>; 575 * then 576 * Fuse Address = (ADDR * 4) + 0x400 577 * Note that if SIZE is greater than 4, then 578 * each subsequent fuse is located at offset 579 * +0x10 in Fusemap Description Table (e.g. 580 * reg = <0x4 0x8> describes fuses 0x410 and 581 * 0x420). 582 */ 583 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ 584 reg = <0x4 0x8>; 585 }; 586 587 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 588 reg = <0x10 4>; 589 }; 590 591 tmu_calib: calib@3c { /* 0x4f0 */ 592 reg = <0x3c 4>; 593 }; 594 595 fec_mac_address: mac-address@90 { /* 0x640 */ 596 reg = <0x90 6>; 597 }; 598 }; 599 600 anatop: clock-controller@30360000 { 601 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; 602 reg = <0x30360000 0x10000>; 603 #clock-cells = <1>; 604 }; 605 606 snvs: snvs@30370000 { 607 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 608 reg = <0x30370000 0x10000>; 609 610 snvs_rtc: snvs-rtc-lp { 611 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 612 regmap = <&snvs>; 613 offset = <0x34>; 614 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 617 clock-names = "snvs-rtc"; 618 }; 619 620 snvs_pwrkey: snvs-powerkey { 621 compatible = "fsl,sec-v4.0-pwrkey"; 622 regmap = <&snvs>; 623 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 625 clock-names = "snvs-pwrkey"; 626 linux,keycode = <KEY_POWER>; 627 wakeup-source; 628 status = "disabled"; 629 }; 630 631 snvs_lpgpr: snvs-lpgpr { 632 compatible = "fsl,imx8mn-snvs-lpgpr", 633 "fsl,imx7d-snvs-lpgpr"; 634 }; 635 }; 636 637 clk: clock-controller@30380000 { 638 compatible = "fsl,imx8mn-ccm"; 639 reg = <0x30380000 0x10000>; 640 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 642 #clock-cells = <1>; 643 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 644 <&clk_ext3>, <&clk_ext4>; 645 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 646 "clk_ext3", "clk_ext4"; 647 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 648 <&clk IMX8MN_CLK_A53_CORE>, 649 <&clk IMX8MN_CLK_NOC>, 650 <&clk IMX8MN_CLK_AUDIO_AHB>, 651 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 652 <&clk IMX8MN_SYS_PLL3>, 653 <&clk IMX8MN_AUDIO_PLL1>, 654 <&clk IMX8MN_AUDIO_PLL2>; 655 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 656 <&clk IMX8MN_ARM_PLL_OUT>, 657 <&clk IMX8MN_SYS_PLL3_OUT>, 658 <&clk IMX8MN_SYS_PLL1_800M>; 659 assigned-clock-rates = <0>, <0>, <0>, 660 <400000000>, 661 <400000000>, 662 <600000000>, 663 <393216000>, 664 <361267200>; 665 }; 666 667 src: reset-controller@30390000 { 668 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 669 reg = <0x30390000 0x10000>; 670 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 671 #reset-cells = <1>; 672 }; 673 674 gpc: gpc@303a0000 { 675 compatible = "fsl,imx8mn-gpc"; 676 reg = <0x303a0000 0x10000>; 677 interrupt-parent = <&gic>; 678 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 679 680 pgc { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 684 pgc_hsiomix: power-domain@0 { 685 #power-domain-cells = <0>; 686 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 687 clocks = <&clk IMX8MN_CLK_USB_BUS>; 688 }; 689 690 pgc_otg1: power-domain@1 { 691 #power-domain-cells = <0>; 692 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 693 }; 694 695 pgc_gpumix: power-domain@2 { 696 #power-domain-cells = <0>; 697 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 698 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 699 <&clk IMX8MN_CLK_GPU_SHADER>, 700 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 701 <&clk IMX8MN_CLK_GPU_AHB>; 702 }; 703 704 pgc_dispmix: power-domain@3 { 705 #power-domain-cells = <0>; 706 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 707 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 708 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 709 }; 710 711 pgc_mipi: power-domain@4 { 712 #power-domain-cells = <0>; 713 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 714 power-domains = <&pgc_dispmix>; 715 }; 716 }; 717 }; 718 }; 719 720 aips2: bus@30400000 { 721 compatible = "fsl,aips-bus", "simple-bus"; 722 reg = <0x30400000 0x400000>; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 ranges; 726 727 pwm1: pwm@30660000 { 728 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 729 reg = <0x30660000 0x10000>; 730 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 732 <&clk IMX8MN_CLK_PWM1_ROOT>; 733 clock-names = "ipg", "per"; 734 #pwm-cells = <3>; 735 status = "disabled"; 736 }; 737 738 pwm2: pwm@30670000 { 739 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 740 reg = <0x30670000 0x10000>; 741 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 743 <&clk IMX8MN_CLK_PWM2_ROOT>; 744 clock-names = "ipg", "per"; 745 #pwm-cells = <3>; 746 status = "disabled"; 747 }; 748 749 pwm3: pwm@30680000 { 750 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 751 reg = <0x30680000 0x10000>; 752 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 754 <&clk IMX8MN_CLK_PWM3_ROOT>; 755 clock-names = "ipg", "per"; 756 #pwm-cells = <3>; 757 status = "disabled"; 758 }; 759 760 pwm4: pwm@30690000 { 761 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 762 reg = <0x30690000 0x10000>; 763 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 765 <&clk IMX8MN_CLK_PWM4_ROOT>; 766 clock-names = "ipg", "per"; 767 #pwm-cells = <3>; 768 status = "disabled"; 769 }; 770 771 system_counter: timer@306a0000 { 772 compatible = "nxp,sysctr-timer"; 773 reg = <0x306a0000 0x20000>; 774 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&osc_24m>; 776 clock-names = "per"; 777 }; 778 }; 779 780 aips3: bus@30800000 { 781 compatible = "fsl,aips-bus", "simple-bus"; 782 reg = <0x30800000 0x400000>; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 ranges; 786 787 spba1: spba-bus@30800000 { 788 compatible = "fsl,spba-bus", "simple-bus"; 789 #address-cells = <1>; 790 #size-cells = <1>; 791 reg = <0x30800000 0x100000>; 792 ranges; 793 794 ecspi1: spi@30820000 { 795 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 reg = <0x30820000 0x10000>; 799 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 801 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 802 clock-names = "ipg", "per"; 803 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 804 dma-names = "rx", "tx"; 805 status = "disabled"; 806 }; 807 808 ecspi2: spi@30830000 { 809 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 reg = <0x30830000 0x10000>; 813 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 815 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 816 clock-names = "ipg", "per"; 817 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 818 dma-names = "rx", "tx"; 819 status = "disabled"; 820 }; 821 822 ecspi3: spi@30840000 { 823 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <0x30840000 0x10000>; 827 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 829 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 830 clock-names = "ipg", "per"; 831 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 832 dma-names = "rx", "tx"; 833 status = "disabled"; 834 }; 835 836 uart1: serial@30860000 { 837 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 838 reg = <0x30860000 0x10000>; 839 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 841 <&clk IMX8MN_CLK_UART1_ROOT>; 842 clock-names = "ipg", "per"; 843 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 844 dma-names = "rx", "tx"; 845 status = "disabled"; 846 }; 847 848 uart3: serial@30880000 { 849 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 850 reg = <0x30880000 0x10000>; 851 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 853 <&clk IMX8MN_CLK_UART3_ROOT>; 854 clock-names = "ipg", "per"; 855 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 856 dma-names = "rx", "tx"; 857 status = "disabled"; 858 }; 859 860 uart2: serial@30890000 { 861 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 862 reg = <0x30890000 0x10000>; 863 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 865 <&clk IMX8MN_CLK_UART2_ROOT>; 866 clock-names = "ipg", "per"; 867 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 868 dma-names = "rx", "tx"; 869 status = "disabled"; 870 }; 871 }; 872 873 crypto: crypto@30900000 { 874 compatible = "fsl,sec-v4.0"; 875 #address-cells = <1>; 876 #size-cells = <1>; 877 reg = <0x30900000 0x40000>; 878 ranges = <0 0x30900000 0x40000>; 879 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&clk IMX8MN_CLK_AHB>, 881 <&clk IMX8MN_CLK_IPG_ROOT>; 882 clock-names = "aclk", "ipg"; 883 884 sec_jr0: jr@1000 { 885 compatible = "fsl,sec-v4.0-job-ring"; 886 reg = <0x1000 0x1000>; 887 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 888 status = "disabled"; 889 }; 890 891 sec_jr1: jr@2000 { 892 compatible = "fsl,sec-v4.0-job-ring"; 893 reg = <0x2000 0x1000>; 894 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 895 }; 896 897 sec_jr2: jr@3000 { 898 compatible = "fsl,sec-v4.0-job-ring"; 899 reg = <0x3000 0x1000>; 900 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 901 }; 902 }; 903 904 i2c1: i2c@30a20000 { 905 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 reg = <0x30a20000 0x10000>; 909 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 911 status = "disabled"; 912 }; 913 914 i2c2: i2c@30a30000 { 915 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 reg = <0x30a30000 0x10000>; 919 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 921 status = "disabled"; 922 }; 923 924 i2c3: i2c@30a40000 { 925 #address-cells = <1>; 926 #size-cells = <0>; 927 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 928 reg = <0x30a40000 0x10000>; 929 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 931 status = "disabled"; 932 }; 933 934 i2c4: i2c@30a50000 { 935 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 reg = <0x30a50000 0x10000>; 939 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 941 status = "disabled"; 942 }; 943 944 uart4: serial@30a60000 { 945 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 946 reg = <0x30a60000 0x10000>; 947 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 949 <&clk IMX8MN_CLK_UART4_ROOT>; 950 clock-names = "ipg", "per"; 951 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 952 dma-names = "rx", "tx"; 953 status = "disabled"; 954 }; 955 956 mu: mailbox@30aa0000 { 957 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 958 reg = <0x30aa0000 0x10000>; 959 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 961 #mbox-cells = <2>; 962 }; 963 964 usdhc1: mmc@30b40000 { 965 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 966 reg = <0x30b40000 0x10000>; 967 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 969 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 970 <&clk IMX8MN_CLK_USDHC1_ROOT>; 971 clock-names = "ipg", "ahb", "per"; 972 fsl,tuning-start-tap = <20>; 973 fsl,tuning-step = <2>; 974 bus-width = <4>; 975 status = "disabled"; 976 }; 977 978 usdhc2: mmc@30b50000 { 979 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 980 reg = <0x30b50000 0x10000>; 981 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 983 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 984 <&clk IMX8MN_CLK_USDHC2_ROOT>; 985 clock-names = "ipg", "ahb", "per"; 986 fsl,tuning-start-tap = <20>; 987 fsl,tuning-step = <2>; 988 bus-width = <4>; 989 status = "disabled"; 990 }; 991 992 usdhc3: mmc@30b60000 { 993 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 994 reg = <0x30b60000 0x10000>; 995 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 997 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 998 <&clk IMX8MN_CLK_USDHC3_ROOT>; 999 clock-names = "ipg", "ahb", "per"; 1000 fsl,tuning-start-tap = <20>; 1001 fsl,tuning-step = <2>; 1002 bus-width = <4>; 1003 status = "disabled"; 1004 }; 1005 1006 flexspi: spi@30bb0000 { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 compatible = "nxp,imx8mm-fspi"; 1010 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1011 reg-names = "fspi_base", "fspi_mmap"; 1012 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 1014 <&clk IMX8MN_CLK_QSPI_ROOT>; 1015 clock-names = "fspi_en", "fspi"; 1016 status = "disabled"; 1017 }; 1018 1019 sdma1: dma-controller@30bd0000 { 1020 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 1021 reg = <0x30bd0000 0x10000>; 1022 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 1024 <&clk IMX8MN_CLK_AHB>; 1025 clock-names = "ipg", "ahb"; 1026 #dma-cells = <3>; 1027 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1028 }; 1029 1030 fec1: ethernet@30be0000 { 1031 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1032 reg = <0x30be0000 0x10000>; 1033 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 1038 <&clk IMX8MN_CLK_ENET1_ROOT>, 1039 <&clk IMX8MN_CLK_ENET_TIMER>, 1040 <&clk IMX8MN_CLK_ENET_REF>, 1041 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1042 clock-names = "ipg", "ahb", "ptp", 1043 "enet_clk_ref", "enet_out"; 1044 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 1045 <&clk IMX8MN_CLK_ENET_TIMER>, 1046 <&clk IMX8MN_CLK_ENET_REF>, 1047 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1048 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1049 <&clk IMX8MN_SYS_PLL2_100M>, 1050 <&clk IMX8MN_SYS_PLL2_125M>, 1051 <&clk IMX8MN_SYS_PLL2_50M>; 1052 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1053 fsl,num-tx-queues = <3>; 1054 fsl,num-rx-queues = <3>; 1055 nvmem-cells = <&fec_mac_address>; 1056 nvmem-cell-names = "mac-address"; 1057 fsl,stop-mode = <&gpr 0x10 3>; 1058 status = "disabled"; 1059 }; 1060 1061 }; 1062 1063 aips4: bus@32c00000 { 1064 compatible = "fsl,aips-bus", "simple-bus"; 1065 reg = <0x32c00000 0x400000>; 1066 #address-cells = <1>; 1067 #size-cells = <1>; 1068 ranges; 1069 1070 lcdif: lcdif@32e00000 { 1071 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; 1072 reg = <0x32e00000 0x10000>; 1073 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1074 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1075 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1076 clock-names = "pix", "axi", "disp_axi"; 1077 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; 1079 status = "disabled"; 1080 1081 port { 1082 lcdif_to_dsim: endpoint { 1083 remote-endpoint = <&dsim_from_lcdif>; 1084 }; 1085 }; 1086 }; 1087 1088 mipi_dsi: dsi@32e10000 { 1089 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 1090 reg = <0x32e10000 0x400>; 1091 clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1092 <&clk IMX8MN_CLK_DSI_PHY_REF>; 1093 clock-names = "bus_clk", "sclk_mipi"; 1094 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1095 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; 1096 status = "disabled"; 1097 1098 ports { 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 1102 port@0 { 1103 reg = <0>; 1104 1105 dsim_from_lcdif: endpoint { 1106 remote-endpoint = <&lcdif_to_dsim>; 1107 }; 1108 }; 1109 1110 port@1 { 1111 reg = <1>; 1112 1113 mipi_dsi_out: endpoint { 1114 }; 1115 }; 1116 }; 1117 }; 1118 1119 isi: isi@32e20000 { 1120 compatible = "fsl,imx8mn-isi"; 1121 reg = <0x32e20000 0x8000>; 1122 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1124 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 1125 clock-names = "axi", "apb"; 1126 fsl,blk-ctrl = <&disp_blk_ctrl>; 1127 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; 1128 status = "disabled"; 1129 1130 ports { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 port@0 { 1135 reg = <0>; 1136 isi_in: endpoint { 1137 remote-endpoint = <&mipi_csi_out>; 1138 }; 1139 }; 1140 }; 1141 }; 1142 1143 disp_blk_ctrl: blk-ctrl@32e28000 { 1144 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 1145 reg = <0x32e28000 0x100>; 1146 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1147 <&pgc_dispmix>, <&pgc_mipi>, 1148 <&pgc_mipi>; 1149 power-domain-names = "bus", "isi", 1150 "lcdif", "mipi-dsi", 1151 "mipi-csi"; 1152 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 1153 <&clk IMX8MN_CLK_DISP_APB>, 1154 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1155 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1156 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1157 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1158 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1159 <&clk IMX8MN_CLK_DSI_CORE>, 1160 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1161 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1162 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 1163 clock-names = "disp_axi", "disp_apb", 1164 "disp_axi_root", "disp_apb_root", 1165 "lcdif-axi", "lcdif-apb", "lcdif-pix", 1166 "dsi-pclk", "dsi-ref", 1167 "csi-aclk", "csi-pclk"; 1168 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1169 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1170 <&clk IMX8MN_CLK_DISP_PIXEL>, 1171 <&clk IMX8MN_CLK_DISP_AXI>, 1172 <&clk IMX8MN_CLK_DISP_APB>; 1173 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1174 <&clk IMX8MN_CLK_24M>, 1175 <&clk IMX8MN_VIDEO_PLL1_OUT>, 1176 <&clk IMX8MN_SYS_PLL2_1000M>, 1177 <&clk IMX8MN_SYS_PLL1_800M>; 1178 assigned-clock-rates = <266000000>, 1179 <24000000>, 1180 <24000000>, 1181 <500000000>, 1182 <200000000>; 1183 #power-domain-cells = <1>; 1184 }; 1185 1186 mipi_csi: mipi-csi@32e30000 { 1187 compatible = "fsl,imx8mm-mipi-csi2"; 1188 reg = <0x32e30000 0x1000>; 1189 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1190 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; 1191 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; 1192 assigned-clock-rates = <333000000>; 1193 clock-frequency = <333000000>; 1194 clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1195 <&clk IMX8MN_CLK_CAMERA_PIXEL>, 1196 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1197 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1198 clock-names = "pclk", "wrap", "phy", "axi"; 1199 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; 1200 status = "disabled"; 1201 1202 ports { 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 port@0 { 1207 reg = <0>; 1208 }; 1209 1210 port@1 { 1211 reg = <1>; 1212 1213 mipi_csi_out: endpoint { 1214 remote-endpoint = <&isi_in>; 1215 }; 1216 }; 1217 }; 1218 }; 1219 1220 usbotg1: usb@32e40000 { 1221 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1222 reg = <0x32e40000 0x200>; 1223 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1225 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1226 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1227 phys = <&usbphynop1>; 1228 fsl,usbmisc = <&usbmisc1 0>; 1229 power-domains = <&pgc_hsiomix>; 1230 status = "disabled"; 1231 }; 1232 1233 usbmisc1: usbmisc@32e40200 { 1234 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", 1235 "fsl,imx6q-usbmisc"; 1236 #index-cells = <1>; 1237 reg = <0x32e40200 0x200>; 1238 }; 1239 }; 1240 1241 dma_apbh: dma-controller@33000000 { 1242 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1243 reg = <0x33000000 0x2000>; 1244 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1248 #dma-cells = <1>; 1249 dma-channels = <4>; 1250 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1251 }; 1252 1253 gpmi: nand-controller@33002000 { 1254 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1258 reg-names = "gpmi-nand", "bch"; 1259 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1260 interrupt-names = "bch"; 1261 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1262 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1263 clock-names = "gpmi_io", "gpmi_bch_apb"; 1264 dmas = <&dma_apbh 0>; 1265 dma-names = "rx-tx"; 1266 status = "disabled"; 1267 }; 1268 1269 gpu: gpu@38000000 { 1270 compatible = "vivante,gc"; 1271 reg = <0x38000000 0x8000>; 1272 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&clk IMX8MN_CLK_GPU_AHB>, 1274 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 1275 <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 1276 <&clk IMX8MN_CLK_GPU_SHADER>; 1277 clock-names = "reg", "bus", "core", "shader"; 1278 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, 1279 <&clk IMX8MN_CLK_GPU_SHADER>, 1280 <&clk IMX8MN_CLK_GPU_AXI>, 1281 <&clk IMX8MN_CLK_GPU_AHB>, 1282 <&clk IMX8MN_GPU_PLL>; 1283 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, 1284 <&clk IMX8MN_GPU_PLL_OUT>, 1285 <&clk IMX8MN_SYS_PLL1_800M>, 1286 <&clk IMX8MN_SYS_PLL1_800M>; 1287 assigned-clock-rates = <400000000>, 1288 <400000000>, 1289 <800000000>, 1290 <400000000>, 1291 <1200000000>; 1292 power-domains = <&pgc_gpumix>; 1293 }; 1294 1295 gic: interrupt-controller@38800000 { 1296 compatible = "arm,gic-v3"; 1297 reg = <0x38800000 0x10000>, 1298 <0x38880000 0xc0000>; 1299 #interrupt-cells = <3>; 1300 interrupt-controller; 1301 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1302 }; 1303 1304 ddrc: memory-controller@3d400000 { 1305 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1306 reg = <0x3d400000 0x400000>; 1307 clock-names = "core", "pll", "alt", "apb"; 1308 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1309 <&clk IMX8MN_DRAM_PLL>, 1310 <&clk IMX8MN_CLK_DRAM_ALT>, 1311 <&clk IMX8MN_CLK_DRAM_APB>; 1312 }; 1313 1314 ddr-pmu@3d800000 { 1315 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1316 reg = <0x3d800000 0x400000>; 1317 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1318 }; 1319 }; 1320 1321 usbphynop1: usbphynop1 { 1322 #phy-cells = <0>; 1323 compatible = "usb-nop-xceiv"; 1324 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1325 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1326 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1327 clock-names = "main_clk"; 1328 power-domains = <&pgc_otg1>; 1329 }; 1330}; 1331