1 /*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2024 Jari Sihvola <jsihv@gmx.com>
5 */
6
7 /* JH7110 PCIe controller driver */
8
9 #include <sys/param.h>
10 #include <sys/systm.h>
11 #include <sys/bus.h>
12 #include <sys/gpio.h>
13 #include <sys/kernel.h>
14 #include <sys/lock.h>
15 #include <sys/malloc.h>
16 #include <sys/module.h>
17 #include <sys/mutex.h>
18 #include <sys/proc.h>
19 #include <sys/rman.h>
20
21 #include <machine/bus.h>
22 #include <machine/intr.h>
23 #include <machine/resource.h>
24
25 #include <dev/clk/clk.h>
26 #include <dev/gpio/gpiobusvar.h>
27 #include <dev/hwreset/hwreset.h>
28 #include <dev/regulator/regulator.h>
29 #include <dev/syscon/syscon.h>
30 #include <dev/ofw/ofw_bus.h>
31 #include <dev/ofw/ofw_bus_subr.h>
32 #include <dev/ofw/ofw_pci.h>
33 #include <dev/ofw/ofwpci.h>
34 #include <dev/pci/pci_host_generic.h>
35 #include <dev/pci/pcireg.h>
36 #include <dev/pci/pcivar.h>
37 #include <dev/pci/pcib_private.h>
38
39 #include "msi_if.h"
40 #include "ofw_bus_if.h"
41 #include "pcib_if.h"
42 #include "pic_if.h"
43 #include "syscon_if.h"
44
45 #define IRQ_LOCAL_MASK 0x180
46 #define IRQ_LOCAL_STATUS 0x184
47 #define IRQ_MSI_BASE 0x190
48 #define IRQ_MSI_STATUS 0x194
49
50 #define MSI_MASK 0x10000000
51 #define INTX_MASK 0xf000000
52 #define ERROR_MASK 0x80770000
53
54 #define MSI_COUNT 32
55 #define MSI_USED 0x1
56 #define MSI_PCIE0_MASK_OFFSET 0xa0;
57 #define MSI_PCIE1_MASK_OFFSET 0xf0;
58
59 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800
60 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804
61 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808
62 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810
63 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80c
64 #define ATR_ENTRY_SIZE 0x20
65 #define ATR0_PCIE_ATR_SIZE 0x25
66 #define ATR0_PCIE_ATR_SIZE_SHIFT 1
67 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600
68 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604
69 #define ATR0_ENABLE 1
70
71 #define PCIE_TXRX_INTERFACE 0x0
72 #define PCIE_CONF_INTERFACE 0x1
73 #define PCIE_WINCONF 0xfc
74 #define PREF_MEM_WIN_64_SUPPORT (1U << 3)
75
76 #define STG_AXI4_SLVL_AW_MASK 0x7fff
77 #define STG_AXI4_SLVL_AR_MASK 0x7fff00
78 #define STG_PCIE0_BASE 0x48
79 #define STG_PCIE1_BASE 0x1f8
80 #define STG_RP_NEP_OFFSET 0xe8
81 #define STG_K_RP_NEP (1U << 8)
82 #define STG_CKREF_MASK 0xC0000
83 #define STG_CKREF_VAL 0x80000
84 #define STG_CLKREQ (1U << 22)
85 #define STG_AR_OFFSET 0x78
86 #define STG_AW_OFFSET 0x7c
87 #define STG_AXI4_SLVL_ARFUNC_SHIFT 0x8
88 #define STG_LNKSTA_OFFSET 0x170
89 #define STG_LINK_UP (1U << 5)
90
91 #define PHY_FUNC_SHIFT 9
92 #define PHY_FUNC_DIS (1U << 15)
93 #define PCI_MISC_REG 0xb4
94 #define PCI_GENERAL_SETUP_REG 0x80
95 #define PCI_CONF_SPACE_REGS 0x1000
96 #define ROOTPORT_ENABLE 0x1
97 #define PMSG_RX_SUPPORT_REG 0x3f0
98 #define PMSG_LTR_SUPPORT (1U << 2)
99 #define PCI_CLASS_BRIDGE_PCI 0x0604
100 #define PCI_IDS_CLASS_CODE_SHIFT 16
101 #define PCIE_PCI_IDS_REG 0x9c
102 #define REV_ID_MASK 0xff
103
104 #define PLDA_AXI_POST_ERR (1U << 16)
105 #define PLDA_AXI_FETCH_ERR (1U << 17)
106 #define PLDA_AXI_DISCARD_ERR (1U << 18)
107 #define PLDA_PCIE_POST_ERR (1U << 20)
108 #define PLDA_PCIE_FETCH_ERR (1U << 21)
109 #define PLDA_PCIE_DISCARD_ERR (1U << 22)
110 #define PLDA_SYS_ERR (1U << 31)
111
112 /* Compatible devices. */
113 static struct ofw_compat_data compat_data[] = {
114 {"starfive,jh7110-pcie", 1},
115 {NULL, 0},
116 };
117
118 struct jh7110_pcie_irqsrc {
119 struct intr_irqsrc isrc;
120 u_int irq;
121 u_int is_used;
122 };
123
124 struct jh7110_pcie_softc {
125 struct ofw_pci_softc ofw_pci;
126 device_t dev;
127 phandle_t node;
128
129 struct resource *reg_mem_res;
130 struct resource *cfg_mem_res;
131 struct resource *irq_res;
132 struct jh7110_pcie_irqsrc *isrcs;
133 void *irq_cookie;
134 struct syscon *stg_syscon;
135 uint64_t stg_baddr;
136
137 struct ofw_pci_range range_mem32;
138 struct ofw_pci_range range_mem64;
139
140 struct mtx msi_mtx;
141 uint64_t msi_mask_offset;
142
143 gpio_pin_t perst_pin;
144
145 clk_t clk_noc;
146 clk_t clk_tl;
147 clk_t clk_axi;
148 clk_t clk_apb;
149
150 hwreset_t rst_mst0;
151 hwreset_t rst_slv0;
152 hwreset_t rst_slv;
153 hwreset_t rst_brg;
154 hwreset_t rst_core;
155 hwreset_t rst_apb;
156 };
157
158 #define LOW32(val) (uint32_t)(val)
159 #define HI32(val) (uint32_t)(val >> 32)
160
161 #define RD4(sc, reg) bus_read_4((sc)->reg_mem_res, (reg))
162 #define WR4(sc, reg, val) bus_write_4((sc)->reg_mem_res, (reg), (val))
163
164 static uint32_t
jh7110_pcie_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)165 jh7110_pcie_read_config(device_t dev, u_int bus, u_int slot, u_int func,
166 u_int reg, int bytes)
167 {
168 struct jh7110_pcie_softc *sc;
169 uint32_t data, offset;
170
171 sc = device_get_softc(dev);
172 offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
173
174 /* Certain config registers are not supposed to be accessed from here */
175 if (bus == 0 && (offset == PCIR_BAR(0) || offset == PCIR_BAR(1)))
176 return (~0U);
177
178 switch (bytes) {
179 case 1:
180 data = bus_read_1(sc->cfg_mem_res, offset);
181 break;
182 case 2:
183 data = le16toh(bus_read_2(sc->cfg_mem_res, offset));
184 break;
185 case 4:
186 data = le32toh(bus_read_4(sc->cfg_mem_res, offset));
187 break;
188 default:
189 return (~0U);
190 }
191
192 return (data);
193 }
194
195 static void
jh7110_pcie_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)196 jh7110_pcie_write_config(device_t dev, u_int bus, u_int slot, u_int func,
197 u_int reg, uint32_t val, int bytes)
198 {
199 struct jh7110_pcie_softc *sc;
200 uint32_t offset;
201
202 sc = device_get_softc(dev);
203 offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
204
205 /* Certain config registers are not supposed to be accessed from here */
206 if (bus == 0 && (offset == PCIR_BAR(0) || offset == PCIR_BAR(1)))
207 return;
208
209 switch (bytes) {
210 case 1:
211 bus_write_1(sc->cfg_mem_res, offset, val);
212 break;
213 case 2:
214 bus_write_2(sc->cfg_mem_res, offset, htole16(val));
215 break;
216 case 4:
217 bus_write_4(sc->cfg_mem_res, offset, htole32(val));
218 break;
219 default:
220 return;
221 }
222 }
223
224 static int
jh7110_pcie_intr(void * arg)225 jh7110_pcie_intr(void *arg)
226 {
227 struct jh7110_pcie_softc *sc;
228 struct trapframe *tf;
229 struct jh7110_pcie_irqsrc *irq;
230 uint32_t reg, irqbits;
231 int err, i;
232
233 sc = (struct jh7110_pcie_softc *)arg;
234 tf = curthread->td_intr_frame;
235
236 reg = RD4(sc, IRQ_LOCAL_STATUS);
237 if (reg == 0)
238 return (ENXIO);
239
240 if ((reg & MSI_MASK) != 0) {
241 WR4(sc, IRQ_LOCAL_STATUS, MSI_MASK);
242
243 irqbits = RD4(sc, IRQ_MSI_STATUS);
244 for (i = 0; irqbits != 0; i++) {
245 if ((irqbits & (1U << i)) != 0) {
246 irq = &sc->isrcs[i];
247 err = intr_isrc_dispatch(&irq->isrc, tf);
248 if (err != 0)
249 device_printf(sc->dev,
250 "MSI 0x%x gives error %d\n",
251 i, err);
252 irqbits &= ~(1U << i);
253 }
254 }
255 }
256 if ((reg & INTX_MASK) != 0) {
257 irqbits = (reg & INTX_MASK);
258 WR4(sc, IRQ_LOCAL_STATUS, irqbits);
259 }
260 if ((reg & ERROR_MASK) != 0) {
261 irqbits = (reg & ERROR_MASK);
262 if ((reg & PLDA_AXI_POST_ERR) != 0)
263 device_printf(sc->dev, "axi post error\n");
264 if ((reg & PLDA_AXI_FETCH_ERR) != 0)
265 device_printf(sc->dev, "axi fetch error\n");
266 if ((reg & PLDA_AXI_DISCARD_ERR) != 0)
267 device_printf(sc->dev, "axi discard error\n");
268 if ((reg & PLDA_PCIE_POST_ERR) != 0)
269 device_printf(sc->dev, "pcie post error\n");
270 if ((reg & PLDA_PCIE_FETCH_ERR) != 0)
271 device_printf(sc->dev, "pcie fetch error\n");
272 if ((reg & PLDA_PCIE_DISCARD_ERR) != 0)
273 device_printf(sc->dev, "pcie discard error\n");
274 if ((reg & PLDA_SYS_ERR) != 0)
275 device_printf(sc->dev, "pcie sys error\n");
276 WR4(sc, IRQ_LOCAL_STATUS, irqbits);
277 }
278
279 return (FILTER_HANDLED);
280 }
281
282 static int
jh7110_pcie_route_interrupt(device_t bus,device_t dev,int pin)283 jh7110_pcie_route_interrupt(device_t bus, device_t dev, int pin)
284 {
285 struct jh7110_pcie_softc *sc;
286 u_int irq;
287
288 sc = device_get_softc(bus);
289 irq = intr_map_clone_irq(rman_get_start(sc->irq_res));
290 device_printf(bus, "route pin %d for device %d.%d to %u\n",
291 pin, pci_get_slot(dev), pci_get_function(dev), irq);
292
293 return (irq);
294 }
295
296 static int
jh7110_pcie_maxslots(device_t dev)297 jh7110_pcie_maxslots(device_t dev)
298 {
299 return (PCI_SLOTMAX);
300 }
301
302 static int
jh7110_pcie_msi_alloc_msi(device_t dev,device_t child,int count,int maxcount,device_t * pic,struct intr_irqsrc ** srcs)303 jh7110_pcie_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount,
304 device_t *pic, struct intr_irqsrc **srcs)
305 {
306 struct jh7110_pcie_softc *sc;
307 int i, beg;
308
309 sc = device_get_softc(dev);
310 mtx_lock(&sc->msi_mtx);
311
312 /* Search for a requested contiguous region */
313 for (beg = 0; beg + count < MSI_COUNT; ) {
314 for (i = beg; i < beg + count; i++) {
315 if (sc->isrcs[i].is_used == MSI_USED)
316 goto next;
317 }
318 goto found;
319 next:
320 beg = i + 1;
321 }
322
323 /* Requested area not found */
324 mtx_unlock(&sc->msi_mtx);
325 device_printf(dev, "warning: failed to allocate %d MSIs.\n", count);
326
327 return (ENXIO);
328
329 found:
330 /* Mark and allocate messages */
331 for (i = 0; i < count; ++i) {
332 sc->isrcs[i + beg].is_used = MSI_USED;
333 srcs[i] = &(sc->isrcs[i + beg].isrc);
334 }
335
336 mtx_unlock(&sc->msi_mtx);
337 *pic = device_get_parent(dev);
338
339 return (0);
340 }
341
342 static int
jh7110_pcie_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)343 jh7110_pcie_alloc_msi(device_t pci, device_t child, int count,
344 int maxcount, int *irqs)
345 {
346 phandle_t msi_parent;
347 int err;
348
349 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
350 err = intr_alloc_msi(pci, child, msi_parent, count, maxcount, irqs);
351
352 return (err);
353 }
354
355 static int
jh7110_pcie_release_msi(device_t pci,device_t child,int count,int * irqs)356 jh7110_pcie_release_msi(device_t pci, device_t child, int count, int *irqs)
357 {
358 phandle_t msi_parent;
359 int err;
360
361 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
362 err = intr_release_msi(pci, child, msi_parent, count, irqs);
363
364 return (err);
365 }
366
367 static int
jh7110_pcie_msi_map_msi(device_t dev,device_t child,struct intr_irqsrc * isrc,uint64_t * addr,uint32_t * data)368 jh7110_pcie_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
369 uint64_t *addr, uint32_t *data)
370 {
371 struct jh7110_pcie_irqsrc *jhirq = (struct jh7110_pcie_irqsrc *)isrc;
372
373 *addr = IRQ_MSI_BASE;
374 *data = jhirq->irq;
375
376 return (0);
377 }
378
379
380 static int
jh7110_pcie_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)381 jh7110_pcie_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
382 uint32_t *data)
383 {
384 phandle_t msi_parent;
385 int err;
386
387 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
388
389 err = intr_map_msi(pci, child, msi_parent, irq, addr, data);
390 if (err != 0) {
391 device_printf(pci, "intr_map_msi() failed\n");
392 return (err);
393 }
394
395 return (err);
396 }
397
398 static int
jh7110_pcie_alloc_msix(device_t pci,device_t child,int * irq)399 jh7110_pcie_alloc_msix(device_t pci, device_t child, int *irq)
400 {
401 return (jh7110_pcie_alloc_msi(pci, child, 1, 32, irq));
402 }
403
404 static int
jh7110_pcie_release_msix(device_t pci,device_t child,int irq)405 jh7110_pcie_release_msix(device_t pci, device_t child, int irq)
406 {
407 phandle_t msi_parent;
408 int err;
409
410 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
411 err = intr_release_msix(pci, child, msi_parent, irq);
412
413 return (err);
414 }
415
416 static int
jh7110_pcie_msi_alloc_msix(device_t dev,device_t child,device_t * pic,struct intr_irqsrc ** isrcp)417 jh7110_pcie_msi_alloc_msix(device_t dev, device_t child, device_t *pic,
418 struct intr_irqsrc **isrcp)
419 {
420 return (jh7110_pcie_msi_alloc_msi(dev, child, 1, 32, pic, isrcp));
421 }
422
423 static int
jh7110_pcie_msi_release_msi(device_t dev,device_t child,int count,struct intr_irqsrc ** isrc)424 jh7110_pcie_msi_release_msi(device_t dev, device_t child, int count,
425 struct intr_irqsrc **isrc)
426 {
427 struct jh7110_pcie_softc *sc;
428 struct jh7110_pcie_irqsrc *irq;
429 int i;
430
431 sc = device_get_softc(dev);
432 mtx_lock(&sc->msi_mtx);
433
434 for (i = 0; i < count; i++) {
435 irq = (struct jh7110_pcie_irqsrc *)isrc[i];
436
437 KASSERT((irq->is_used & MSI_USED) == MSI_USED,
438 ("%s: Trying to release an unused MSI(-X) interrupt",
439 __func__));
440
441 irq->is_used = 0;
442 }
443
444 mtx_unlock(&sc->msi_mtx);
445 return (0);
446 }
447
448 static int
jh7110_pcie_msi_release_msix(device_t dev,device_t child,struct intr_irqsrc * isrc)449 jh7110_pcie_msi_release_msix(device_t dev, device_t child,
450 struct intr_irqsrc *isrc)
451 {
452 return (jh7110_pcie_msi_release_msi(dev, child, 1, &isrc));
453 }
454
455 static void
jh7110_pcie_msi_mask(device_t dev,struct intr_irqsrc * isrc,bool mask)456 jh7110_pcie_msi_mask(device_t dev, struct intr_irqsrc *isrc, bool mask)
457 {
458 struct jh7110_pcie_softc *sc;
459 struct jh7110_pcie_irqsrc *jhirq = (struct jh7110_pcie_irqsrc *)isrc;
460 uint32_t reg, irq;
461
462 sc = device_get_softc(dev);
463 irq = jhirq->irq;
464
465 reg = bus_read_4(sc->cfg_mem_res, sc->msi_mask_offset);
466 if (mask != 0)
467 reg &= ~(1U << irq);
468 else
469 reg |= (1U << irq);
470 bus_write_4(sc->cfg_mem_res, sc->msi_mask_offset, reg);
471 }
472
473 static void
jh7110_pcie_msi_disable_intr(device_t dev,struct intr_irqsrc * isrc)474 jh7110_pcie_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc)
475 {
476 jh7110_pcie_msi_mask(dev, isrc, true);
477 }
478
479 static void
jh7110_pcie_msi_enable_intr(device_t dev,struct intr_irqsrc * isrc)480 jh7110_pcie_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc)
481 {
482 jh7110_pcie_msi_mask(dev, isrc, false);
483 }
484
485 static void
jh7110_pcie_msi_post_filter(device_t dev,struct intr_irqsrc * isrc)486 jh7110_pcie_msi_post_filter(device_t dev, struct intr_irqsrc *isrc)
487 {
488 }
489
490 static void
jh7110_pcie_msi_post_ithread(device_t dev,struct intr_irqsrc * isrc)491 jh7110_pcie_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc)
492 {
493 }
494
495 static void
jh7110_pcie_msi_pre_ithread(device_t dev,struct intr_irqsrc * isrc)496 jh7110_pcie_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
497 {
498 struct jh7110_pcie_softc *sc;
499 struct jh7110_pcie_irqsrc *jhirq = (struct jh7110_pcie_irqsrc *)isrc;
500 uint32_t irq;
501
502 sc = device_get_softc(dev);
503 irq = jhirq->irq;
504
505 /* MSI bottom ack */
506 WR4(sc, IRQ_MSI_STATUS, (1U << irq));
507 }
508
509 static int
jh7110_pcie_decode_ranges(struct jh7110_pcie_softc * sc,struct ofw_pci_range * ranges,int nranges)510 jh7110_pcie_decode_ranges(struct jh7110_pcie_softc *sc,
511 struct ofw_pci_range *ranges, int nranges)
512 {
513 int i;
514
515 for (i = 0; i < nranges; i++) {
516 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
517 OFW_PCI_PHYS_HI_SPACE_MEM64)) {
518 if (sc->range_mem64.size != 0) {
519 device_printf(sc->dev,
520 "Duplicate range mem64 found in DT\n");
521 return (ENXIO);
522 }
523 sc->range_mem64 = ranges[i];
524 } else if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
525 OFW_PCI_PHYS_HI_SPACE_MEM32)) {
526 if (sc->range_mem32.size != 0) {
527 device_printf(sc->dev,
528 "Duplicated range mem32 found in DT\n");
529 return (ENXIO);
530 }
531 sc->range_mem32 = ranges[i];
532 }
533 }
534 return (0);
535 }
536
537 static int
jh7110_pcie_probe(device_t dev)538 jh7110_pcie_probe(device_t dev)
539 {
540 if (!ofw_bus_status_okay(dev))
541 return (ENXIO);
542
543 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
544 return (ENXIO);
545
546 device_set_desc(dev, "Starfive JH7110 PCIe controller");
547
548 return (BUS_PROBE_DEFAULT);
549 }
550
551 static void
jh7110_pcie_set_atr(device_t dev,uint64_t axi_begin,uint64_t pci_begin,uint64_t win_size,uint32_t win_idx)552 jh7110_pcie_set_atr(device_t dev, uint64_t axi_begin, uint64_t pci_begin,
553 uint64_t win_size, uint32_t win_idx)
554 {
555 struct jh7110_pcie_softc *sc;
556 uint32_t val, taddr_size;
557
558 sc = device_get_softc(dev);
559
560 if (win_idx == 0)
561 val = PCIE_CONF_INTERFACE;
562 else
563 val = PCIE_TXRX_INTERFACE;
564
565 WR4(sc, ATR0_AXI4_SLV0_TRSL_PARAM + win_idx * ATR_ENTRY_SIZE, val);
566
567 taddr_size = ilog2(win_size) - 1;
568 val = LOW32(axi_begin) | taddr_size << ATR0_PCIE_ATR_SIZE_SHIFT |
569 ATR0_ENABLE;
570
571 WR4(sc, ATR0_AXI4_SLV0_SRCADDR_PARAM + win_idx * ATR_ENTRY_SIZE, val);
572
573 val = HI32(axi_begin);
574 WR4(sc, ATR0_AXI4_SLV0_SRC_ADDR + win_idx * ATR_ENTRY_SIZE, val);
575
576 val = LOW32(pci_begin);
577 WR4(sc, ATR0_AXI4_SLV0_TRSL_ADDR_LSB + win_idx * ATR_ENTRY_SIZE, val);
578
579 val = HI32(pci_begin);
580 WR4(sc, ATR0_AXI4_SLV0_TRSL_ADDR_UDW + win_idx * ATR_ENTRY_SIZE, val);
581
582 val = RD4(sc, ATR0_PCIE_WIN0_SRCADDR_PARAM);
583 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT);
584
585 WR4(sc, ATR0_PCIE_WIN0_SRCADDR_PARAM, val);
586 WR4(sc, ATR0_PCIE_WIN0_SRC_ADDR, 0);
587 }
588
589 static int
jh7110_pcie_parse_fdt_resources(struct jh7110_pcie_softc * sc)590 jh7110_pcie_parse_fdt_resources(struct jh7110_pcie_softc *sc)
591 {
592 uint32_t val;
593 int err;
594
595 /* Getting clocks */
596 if (clk_get_by_ofw_name(sc->dev, 0, "noc", &sc->clk_noc) != 0) {
597 device_printf(sc->dev, "could not get noc clock\n");
598 sc->clk_noc = NULL;
599 return (ENXIO);
600 }
601 if (clk_get_by_ofw_name(sc->dev, 0, "tl", &sc->clk_tl) != 0) {
602 device_printf(sc->dev, "could not get tl clock\n");
603 sc->clk_tl = NULL;
604 return (ENXIO);
605 }
606 if (clk_get_by_ofw_name(sc->dev, 0, "axi_mst0", &sc->clk_axi) != 0) {
607 device_printf(sc->dev, "could not get axi_mst0 clock\n");
608 sc->clk_axi = NULL;
609 return (ENXIO);
610 }
611 if (clk_get_by_ofw_name(sc->dev, 0, "apb", &sc->clk_apb) != 0) {
612 device_printf(sc->dev, "could not get apb clock\n");
613 sc->clk_apb = NULL;
614 return (ENXIO);
615 }
616
617 /* Getting resets */
618 err = hwreset_get_by_ofw_name(sc->dev, 0, "mst0", &sc->rst_mst0);
619 if (err != 0) {
620 device_printf(sc->dev, "cannot get 'rst_mst0' reset\n");
621 return (ENXIO);
622 }
623 err = hwreset_get_by_ofw_name(sc->dev, 0, "slv0", &sc->rst_slv0);
624 if (err != 0) {
625 device_printf(sc->dev, "cannot get 'rst_slv0' reset\n");
626 return (ENXIO);
627 }
628 err = hwreset_get_by_ofw_name(sc->dev, 0, "slv", &sc->rst_slv);
629 if (err != 0) {
630 device_printf(sc->dev, "cannot get 'rst_slv' reset\n");
631 return (ENXIO);
632 }
633 err = hwreset_get_by_ofw_name(sc->dev, 0, "brg", &sc->rst_brg);
634 if (err != 0) {
635 device_printf(sc->dev, "cannot get 'rst_brg' reset\n");
636 return (ENXIO);
637 }
638 err = hwreset_get_by_ofw_name(sc->dev, 0, "core", &sc->rst_core);
639 if (err != 0) {
640 device_printf(sc->dev, "cannot get 'rst_core' reset\n");
641 return (ENXIO);
642 }
643 err = hwreset_get_by_ofw_name(sc->dev, 0, "apb", &sc->rst_apb);
644 if (err != 0) {
645 device_printf(sc->dev, "cannot get 'rst_apb' reset\n");
646 return (ENXIO);
647 }
648
649 /* Getting PCI endpoint reset pin */
650 err = gpio_pin_get_by_ofw_property(sc->dev, sc->node, "perst-gpios",
651 &sc->perst_pin);
652 if (err != 0) {
653 device_printf(sc->dev, "Cannot get perst-gpios\n");
654 return (ENXIO);
655 }
656
657 /* Getting syscon property */
658 if (syscon_get_by_ofw_property(sc->dev, sc->node, "starfive,stg-syscon",
659 &sc->stg_syscon) != 0) {
660 device_printf(sc->dev, "Cannot get starfive,stg-syscon\n");
661 return (ENXIO);
662 }
663
664 /* Assigning syscon base address and MSI mask offset */
665 err = OF_getencprop(sc->node, "linux,pci-domain", &val, sizeof(val));
666 if (err == -1) {
667 device_printf(sc->dev,
668 "Couldn't get pci-domain property, error: %d\n", err);
669 return (ENXIO);
670 }
671
672 if (val == 0) {
673 sc->stg_baddr = STG_PCIE0_BASE;
674 sc->msi_mask_offset = MSI_PCIE0_MASK_OFFSET;
675 } else if (val == 1) {
676 sc->stg_baddr = STG_PCIE1_BASE;
677 sc->msi_mask_offset = MSI_PCIE1_MASK_OFFSET;
678 } else {
679 device_printf(sc->dev, "Error: an invalid pci-domain value\n");
680 return (ENXIO);
681 }
682
683 return (0);
684 }
685
686 static void
jh7110_pcie_release_resources(device_t dev)687 jh7110_pcie_release_resources(device_t dev)
688 {
689 struct jh7110_pcie_softc *sc;
690
691 sc = device_get_softc(dev);
692
693 if (sc->irq_res != NULL)
694 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
695 if (sc->irq_res != NULL)
696 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
697 if (sc->reg_mem_res != NULL)
698 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg_mem_res);
699 if (sc->cfg_mem_res != NULL)
700 bus_free_resource(dev, SYS_RES_MEMORY, sc->cfg_mem_res);
701
702 if (sc->clk_noc != NULL)
703 clk_release(sc->clk_noc);
704 if (sc->clk_tl != NULL)
705 clk_release(sc->clk_tl);
706 if (sc->clk_axi != NULL)
707 clk_release(sc->clk_axi);
708 if (sc->clk_apb != NULL)
709 clk_release(sc->clk_apb);
710
711 gpio_pin_release(sc->perst_pin);
712
713 hwreset_release(sc->rst_mst0);
714 hwreset_release(sc->rst_slv0);
715 hwreset_release(sc->rst_slv);
716 hwreset_release(sc->rst_brg);
717 hwreset_release(sc->rst_core);
718 hwreset_release(sc->rst_apb);
719
720 mtx_destroy(&sc->msi_mtx);
721 }
722
723 static int
jh7110_pcie_detach(device_t dev)724 jh7110_pcie_detach(device_t dev)
725 {
726 ofw_pcib_fini(dev);
727 jh7110_pcie_release_resources(dev);
728
729 return (0);
730 }
731
732 static int
jh7110_pcie_attach(device_t dev)733 jh7110_pcie_attach(device_t dev)
734 {
735 struct jh7110_pcie_softc *sc;
736 phandle_t xref;
737 uint32_t val;
738 int i, err, rid, irq, win_idx = 0;
739 char name[INTR_ISRC_NAMELEN];
740
741 sc = device_get_softc(dev);
742 sc->dev = dev;
743 sc->node = ofw_bus_get_node(dev);
744
745 sc->irq_res = NULL;
746 sc->reg_mem_res = NULL;
747 sc->cfg_mem_res = NULL;
748 sc->clk_noc = NULL;
749 sc->clk_tl = NULL;
750 sc->clk_axi = NULL;
751 sc->clk_apb = NULL;
752
753 mtx_init(&sc->msi_mtx, "jh7110_pcie, msi_mtx", NULL, MTX_DEF);
754
755 /* Allocating memory */
756 err = ofw_bus_find_string_index(sc->node, "reg-names", "apb", &rid);
757 if (err != 0) {
758 device_printf(dev, "Cannot get apb memory\n");
759 goto out;
760 }
761
762 sc->reg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
763 RF_ACTIVE);
764 if (sc->reg_mem_res == NULL) {
765 device_printf(dev, "Cannot allocate apb memory\n");
766 err = ENXIO;
767 goto out;
768 }
769
770 err = ofw_bus_find_string_index(sc->node, "reg-names", "cfg", &rid);
771 if (err != 0) {
772 device_printf(dev, "Cannot get cfg memory\n");
773 err = ENXIO;
774 goto out;
775 }
776
777 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
778 RF_ACTIVE);
779 if (sc->cfg_mem_res == NULL) {
780 device_printf(dev, "Cannot allocate cfg memory\n");
781 err = ENXIO;
782 goto out;
783 }
784
785 /* Getting device tree properties */
786 if (jh7110_pcie_parse_fdt_resources(sc) != 0)
787 goto out;
788
789 /* Clearing interrupts, enabling MSI */
790 WR4(sc, IRQ_LOCAL_STATUS, 0xffffffff);
791 WR4(sc, IRQ_LOCAL_MASK, INTX_MASK | ERROR_MASK | MSI_MASK);
792
793 /* Setting host up */
794 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_RP_NEP_OFFSET,
795 STG_K_RP_NEP, STG_K_RP_NEP);
796 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_AW_OFFSET,
797 STG_CKREF_MASK, STG_CKREF_VAL);
798 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_AW_OFFSET,
799 STG_CLKREQ, STG_CLKREQ);
800
801 /* Enabling clocks */
802 if (clk_enable(sc->clk_noc) != 0) {
803 device_printf(dev, "could not enable noc clock\n");
804 goto out;
805 }
806 if (clk_enable(sc->clk_tl) != 0) {
807 device_printf(dev, "could not enable tl clock\n");
808 goto out;
809 }
810 if (clk_enable(sc->clk_axi) != 0) {
811 device_printf(dev, "could not enable axi_mst0 clock\n");
812 goto out;
813 }
814 if (clk_enable(sc->clk_apb) != 0) {
815 device_printf(dev, "could not enable apb clock\n");
816 goto out;
817 }
818
819 /* Deasserting resets */
820 err = hwreset_deassert(sc->rst_mst0);
821 if (err != 0) {
822 device_printf(sc->dev, "cannot deassert 'mst0' reset\n");
823 goto out;
824 }
825 err = hwreset_deassert(sc->rst_slv0);
826 if (err != 0) {
827 device_printf(sc->dev, "cannot deassert 'slv0' reset\n");
828 goto out;
829 }
830 err = hwreset_deassert(sc->rst_slv);
831 if (err != 0) {
832 device_printf(sc->dev, "cannot deassert 'slv' reset\n");
833 goto out;
834 }
835 err = hwreset_deassert(sc->rst_brg);
836 if (err != 0) {
837 device_printf(sc->dev, "cannot deassert 'brg' reset\n");
838 goto out;
839 }
840 err = hwreset_deassert(sc->rst_core);
841 if (err != 0) {
842 device_printf(sc->dev, "cannot deassert 'core' reset\n");
843 goto out;
844 }
845 err = hwreset_deassert(sc->rst_apb);
846 if (err != 0) {
847 device_printf(sc->dev, "cannot deassert 'apb' reset\n");
848 goto out;
849 }
850
851 err = gpio_pin_set_active(sc->perst_pin, true);
852 if (err != 0) {
853 device_printf(dev, "Cannot activate gpio pin, error %d\n", err);
854 goto out;
855 }
856
857 /* Switching off PHY functions 1-3 */
858 for (i = 1; i != 4; i++) {
859 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_AR_OFFSET,
860 STG_AXI4_SLVL_AR_MASK, (i << PHY_FUNC_SHIFT)
861 << STG_AXI4_SLVL_ARFUNC_SHIFT);
862 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_AW_OFFSET,
863 STG_AXI4_SLVL_AW_MASK, i << PHY_FUNC_SHIFT);
864
865 val = RD4(sc, PCI_MISC_REG);
866 WR4(sc, PCI_MISC_REG, val | PHY_FUNC_DIS);
867 }
868
869 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_AR_OFFSET,
870 STG_AXI4_SLVL_AR_MASK, 0);
871 SYSCON_MODIFY_4(sc->stg_syscon, sc->stg_baddr + STG_AW_OFFSET,
872 STG_AXI4_SLVL_AW_MASK, 0);
873
874 /* Enabling root port */
875 val = RD4(sc, PCI_GENERAL_SETUP_REG);
876 WR4(sc, PCI_GENERAL_SETUP_REG, val | ROOTPORT_ENABLE);
877
878 /* Zeroing RC BAR */
879 WR4(sc, PCI_CONF_SPACE_REGS + PCIR_BAR(0), 0);
880 WR4(sc, PCI_CONF_SPACE_REGS + PCIR_BAR(1), 0);
881
882 /* Setting standard class */
883 val = RD4(sc, PCIE_PCI_IDS_REG);
884 val &= REV_ID_MASK;
885 val |= (PCI_CLASS_BRIDGE_PCI << PCI_IDS_CLASS_CODE_SHIFT);
886 WR4(sc, PCIE_PCI_IDS_REG, val);
887
888 /* Disabling latency tolerance reporting */
889 val = RD4(sc, PMSG_RX_SUPPORT_REG);
890 WR4(sc, PMSG_RX_SUPPORT_REG, val & ~PMSG_LTR_SUPPORT);
891
892 /* Setting support for 64-bit pref window */
893 val = RD4(sc, PCIE_WINCONF);
894 WR4(sc, PCIE_WINCONF, val | PREF_MEM_WIN_64_SUPPORT);
895
896 /* Holding PCI endpoint reset (perst) for 100ms, setting the pin */
897 DELAY(100);
898 err = gpio_pin_set_active(sc->perst_pin, false);
899 if (err != 0) {
900 device_printf(dev, "Cannot deassert perst pin: %d\n", err);
901 goto out;
902 }
903
904 /* Setting up an address translation window */
905 jh7110_pcie_set_atr(dev, rman_get_start(sc->cfg_mem_res), 0,
906 rman_get_size(sc->cfg_mem_res), win_idx);
907
908 err = ofw_pcib_init(dev);
909 if (err != 0) {
910 device_printf(dev, "ofw_pcib_init() fails\n");
911 goto out;
912 }
913
914 jh7110_pcie_decode_ranges(sc, sc->ofw_pci.sc_range,
915 sc->ofw_pci.sc_nrange);
916
917 jh7110_pcie_set_atr(dev, sc->range_mem32.pci, sc->range_mem32.pci,
918 sc->range_mem32.size, ++win_idx);
919 jh7110_pcie_set_atr(dev, sc->range_mem64.pci, sc->range_mem64.pci,
920 sc->range_mem64.size, ++win_idx);
921
922 /* Checking data link status */
923 for (i = 0; i != 1000; i++) {
924 val = SYSCON_READ_4(sc->stg_syscon,
925 sc->stg_baddr + STG_LNKSTA_OFFSET);
926 if ((val & STG_LINK_UP) != 0) {
927 device_printf(dev, "Link up\n");
928 break;
929 }
930 DELAY(100);
931 }
932 if ((val & STG_LINK_UP) == 0) {
933 device_printf(dev, "Cannot establish data link\n");
934 goto out;
935 }
936
937 /* Setup interrupts */
938 rid = 0;
939 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
940 if (sc->irq_res == NULL) {
941 device_printf(dev, "Cannot allocate IRQ resource\n");
942 err = ENXIO;
943 goto out_full;
944 }
945
946 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
947 jh7110_pcie_intr, NULL, sc, &sc->irq_cookie);
948 if (err != 0) {
949 device_printf(dev, "Cannot setup interrupt handler\n");
950 err = ENXIO;
951 goto out_full;
952 }
953
954 sc->isrcs = malloc(sizeof(*sc->isrcs) * MSI_COUNT, M_DEVBUF,
955 M_WAITOK | M_ZERO);
956
957 snprintf(name, INTR_ISRC_NAMELEN, "%s, MSI",
958 device_get_nameunit(sc->dev));
959
960 for (irq = 0; irq < MSI_COUNT; irq++) {
961 sc->isrcs[irq].irq = irq;
962 err = intr_isrc_register(&sc->isrcs[irq].isrc, sc->dev, 0,
963 "%s,%u", name, irq);
964 if (err != 0) {
965 device_printf(dev,
966 "intr_isrs_register failed for MSI irq %d\n", irq);
967 goto out_full;
968 }
969 }
970
971 xref = OF_xref_from_node(sc->node);
972 OF_device_register_xref(xref, dev);
973
974 err = intr_msi_register(dev, xref);
975 if (err != 0) {
976 device_printf(dev, "intr_msi_register() fails\n");
977 goto out_full;
978 }
979
980 device_add_child(dev, "pci", DEVICE_UNIT_ANY);
981 bus_attach_children(dev);
982
983 return (0);
984
985 out_full:
986 ofw_pcib_fini(dev);
987 out:
988 jh7110_pcie_release_resources(dev);
989
990 return (err);
991 }
992
993 static device_method_t jh7110_pcie_methods[] = {
994 /* Device interface */
995 DEVMETHOD(device_probe, jh7110_pcie_probe),
996 DEVMETHOD(device_attach, jh7110_pcie_attach),
997 DEVMETHOD(device_detach, jh7110_pcie_detach),
998
999 /* pcib interface */
1000 DEVMETHOD(pcib_maxslots, jh7110_pcie_maxslots),
1001 DEVMETHOD(pcib_read_config, jh7110_pcie_read_config),
1002 DEVMETHOD(pcib_write_config, jh7110_pcie_write_config),
1003 DEVMETHOD(pcib_route_interrupt, jh7110_pcie_route_interrupt),
1004 DEVMETHOD(pcib_map_msi, jh7110_pcie_map_msi),
1005 DEVMETHOD(pcib_alloc_msi, jh7110_pcie_alloc_msi),
1006 DEVMETHOD(pcib_release_msi, jh7110_pcie_release_msi),
1007 DEVMETHOD(pcib_alloc_msix, jh7110_pcie_alloc_msix),
1008 DEVMETHOD(pcib_release_msix, jh7110_pcie_release_msix),
1009 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
1010
1011 /* MSI/MSI-X */
1012 DEVMETHOD(msi_alloc_msi, jh7110_pcie_msi_alloc_msi),
1013 DEVMETHOD(msi_alloc_msix, jh7110_pcie_msi_alloc_msix),
1014 DEVMETHOD(msi_release_msi, jh7110_pcie_msi_release_msi),
1015 DEVMETHOD(msi_release_msix, jh7110_pcie_msi_release_msix),
1016 DEVMETHOD(msi_map_msi, jh7110_pcie_msi_map_msi),
1017
1018 /* Interrupt controller interface */
1019 DEVMETHOD(pic_enable_intr, jh7110_pcie_msi_enable_intr),
1020 DEVMETHOD(pic_disable_intr, jh7110_pcie_msi_disable_intr),
1021 DEVMETHOD(pic_post_filter, jh7110_pcie_msi_post_filter),
1022 DEVMETHOD(pic_post_ithread, jh7110_pcie_msi_post_ithread),
1023 DEVMETHOD(pic_pre_ithread, jh7110_pcie_msi_pre_ithread),
1024
1025 /* OFW bus interface */
1026 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
1027 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
1028 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
1029 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
1030 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
1031
1032 DEVMETHOD_END
1033 };
1034
1035 DEFINE_CLASS_1(pcib, jh7110_pcie_driver, jh7110_pcie_methods,
1036 sizeof(struct jh7110_pcie_softc), ofw_pcib_driver);
1037 DRIVER_MODULE(jh7110_pcie, simplebus, jh7110_pcie_driver, NULL, NULL);
1038