1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6 * Copyright (c) 2012 Luiz Otavio O Souza.
7 * Copyright (c) 2022 Julien Cassette <julien.cassette@gmail.com>
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/rman.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/gpio.h>
43 #include <sys/proc.h>
44
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/intr.h>
48
49 #include <dev/gpio/gpiobusvar.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/fdt/fdt_pinctrl.h>
53
54 #include <arm/allwinner/aw_machdep.h>
55 #include <arm/allwinner/allwinner_pinctrl.h>
56 #include <dev/clk/clk.h>
57 #include <dev/hwreset/hwreset.h>
58 #include <dev/regulator/regulator.h>
59
60 #if defined(__aarch64__) || defined(__riscv)
61 #include "opt_soc.h"
62 #endif
63
64 #include "pic_if.h"
65 #include "gpio_if.h"
66
67 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
68 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN);
69
70 #define AW_GPIO_INTR_CAPS (GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | \
71 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH)
72
73 #define AW_GPIO_NONE 0
74 #define AW_GPIO_PULLUP 1
75 #define AW_GPIO_PULLDOWN 2
76
77 #define AW_GPIO_INPUT 0
78 #define AW_GPIO_OUTPUT 1
79
80 #define AW_GPIO_DRV_MASK 0x3
81 #define AW_GPIO_PUD_MASK 0x3
82
83 #define AW_PINCTRL 1
84 #define AW_R_PINCTRL 2
85
86 #if defined(__arm__) || defined(__aarch64__)
87 #define IRQ_MEMORY_BARRIER(x) arm_irq_memory_barrier(x)
88 #else
89 #define IRQ_MEMORY_BARRIER(x) fence()
90 #endif
91
92 struct aw_gpio_conf {
93 struct allwinner_padconf *padconf;
94 const char *banks;
95 uint32_t bank_size;
96 uint32_t drv_pin_shift;
97 uint32_t pul_offset;
98 };
99
100 /* Defined in aw_padconf.c */
101 #ifdef SOC_ALLWINNER_A10
102 extern struct allwinner_padconf a10_padconf;
103 struct aw_gpio_conf a10_gpio_conf = {
104 .padconf = &a10_padconf,
105 .banks = "abcdefghi",
106 .bank_size = 0x24,
107 .drv_pin_shift = 1,
108 .pul_offset = 0x1C,
109 };
110 #endif
111
112 /* Defined in a13_padconf.c */
113 #ifdef SOC_ALLWINNER_A13
114 extern struct allwinner_padconf a13_padconf;
115 struct aw_gpio_conf a13_gpio_conf = {
116 .padconf = &a13_padconf,
117 .banks = "bcdefg",
118 .bank_size = 0x24,
119 .drv_pin_shift = 1,
120 .pul_offset = 0x1C,
121 };
122 #endif
123
124 /* Defined in a20_padconf.c */
125 #ifdef SOC_ALLWINNER_A20
126 extern struct allwinner_padconf a20_padconf;
127 struct aw_gpio_conf a20_gpio_conf = {
128 .padconf = &a20_padconf,
129 .banks = "abcdefghi",
130 .bank_size = 0x24,
131 .drv_pin_shift = 1,
132 .pul_offset = 0x1C,
133 };
134 #endif
135
136 /* Defined in a31_padconf.c */
137 #ifdef SOC_ALLWINNER_A31
138 extern struct allwinner_padconf a31_padconf;
139 struct aw_gpio_conf a31_gpio_conf = {
140 .padconf = &a31_padconf,
141 .banks = "abcdefgh",
142 .bank_size = 0x24,
143 .drv_pin_shift = 1,
144 .pul_offset = 0x1C,
145 };
146 #endif
147
148 /* Defined in a31s_padconf.c */
149 #ifdef SOC_ALLWINNER_A31S
150 extern struct allwinner_padconf a31s_padconf;
151 struct aw_gpio_conf a31s_gpio_conf = {
152 .padconf = &a31s_padconf,
153 .banks = "abcdefgh",
154 .bank_size = 0x24,
155 .drv_pin_shift = 1,
156 .pul_offset = 0x1C,
157 };
158 #endif
159
160 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
161 extern struct allwinner_padconf a31_r_padconf;
162 struct aw_gpio_conf a31_r_gpio_conf = {
163 .padconf = &a31_r_padconf,
164 .banks = "lm",
165 .bank_size = 0x24,
166 .drv_pin_shift = 1,
167 .pul_offset = 0x1C,
168 };
169 #endif
170
171 /* Defined in a33_padconf.c */
172 #ifdef SOC_ALLWINNER_A33
173 extern struct allwinner_padconf a33_padconf;
174 struct aw_gpio_conf a33_gpio_conf = {
175 .padconf = &a33_padconf,
176 .banks = "bcdefgh",
177 .bank_size = 0x24,
178 .drv_pin_shift = 1,
179 .pul_offset = 0x1C,
180 };
181 #endif
182
183 /* Defined in h3_padconf.c */
184 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
185 extern struct allwinner_padconf h3_padconf;
186 extern struct allwinner_padconf h3_r_padconf;
187 struct aw_gpio_conf h3_gpio_conf = {
188 .padconf = &h3_padconf,
189 .banks = "acdefg",
190 .bank_size = 0x24,
191 .drv_pin_shift = 1,
192 .pul_offset = 0x1C,
193 };
194 struct aw_gpio_conf h3_r_gpio_conf = {
195 .padconf = &h3_r_padconf,
196 .banks = "l",
197 .bank_size = 0x24,
198 .drv_pin_shift = 1,
199 .pul_offset = 0x1C,
200 };
201 #endif
202
203 /* Defined in a83t_padconf.c */
204 #ifdef SOC_ALLWINNER_A83T
205 extern struct allwinner_padconf a83t_padconf;
206 extern struct allwinner_padconf a83t_r_padconf;
207 struct aw_gpio_conf a83t_gpio_conf = {
208 .padconf = &a83t_padconf,
209 .banks = "bcdefgh",
210 .bank_size = 0x24,
211 .drv_pin_shift = 1,
212 .pul_offset = 0x1C,
213 };
214 struct aw_gpio_conf a83t_r_gpio_conf = {
215 .padconf = &a83t_r_padconf,
216 .banks = "l",
217 .bank_size = 0x24,
218 .drv_pin_shift = 1,
219 .pul_offset = 0x1C,
220 };
221 #endif
222
223 /* Defined in a64_padconf.c */
224 #ifdef SOC_ALLWINNER_A64
225 extern struct allwinner_padconf a64_padconf;
226 extern struct allwinner_padconf a64_r_padconf;
227 struct aw_gpio_conf a64_gpio_conf = {
228 .padconf = &a64_padconf,
229 .banks = "bcdefgh",
230 .bank_size = 0x24,
231 .drv_pin_shift = 1,
232 .pul_offset = 0x1C,
233 };
234 struct aw_gpio_conf a64_r_gpio_conf = {
235 .padconf = &a64_r_padconf,
236 .banks = "l",
237 .bank_size = 0x24,
238 .drv_pin_shift = 1,
239 .pul_offset = 0x1C,
240 };
241 #endif
242
243 /* Defined in d1_padconf.c */
244 #ifdef SOC_ALLWINNER_D1
245 extern struct allwinner_padconf d1_padconf;
246 struct aw_gpio_conf d1_gpio_conf = {
247 .padconf = &d1_padconf,
248 .banks = "bcdefg",
249 .bank_size = 0x30,
250 .drv_pin_shift = 2,
251 .pul_offset = 0x24,
252 };
253 #endif
254
255 /* Defined in h6_padconf.c */
256 #ifdef SOC_ALLWINNER_H6
257 extern struct allwinner_padconf h6_padconf;
258 extern struct allwinner_padconf h6_r_padconf;
259 struct aw_gpio_conf h6_gpio_conf = {
260 .padconf = &h6_padconf,
261 .banks = "cdfgh",
262 .bank_size = 0x24,
263 .drv_pin_shift = 1,
264 .pul_offset = 0x1C,
265 };
266 struct aw_gpio_conf h6_r_gpio_conf = {
267 .padconf = &h6_r_padconf,
268 .banks = "lm",
269 .bank_size = 0x24,
270 .drv_pin_shift = 1,
271 .pul_offset = 0x1C,
272 };
273 #endif
274
275 /* Defined in h616_padconf.c */
276 #ifdef SOC_ALLWINNER_H616
277 extern struct allwinner_padconf h616_padconf;
278 extern struct allwinner_padconf h616_r_padconf;
279 struct aw_gpio_conf h616_gpio_conf = {
280 .padconf = &h616_padconf,
281 .banks = "cfghi",
282 .bank_size = 0x24,
283 .drv_pin_shift = 1,
284 .pul_offset = 0x1C,
285 };
286 struct aw_gpio_conf h616_r_gpio_conf = {
287 .padconf = &h616_r_padconf,
288 .banks = "l",
289 .bank_size = 0x24,
290 .drv_pin_shift = 1,
291 .pul_offset = 0x1C,
292 };
293 #endif
294
295 static struct ofw_compat_data compat_data[] = {
296 #ifdef SOC_ALLWINNER_A10
297 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
298 #endif
299 #ifdef SOC_ALLWINNER_A13
300 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
301 #endif
302 #ifdef SOC_ALLWINNER_A20
303 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
304 #endif
305 #ifdef SOC_ALLWINNER_A31
306 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
307 #endif
308 #ifdef SOC_ALLWINNER_A31S
309 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
310 #endif
311 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
312 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
313 #endif
314 #ifdef SOC_ALLWINNER_A33
315 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
316 #endif
317 #ifdef SOC_ALLWINNER_A83T
318 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
319 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf},
320 #endif
321 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
322 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf},
323 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf},
324 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf},
325 #endif
326 #ifdef SOC_ALLWINNER_A64
327 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf},
328 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf},
329 #endif
330 #ifdef SOC_ALLWINNER_D1
331 {"allwinner,sun20i-d1-pinctrl", (uintptr_t)&d1_gpio_conf},
332 #endif
333 #ifdef SOC_ALLWINNER_H6
334 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf},
335 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf},
336 #endif
337 #ifdef SOC_ALLWINNER_H616
338 {"allwinner,sun50i-h616-pinctrl", (uintptr_t)&h616_gpio_conf},
339 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h616_r_gpio_conf},
340 #endif
341 {NULL, 0}
342 };
343
344 struct clk_list {
345 TAILQ_ENTRY(clk_list) next;
346 clk_t clk;
347 };
348
349 struct gpio_irqsrc {
350 struct intr_irqsrc isrc;
351 u_int irq;
352 uint32_t mode;
353 uint32_t pin;
354 uint32_t bank;
355 uint32_t intnum;
356 uint32_t intfunc;
357 uint32_t oldfunc;
358 bool enabled;
359 };
360
361 #define AW_GPIO_MEMRES 0
362 #define AW_GPIO_IRQRES 1
363 #define AW_GPIO_RESSZ 2
364
365 struct aw_gpio_softc {
366 device_t sc_dev;
367 device_t sc_busdev;
368 struct resource * sc_res[AW_GPIO_RESSZ];
369 struct mtx sc_mtx;
370 struct resource * sc_mem_res;
371 struct resource * sc_irq_res;
372 void * sc_intrhand;
373 struct aw_gpio_conf *conf;
374 TAILQ_HEAD(, clk_list) clk_list;
375
376 struct gpio_irqsrc *gpio_pic_irqsrc;
377 int nirqs;
378 };
379
380 static struct resource_spec aw_gpio_res_spec[] = {
381 { SYS_RES_MEMORY, 0, RF_ACTIVE },
382 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
383 { -1, 0, 0 }
384 };
385
386 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
387 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
388 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
389
390 #define AW_GPIO_GP_BASE(_sc, _bank) ((_sc)->conf->bank_size * (_bank))
391
392 #define AW_GPIO_GP_CFG(_sc, _bank, _idx) \
393 (AW_GPIO_GP_BASE(_sc, _bank) + 0x00 + ((_idx) << 2))
394 #define AW_GPIO_GP_DAT(_sc, _bank) \
395 (AW_GPIO_GP_BASE(_sc, _bank) + 0x10)
396 #define AW_GPIO_GP_DRV(_sc, _bank, _idx) \
397 (AW_GPIO_GP_BASE(_sc, _bank) + 0x14 + ((_idx) << 2))
398 #define AW_GPIO_GP_PUL(_sc, _bank, _idx) \
399 (AW_GPIO_GP_BASE(_sc, _bank) + (_sc)->conf->pul_offset + ((_idx) << 2))
400
401 #define AW_GPIO_GP_INT_BASE(_bank) (0x200 + 0x20 * _bank)
402
403 #define AW_GPIO_GP_INT_CFG(_bank, _pin) (AW_GPIO_GP_INT_BASE(_bank) + (0x4 * ((_pin) / 8)))
404 #define AW_GPIO_GP_INT_CTL(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x10)
405 #define AW_GPIO_GP_INT_STA(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x14)
406 #define AW_GPIO_GP_INT_DEB(_bank) (AW_GPIO_GP_INT_BASE(_bank) + 0x18)
407
408 #define AW_GPIO_INT_EDGE_POSITIVE 0x0
409 #define AW_GPIO_INT_EDGE_NEGATIVE 0x1
410 #define AW_GPIO_INT_LEVEL_HIGH 0x2
411 #define AW_GPIO_INT_LEVEL_LOW 0x3
412 #define AW_GPIO_INT_EDGE_BOTH 0x4
413
414 static char *aw_gpio_parse_function(phandle_t node);
415 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb);
416 static uint32_t aw_gpio_parse_bias(phandle_t node);
417 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive);
418
419 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
420 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
421 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value);
422 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value);
423
424 static void aw_gpio_intr(void *arg);
425 static void aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc);
426 static void aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc);
427 static void aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc);
428 static int aw_gpio_register_isrcs(struct aw_gpio_softc *sc);
429
430 #define AW_GPIO_WRITE(_sc, _off, _val) \
431 bus_write_4((_sc)->sc_res[AW_GPIO_MEMRES], _off, _val)
432 #define AW_GPIO_READ(_sc, _off) \
433 bus_read_4((_sc)->sc_res[AW_GPIO_MEMRES], _off)
434
435 static uint32_t
aw_gpio_get_function(struct aw_gpio_softc * sc,uint32_t pin)436 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin)
437 {
438 uint32_t bank, func, offset;
439
440 /* Must be called with lock held. */
441 AW_GPIO_LOCK_ASSERT(sc);
442
443 if (pin > sc->conf->padconf->npins)
444 return (0);
445 bank = sc->conf->padconf->pins[pin].port;
446 pin = sc->conf->padconf->pins[pin].pin;
447 offset = ((pin & 0x07) << 2);
448
449 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(sc, bank, pin >> 3));
450
451 return ((func >> offset) & 0xF);
452 }
453
454 static int
aw_gpio_set_function(struct aw_gpio_softc * sc,uint32_t pin,uint32_t f)455 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f)
456 {
457 uint32_t bank, data, offset;
458
459 /* Check if the function exists in the padconf data */
460 if (sc->conf->padconf->pins[pin].functions[f] == NULL)
461 return (EINVAL);
462
463 /* Must be called with lock held. */
464 AW_GPIO_LOCK_ASSERT(sc);
465
466 bank = sc->conf->padconf->pins[pin].port;
467 pin = sc->conf->padconf->pins[pin].pin;
468 offset = ((pin & 0x07) << 2);
469
470 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(sc, bank, pin >> 3));
471 data &= ~(0xF << offset);
472 data |= (f << offset);
473 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(sc, bank, pin >> 3), data);
474
475 return (0);
476 }
477
478 static uint32_t
aw_gpio_get_pud(struct aw_gpio_softc * sc,uint32_t pin)479 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin)
480 {
481 uint32_t bank, offset, val;
482
483 /* Must be called with lock held. */
484 AW_GPIO_LOCK_ASSERT(sc);
485
486 bank = sc->conf->padconf->pins[pin].port;
487 pin = sc->conf->padconf->pins[pin].pin;
488 offset = ((pin & 0x0f) << 1);
489
490 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(sc, bank, pin >> 4));
491
492 return ((val >> offset) & AW_GPIO_PUD_MASK);
493 }
494
495 static void
aw_gpio_set_pud(struct aw_gpio_softc * sc,uint32_t pin,uint32_t state)496 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state)
497 {
498 uint32_t bank, offset, val;
499
500 if (aw_gpio_get_pud(sc, pin) == state)
501 return;
502
503 /* Must be called with lock held. */
504 AW_GPIO_LOCK_ASSERT(sc);
505
506 bank = sc->conf->padconf->pins[pin].port;
507 pin = sc->conf->padconf->pins[pin].pin;
508 offset = ((pin & 0x0f) << 1);
509
510 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(sc, bank, pin >> 4));
511 val &= ~(AW_GPIO_PUD_MASK << offset);
512 val |= (state << offset);
513 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(sc, bank, pin >> 4), val);
514 }
515
516 static uint32_t
aw_gpio_get_drv(struct aw_gpio_softc * sc,uint32_t pin)517 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin)
518 {
519 uint32_t bank, idx, offset, val;
520
521 /* Must be called with lock held. */
522 AW_GPIO_LOCK_ASSERT(sc);
523
524 bank = sc->conf->padconf->pins[pin].port;
525 pin = sc->conf->padconf->pins[pin].pin;
526 offset = (pin << sc->conf->drv_pin_shift) & 0x1F;
527 idx = (pin << sc->conf->drv_pin_shift) >> 5;
528
529 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(sc, bank, idx));
530
531 return ((val >> offset) & AW_GPIO_DRV_MASK);
532 }
533
534 static void
aw_gpio_set_drv(struct aw_gpio_softc * sc,uint32_t pin,uint32_t drive)535 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive)
536 {
537 uint32_t bank, idx, offset, val;
538
539 if (aw_gpio_get_drv(sc, pin) == drive)
540 return;
541
542 /* Must be called with lock held. */
543 AW_GPIO_LOCK_ASSERT(sc);
544
545 bank = sc->conf->padconf->pins[pin].port;
546 pin = sc->conf->padconf->pins[pin].pin;
547 offset = (pin << sc->conf->drv_pin_shift) & 0x1F;
548 idx = (pin << sc->conf->drv_pin_shift) >> 5;
549
550 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(sc, bank, idx));
551 val &= ~(AW_GPIO_DRV_MASK << offset);
552 val |= (drive << offset);
553 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(sc, bank, idx), val);
554 }
555
556 static int
aw_gpio_pin_configure(struct aw_gpio_softc * sc,uint32_t pin,uint32_t flags)557 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags)
558 {
559 u_int val;
560 int err = 0;
561
562 /* Must be called with lock held. */
563 AW_GPIO_LOCK_ASSERT(sc);
564
565 if (pin > sc->conf->padconf->npins)
566 return (EINVAL);
567
568 /* Manage input/output. */
569 if (flags & GPIO_PIN_INPUT) {
570 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
571 } else if ((flags & GPIO_PIN_OUTPUT) &&
572 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) {
573 if (flags & GPIO_PIN_PRESET_LOW) {
574 aw_gpio_pin_set_locked(sc, pin, 0);
575 } else if (flags & GPIO_PIN_PRESET_HIGH) {
576 aw_gpio_pin_set_locked(sc, pin, 1);
577 } else {
578 /* Read the pin and preset output to current state. */
579 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
580 if (err == 0) {
581 aw_gpio_pin_get_locked(sc, pin, &val);
582 aw_gpio_pin_set_locked(sc, pin, val);
583 }
584 }
585 if (err == 0)
586 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT);
587 }
588
589 if (err)
590 return (err);
591
592 /* Manage Pull-up/pull-down. */
593 if (flags & GPIO_PIN_PULLUP)
594 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP);
595 else if (flags & GPIO_PIN_PULLDOWN)
596 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN);
597 else
598 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE);
599
600 return (0);
601 }
602
603 static device_t
aw_gpio_get_bus(device_t dev)604 aw_gpio_get_bus(device_t dev)
605 {
606 struct aw_gpio_softc *sc;
607
608 sc = device_get_softc(dev);
609
610 return (sc->sc_busdev);
611 }
612
613 static int
aw_gpio_pin_max(device_t dev,int * maxpin)614 aw_gpio_pin_max(device_t dev, int *maxpin)
615 {
616 struct aw_gpio_softc *sc;
617
618 sc = device_get_softc(dev);
619
620 *maxpin = sc->conf->padconf->npins - 1;
621 return (0);
622 }
623
624 static int
aw_gpio_pin_getcaps(device_t dev,uint32_t pin,uint32_t * caps)625 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
626 {
627 struct aw_gpio_softc *sc;
628
629 sc = device_get_softc(dev);
630 if (pin >= sc->conf->padconf->npins)
631 return (EINVAL);
632
633 *caps = AW_GPIO_DEFAULT_CAPS;
634 if (sc->conf->padconf->pins[pin].eint_func != 0)
635 *caps |= AW_GPIO_INTR_CAPS;
636
637 return (0);
638 }
639
640 static int
aw_gpio_pin_getflags(device_t dev,uint32_t pin,uint32_t * flags)641 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
642 {
643 struct aw_gpio_softc *sc;
644 uint32_t func;
645 uint32_t pud;
646
647 sc = device_get_softc(dev);
648 if (pin >= sc->conf->padconf->npins)
649 return (EINVAL);
650
651 AW_GPIO_LOCK(sc);
652 func = aw_gpio_get_function(sc, pin);
653 switch (func) {
654 case AW_GPIO_INPUT:
655 *flags = GPIO_PIN_INPUT;
656 break;
657 case AW_GPIO_OUTPUT:
658 *flags = GPIO_PIN_OUTPUT;
659 break;
660 default:
661 *flags = 0;
662 break;
663 }
664
665 pud = aw_gpio_get_pud(sc, pin);
666 switch (pud) {
667 case AW_GPIO_PULLDOWN:
668 *flags |= GPIO_PIN_PULLDOWN;
669 break;
670 case AW_GPIO_PULLUP:
671 *flags |= GPIO_PIN_PULLUP;
672 break;
673 default:
674 break;
675 }
676
677 AW_GPIO_UNLOCK(sc);
678
679 return (0);
680 }
681
682 static int
aw_gpio_pin_getname(device_t dev,uint32_t pin,char * name)683 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
684 {
685 struct aw_gpio_softc *sc;
686
687 sc = device_get_softc(dev);
688 if (pin >= sc->conf->padconf->npins)
689 return (EINVAL);
690
691 snprintf(name, GPIOMAXNAME - 1, "%s",
692 sc->conf->padconf->pins[pin].name);
693 name[GPIOMAXNAME - 1] = '\0';
694
695 return (0);
696 }
697
698 static int
aw_gpio_pin_setflags(device_t dev,uint32_t pin,uint32_t flags)699 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
700 {
701 struct aw_gpio_softc *sc;
702 int err;
703
704 sc = device_get_softc(dev);
705 if (pin > sc->conf->padconf->npins)
706 return (EINVAL);
707
708 AW_GPIO_LOCK(sc);
709 err = aw_gpio_pin_configure(sc, pin, flags);
710 AW_GPIO_UNLOCK(sc);
711
712 return (err);
713 }
714
715 static int
aw_gpio_pin_set_locked(struct aw_gpio_softc * sc,uint32_t pin,unsigned int value)716 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin,
717 unsigned int value)
718 {
719 uint32_t bank, data;
720
721 AW_GPIO_LOCK_ASSERT(sc);
722
723 if (pin > sc->conf->padconf->npins)
724 return (EINVAL);
725
726 bank = sc->conf->padconf->pins[pin].port;
727 pin = sc->conf->padconf->pins[pin].pin;
728
729 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
730 if (value)
731 data |= (1 << pin);
732 else
733 data &= ~(1 << pin);
734 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(sc, bank), data);
735
736 return (0);
737 }
738
739 static int
aw_gpio_pin_set(device_t dev,uint32_t pin,unsigned int value)740 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
741 {
742 struct aw_gpio_softc *sc;
743 int ret;
744
745 sc = device_get_softc(dev);
746
747 AW_GPIO_LOCK(sc);
748 ret = aw_gpio_pin_set_locked(sc, pin, value);
749 AW_GPIO_UNLOCK(sc);
750
751 return (ret);
752 }
753
754 static int
aw_gpio_pin_get_locked(struct aw_gpio_softc * sc,uint32_t pin,unsigned int * val)755 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin,
756 unsigned int *val)
757 {
758 uint32_t bank, reg_data;
759 int32_t func;
760 int err;
761
762 AW_GPIO_LOCK_ASSERT(sc);
763
764 if (pin > sc->conf->padconf->npins)
765 return (EINVAL);
766
767 func = aw_gpio_get_function(sc, pin);
768 if (func == sc->conf->padconf->pins[pin].eint_func) { /* "pl_eintX */
769 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT);
770 if (err != 0)
771 return (err);
772 }
773
774 bank = sc->conf->padconf->pins[pin].port;
775 pin = sc->conf->padconf->pins[pin].pin;
776
777 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
778 *val = (reg_data & (1 << pin)) ? 1 : 0;
779
780 if (func == sc->conf->padconf->pins[pin].eint_func)
781 (void)aw_gpio_set_function(sc, pin, func);
782
783 return (0);
784 }
785
786 static char *
aw_gpio_parse_function(phandle_t node)787 aw_gpio_parse_function(phandle_t node)
788 {
789 char *function;
790
791 if (OF_getprop_alloc(node, "function",
792 (void **)&function) != -1)
793 return (function);
794 if (OF_getprop_alloc(node, "allwinner,function",
795 (void **)&function) != -1)
796 return (function);
797
798 return (NULL);
799 }
800
801 static const char **
aw_gpio_parse_pins(phandle_t node,int * pins_nb)802 aw_gpio_parse_pins(phandle_t node, int *pins_nb)
803 {
804 const char **pinlist;
805
806 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
807 if (*pins_nb > 0)
808 return (pinlist);
809
810 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
811 &pinlist);
812 if (*pins_nb > 0)
813 return (pinlist);
814
815 return (NULL);
816 }
817
818 static uint32_t
aw_gpio_parse_bias(phandle_t node)819 aw_gpio_parse_bias(phandle_t node)
820 {
821 uint32_t bias;
822
823 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1)
824 return (bias);
825 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1)
826 return (bias);
827 if (OF_hasprop(node, "bias-disable"))
828 return (AW_GPIO_NONE);
829 if (OF_hasprop(node, "bias-pull-up"))
830 return (AW_GPIO_PULLUP);
831 if (OF_hasprop(node, "bias-pull-down"))
832 return (AW_GPIO_PULLDOWN);
833
834 return (AW_GPIO_NONE);
835 }
836
837 static int
aw_gpio_parse_drive_strength(phandle_t node,uint32_t * drive)838 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive)
839 {
840 uint32_t drive_str;
841
842 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1)
843 return (0);
844 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1)
845 return (0);
846 if (OF_getencprop(node, "drive-strength", &drive_str,
847 sizeof(drive_str)) != -1) {
848 *drive = (drive_str / 10) - 1;
849 return (0);
850 }
851
852 return (1);
853 }
854
855 static int
aw_gpio_pin_get(device_t dev,uint32_t pin,unsigned int * val)856 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
857 {
858 struct aw_gpio_softc *sc;
859 int ret;
860
861 sc = device_get_softc(dev);
862
863 AW_GPIO_LOCK(sc);
864 ret = aw_gpio_pin_get_locked(sc, pin, val);
865 AW_GPIO_UNLOCK(sc);
866
867 return (ret);
868 }
869
870 static int
aw_gpio_pin_toggle(device_t dev,uint32_t pin)871 aw_gpio_pin_toggle(device_t dev, uint32_t pin)
872 {
873 struct aw_gpio_softc *sc;
874 uint32_t bank, data;
875
876 sc = device_get_softc(dev);
877 if (pin > sc->conf->padconf->npins)
878 return (EINVAL);
879
880 bank = sc->conf->padconf->pins[pin].port;
881 pin = sc->conf->padconf->pins[pin].pin;
882
883 AW_GPIO_LOCK(sc);
884 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
885 if (data & (1 << pin))
886 data &= ~(1 << pin);
887 else
888 data |= (1 << pin);
889 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(sc, bank), data);
890 AW_GPIO_UNLOCK(sc);
891
892 return (0);
893 }
894
895 static int
aw_gpio_pin_access_32(device_t dev,uint32_t first_pin,uint32_t clear_pins,uint32_t change_pins,uint32_t * orig_pins)896 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
897 uint32_t change_pins, uint32_t *orig_pins)
898 {
899 struct aw_gpio_softc *sc;
900 uint32_t bank, data, pin;
901
902 sc = device_get_softc(dev);
903 if (first_pin > sc->conf->padconf->npins)
904 return (EINVAL);
905
906 /*
907 * We require that first_pin refers to the first pin in a bank, because
908 * this API is not about convenience, it's for making a set of pins
909 * change simultaneously (required) with reasonably high performance
910 * (desired); we need to do a read-modify-write on a single register.
911 */
912 bank = sc->conf->padconf->pins[first_pin].port;
913 pin = sc->conf->padconf->pins[first_pin].pin;
914 if (pin != 0)
915 return (EINVAL);
916
917 AW_GPIO_LOCK(sc);
918 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(sc, bank));
919 if ((clear_pins | change_pins) != 0)
920 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(sc, bank),
921 (data & ~clear_pins) ^ change_pins);
922 AW_GPIO_UNLOCK(sc);
923
924 if (orig_pins != NULL)
925 *orig_pins = data;
926
927 return (0);
928 }
929
930 static int
aw_gpio_pin_config_32(device_t dev,uint32_t first_pin,uint32_t num_pins,uint32_t * pin_flags)931 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
932 uint32_t *pin_flags)
933 {
934 struct aw_gpio_softc *sc;
935 uint32_t pin;
936 int err;
937
938 sc = device_get_softc(dev);
939 if (first_pin > sc->conf->padconf->npins)
940 return (EINVAL);
941
942 if (sc->conf->padconf->pins[first_pin].pin != 0)
943 return (EINVAL);
944
945 /*
946 * The configuration for a bank of pins is scattered among several
947 * registers; we cannot g'tee to simultaneously change the state of all
948 * the pins in the flags array. So just loop through the array
949 * configuring each pin for now. If there was a strong need, it might
950 * be possible to support some limited simultaneous config, such as
951 * adjacent groups of 8 pins that line up the same as the config regs.
952 */
953 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
954 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
955 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]);
956 }
957
958 return (err);
959 }
960
961 static int
aw_gpio_map_gpios(device_t bus,phandle_t dev,phandle_t gparent,int gcells,pcell_t * gpios,uint32_t * pin,uint32_t * flags)962 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
963 pcell_t *gpios, uint32_t *pin, uint32_t *flags)
964 {
965 struct aw_gpio_softc *sc;
966 int i;
967
968 sc = device_get_softc(bus);
969
970 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
971 for (i = 0; i < sc->conf->padconf->npins; i++)
972 if (sc->conf->padconf->pins[i].port == gpios[0] &&
973 sc->conf->padconf->pins[i].pin == gpios[1]) {
974 *pin = i;
975 break;
976 }
977 *flags = gpios[gcells - 1];
978
979 return (0);
980 }
981
982 static int
aw_find_pinnum_by_name(struct aw_gpio_softc * sc,const char * pinname)983 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname)
984 {
985 int i;
986
987 for (i = 0; i < sc->conf->padconf->npins; i++)
988 if (!strcmp(pinname, sc->conf->padconf->pins[i].name))
989 return i;
990
991 return (-1);
992 }
993
994 static int
aw_find_pin_func(struct aw_gpio_softc * sc,int pin,const char * func)995 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func)
996 {
997 int i;
998
999 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
1000 if (sc->conf->padconf->pins[pin].functions[i] &&
1001 !strcmp(func, sc->conf->padconf->pins[pin].functions[i]))
1002 return (i);
1003
1004 return (-1);
1005 }
1006
1007 static int
aw_fdt_configure_pins(device_t dev,phandle_t cfgxref)1008 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
1009 {
1010 struct aw_gpio_softc *sc;
1011 phandle_t node;
1012 const char **pinlist = NULL;
1013 char *pin_function = NULL;
1014 uint32_t pin_drive, pin_pull;
1015 int pins_nb, pin_num, pin_func, i, ret;
1016 bool set_drive;
1017
1018 sc = device_get_softc(dev);
1019 node = OF_node_from_xref(cfgxref);
1020 ret = 0;
1021 set_drive = false;
1022
1023 /* Getting all prop for configuring pins */
1024 pinlist = aw_gpio_parse_pins(node, &pins_nb);
1025 if (pinlist == NULL)
1026 return (ENOENT);
1027
1028 pin_function = aw_gpio_parse_function(node);
1029 if (pin_function == NULL) {
1030 ret = ENOENT;
1031 goto out;
1032 }
1033
1034 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0)
1035 set_drive = true;
1036
1037 pin_pull = aw_gpio_parse_bias(node);
1038
1039 /* Configure each pin to the correct function, drive and pull */
1040 for (i = 0; i < pins_nb; i++) {
1041 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
1042 if (pin_num == -1) {
1043 ret = ENOENT;
1044 goto out;
1045 }
1046 pin_func = aw_find_pin_func(sc, pin_num, pin_function);
1047 if (pin_func == -1) {
1048 ret = ENOENT;
1049 goto out;
1050 }
1051
1052 AW_GPIO_LOCK(sc);
1053
1054 if (aw_gpio_get_function(sc, pin_num) != pin_func)
1055 aw_gpio_set_function(sc, pin_num, pin_func);
1056 if (set_drive)
1057 aw_gpio_set_drv(sc, pin_num, pin_drive);
1058 if (pin_pull != AW_GPIO_NONE)
1059 aw_gpio_set_pud(sc, pin_num, pin_pull);
1060
1061 AW_GPIO_UNLOCK(sc);
1062 }
1063
1064 out:
1065 OF_prop_free(pinlist);
1066 OF_prop_free(pin_function);
1067 return (ret);
1068 }
1069
1070 static void
aw_gpio_enable_bank_supply(void * arg)1071 aw_gpio_enable_bank_supply(void *arg)
1072 {
1073 struct aw_gpio_softc *sc = arg;
1074 regulator_t vcc_supply;
1075 char bank_reg_name[16];
1076 int i, nbanks;
1077
1078 nbanks = strlen(sc->conf->banks);
1079 for (i = 0; i < nbanks; i++) {
1080 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply",
1081 sc->conf->banks[i]);
1082
1083 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) {
1084 if (bootverbose)
1085 device_printf(sc->sc_dev,
1086 "Enabling regulator for gpio bank %c\n",
1087 sc->conf->banks[i]);
1088 if (regulator_enable(vcc_supply) != 0) {
1089 device_printf(sc->sc_dev,
1090 "Cannot enable regulator for bank %c\n",
1091 sc->conf->banks[i]);
1092 }
1093 }
1094 }
1095 }
1096
1097 static int
aw_gpio_probe(device_t dev)1098 aw_gpio_probe(device_t dev)
1099 {
1100
1101 if (!ofw_bus_status_okay(dev))
1102 return (ENXIO);
1103
1104 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1105 return (ENXIO);
1106
1107 device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
1108 return (BUS_PROBE_DEFAULT);
1109 }
1110
1111 static int
aw_gpio_attach(device_t dev)1112 aw_gpio_attach(device_t dev)
1113 {
1114 int error;
1115 phandle_t gpio;
1116 struct aw_gpio_softc *sc;
1117 struct clk_list *clkp, *clkp_tmp;
1118 clk_t clk;
1119 hwreset_t rst = NULL;
1120 int off, err, clkret;
1121
1122 sc = device_get_softc(dev);
1123 sc->sc_dev = dev;
1124
1125 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN);
1126
1127 if (bus_alloc_resources(dev, aw_gpio_res_spec, sc->sc_res) != 0) {
1128 device_printf(dev, "cannot allocate device resources\n");
1129 return (ENXIO);
1130 }
1131
1132 if (bus_setup_intr(dev, sc->sc_res[AW_GPIO_IRQRES],
1133 INTR_TYPE_CLK | INTR_MPSAFE, NULL, aw_gpio_intr, sc,
1134 &sc->sc_intrhand)) {
1135 device_printf(dev, "cannot setup interrupt handler\n");
1136 goto fail;
1137 }
1138
1139 /* Find our node. */
1140 gpio = ofw_bus_get_node(sc->sc_dev);
1141 if (!OF_hasprop(gpio, "gpio-controller"))
1142 /* Node is not a GPIO controller. */
1143 goto fail;
1144
1145 /* Use the right pin data for the current SoC */
1146 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev,
1147 compat_data)->ocd_data;
1148
1149 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
1150 error = hwreset_deassert(rst);
1151 if (error != 0) {
1152 device_printf(dev, "cannot de-assert reset\n");
1153 goto fail;
1154 }
1155 }
1156
1157 TAILQ_INIT(&sc->clk_list);
1158 for (off = 0, clkret = 0; clkret == 0; off++) {
1159 clkret = clk_get_by_ofw_index(dev, 0, off, &clk);
1160 if (clkret != 0)
1161 break;
1162 err = clk_enable(clk);
1163 if (err != 0) {
1164 device_printf(dev, "Could not enable clock %s\n",
1165 clk_get_name(clk));
1166 goto fail;
1167 }
1168 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
1169 clkp->clk = clk;
1170 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
1171 }
1172 if (clkret != 0 && clkret != ENOENT) {
1173 device_printf(dev, "Could not find clock at offset %d (%d)\n",
1174 off, clkret);
1175 goto fail;
1176 }
1177
1178 aw_gpio_register_isrcs(sc);
1179 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
1180
1181 /*
1182 * Register as a pinctrl device
1183 */
1184 fdt_pinctrl_register(dev, "pins");
1185 fdt_pinctrl_configure_tree(dev);
1186 fdt_pinctrl_register(dev, "allwinner,pins");
1187 fdt_pinctrl_configure_tree(dev);
1188
1189 sc->sc_busdev = gpiobus_add_bus(dev);
1190 if (sc->sc_busdev == NULL)
1191 goto fail;
1192
1193 config_intrhook_oneshot(aw_gpio_enable_bank_supply, sc);
1194 bus_attach_children(dev);
1195
1196 return (0);
1197
1198 fail:
1199 if (sc->sc_irq_res)
1200 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
1201 if (sc->sc_mem_res)
1202 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
1203 mtx_destroy(&sc->sc_mtx);
1204
1205 /* Disable clock */
1206 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
1207 err = clk_disable(clkp->clk);
1208 if (err != 0)
1209 device_printf(dev, "Could not disable clock %s\n",
1210 clk_get_name(clkp->clk));
1211 err = clk_release(clkp->clk);
1212 if (err != 0)
1213 device_printf(dev, "Could not release clock %s\n",
1214 clk_get_name(clkp->clk));
1215 TAILQ_REMOVE(&sc->clk_list, clkp, next);
1216 free(clkp, M_DEVBUF);
1217 }
1218
1219 /* Assert resets */
1220 if (rst) {
1221 hwreset_assert(rst);
1222 hwreset_release(rst);
1223 }
1224
1225 return (ENXIO);
1226 }
1227
1228 static int
aw_gpio_detach(device_t dev)1229 aw_gpio_detach(device_t dev)
1230 {
1231
1232 return (EBUSY);
1233 }
1234
1235 static void
aw_gpio_intr(void * arg)1236 aw_gpio_intr(void *arg)
1237 {
1238 struct aw_gpio_softc *sc;
1239 struct intr_irqsrc *isrc;
1240 uint32_t reg;
1241 int irq;
1242
1243 sc = (struct aw_gpio_softc *)arg;
1244
1245 AW_GPIO_LOCK(sc);
1246 for (irq = 0; irq < sc->nirqs; irq++) {
1247 if (!sc->gpio_pic_irqsrc[irq].enabled)
1248 continue;
1249
1250 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));
1251 if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))
1252 continue;
1253
1254 isrc = &sc->gpio_pic_irqsrc[irq].isrc;
1255 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) {
1256 aw_gpio_pic_disable_intr_locked(sc, isrc);
1257 aw_gpio_pic_post_filter(sc->sc_dev, isrc);
1258 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq);
1259 }
1260 }
1261 AW_GPIO_UNLOCK(sc);
1262 }
1263
1264 /*
1265 * Interrupts support
1266 */
1267
1268 static int
aw_gpio_register_isrcs(struct aw_gpio_softc * sc)1269 aw_gpio_register_isrcs(struct aw_gpio_softc *sc)
1270 {
1271 const char *name;
1272 int nirqs;
1273 int pin;
1274 int err;
1275
1276 name = device_get_nameunit(sc->sc_dev);
1277
1278 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1279 if (sc->conf->padconf->pins[pin].eint_func == 0)
1280 continue;
1281
1282 nirqs++;
1283 }
1284
1285 sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs,
1286 M_DEVBUF, M_WAITOK | M_ZERO);
1287 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) {
1288 if (sc->conf->padconf->pins[pin].eint_func == 0)
1289 continue;
1290
1291 sc->gpio_pic_irqsrc[nirqs].pin = pin;
1292 sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank;
1293 sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num;
1294 sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func;
1295 sc->gpio_pic_irqsrc[nirqs].irq = nirqs;
1296 sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM;
1297
1298 err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc,
1299 sc->sc_dev, 0, "%s,%s", name,
1300 sc->conf->padconf->pins[pin].functions[sc->conf->padconf->pins[pin].eint_func]);
1301 if (err) {
1302 device_printf(sc->sc_dev, "intr_isrs_register failed for irq %d\n", nirqs);
1303 }
1304
1305 nirqs++;
1306 }
1307
1308 sc->nirqs = nirqs;
1309
1310 return (0);
1311 }
1312
1313 static void
aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc * sc,struct intr_irqsrc * isrc)1314 aw_gpio_pic_disable_intr_locked(struct aw_gpio_softc *sc, struct intr_irqsrc *isrc)
1315 {
1316 u_int irq;
1317 uint32_t reg;
1318
1319 AW_GPIO_LOCK_ASSERT(sc);
1320 irq = ((struct gpio_irqsrc *)isrc)->irq;
1321 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1322 reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);
1323 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1324
1325 sc->gpio_pic_irqsrc[irq].enabled = false;
1326 }
1327
1328 static void
aw_gpio_pic_disable_intr(device_t dev,struct intr_irqsrc * isrc)1329 aw_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
1330 {
1331 struct aw_gpio_softc *sc;
1332
1333 sc = device_get_softc(dev);
1334
1335 AW_GPIO_LOCK(sc);
1336 aw_gpio_pic_disable_intr_locked(sc, isrc);
1337 AW_GPIO_UNLOCK(sc);
1338 }
1339
1340 static void
aw_gpio_pic_enable_intr(device_t dev,struct intr_irqsrc * isrc)1341 aw_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
1342 {
1343 struct aw_gpio_softc *sc;
1344 u_int irq;
1345 uint32_t reg;
1346
1347 sc = device_get_softc(dev);
1348 irq = ((struct gpio_irqsrc *)isrc)->irq;
1349 AW_GPIO_LOCK(sc);
1350 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1351 reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;
1352 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1353 AW_GPIO_UNLOCK(sc);
1354
1355 sc->gpio_pic_irqsrc[irq].enabled = true;
1356 }
1357
1358 static int
aw_gpio_pic_map_gpio(struct aw_gpio_softc * sc,struct intr_map_data_gpio * dag,u_int * irqp,u_int * mode)1359 aw_gpio_pic_map_gpio(struct aw_gpio_softc *sc, struct intr_map_data_gpio *dag,
1360 u_int *irqp, u_int *mode)
1361 {
1362 u_int irq;
1363 int pin;
1364
1365 irq = dag->gpio_pin_num;
1366
1367 for (pin = 0; pin < sc->nirqs; pin++)
1368 if (sc->gpio_pic_irqsrc[pin].pin == irq)
1369 break;
1370 if (pin == sc->nirqs) {
1371 device_printf(sc->sc_dev, "Invalid interrupt number %u\n", irq);
1372 return (EINVAL);
1373 }
1374
1375 switch (dag->gpio_intr_mode) {
1376 case GPIO_INTR_LEVEL_LOW:
1377 case GPIO_INTR_LEVEL_HIGH:
1378 case GPIO_INTR_EDGE_RISING:
1379 case GPIO_INTR_EDGE_FALLING:
1380 case GPIO_INTR_EDGE_BOTH:
1381 break;
1382 default:
1383 device_printf(sc->sc_dev, "Unsupported interrupt mode 0x%8x\n",
1384 dag->gpio_intr_mode);
1385 return (EINVAL);
1386 }
1387
1388 *irqp = pin;
1389 if (mode != NULL)
1390 *mode = dag->gpio_intr_mode;
1391
1392 return (0);
1393 }
1394
1395 static int
aw_gpio_pic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)1396 aw_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
1397 struct intr_irqsrc **isrcp)
1398 {
1399 struct aw_gpio_softc *sc;
1400 u_int irq;
1401 int err;
1402
1403 sc = device_get_softc(dev);
1404 switch (data->type) {
1405 case INTR_MAP_DATA_GPIO:
1406 err = aw_gpio_pic_map_gpio(sc,
1407 (struct intr_map_data_gpio *)data,
1408 &irq, NULL);
1409 break;
1410 default:
1411 return (ENOTSUP);
1412 };
1413
1414 if (err == 0)
1415 *isrcp = &sc->gpio_pic_irqsrc[irq].isrc;
1416 return (0);
1417 }
1418
1419 static int
aw_gpio_pic_setup_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1420 aw_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
1421 struct resource *res, struct intr_map_data *data)
1422 {
1423 struct aw_gpio_softc *sc;
1424 uint32_t irqcfg;
1425 uint32_t pinidx, reg;
1426 u_int irq, mode;
1427 int err;
1428
1429 sc = device_get_softc(dev);
1430
1431 err = 0;
1432 switch (data->type) {
1433 case INTR_MAP_DATA_GPIO:
1434 err = aw_gpio_pic_map_gpio(sc,
1435 (struct intr_map_data_gpio *)data,
1436 &irq, &mode);
1437 if (err != 0)
1438 return (err);
1439 break;
1440 default:
1441 return (ENOTSUP);
1442 };
1443
1444 pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4;
1445
1446 AW_GPIO_LOCK(sc);
1447 switch (mode) {
1448 case GPIO_INTR_LEVEL_LOW:
1449 irqcfg = AW_GPIO_INT_LEVEL_LOW << pinidx;
1450 break;
1451 case GPIO_INTR_LEVEL_HIGH:
1452 irqcfg = AW_GPIO_INT_LEVEL_HIGH << pinidx;
1453 break;
1454 case GPIO_INTR_EDGE_RISING:
1455 irqcfg = AW_GPIO_INT_EDGE_POSITIVE << pinidx;
1456 break;
1457 case GPIO_INTR_EDGE_FALLING:
1458 irqcfg = AW_GPIO_INT_EDGE_NEGATIVE << pinidx;
1459 break;
1460 case GPIO_INTR_EDGE_BOTH:
1461 irqcfg = AW_GPIO_INT_EDGE_BOTH << pinidx;
1462 break;
1463 }
1464
1465 /* Switch the pin to interrupt mode */
1466 sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc,
1467 sc->gpio_pic_irqsrc[irq].pin);
1468 aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin,
1469 sc->gpio_pic_irqsrc[irq].intfunc);
1470
1471 /* Write interrupt mode */
1472 reg = AW_GPIO_READ(sc,
1473 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1474 sc->gpio_pic_irqsrc[irq].intnum));
1475 reg &= ~(0xF << pinidx);
1476 reg |= irqcfg;
1477 AW_GPIO_WRITE(sc,
1478 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1479 sc->gpio_pic_irqsrc[irq].intnum),
1480 reg);
1481
1482 AW_GPIO_UNLOCK(sc);
1483
1484 return (0);
1485 }
1486
1487 static int
aw_gpio_pic_teardown_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)1488 aw_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
1489 struct resource *res, struct intr_map_data *data)
1490 {
1491 struct aw_gpio_softc *sc;
1492 struct gpio_irqsrc *gi;
1493
1494 sc = device_get_softc(dev);
1495 gi = (struct gpio_irqsrc *)isrc;
1496
1497 /* Switch back the pin to it's original function */
1498 AW_GPIO_LOCK(sc);
1499 aw_gpio_set_function(sc, gi->pin, gi->oldfunc);
1500 AW_GPIO_UNLOCK(sc);
1501
1502 return (0);
1503 }
1504
1505 static void
aw_gpio_pic_post_filter(device_t dev,struct intr_irqsrc * isrc)1506 aw_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
1507 {
1508 struct aw_gpio_softc *sc;
1509 struct gpio_irqsrc *gi;
1510
1511 sc = device_get_softc(dev);
1512 gi = (struct gpio_irqsrc *)isrc;
1513
1514 IRQ_MEMORY_BARRIER(0);
1515 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1516 }
1517
1518 static void
aw_gpio_pic_post_ithread(device_t dev,struct intr_irqsrc * isrc)1519 aw_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
1520 {
1521 struct aw_gpio_softc *sc;
1522 struct gpio_irqsrc *gi;
1523
1524 sc = device_get_softc(dev);
1525 gi = (struct gpio_irqsrc *)isrc;
1526
1527 IRQ_MEMORY_BARRIER(0);
1528 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum);
1529 aw_gpio_pic_enable_intr(dev, isrc);
1530 }
1531
1532 static void
aw_gpio_pic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)1533 aw_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
1534 {
1535 struct aw_gpio_softc *sc;
1536
1537 sc = device_get_softc(dev);
1538 aw_gpio_pic_disable_intr_locked(sc, isrc);
1539 }
1540
1541 /*
1542 * OFWBUS Interface
1543 */
1544 static phandle_t
aw_gpio_get_node(device_t dev,device_t bus)1545 aw_gpio_get_node(device_t dev, device_t bus)
1546 {
1547
1548 /* We only have one child, the GPIO bus, which needs our own node. */
1549 return (ofw_bus_get_node(dev));
1550 }
1551
1552 static device_method_t aw_gpio_methods[] = {
1553 /* Device interface */
1554 DEVMETHOD(device_probe, aw_gpio_probe),
1555 DEVMETHOD(device_attach, aw_gpio_attach),
1556 DEVMETHOD(device_detach, aw_gpio_detach),
1557
1558 /* Bus interface */
1559 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1560 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1561
1562 /* Interrupt controller interface */
1563 DEVMETHOD(pic_disable_intr, aw_gpio_pic_disable_intr),
1564 DEVMETHOD(pic_enable_intr, aw_gpio_pic_enable_intr),
1565 DEVMETHOD(pic_map_intr, aw_gpio_pic_map_intr),
1566 DEVMETHOD(pic_setup_intr, aw_gpio_pic_setup_intr),
1567 DEVMETHOD(pic_teardown_intr, aw_gpio_pic_teardown_intr),
1568 DEVMETHOD(pic_post_filter, aw_gpio_pic_post_filter),
1569 DEVMETHOD(pic_post_ithread, aw_gpio_pic_post_ithread),
1570 DEVMETHOD(pic_pre_ithread, aw_gpio_pic_pre_ithread),
1571
1572 /* GPIO protocol */
1573 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus),
1574 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max),
1575 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname),
1576 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags),
1577 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps),
1578 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags),
1579 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get),
1580 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set),
1581 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle),
1582 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32),
1583 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32),
1584 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios),
1585
1586 /* ofw_bus interface */
1587 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node),
1588
1589 /* fdt_pinctrl interface */
1590 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
1591
1592 DEVMETHOD_END
1593 };
1594
1595 static driver_t aw_gpio_driver = {
1596 "gpio",
1597 aw_gpio_methods,
1598 sizeof(struct aw_gpio_softc),
1599 };
1600
1601 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, 0, 0,
1602 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
1603