1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020-2025 Intel Corporation
4 */
5
6 #include <linux/firmware.h>
7 #include <linux/highmem.h>
8 #include <linux/moduleparam.h>
9 #include <linux/pci.h>
10
11 #include "vpu_boot_api.h"
12 #include "ivpu_drv.h"
13 #include "ivpu_fw.h"
14 #include "ivpu_fw_log.h"
15 #include "ivpu_gem.h"
16 #include "ivpu_hw.h"
17 #include "ivpu_ipc.h"
18 #include "ivpu_pm.h"
19
20 #define FW_SHAVE_NN_MAX_SIZE SZ_2M
21 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE)
22 #define FW_PREEMPT_BUF_MIN_SIZE SZ_4K
23 #define FW_PREEMPT_BUF_MAX_SIZE SZ_32M
24
25 #define WATCHDOG_MSS_REDIRECT 32
26 #define WATCHDOG_NCE_REDIRECT 33
27
28 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31)
29
30 /* Check if FW API is compatible with the driver */
31 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \
32 ivpu_fw_check_api(vdev, fw_hdr, #name, \
33 VPU_##name##_API_VER_INDEX, \
34 VPU_##name##_API_VER_MAJOR, \
35 VPU_##name##_API_VER_MINOR, min_major)
36
37 /* Check if API version is lower that the given version */
38 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \
39 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor)
40
41 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000
42
43 static char *ivpu_firmware;
44 #if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
45 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644);
46 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/..");
47 #endif
48
49 static struct {
50 int gen;
51 const char *name;
52 } fw_names[] = {
53 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v1.bin" },
54 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
55 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v1.bin" },
56 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
57 { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v1.bin" },
58 { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" },
59 { IVPU_HW_IP_60XX, "intel/vpu/vpu_60xx_v1.bin" },
60 };
61
62 /* Production fw_names from the table above */
63 MODULE_FIRMWARE("intel/vpu/vpu_37xx_v1.bin");
64 MODULE_FIRMWARE("intel/vpu/vpu_40xx_v1.bin");
65 MODULE_FIRMWARE("intel/vpu/vpu_50xx_v1.bin");
66 MODULE_FIRMWARE("intel/vpu/vpu_60xx_v1.bin");
67
ivpu_fw_request(struct ivpu_device * vdev)68 static int ivpu_fw_request(struct ivpu_device *vdev)
69 {
70 int ret = -ENOENT;
71 int i;
72
73 if (ivpu_firmware) {
74 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev);
75 if (!ret)
76 vdev->fw->name = ivpu_firmware;
77 return ret;
78 }
79
80 for (i = 0; i < ARRAY_SIZE(fw_names); i++) {
81 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev))
82 continue;
83
84 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev);
85 if (!ret) {
86 vdev->fw->name = fw_names[i].name;
87 return 0;
88 }
89 }
90
91 ivpu_err(vdev, "Failed to request firmware: %d\n", ret);
92 return ret;
93 }
94
95 static int
ivpu_fw_check_api(struct ivpu_device * vdev,const struct vpu_firmware_header * fw_hdr,const char * str,int index,u16 expected_major,u16 expected_minor,u16 min_major)96 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
97 const char *str, int index, u16 expected_major, u16 expected_minor,
98 u16 min_major)
99 {
100 u16 major = (u16)(fw_hdr->api_version[index] >> 16);
101 u16 minor = (u16)(fw_hdr->api_version[index]);
102
103 if (major < min_major) {
104 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n",
105 str, major, minor, min_major);
106 return -EINVAL;
107 }
108 if (major != expected_major) {
109 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n",
110 str, major, minor, expected_major, expected_minor);
111 }
112 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n",
113 str, major, minor, expected_major, expected_minor);
114
115 return 0;
116 }
117
118 static bool
ivpu_fw_check_api_ver_lt(struct ivpu_device * vdev,const struct vpu_firmware_header * fw_hdr,const char * str,int index,u16 major,u16 minor)119 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr,
120 const char *str, int index, u16 major, u16 minor)
121 {
122 u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16);
123 u16 fw_minor = (u16)(fw_hdr->api_version[index]);
124
125 if (fw_major < major || (fw_major == major && fw_minor < minor))
126 return true;
127
128 return false;
129 }
130
ivpu_is_within_range(u64 addr,size_t size,struct ivpu_addr_range * range)131 bool ivpu_is_within_range(u64 addr, size_t size, struct ivpu_addr_range *range)
132 {
133 u64 addr_end;
134
135 if (!range || check_add_overflow(addr, size, &addr_end))
136 return false;
137
138 if (addr < range->start || addr_end > range->end)
139 return false;
140
141 return true;
142 }
143
144 static u32
ivpu_fw_sched_mode_select(struct ivpu_device * vdev,const struct vpu_firmware_header * fw_hdr)145 ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
146 {
147 if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_60XX &&
148 ivpu_sched_mode == VPU_SCHEDULING_MODE_OS) {
149 ivpu_warn(vdev, "OS sched mode is not supported, using HW mode\n");
150 return VPU_SCHEDULING_MODE_HW;
151 }
152
153 if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO)
154 return ivpu_sched_mode;
155
156 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, JSM, 3, 24))
157 return VPU_SCHEDULING_MODE_OS;
158
159 return VPU_SCHEDULING_MODE_HW;
160 }
161
162 static void
ivpu_preemption_config_parse(struct ivpu_device * vdev,const struct vpu_firmware_header * fw_hdr)163 ivpu_preemption_config_parse(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr)
164 {
165 struct ivpu_fw_info *fw = vdev->fw;
166 u32 primary_preempt_buf_size, secondary_preempt_buf_size;
167
168 if (fw_hdr->preemption_buffer_1_max_size)
169 primary_preempt_buf_size = fw_hdr->preemption_buffer_1_max_size;
170 else
171 primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size;
172
173 if (fw_hdr->preemption_buffer_2_max_size)
174 secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_max_size;
175 else
176 secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size;
177
178 ivpu_dbg(vdev, FW_BOOT, "Preemption buffer size, primary: %u, secondary: %u\n",
179 primary_preempt_buf_size, secondary_preempt_buf_size);
180
181 if (primary_preempt_buf_size < FW_PREEMPT_BUF_MIN_SIZE ||
182 secondary_preempt_buf_size < FW_PREEMPT_BUF_MIN_SIZE) {
183 ivpu_warn(vdev, "Preemption buffers size too small\n");
184 return;
185 }
186
187 if (primary_preempt_buf_size > FW_PREEMPT_BUF_MAX_SIZE ||
188 secondary_preempt_buf_size > FW_PREEMPT_BUF_MAX_SIZE) {
189 ivpu_warn(vdev, "Preemption buffers size too big\n");
190 return;
191 }
192
193 if (fw->sched_mode != VPU_SCHEDULING_MODE_HW)
194 return;
195
196 if (ivpu_test_mode & IVPU_TEST_MODE_MIP_DISABLE)
197 return;
198
199 vdev->fw->primary_preempt_buf_size = ALIGN(primary_preempt_buf_size, PAGE_SIZE);
200 vdev->fw->secondary_preempt_buf_size = ALIGN(secondary_preempt_buf_size, PAGE_SIZE);
201 }
202
ivpu_fw_parse(struct ivpu_device * vdev)203 static int ivpu_fw_parse(struct ivpu_device *vdev)
204 {
205 struct ivpu_fw_info *fw = vdev->fw;
206 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data;
207 struct ivpu_addr_range fw_image_range;
208 u64 boot_params_addr, boot_params_size;
209 u64 fw_version_addr, fw_version_size;
210 u64 runtime_addr, runtime_size;
211 u64 image_load_addr, image_size;
212
213 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) {
214 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size);
215 return -EINVAL;
216 }
217
218 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) {
219 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version);
220 return -EINVAL;
221 }
222
223 boot_params_addr = fw_hdr->boot_params_load_address;
224 boot_params_size = SZ_4K;
225
226 if (!ivpu_is_within_range(boot_params_addr, boot_params_size, &vdev->hw->ranges.runtime)) {
227 ivpu_err(vdev, "Invalid boot params address: 0x%llx\n", boot_params_addr);
228 return -EINVAL;
229 }
230
231 fw_version_addr = fw_hdr->firmware_version_load_address;
232 fw_version_size = ALIGN(fw_hdr->firmware_version_size, SZ_4K);
233
234 if (fw_version_size != SZ_4K) {
235 ivpu_err(vdev, "Invalid firmware version size: %u\n",
236 fw_hdr->firmware_version_size);
237 return -EINVAL;
238 }
239
240 if (!ivpu_is_within_range(fw_version_addr, fw_version_size, &vdev->hw->ranges.runtime)) {
241 ivpu_err(vdev, "Invalid firmware version address: 0x%llx\n", fw_version_addr);
242 return -EINVAL;
243 }
244
245 runtime_addr = fw_hdr->image_load_address;
246 runtime_size = fw_hdr->runtime_size - boot_params_size - fw_version_size;
247
248 image_load_addr = fw_hdr->image_load_address;
249 image_size = fw_hdr->image_size;
250
251 if (!ivpu_is_within_range(runtime_addr, runtime_size, &vdev->hw->ranges.runtime)) {
252 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx and size %llu\n",
253 runtime_addr, runtime_size);
254 return -EINVAL;
255 }
256
257 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) {
258 ivpu_err(vdev, "Invalid image size: %llu\n", image_size);
259 return -EINVAL;
260 }
261
262 if (!PAGE_ALIGNED(runtime_addr)) {
263 ivpu_err(vdev, "Runtime address 0x%llx not page aligned\n", runtime_addr);
264 return -EINVAL;
265 }
266
267 if (!PAGE_ALIGNED(runtime_size)) {
268 ivpu_err(vdev, "Runtime size %llu not page aligned\n", runtime_size);
269 return -EINVAL;
270 }
271
272 if (runtime_size < image_size) {
273 ivpu_err(vdev, "Runtime size too small: %llu, image size: %llu\n",
274 runtime_size, image_size);
275 return -EINVAL;
276 }
277
278 if (!ivpu_is_within_range(image_load_addr, image_size, &vdev->hw->ranges.runtime)) {
279 ivpu_err(vdev, "Invalid firmware load address: 0x%llx and size %llu\n",
280 image_load_addr, image_size);
281 return -EINVAL;
282 }
283
284 if (ivpu_hw_range_init(vdev, &fw_image_range, image_load_addr, image_size))
285 return -EINVAL;
286
287 if (!ivpu_is_within_range(fw_hdr->entry_point, SZ_4K, &fw_image_range)) {
288 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point);
289 return -EINVAL;
290 }
291
292 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) {
293 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size);
294 return -EINVAL;
295 }
296
297 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n",
298 fw_hdr->header_version, fw_hdr->image_format);
299
300 if (!scnprintf(fw->version, sizeof(fw->version), "%s", fw->file->data + VPU_FW_HEADER_SIZE))
301 ivpu_warn(vdev, "Missing firmware version\n");
302
303 ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version);
304
305 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3))
306 return -EINVAL;
307 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3))
308 return -EINVAL;
309
310 fw->boot_params_addr = boot_params_addr;
311 fw->boot_params_size = boot_params_size;
312 fw->fw_version_addr = fw_version_addr;
313 fw->fw_version_size = fw_version_size;
314 fw->runtime_addr = runtime_addr;
315 fw->runtime_size = runtime_size;
316 fw->image_load_offset = image_load_addr - runtime_addr;
317 fw->image_size = image_size;
318 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size);
319 fw->cold_boot_entry_point = fw_hdr->entry_point;
320
321 fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL);
322 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING;
323 fw->trace_hw_component_mask = -1;
324
325 fw->dvfs_mode = 0;
326
327 fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr);
328 ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS");
329
330 ivpu_preemption_config_parse(vdev, fw_hdr);
331 ivpu_dbg(vdev, FW_BOOT, "Mid-inference preemption %s supported\n",
332 ivpu_fw_preempt_buf_size(vdev) ? "is" : "is not");
333
334 if (fw_hdr->ro_section_start_address &&
335 !ivpu_is_within_range(fw_hdr->ro_section_start_address, fw_hdr->ro_section_size,
336 &fw_image_range)) {
337 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n",
338 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size);
339 return -EINVAL;
340 }
341
342 fw->read_only_addr = fw_hdr->ro_section_start_address;
343 fw->read_only_size = fw_hdr->ro_section_size;
344
345 ivpu_dbg(vdev, FW_BOOT, "Boot params: address 0x%llx, size %llu\n",
346 fw->boot_params_addr, fw->boot_params_size);
347 ivpu_dbg(vdev, FW_BOOT, "FW version: address 0x%llx, size %llu\n",
348 fw->fw_version_addr, fw->fw_version_size);
349 ivpu_dbg(vdev, FW_BOOT, "Runtime: address 0x%llx, size %u\n",
350 fw->runtime_addr, fw->runtime_size);
351 ivpu_dbg(vdev, FW_BOOT, "Image load offset: 0x%llx, size %u\n",
352 fw->image_load_offset, fw->image_size);
353 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n",
354 fw->read_only_addr, fw->read_only_size);
355 ivpu_dbg(vdev, FW_BOOT, "FW cold boot entry point: 0x%llx\n", fw->cold_boot_entry_point);
356 ivpu_dbg(vdev, FW_BOOT, "SHAVE NN size: %u\n", fw->shave_nn_size);
357
358 return 0;
359 }
360
ivpu_fw_release(struct ivpu_device * vdev)361 static void ivpu_fw_release(struct ivpu_device *vdev)
362 {
363 release_firmware(vdev->fw->file);
364 }
365
366 /* Initialize workarounds that depend on FW version */
367 static void
ivpu_fw_init_wa(struct ivpu_device * vdev)368 ivpu_fw_init_wa(struct ivpu_device *vdev)
369 {
370 const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
371
372 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
373 (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
374 vdev->wa.disable_d0i3_msg = true;
375
376 /* Force enable the feature for testing purposes */
377 if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
378 vdev->wa.disable_d0i3_msg = false;
379
380 IVPU_PRINT_WA(disable_d0i3_msg);
381 }
382
ivpu_fw_mem_init(struct ivpu_device * vdev)383 static int ivpu_fw_mem_init(struct ivpu_device *vdev)
384 {
385 struct ivpu_fw_info *fw = vdev->fw;
386 int log_verb_size;
387 int ret;
388
389 fw->mem_bp = ivpu_bo_create_runtime(vdev, fw->boot_params_addr, fw->boot_params_size,
390 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
391 if (!fw->mem_bp) {
392 ivpu_err(vdev, "Failed to create firmware boot params memory buffer\n");
393 return -ENOMEM;
394 }
395
396 fw->mem_fw_ver = ivpu_bo_create_runtime(vdev, fw->fw_version_addr, fw->fw_version_size,
397 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
398 if (!fw->mem_fw_ver) {
399 ivpu_err(vdev, "Failed to create firmware version memory buffer\n");
400 ret = -ENOMEM;
401 goto err_free_bp;
402 }
403
404 fw->mem = ivpu_bo_create_runtime(vdev, fw->runtime_addr, fw->runtime_size,
405 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE);
406 if (!fw->mem) {
407 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n");
408 ret = -ENOMEM;
409 goto err_free_fw_ver;
410 }
411
412 ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr,
413 fw->read_only_size);
414 if (ret) {
415 ivpu_err(vdev, "Failed to set firmware image read-only\n");
416 goto err_free_fw_mem;
417 }
418
419 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE,
420 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
421 if (!fw->mem_log_crit) {
422 ivpu_err(vdev, "Failed to create critical log buffer\n");
423 ret = -ENOMEM;
424 goto err_free_fw_mem;
425 }
426
427 if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO)
428 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE;
429 else
430 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE;
431
432 fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size,
433 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE);
434 if (!fw->mem_log_verb) {
435 ivpu_err(vdev, "Failed to create verbose log buffer\n");
436 ret = -ENOMEM;
437 goto err_free_log_crit;
438 }
439
440 if (fw->shave_nn_size) {
441 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave,
442 fw->shave_nn_size, DRM_IVPU_BO_WC);
443 if (!fw->mem_shave_nn) {
444 ivpu_err(vdev, "Failed to create shavenn buffer\n");
445 ret = -ENOMEM;
446 goto err_free_log_verb;
447 }
448 }
449
450 return 0;
451
452 err_free_log_verb:
453 ivpu_bo_free(fw->mem_log_verb);
454 err_free_log_crit:
455 ivpu_bo_free(fw->mem_log_crit);
456 err_free_fw_mem:
457 ivpu_bo_free(fw->mem);
458 err_free_fw_ver:
459 ivpu_bo_free(fw->mem_fw_ver);
460 err_free_bp:
461 ivpu_bo_free(fw->mem_bp);
462 return ret;
463 }
464
ivpu_fw_mem_fini(struct ivpu_device * vdev)465 static void ivpu_fw_mem_fini(struct ivpu_device *vdev)
466 {
467 struct ivpu_fw_info *fw = vdev->fw;
468
469 if (fw->mem_shave_nn) {
470 ivpu_bo_free(fw->mem_shave_nn);
471 fw->mem_shave_nn = NULL;
472 }
473
474 ivpu_bo_free(fw->mem_log_verb);
475 ivpu_bo_free(fw->mem_log_crit);
476 ivpu_bo_free(fw->mem);
477 ivpu_bo_free(fw->mem_fw_ver);
478 ivpu_bo_free(fw->mem_bp);
479
480 fw->mem_log_verb = NULL;
481 fw->mem_log_crit = NULL;
482 fw->mem = NULL;
483 fw->mem_fw_ver = NULL;
484 fw->mem_bp = NULL;
485 }
486
ivpu_fw_init(struct ivpu_device * vdev)487 int ivpu_fw_init(struct ivpu_device *vdev)
488 {
489 int ret;
490
491 ret = ivpu_fw_request(vdev);
492 if (ret)
493 return ret;
494
495 ret = ivpu_fw_parse(vdev);
496 if (ret)
497 goto err_fw_release;
498
499 ivpu_fw_init_wa(vdev);
500
501 ret = ivpu_fw_mem_init(vdev);
502 if (ret)
503 goto err_fw_release;
504
505 ivpu_fw_load(vdev);
506
507 return 0;
508
509 err_fw_release:
510 ivpu_fw_release(vdev);
511 return ret;
512 }
513
ivpu_fw_fini(struct ivpu_device * vdev)514 void ivpu_fw_fini(struct ivpu_device *vdev)
515 {
516 ivpu_fw_mem_fini(vdev);
517 ivpu_fw_release(vdev);
518 }
519
ivpu_fw_load(struct ivpu_device * vdev)520 void ivpu_fw_load(struct ivpu_device *vdev)
521 {
522 struct ivpu_fw_info *fw = vdev->fw;
523 u64 image_end_offset = fw->image_load_offset + fw->image_size;
524
525 memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset);
526 memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset,
527 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size);
528
529 if (IVPU_WA(clear_runtime_mem)) {
530 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset;
531 u64 size = ivpu_bo_size(fw->mem) - image_end_offset;
532
533 memset(start, 0, size);
534 }
535
536 wmb(); /* Flush WC buffers after writing fw->mem */
537 }
538
ivpu_fw_boot_params_print(struct ivpu_device * vdev,struct vpu_boot_params * boot_params)539 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
540 {
541 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n",
542 boot_params->magic);
543 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n",
544 boot_params->vpu_id);
545 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n",
546 boot_params->vpu_count);
547 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n",
548 boot_params->frequency);
549 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n",
550 boot_params->perf_clk_frequency);
551
552 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n",
553 boot_params->ipc_header_area_start);
554 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n",
555 boot_params->ipc_header_area_size);
556 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n",
557 boot_params->shared_region_base);
558 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n",
559 boot_params->shared_region_size);
560 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n",
561 boot_params->ipc_payload_area_start);
562 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n",
563 boot_params->ipc_payload_area_size);
564 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n",
565 boot_params->global_aliased_pio_base);
566 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n",
567 boot_params->global_aliased_pio_size);
568
569 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n",
570 boot_params->autoconfig);
571
572 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n",
573 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use);
574 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n",
575 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg);
576
577 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n",
578 boot_params->shave_nn_fw_base);
579
580 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n",
581 boot_params->watchdog_irq_mss);
582 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n",
583 boot_params->watchdog_irq_nce);
584
585 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n",
586 boot_params->host_version_id);
587 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n",
588 boot_params->si_stepping);
589 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n",
590 boot_params->device_id);
591 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n",
592 boot_params->feature_exclusion);
593 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n",
594 boot_params->sku);
595 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n",
596 boot_params->min_freq_pll_ratio);
597 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n",
598 boot_params->pn_freq_pll_ratio);
599 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n",
600 boot_params->max_freq_pll_ratio);
601 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n",
602 boot_params->default_trace_level);
603 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n",
604 boot_params->tracing_buff_message_format_mask);
605 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n",
606 boot_params->trace_destination_mask);
607 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n",
608 boot_params->trace_hw_component_mask);
609 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n",
610 boot_params->boot_type);
611 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n",
612 boot_params->punit_telemetry_sram_base);
613 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n",
614 boot_params->punit_telemetry_sram_size);
615 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n",
616 boot_params->vpu_telemetry_enable);
617 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n",
618 boot_params->vpu_scheduling_mode);
619 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n",
620 boot_params->dvfs_mode);
621 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n",
622 boot_params->d0i3_delayed_entry);
623 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
624 boot_params->d0i3_residency_time_us);
625 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
626 boot_params->d0i3_entry_vpu_ts);
627 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
628 boot_params->system_time_us);
629 ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n",
630 boot_params->power_profile);
631 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_uses_ecc_mca_signal = 0x%x\n",
632 boot_params->vpu_uses_ecc_mca_signal);
633 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", boot_params->boot_type);
634 }
635
ivpu_fw_boot_params_setup(struct ivpu_device * vdev,struct vpu_boot_params * boot_params)636 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params)
637 {
638 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx;
639
640 /* In case of warm boot only update variable params */
641 if (ivpu_fw_is_warm_boot(vdev)) {
642 boot_params->d0i3_residency_time_us =
643 ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts);
644 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts;
645 boot_params->system_time_us = ktime_to_us(ktime_get_real());
646
647 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n",
648 boot_params->d0i3_residency_time_us);
649 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n",
650 boot_params->d0i3_entry_vpu_ts);
651 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n",
652 boot_params->system_time_us);
653 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", boot_params->boot_type);
654
655 boot_params->save_restore_ret_address = 0;
656 boot_params->boot_type = VPU_BOOT_TYPE_WARMBOOT;
657 wmb(); /* Flush WC buffers after writing save_restore_ret_address */
658 return;
659 }
660
661 memset(boot_params, 0, sizeof(*boot_params));
662 boot_params->boot_type = VPU_BOOT_TYPE_COLDBOOT;
663 boot_params->magic = VPU_BOOT_PARAMS_MAGIC;
664 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number;
665
666 /*
667 * This param is a debug firmware feature. It switches default clock
668 * to higher resolution one for fine-grained and more accurate firmware
669 * task profiling.
670 */
671 boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev);
672
673 /*
674 * Uncached region of VPU address space, covers IPC buffers, job queues
675 * and log buffers, programmable to L2$ Uncached by VPU MTRR
676 */
677 boot_params->shared_region_base = vdev->hw->ranges.global.start;
678 boot_params->shared_region_size = vdev->hw->ranges.global.end -
679 vdev->hw->ranges.global.start;
680
681 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
682 boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
683
684 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2;
685 boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2;
686
687 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) {
688 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
689 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
690 }
691
692 /* Allow configuration for L2C_PAGE_TABLE with boot param value */
693 boot_params->autoconfig = 1;
694
695 /* Enable L2 cache for first 2GB of high memory */
696 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
697 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
698 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
699
700 if (vdev->fw->mem_shave_nn)
701 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
702
703 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT;
704 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT;
705 boot_params->si_stepping = ivpu_revision(vdev);
706 boot_params->device_id = ivpu_device_id(vdev);
707 boot_params->feature_exclusion = vdev->hw->tile_fuse;
708 boot_params->sku = vdev->hw->sku;
709
710 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio;
711 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio;
712 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio;
713
714 boot_params->default_trace_level = vdev->fw->trace_level;
715 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING);
716 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask;
717 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask;
718 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr;
719 boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit);
720 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr;
721 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb);
722
723 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev);
724 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev);
725 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev);
726 boot_params->vpu_scheduling_mode = vdev->fw->sched_mode;
727 if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
728 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
729 boot_params->dvfs_mode = vdev->fw->dvfs_mode;
730 if (!IVPU_WA(disable_d0i3_msg))
731 boot_params->d0i3_delayed_entry = 1;
732 boot_params->d0i3_residency_time_us = 0;
733 boot_params->d0i3_entry_vpu_ts = 0;
734 if (IVPU_WA(disable_d0i2))
735 boot_params->power_profile |= BIT(1);
736 boot_params->vpu_uses_ecc_mca_signal =
737 ivpu_hw_uses_ecc_mca_signal(vdev) ? VPU_BOOT_MCA_ECC_BOTH : 0;
738
739 boot_params->system_time_us = ktime_to_us(ktime_get_real());
740 wmb(); /* Flush WC buffers after writing bootparams */
741
742 ivpu_fw_boot_params_print(vdev, boot_params);
743 }
744