1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * NXP LPC32xx SoC 4 * 5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com> 6 * Copyright 2012 Roland Stigge <stigge@antcom.de> 7 */ 8 9#include <dt-bindings/clock/lpc32xx-clock.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 compatible = "nxp,lpc3220"; 16 interrupt-parent = <&mic>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu@0 { 23 compatible = "arm,arm926ej-s"; 24 device_type = "cpu"; 25 reg = <0x0>; 26 }; 27 }; 28 29 clocks { 30 xtal_32k: xtal_32k { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <32768>; 34 clock-output-names = "xtal_32k"; 35 }; 36 37 xtal: xtal { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <13000000>; 41 clock-output-names = "xtal"; 42 }; 43 }; 44 45 ahb { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 compatible = "simple-bus"; 49 ranges = <0x00000000 0x00000000 0x10000000>, 50 <0x20000000 0x20000000 0x30000000>, 51 <0xe0000000 0xe0000000 0x04000000>; 52 53 iram: sram@8000000 { 54 compatible = "mmio-sram"; 55 reg = <0x08000000 0x20000>; 56 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges = <0x00000000 0x08000000 0x20000>; 60 }; 61 62 /* 63 * Enable either SLC or MLC 64 */ 65 slc: nand-controller@20020000 { 66 compatible = "nxp,lpc3220-slc"; 67 reg = <0x20020000 0x1000>; 68 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&clk LPC32XX_CLK_SLC>; 70 dmas = <&dma 1 1>; 71 dma-names = "rx-tx"; 72 status = "disabled"; 73 }; 74 75 mlc: nand-controller@200a8000 { 76 compatible = "nxp,lpc3220-mlc"; 77 reg = <0x200a8000 0x11000>; 78 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&clk LPC32XX_CLK_MLC>; 80 dmas = <&dma 12 1>; 81 dma-names = "rx-tx"; 82 status = "disabled"; 83 }; 84 85 dma: dma-controller@31000000 { 86 compatible = "arm,pl080", "arm,primecell"; 87 reg = <0x31000000 0x1000>; 88 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&clk LPC32XX_CLK_DMA>; 90 clock-names = "apb_pclk"; 91 dma-channels = <8>; 92 dma-requests = <16>; 93 lli-bus-interface-ahb1; 94 lli-bus-interface-ahb2; 95 mem-bus-interface-ahb1; 96 mem-bus-interface-ahb2; 97 memcpy-burst-size = <256>; 98 memcpy-bus-width = <32>; 99 #dma-cells = <2>; 100 }; 101 102 /* 103 * Enable either ohci or usbd (gadget)! 104 */ 105 ohci: usb@31020000 { 106 compatible = "nxp,ohci-nxp", "usb-ohci"; 107 reg = <0x31020000 0x300>; 108 interrupt-parent = <&sic1>; 109 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&usbclk LPC32XX_USB_CLK_HOST>; 111 status = "disabled"; 112 }; 113 114 usbd: usbd@31020000 { 115 compatible = "nxp,lpc3220-udc"; 116 reg = <0x31020000 0x300>; 117 interrupt-parent = <&sic1>; 118 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, 119 <30 IRQ_TYPE_LEVEL_HIGH>, 120 <28 IRQ_TYPE_LEVEL_HIGH>, 121 <26 IRQ_TYPE_LEVEL_LOW>; 122 clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; 123 status = "disabled"; 124 }; 125 126 i2cusb: i2c@31020300 { 127 compatible = "nxp,pnx-i2c"; 128 reg = <0x31020300 0x100>; 129 interrupt-parent = <&sic1>; 130 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&usbclk LPC32XX_USB_CLK_I2C>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 }; 135 136 usbclk: clock-controller@31020f00 { 137 compatible = "nxp,lpc3220-usb-clk"; 138 reg = <0x31020f00 0x100>; 139 #clock-cells = <1>; 140 }; 141 142 clcd: clcd@31040000 { 143 compatible = "arm,pl111", "arm,primecell"; 144 reg = <0x31040000 0x1000>; 145 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; 147 clock-names = "clcdclk", "apb_pclk"; 148 status = "disabled"; 149 }; 150 151 mac: ethernet@31060000 { 152 compatible = "nxp,lpc-eth"; 153 reg = <0x31060000 0x1000>; 154 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clk LPC32XX_CLK_MAC>; 156 status = "disabled"; 157 }; 158 159 emc: memory-controller@31080000 { 160 compatible = "arm,pl175", "arm,primecell"; 161 reg = <0x31080000 0x1000>; 162 clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; 163 clock-names = "mpmcclk", "apb_pclk"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 ranges = <0 0xe0000000 0x01000000>, 168 <1 0xe1000000 0x01000000>, 169 <2 0xe2000000 0x01000000>, 170 <3 0xe3000000 0x01000000>; 171 status = "disabled"; 172 }; 173 174 apb { 175 #address-cells = <1>; 176 #size-cells = <1>; 177 compatible = "simple-bus"; 178 ranges = <0x20000000 0x20000000 0x30000000>; 179 180 /* 181 * ssp0 and spi1 are shared pins; 182 * enable one in your board dts, as needed. 183 */ 184 ssp0: spi@20084000 { 185 compatible = "arm,pl022", "arm,primecell"; 186 reg = <0x20084000 0x1000>; 187 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>; 189 clock-names = "sspclk", "apb_pclk"; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 status = "disabled"; 193 }; 194 195 spi1: spi@20088000 { 196 compatible = "nxp,lpc3220-spi"; 197 reg = <0x20088000 0x1000>; 198 clocks = <&clk LPC32XX_CLK_SPI1>; 199 dmas = <&dmamux 11 1 0>; 200 dma-names = "rx-tx"; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 status = "disabled"; 204 }; 205 206 /* 207 * ssp1 and spi2 are shared pins; 208 * enable one in your board dts, as needed. 209 */ 210 ssp1: spi@2008c000 { 211 compatible = "arm,pl022", "arm,primecell"; 212 reg = <0x2008c000 0x1000>; 213 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>; 215 clock-names = "sspclk", "apb_pclk"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 status = "disabled"; 219 }; 220 221 spi2: spi@20090000 { 222 compatible = "nxp,lpc3220-spi"; 223 reg = <0x20090000 0x1000>; 224 clocks = <&clk LPC32XX_CLK_SPI2>; 225 dmas = <&dmamux 3 1 0>; 226 dma-names = "rx-tx"; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 status = "disabled"; 230 }; 231 232 i2s0: i2s@20094000 { 233 compatible = "nxp,lpc3220-i2s"; 234 reg = <0x20094000 0x1000>; 235 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&clk LPC32XX_CLK_I2S0>; 237 dmas = <&dma 0 1>, <&dma 13 1>; 238 dma-names = "rx", "tx"; 239 #sound-dai-cells = <0>; 240 status = "disabled"; 241 }; 242 243 sd: mmc@20098000 { 244 compatible = "arm,pl180", "arm,primecell"; 245 reg = <0x20098000 0x1000>; 246 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 247 <13 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clk LPC32XX_CLK_SD>; 249 clock-names = "apb_pclk"; 250 status = "disabled"; 251 }; 252 253 i2s1: i2s@2009c000 { 254 compatible = "nxp,lpc3220-i2s"; 255 reg = <0x2009c000 0x1000>; 256 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clk LPC32XX_CLK_I2S1>; 258 dmas = <&dma 2 1>, <&dmamux 10 1 1>; 259 dma-names = "rx", "tx"; 260 #sound-dai-cells = <0>; 261 status = "disabled"; 262 }; 263 264 /* UART5 first since it is the default console, ttyS0 */ 265 uart5: serial@40090000 { 266 /* actually, ns16550a w/ 64 byte fifos! */ 267 compatible = "nxp,lpc3220-uart"; 268 reg = <0x40090000 0x1000>; 269 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 270 reg-shift = <2>; 271 clocks = <&clk LPC32XX_CLK_UART5>; 272 status = "disabled"; 273 }; 274 275 uart3: serial@40080000 { 276 compatible = "nxp,lpc3220-uart"; 277 reg = <0x40080000 0x1000>; 278 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 279 reg-shift = <2>; 280 clocks = <&clk LPC32XX_CLK_UART3>; 281 status = "disabled"; 282 }; 283 284 uart4: serial@40088000 { 285 compatible = "nxp,lpc3220-uart"; 286 reg = <0x40088000 0x1000>; 287 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 288 reg-shift = <2>; 289 clocks = <&clk LPC32XX_CLK_UART4>; 290 status = "disabled"; 291 }; 292 293 uart6: serial@40098000 { 294 compatible = "nxp,lpc3220-uart"; 295 reg = <0x40098000 0x1000>; 296 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 297 reg-shift = <2>; 298 clocks = <&clk LPC32XX_CLK_UART6>; 299 status = "disabled"; 300 }; 301 302 i2c1: i2c@400a0000 { 303 compatible = "nxp,pnx-i2c"; 304 reg = <0x400a0000 0x100>; 305 interrupt-parent = <&sic1>; 306 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 clocks = <&clk LPC32XX_CLK_I2C1>; 310 }; 311 312 i2c2: i2c@400a8000 { 313 compatible = "nxp,pnx-i2c"; 314 reg = <0x400a8000 0x100>; 315 interrupt-parent = <&sic1>; 316 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 clocks = <&clk LPC32XX_CLK_I2C2>; 320 }; 321 322 mpwm: pwm@400e8000 { 323 compatible = "nxp,lpc3220-motor-pwm"; 324 reg = <0x400e8000 0x78>; 325 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 326 clocks = <&clk LPC32XX_CLK_MCPWM>; 327 #pwm-cells = <3>; 328 status = "disabled"; 329 }; 330 }; 331 332 fab { 333 #address-cells = <1>; 334 #size-cells = <1>; 335 compatible = "simple-bus"; 336 ranges = <0x20000000 0x20000000 0x30000000>; 337 338 /* System Control Block */ 339 syscon@40004000 { 340 compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd"; 341 reg = <0x40004000 0x1000>; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0 0x40004000 0x1000>; 345 346 clk: clock-controller@0 { 347 compatible = "nxp,lpc3220-clk"; 348 reg = <0x00 0x114>; 349 #clock-cells = <1>; 350 clocks = <&xtal_32k>, <&xtal>; 351 clock-names = "xtal_32k", "xtal"; 352 }; 353 354 dmamux: dma-router@78 { 355 compatible = "nxp,lpc3220-dmamux"; 356 reg = <0x78 0x8>; 357 dma-masters = <&dma>; 358 #dma-cells = <3>; 359 }; 360 }; 361 362 mic: interrupt-controller@40008000 { 363 compatible = "nxp,lpc3220-mic"; 364 reg = <0x40008000 0x4000>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 }; 368 369 sic1: interrupt-controller@4000c000 { 370 compatible = "nxp,lpc3220-sic"; 371 reg = <0x4000c000 0x4000>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 375 interrupt-parent = <&mic>; 376 interrupts = <0 IRQ_TYPE_LEVEL_LOW>, 377 <30 IRQ_TYPE_LEVEL_LOW>; 378 }; 379 380 sic2: interrupt-controller@40010000 { 381 compatible = "nxp,lpc3220-sic"; 382 reg = <0x40010000 0x4000>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 386 interrupt-parent = <&mic>; 387 interrupts = <1 IRQ_TYPE_LEVEL_LOW>, 388 <31 IRQ_TYPE_LEVEL_LOW>; 389 }; 390 391 uart1: serial@40014000 { 392 compatible = "nxp,lpc3220-hsuart"; 393 reg = <0x40014000 0x1000>; 394 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; 395 status = "disabled"; 396 }; 397 398 uart2: serial@40018000 { 399 compatible = "nxp,lpc3220-hsuart"; 400 reg = <0x40018000 0x1000>; 401 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; 402 status = "disabled"; 403 }; 404 405 uart7: serial@4001c000 { 406 compatible = "nxp,lpc3220-hsuart"; 407 reg = <0x4001c000 0x1000>; 408 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 409 status = "disabled"; 410 }; 411 412 rtc: rtc@40024000 { 413 compatible = "nxp,lpc3220-rtc"; 414 reg = <0x40024000 0x1000>; 415 interrupt-parent = <&sic1>; 416 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clk LPC32XX_CLK_RTC>; 418 }; 419 420 gpio: gpio@40028000 { 421 compatible = "nxp,lpc3220-gpio"; 422 reg = <0x40028000 0x1000>; 423 gpio-controller; 424 #gpio-cells = <3>; /* bank, pin, flags */ 425 }; 426 427 timer4: timer@4002c000 { 428 compatible = "nxp,lpc3220-timer"; 429 reg = <0x4002c000 0x1000>; 430 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 431 clocks = <&clk LPC32XX_CLK_TIMER4>; 432 clock-names = "timerclk"; 433 status = "disabled"; 434 }; 435 436 timer5: timer@40030000 { 437 compatible = "nxp,lpc3220-timer"; 438 reg = <0x40030000 0x1000>; 439 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 440 clocks = <&clk LPC32XX_CLK_TIMER5>; 441 clock-names = "timerclk"; 442 status = "disabled"; 443 }; 444 445 watchdog: watchdog@4003c000 { 446 compatible = "nxp,pnx4008-wdt"; 447 reg = <0x4003c000 0x1000>; 448 clocks = <&clk LPC32XX_CLK_WDOG>; 449 }; 450 451 timer0: timer@40044000 { 452 compatible = "nxp,lpc3220-timer"; 453 reg = <0x40044000 0x1000>; 454 clocks = <&clk LPC32XX_CLK_TIMER0>; 455 clock-names = "timerclk"; 456 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 457 }; 458 459 /* 460 * TSC vs. ADC: Since those two share the same 461 * hardware, you need to choose from one of the 462 * following two and do 'status = "okay";' for one of 463 * them 464 */ 465 466 adc: adc@40048000 { 467 compatible = "nxp,lpc3220-adc"; 468 reg = <0x40048000 0x1000>; 469 interrupt-parent = <&sic1>; 470 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clk LPC32XX_CLK_ADC>; 472 status = "disabled"; 473 }; 474 475 tsc: tsc@40048000 { 476 compatible = "nxp,lpc3220-tsc"; 477 reg = <0x40048000 0x1000>; 478 interrupt-parent = <&sic1>; 479 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clk LPC32XX_CLK_ADC>; 481 status = "disabled"; 482 }; 483 484 timer1: timer@4004c000 { 485 compatible = "nxp,lpc3220-timer"; 486 reg = <0x4004c000 0x1000>; 487 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 488 clocks = <&clk LPC32XX_CLK_TIMER1>; 489 clock-names = "timerclk"; 490 }; 491 492 key: key@40050000 { 493 compatible = "nxp,lpc3220-key"; 494 reg = <0x40050000 0x1000>; 495 clocks = <&clk LPC32XX_CLK_KEY>; 496 interrupt-parent = <&sic1>; 497 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 498 status = "disabled"; 499 }; 500 501 timer2: timer@40058000 { 502 compatible = "nxp,lpc3220-timer"; 503 reg = <0x40058000 0x1000>; 504 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 505 clocks = <&clk LPC32XX_CLK_TIMER2>; 506 clock-names = "timerclk"; 507 status = "disabled"; 508 }; 509 510 pwm1: pwm@4005c000 { 511 compatible = "nxp,lpc3220-pwm"; 512 reg = <0x4005c000 0x4>; 513 clocks = <&clk LPC32XX_CLK_PWM1>; 514 #pwm-cells = <3>; 515 assigned-clocks = <&clk LPC32XX_CLK_PWM1>; 516 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; 517 status = "disabled"; 518 }; 519 520 pwm2: pwm@4005c004 { 521 compatible = "nxp,lpc3220-pwm"; 522 reg = <0x4005c004 0x4>; 523 clocks = <&clk LPC32XX_CLK_PWM2>; 524 #pwm-cells = <3>; 525 assigned-clocks = <&clk LPC32XX_CLK_PWM2>; 526 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; 527 status = "disabled"; 528 }; 529 530 timer3: timer@40060000 { 531 compatible = "nxp,lpc3220-timer"; 532 reg = <0x40060000 0x1000>; 533 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 534 clocks = <&clk LPC32XX_CLK_TIMER3>; 535 clock-names = "timerclk"; 536 status = "disabled"; 537 }; 538 }; 539 }; 540}; 541