1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2002 Motorola GSG-China
4 *
5 * Author:
6 * Darius Augulis, Teltonika Inc.
7 *
8 * Desc.:
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
11 *
12 * Derived from Motorola GSG China I2C example driver
13 *
14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16 * Copyright (C) 2007 RightHand Technologies, Inc.
17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 *
19 * Copyright 2013 Freescale Semiconductor, Inc.
20 * Copyright 2020, 2024 NXP
21 *
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/cleanup.h>
27 #include <linux/completion.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmaengine.h>
31 #include <linux/dmapool.h>
32 #include <linux/err.h>
33 #include <linux/errno.h>
34 #include <linux/gpio/consumer.h>
35 #include <linux/i2c.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/io.h>
39 #include <linux/iopoll.h>
40 #include <linux/kernel.h>
41 #include <linux/spinlock.h>
42 #include <linux/hrtimer.h>
43 #include <linux/module.h>
44 #include <linux/of.h>
45 #include <linux/of_dma.h>
46 #include <linux/pinctrl/consumer.h>
47 #include <linux/platform_data/i2c-imx.h>
48 #include <linux/platform_device.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/sched.h>
51 #include <linux/slab.h>
52
53 /* This will be the driver name the kernel reports */
54 #define DRIVER_NAME "imx-i2c"
55
56 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */
57
58 /*
59 * Enable DMA if transfer byte size is bigger than this threshold.
60 * As the hardware request, it must bigger than 4 bytes.\
61 * I have set '16' here, maybe it's not the best but I think it's
62 * the appropriate.
63 */
64 #define DMA_THRESHOLD 16
65 #define DMA_TIMEOUT 1000
66
67 /* IMX I2C registers:
68 * the I2C register offset is different between SoCs,
69 * to provide support for all these chips, split the
70 * register offset into a fixed base address and a
71 * variable shift value, then the full register offset
72 * will be calculated by
73 * reg_off = ( reg_base_addr << reg_shift)
74 */
75 #define IMX_I2C_IADR 0x00 /* i2c slave address */
76 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
77 #define IMX_I2C_I2CR 0x02 /* i2c control */
78 #define IMX_I2C_I2SR 0x03 /* i2c status */
79 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
80
81 /*
82 * All of the layerscape series SoCs support IBIC register.
83 */
84 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
85
86 #define IMX_I2C_REGSHIFT 2
87 #define VF610_I2C_REGSHIFT 0
88 #define S32G_I2C_REGSHIFT 0
89
90 /* Bits of IMX I2C registers */
91 #define I2SR_RXAK 0x01
92 #define I2SR_IIF 0x02
93 #define I2SR_SRW 0x04
94 #define I2SR_IAL 0x10
95 #define I2SR_IBB 0x20
96 #define I2SR_IAAS 0x40
97 #define I2SR_ICF 0x80
98 #define I2CR_DMAEN 0x02
99 #define I2CR_RSTA 0x04
100 #define I2CR_TXAK 0x08
101 #define I2CR_MTX 0x10
102 #define I2CR_MSTA 0x20
103 #define I2CR_IIEN 0x40
104 #define I2CR_IEN 0x80
105 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
106
107 /* register bits different operating codes definition:
108 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
109 * - write zero to clear(w0c) INT flag on i.MX,
110 * - but write one to clear(w1c) INT flag on Vybrid.
111 * 2) I2CR: I2C module enable operation also differ between SoCs:
112 * - set I2CR_IEN bit enable the module on i.MX,
113 * - but clear I2CR_IEN bit enable the module on Vybrid.
114 */
115 #define I2SR_CLR_OPCODE_W0C 0x0
116 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
117 #define I2CR_IEN_OPCODE_0 0x0
118 #define I2CR_IEN_OPCODE_1 I2CR_IEN
119
120 #define I2C_PM_TIMEOUT 10 /* ms */
121
122 /*
123 * sorted list of clock divider, register value pairs
124 * taken from table 26-5, p.26-9, Freescale i.MX
125 * Integrated Portable System Processor Reference Manual
126 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
127 *
128 * Duplicated divider values removed from list
129 */
130 struct imx_i2c_clk_pair {
131 u16 div;
132 u16 val;
133 };
134
135 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
136 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
137 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
138 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
139 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
140 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
141 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
142 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
143 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
144 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
145 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
146 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
147 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
148 { 3072, 0x1E }, { 3840, 0x1F }
149 };
150
151 /* Vybrid VF610 clock divider, register value pairs */
152 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
153 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
154 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
155 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
156 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
157 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
158 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
159 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
160 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
161 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
162 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
163 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
164 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
165 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
166 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
167 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
168 };
169
170 /* S32G2/S32G3 clock divider, register value pairs */
171 static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = {
172 { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 },
173 { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 },
174 { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C },
175 { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 },
176 { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 },
177 { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 },
178 { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 },
179 { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 },
180 { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 },
181 { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F },
182 { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 },
183 { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
184 { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E },
185 { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 },
186 { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A },
187 { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D },
188 { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B },
189 { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA },
190 { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD },
191 { 12288, 0xBE }, { 15360, 0xBF },
192 };
193
194 enum imx_i2c_type {
195 IMX1_I2C,
196 IMX21_I2C,
197 S32G_I2C,
198 VF610_I2C,
199 };
200
201 struct imx_i2c_hwdata {
202 enum imx_i2c_type devtype;
203 unsigned int regshift;
204 struct imx_i2c_clk_pair *clk_div;
205 unsigned int ndivs;
206 unsigned int i2sr_clr_opcode;
207 unsigned int i2cr_ien_opcode;
208 /*
209 * Errata ERR007805 or e7805:
210 * I2C: When the I2C clock speed is configured for 400 kHz,
211 * the SCL low period violates the I2C spec of 1.3 uS min.
212 */
213 bool has_err007805;
214 };
215
216 struct imx_i2c_dma {
217 struct dma_chan *chan_tx;
218 struct dma_chan *chan_rx;
219 struct dma_chan *chan_using;
220 struct completion cmd_complete;
221 dma_addr_t dma_buf;
222 unsigned int dma_len;
223 enum dma_transfer_direction dma_transfer_dir;
224 enum dma_data_direction dma_data_dir;
225 };
226
227 enum imx_i2c_state {
228 IMX_I2C_STATE_DONE,
229 IMX_I2C_STATE_FAILED,
230 IMX_I2C_STATE_WRITE,
231 IMX_I2C_STATE_DMA,
232 IMX_I2C_STATE_READ,
233 IMX_I2C_STATE_READ_CONTINUE,
234 IMX_I2C_STATE_READ_BLOCK_DATA,
235 IMX_I2C_STATE_READ_BLOCK_DATA_LEN,
236 };
237
238 struct imx_i2c_struct {
239 struct i2c_adapter adapter;
240 struct clk *clk;
241 struct notifier_block clk_change_nb;
242 void __iomem *base;
243 wait_queue_head_t queue;
244 unsigned long i2csr;
245 unsigned int disable_delay;
246 int stopped;
247 unsigned int ifdr; /* IMX_I2C_IFDR */
248 unsigned int cur_clk;
249 unsigned int bitrate;
250 const struct imx_i2c_hwdata *hwdata;
251 struct i2c_bus_recovery_info rinfo;
252
253 struct imx_i2c_dma *dma;
254 struct i2c_client *slave;
255 enum i2c_slave_event last_slave_event;
256
257 struct i2c_msg *msg;
258 unsigned int msg_buf_idx;
259 int isr_result;
260 bool is_lastmsg;
261 enum imx_i2c_state state;
262
263 bool multi_master;
264
265 /* For checking slave events. */
266 spinlock_t slave_lock;
267 struct hrtimer slave_timer;
268 };
269
270 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
271 .devtype = IMX1_I2C,
272 .regshift = IMX_I2C_REGSHIFT,
273 .clk_div = imx_i2c_clk_div,
274 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
275 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
276 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
277
278 };
279
280 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
281 .devtype = IMX21_I2C,
282 .regshift = IMX_I2C_REGSHIFT,
283 .clk_div = imx_i2c_clk_div,
284 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
285 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
286 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
287
288 };
289
290 static const struct imx_i2c_hwdata imx6_i2c_hwdata = {
291 .devtype = IMX21_I2C,
292 .regshift = IMX_I2C_REGSHIFT,
293 .clk_div = imx_i2c_clk_div,
294 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
295 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
296 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
297 .has_err007805 = true,
298 };
299
300 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
301 .devtype = VF610_I2C,
302 .regshift = VF610_I2C_REGSHIFT,
303 .clk_div = vf610_i2c_clk_div,
304 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
305 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
306 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
307 };
308
309 static const struct imx_i2c_hwdata s32g2_i2c_hwdata = {
310 .devtype = S32G_I2C,
311 .regshift = S32G_I2C_REGSHIFT,
312 .clk_div = s32g2_i2c_clk_div,
313 .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div),
314 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
315 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
316 };
317
318 static const struct platform_device_id imx_i2c_devtype[] = {
319 {
320 .name = "imx1-i2c",
321 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
322 }, {
323 .name = "imx21-i2c",
324 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
325 }, {
326 /* sentinel */
327 }
328 };
329 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
330
331 static const struct of_device_id i2c_imx_dt_ids[] = {
332 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
333 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
334 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },
335 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },
336 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },
337 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },
338 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },
339 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, },
340 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },
341 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },
342 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },
343 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
344 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
345 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
346 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, },
347 { /* sentinel */ }
348 };
349 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
350
351 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
352 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
353 { }
354 };
355 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
356
is_imx1_i2c(struct imx_i2c_struct * i2c_imx)357 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
358 {
359 return i2c_imx->hwdata->devtype == IMX1_I2C;
360 }
361
is_vf610_i2c(struct imx_i2c_struct * i2c_imx)362 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
363 {
364 return i2c_imx->hwdata->devtype == VF610_I2C;
365 }
366
imx_i2c_write_reg(unsigned int val,struct imx_i2c_struct * i2c_imx,unsigned int reg)367 static inline void imx_i2c_write_reg(unsigned int val,
368 struct imx_i2c_struct *i2c_imx, unsigned int reg)
369 {
370 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
371 }
372
imx_i2c_read_reg(struct imx_i2c_struct * i2c_imx,unsigned int reg)373 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
374 unsigned int reg)
375 {
376 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
377 }
378
i2c_imx_clear_irq(struct imx_i2c_struct * i2c_imx,unsigned int bits)379 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
380 {
381 unsigned int temp;
382
383 /*
384 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
385 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
386 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
387 */
388 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
389 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
390 }
391
392 /* Set up i2c controller register and i2c status register to default value. */
i2c_imx_reset_regs(struct imx_i2c_struct * i2c_imx)393 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
394 {
395 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
396 i2c_imx, IMX_I2C_I2CR);
397 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
398 }
399
400 /* Functions for DMA support */
i2c_imx_dma_request(struct imx_i2c_struct * i2c_imx,dma_addr_t phy_addr)401 static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr)
402 {
403 struct imx_i2c_dma *dma;
404 struct dma_slave_config dma_sconfig;
405 struct device *dev = i2c_imx->adapter.dev.parent;
406 int ret;
407
408 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
409 if (!dma)
410 return -ENOMEM;
411
412 dma->chan_tx = dma_request_chan(dev, "tx");
413 if (IS_ERR(dma->chan_tx)) {
414 ret = PTR_ERR(dma->chan_tx);
415 if (ret != -ENODEV && ret != -EPROBE_DEFER)
416 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
417 goto fail_al;
418 }
419
420 dma_sconfig.dst_addr = phy_addr +
421 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
422 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
423 dma_sconfig.dst_maxburst = 1;
424 dma_sconfig.direction = DMA_MEM_TO_DEV;
425 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
426 if (ret < 0) {
427 dev_err(dev, "can't configure tx channel (%d)\n", ret);
428 goto fail_tx;
429 }
430
431 dma->chan_rx = dma_request_chan(dev, "rx");
432 if (IS_ERR(dma->chan_rx)) {
433 ret = PTR_ERR(dma->chan_rx);
434 if (ret != -ENODEV && ret != -EPROBE_DEFER)
435 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
436 goto fail_tx;
437 }
438
439 dma_sconfig.src_addr = phy_addr +
440 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
441 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
442 dma_sconfig.src_maxburst = 1;
443 dma_sconfig.direction = DMA_DEV_TO_MEM;
444 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
445 if (ret < 0) {
446 dev_err(dev, "can't configure rx channel (%d)\n", ret);
447 goto fail_rx;
448 }
449
450 i2c_imx->dma = dma;
451 init_completion(&dma->cmd_complete);
452 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
453 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
454
455 return 0;
456
457 fail_rx:
458 dma_release_channel(dma->chan_rx);
459 fail_tx:
460 dma_release_channel(dma->chan_tx);
461 fail_al:
462 devm_kfree(dev, dma);
463
464 return ret;
465 }
466
i2c_imx_dma_callback(void * arg)467 static void i2c_imx_dma_callback(void *arg)
468 {
469 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
470 struct imx_i2c_dma *dma = i2c_imx->dma;
471
472 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
473 dma->dma_len, dma->dma_data_dir);
474 complete(&dma->cmd_complete);
475 }
476
i2c_imx_dma_xfer(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)477 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
478 struct i2c_msg *msgs)
479 {
480 struct imx_i2c_dma *dma = i2c_imx->dma;
481 struct dma_async_tx_descriptor *txdesc;
482 struct device *dev = &i2c_imx->adapter.dev;
483 struct device *chan_dev = dma->chan_using->device->dev;
484
485 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
486 dma->dma_len, dma->dma_data_dir);
487 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
488 dev_err(dev, "DMA mapping failed\n");
489 goto err_map;
490 }
491
492 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
493 dma->dma_len, dma->dma_transfer_dir,
494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
495 if (!txdesc) {
496 dev_err(dev, "Not able to get desc for DMA xfer\n");
497 goto err_desc;
498 }
499
500 reinit_completion(&dma->cmd_complete);
501 txdesc->callback = i2c_imx_dma_callback;
502 txdesc->callback_param = i2c_imx;
503 if (dma_submit_error(dmaengine_submit(txdesc))) {
504 dev_err(dev, "DMA submit failed\n");
505 goto err_submit;
506 }
507
508 dma_async_issue_pending(dma->chan_using);
509 return 0;
510
511 err_submit:
512 dmaengine_terminate_sync(dma->chan_using);
513 err_desc:
514 dma_unmap_single(chan_dev, dma->dma_buf,
515 dma->dma_len, dma->dma_data_dir);
516 err_map:
517 return -EINVAL;
518 }
519
i2c_imx_dma_free(struct imx_i2c_struct * i2c_imx)520 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
521 {
522 struct imx_i2c_dma *dma = i2c_imx->dma;
523
524 dma->dma_buf = 0;
525 dma->dma_len = 0;
526
527 dma_release_channel(dma->chan_tx);
528 dma->chan_tx = NULL;
529
530 dma_release_channel(dma->chan_rx);
531 dma->chan_rx = NULL;
532
533 dma->chan_using = NULL;
534 }
535
i2c_imx_bus_busy(struct imx_i2c_struct * i2c_imx,int for_busy,bool atomic)536 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
537 {
538 bool multi_master = i2c_imx->multi_master;
539 unsigned long orig_jiffies = jiffies;
540 unsigned int temp;
541
542 while (1) {
543 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
544
545 /* check for arbitration lost */
546 if (multi_master && (temp & I2SR_IAL)) {
547 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
548 return -EAGAIN;
549 }
550
551 if (for_busy && (!multi_master || (temp & I2SR_IBB))) {
552 i2c_imx->stopped = 0;
553 break;
554 }
555 if (!for_busy && !(temp & I2SR_IBB)) {
556 i2c_imx->stopped = 1;
557 break;
558 }
559 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
560 dev_dbg(&i2c_imx->adapter.dev,
561 "<%s> I2C bus is busy\n", __func__);
562 return -ETIMEDOUT;
563 }
564 if (atomic)
565 udelay(100);
566 else
567 schedule();
568 }
569
570 return 0;
571 }
572
i2c_imx_trx_complete(struct imx_i2c_struct * i2c_imx,bool atomic)573 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
574 {
575 if (atomic) {
576 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
577 unsigned int regval;
578
579 /*
580 * The formula for the poll timeout is documented in the RM
581 * Rev.5 on page 1878:
582 * T_min = 10/F_scl
583 * Set the value hard as it is done for the non-atomic use-case.
584 * Use 10 kHz for the calculation since this is the minimum
585 * allowed SMBus frequency. Also add an offset of 100us since it
586 * turned out that the I2SR_IIF bit isn't set correctly within
587 * the minimum timeout in polling mode.
588 */
589 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
590 i2c_imx->i2csr = regval;
591 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
592 } else {
593 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
594 }
595
596 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
597 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
598 return -ETIMEDOUT;
599 }
600
601 /* In multi-master mode check for arbitration lost */
602 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) {
603 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
604 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
605
606 i2c_imx->i2csr = 0;
607 return -EAGAIN;
608 }
609
610 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
611 i2c_imx->i2csr = 0;
612 return 0;
613 }
614
i2c_imx_acked(struct imx_i2c_struct * i2c_imx)615 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
616 {
617 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
618 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
619 return -ENXIO; /* No ACK */
620 }
621
622 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
623 return 0;
624 }
625
i2c_imx_set_clk(struct imx_i2c_struct * i2c_imx,unsigned int i2c_clk_rate)626 static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
627 unsigned int i2c_clk_rate)
628 {
629 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
630 unsigned int div;
631 int i;
632
633 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {
634 dev_dbg(&i2c_imx->adapter.dev,
635 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n",
636 i2c_imx->bitrate);
637 i2c_imx->bitrate = 384000;
638 }
639
640 /* Divider value calculation */
641 if (i2c_imx->cur_clk == i2c_clk_rate)
642 return 0;
643
644 /* Keep the denominator of the following program always NOT equal to 0. */
645 if (!(i2c_clk_rate / 2))
646 return -EINVAL;
647
648 i2c_imx->cur_clk = i2c_clk_rate;
649
650 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
651 if (div < i2c_clk_div[0].div)
652 i = 0;
653 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
654 i = i2c_imx->hwdata->ndivs - 1;
655 else
656 for (i = 0; i2c_clk_div[i].div < div; i++)
657 ;
658
659 /* Store divider value */
660 i2c_imx->ifdr = i2c_clk_div[i].val;
661
662 /*
663 * There dummy delay is calculated.
664 * It should be about one I2C clock period long.
665 * This delay is used in I2C bus disable function
666 * to fix chip hardware bug.
667 */
668 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
669 i2c_clk_rate / 2);
670
671 #ifdef CONFIG_I2C_DEBUG_BUS
672 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
673 i2c_clk_rate, div);
674 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
675 i2c_clk_div[i].val, i2c_clk_div[i].div);
676 #endif
677
678 return 0;
679 }
680
i2c_imx_clk_notifier_call(struct notifier_block * nb,unsigned long action,void * data)681 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
682 unsigned long action, void *data)
683 {
684 struct clk_notifier_data *ndata = data;
685 struct imx_i2c_struct *i2c_imx = container_of(nb,
686 struct imx_i2c_struct,
687 clk_change_nb);
688 int ret = 0;
689
690 if (action & POST_RATE_CHANGE)
691 ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate);
692
693 return notifier_from_errno(ret);
694 }
695
i2c_imx_start(struct imx_i2c_struct * i2c_imx,bool atomic)696 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
697 {
698 unsigned int temp = 0;
699 int result;
700
701 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
702 /* Enable I2C controller */
703 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
704 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
705
706 /* Wait controller to be stable */
707 if (atomic)
708 udelay(50);
709 else
710 usleep_range(50, 150);
711
712 /* Start I2C transaction */
713 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
714 temp |= I2CR_MSTA;
715 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
716 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
717 if (result)
718 return result;
719
720 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
721 if (atomic)
722 temp &= ~I2CR_IIEN; /* Disable interrupt */
723
724 temp &= ~I2CR_DMAEN;
725 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
726 return result;
727 }
728
i2c_imx_stop(struct imx_i2c_struct * i2c_imx,bool atomic)729 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
730 {
731 unsigned int temp = 0;
732
733 if (!i2c_imx->stopped) {
734 /* Stop I2C transaction */
735 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
736 if (!(temp & I2CR_MSTA))
737 i2c_imx->stopped = 1;
738 temp &= ~(I2CR_MSTA | I2CR_MTX);
739 if (i2c_imx->dma)
740 temp &= ~I2CR_DMAEN;
741 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
742 }
743 if (is_imx1_i2c(i2c_imx)) {
744 /*
745 * This delay caused by an i.MXL hardware bug.
746 * If no (or too short) delay, no "STOP" bit will be generated.
747 */
748 udelay(i2c_imx->disable_delay);
749 }
750
751 if (!i2c_imx->stopped)
752 i2c_imx_bus_busy(i2c_imx, 0, atomic);
753
754 /* Disable I2C controller */
755 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN;
756 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
757 }
758
759 /*
760 * Enable bus idle interrupts
761 * Note: IBIC register will be cleared after disabled i2c module.
762 * All of layerscape series SoCs support IBIC register.
763 */
i2c_imx_enable_bus_idle(struct imx_i2c_struct * i2c_imx)764 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
765 {
766 if (is_vf610_i2c(i2c_imx)) {
767 unsigned int temp;
768
769 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
770 temp |= IBIC_BIIE;
771 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
772 }
773 }
774
i2c_imx_slave_event(struct imx_i2c_struct * i2c_imx,enum i2c_slave_event event,u8 * val)775 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
776 enum i2c_slave_event event, u8 *val)
777 {
778 i2c_slave_event(i2c_imx->slave, event, val);
779 i2c_imx->last_slave_event = event;
780 }
781
i2c_imx_slave_finish_op(struct imx_i2c_struct * i2c_imx)782 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
783 {
784 u8 val = 0;
785
786 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
787 switch (i2c_imx->last_slave_event) {
788 case I2C_SLAVE_READ_REQUESTED:
789 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
790 &val);
791 break;
792
793 case I2C_SLAVE_WRITE_REQUESTED:
794 case I2C_SLAVE_READ_PROCESSED:
795 case I2C_SLAVE_WRITE_RECEIVED:
796 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
797 break;
798
799 case I2C_SLAVE_STOP:
800 break;
801 }
802 }
803 }
804
805 /* Returns true if the timer should be restarted, false if not. */
i2c_imx_slave_handle(struct imx_i2c_struct * i2c_imx,unsigned int status,unsigned int ctl)806 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,
807 unsigned int status, unsigned int ctl)
808 {
809 u8 value = 0;
810
811 if (status & I2SR_IAL) { /* Arbitration lost */
812 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
813 if (!(status & I2SR_IAAS))
814 return IRQ_HANDLED;
815 }
816
817 if (!(status & I2SR_IBB)) {
818 /* No master on the bus, that could mean a stop condition. */
819 i2c_imx_slave_finish_op(i2c_imx);
820 return IRQ_HANDLED;
821 }
822
823 if (!(status & I2SR_ICF))
824 /* Data transfer still in progress, ignore this. */
825 goto out;
826
827 if (status & I2SR_IAAS) { /* Addressed as a slave */
828 i2c_imx_slave_finish_op(i2c_imx);
829 if (status & I2SR_SRW) { /* Master wants to read from us*/
830 dev_dbg(&i2c_imx->adapter.dev, "read requested");
831 i2c_imx_slave_event(i2c_imx,
832 I2C_SLAVE_READ_REQUESTED, &value);
833
834 /* Slave transmit */
835 ctl |= I2CR_MTX;
836 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
837
838 /* Send data */
839 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
840 } else { /* Master wants to write to us */
841 dev_dbg(&i2c_imx->adapter.dev, "write requested");
842 i2c_imx_slave_event(i2c_imx,
843 I2C_SLAVE_WRITE_REQUESTED, &value);
844
845 /* Slave receive */
846 ctl &= ~I2CR_MTX;
847 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
848 /* Dummy read */
849 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
850 }
851 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
852 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
853 i2c_imx_slave_event(i2c_imx,
854 I2C_SLAVE_WRITE_RECEIVED, &value);
855 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
856 ctl |= I2CR_MTX;
857 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
858
859 i2c_imx_slave_event(i2c_imx,
860 I2C_SLAVE_READ_PROCESSED, &value);
861
862 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
863 } else { /* Transmit mode received NAK, operation is done */
864 ctl &= ~I2CR_MTX;
865 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
866 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
867
868 /* flag the last byte as processed */
869 i2c_imx_slave_event(i2c_imx,
870 I2C_SLAVE_READ_PROCESSED, &value);
871
872 i2c_imx_slave_finish_op(i2c_imx);
873 return IRQ_HANDLED;
874 }
875
876 out:
877 /*
878 * No need to check the return value here. If it returns 0 or
879 * 1, then everything is fine. If it returns -1, then the
880 * timer is running in the handler. This will still work,
881 * though it may be redone (or already have been done) by the
882 * timer function.
883 */
884 hrtimer_try_to_cancel(&i2c_imx->slave_timer);
885 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
886 hrtimer_restart(&i2c_imx->slave_timer);
887 return IRQ_HANDLED;
888 }
889
i2c_imx_slave_timeout(struct hrtimer * t)890 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)
891 {
892 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,
893 slave_timer);
894 unsigned int ctl, status;
895
896 guard(spinlock_irqsave)(&i2c_imx->slave_lock);
897
898 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
899 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
900 i2c_imx_slave_handle(i2c_imx, status, ctl);
901
902 return HRTIMER_NORESTART;
903 }
904
i2c_imx_slave_init(struct imx_i2c_struct * i2c_imx)905 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
906 {
907 int temp;
908
909 /* Set slave addr. */
910 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
911
912 i2c_imx_reset_regs(i2c_imx);
913
914 /* Enable module */
915 temp = i2c_imx->hwdata->i2cr_ien_opcode;
916 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
917
918 /* Enable interrupt from i2c module */
919 temp |= I2CR_IIEN;
920 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
921
922 i2c_imx_enable_bus_idle(i2c_imx);
923 }
924
i2c_imx_reg_slave(struct i2c_client * client)925 static int i2c_imx_reg_slave(struct i2c_client *client)
926 {
927 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
928 int ret;
929
930 if (i2c_imx->slave)
931 return -EBUSY;
932
933 i2c_imx->slave = client;
934 i2c_imx->last_slave_event = I2C_SLAVE_STOP;
935
936 /* Resume */
937 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
938 if (ret < 0) {
939 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
940 return ret;
941 }
942
943 i2c_imx_slave_init(i2c_imx);
944
945 return 0;
946 }
947
i2c_imx_unreg_slave(struct i2c_client * client)948 static int i2c_imx_unreg_slave(struct i2c_client *client)
949 {
950 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
951 int ret;
952
953 if (!i2c_imx->slave)
954 return -EINVAL;
955
956 /* Reset slave address. */
957 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
958
959 i2c_imx_reset_regs(i2c_imx);
960
961 i2c_imx->slave = NULL;
962
963 /* Suspend */
964 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
965 if (ret < 0)
966 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
967
968 return ret;
969 }
970
i2c_imx_isr_acked(struct imx_i2c_struct * i2c_imx)971 static inline int i2c_imx_isr_acked(struct imx_i2c_struct *i2c_imx)
972 {
973 i2c_imx->isr_result = 0;
974
975 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
976 i2c_imx->state = IMX_I2C_STATE_FAILED;
977 i2c_imx->isr_result = -ENXIO;
978 wake_up(&i2c_imx->queue);
979 }
980
981 return i2c_imx->isr_result;
982 }
983
i2c_imx_isr_write(struct imx_i2c_struct * i2c_imx)984 static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx)
985 {
986 int result;
987
988 result = i2c_imx_isr_acked(i2c_imx);
989 if (result)
990 return result;
991
992 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx)
993 return 0;
994
995 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR);
996
997 return 1;
998 }
999
i2c_imx_isr_read(struct imx_i2c_struct * i2c_imx)1000 static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx)
1001 {
1002 int result;
1003 unsigned int temp;
1004
1005 result = i2c_imx_isr_acked(i2c_imx);
1006 if (result)
1007 return result;
1008
1009 /* setup bus to read data */
1010 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1011 temp &= ~I2CR_MTX;
1012 if ((i2c_imx->msg->len - 1) || (i2c_imx->msg->flags & I2C_M_RECV_LEN))
1013 temp &= ~I2CR_TXAK;
1014
1015 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1016 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1017
1018 return 0;
1019 }
1020
i2c_imx_isr_read_continue(struct imx_i2c_struct * i2c_imx)1021 static inline void i2c_imx_isr_read_continue(struct imx_i2c_struct *i2c_imx)
1022 {
1023 unsigned int temp;
1024
1025 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) {
1026 if (i2c_imx->is_lastmsg) {
1027 /*
1028 * It must generate STOP before read I2DR to prevent
1029 * controller from generating another clock cycle
1030 */
1031 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1032 if (!(temp & I2CR_MSTA))
1033 i2c_imx->stopped = 1;
1034 temp &= ~(I2CR_MSTA | I2CR_MTX);
1035 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1036 } else {
1037 /*
1038 * For i2c master receiver repeat restart operation like:
1039 * read -> repeat MSTA -> read/write
1040 * The controller must set MTX before read the last byte in
1041 * the first read operation, otherwise the first read cost
1042 * one extra clock cycle.
1043 */
1044 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1045 temp |= I2CR_MTX;
1046 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1047 }
1048 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) {
1049 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1050 temp |= I2CR_TXAK;
1051 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1052 }
1053
1054 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1055 }
1056
i2c_imx_isr_read_block_data_len(struct imx_i2c_struct * i2c_imx)1057 static inline void i2c_imx_isr_read_block_data_len(struct imx_i2c_struct *i2c_imx)
1058 {
1059 u8 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1060
1061 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) {
1062 i2c_imx->isr_result = -EPROTO;
1063 i2c_imx->state = IMX_I2C_STATE_FAILED;
1064 wake_up(&i2c_imx->queue);
1065 }
1066 i2c_imx->msg->len += len;
1067 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = len;
1068 }
1069
i2c_imx_master_isr(struct imx_i2c_struct * i2c_imx,unsigned int status)1070 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
1071 {
1072 /*
1073 * This state machine handles I2C reception and transmission in non-DMA
1074 * mode. We must process all the data in the ISR to reduce the delay
1075 * between two consecutive messages. If the data is not processed in
1076 * the ISR, SMBus devices may timeout, leading to a bus error.
1077 */
1078 switch (i2c_imx->state) {
1079 case IMX_I2C_STATE_DMA:
1080 i2c_imx->i2csr = status;
1081 wake_up(&i2c_imx->queue);
1082 break;
1083
1084 case IMX_I2C_STATE_READ:
1085 if (i2c_imx_isr_read(i2c_imx))
1086 break;
1087 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE;
1088 break;
1089
1090 case IMX_I2C_STATE_READ_CONTINUE:
1091 i2c_imx_isr_read_continue(i2c_imx);
1092 if (i2c_imx->msg_buf_idx == i2c_imx->msg->len) {
1093 i2c_imx->state = IMX_I2C_STATE_DONE;
1094 wake_up(&i2c_imx->queue);
1095 }
1096 break;
1097
1098 case IMX_I2C_STATE_READ_BLOCK_DATA:
1099 if (i2c_imx_isr_read(i2c_imx))
1100 break;
1101 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN;
1102 break;
1103
1104 case IMX_I2C_STATE_READ_BLOCK_DATA_LEN:
1105 i2c_imx_isr_read_block_data_len(i2c_imx);
1106 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE;
1107 break;
1108
1109 case IMX_I2C_STATE_WRITE:
1110 if (i2c_imx_isr_write(i2c_imx))
1111 break;
1112 i2c_imx->state = IMX_I2C_STATE_DONE;
1113 wake_up(&i2c_imx->queue);
1114 break;
1115
1116 default:
1117 i2c_imx->i2csr = status;
1118 i2c_imx->state = IMX_I2C_STATE_FAILED;
1119 i2c_imx->isr_result = -EINVAL;
1120 wake_up(&i2c_imx->queue);
1121 }
1122
1123 return IRQ_HANDLED;
1124 }
1125
i2c_imx_isr(int irq,void * dev_id)1126 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
1127 {
1128 struct imx_i2c_struct *i2c_imx = dev_id;
1129 unsigned int ctl, status;
1130
1131 scoped_guard(spinlock_irqsave, &i2c_imx->slave_lock) {
1132 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1133 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1134
1135 if (!(status & I2SR_IIF))
1136 return IRQ_NONE;
1137
1138 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
1139
1140 if (i2c_imx->slave) {
1141 if (!(ctl & I2CR_MSTA))
1142 return i2c_imx_slave_handle(i2c_imx,
1143 status, ctl);
1144
1145 i2c_imx_slave_finish_op(i2c_imx);
1146 }
1147 }
1148
1149 return i2c_imx_master_isr(i2c_imx, status);
1150 }
1151
i2c_imx_dma_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)1152 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
1153 struct i2c_msg *msgs)
1154 {
1155 int result;
1156 unsigned long time_left;
1157 unsigned int temp = 0;
1158 unsigned long orig_jiffies = jiffies;
1159 struct imx_i2c_dma *dma = i2c_imx->dma;
1160 struct device *dev = &i2c_imx->adapter.dev;
1161
1162 i2c_imx->state = IMX_I2C_STATE_DMA;
1163
1164 dma->chan_using = dma->chan_tx;
1165 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
1166 dma->dma_data_dir = DMA_TO_DEVICE;
1167 dma->dma_len = msgs->len - 1;
1168 result = i2c_imx_dma_xfer(i2c_imx, msgs);
1169 if (result)
1170 return result;
1171
1172 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1173 temp |= I2CR_DMAEN;
1174 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1175
1176 /*
1177 * Write slave address.
1178 * The first byte must be transmitted by the CPU.
1179 */
1180 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1181 time_left = wait_for_completion_timeout(
1182 &i2c_imx->dma->cmd_complete,
1183 msecs_to_jiffies(DMA_TIMEOUT));
1184 if (time_left == 0) {
1185 dmaengine_terminate_sync(dma->chan_using);
1186 return -ETIMEDOUT;
1187 }
1188
1189 /* Waiting for transfer complete. */
1190 while (1) {
1191 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1192 if (temp & I2SR_ICF)
1193 break;
1194 if (time_after(jiffies, orig_jiffies +
1195 msecs_to_jiffies(DMA_TIMEOUT))) {
1196 dev_dbg(dev, "<%s> Timeout\n", __func__);
1197 return -ETIMEDOUT;
1198 }
1199 schedule();
1200 }
1201
1202 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1203 temp &= ~I2CR_DMAEN;
1204 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1205
1206 /* The last data byte must be transferred by the CPU. */
1207 imx_i2c_write_reg(msgs->buf[msgs->len-1],
1208 i2c_imx, IMX_I2C_I2DR);
1209 result = i2c_imx_trx_complete(i2c_imx, false);
1210 if (result)
1211 return result;
1212
1213 return i2c_imx_acked(i2c_imx);
1214 }
1215
i2c_imx_prepare_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool use_dma)1216 static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx,
1217 struct i2c_msg *msgs, bool use_dma)
1218 {
1219 int result;
1220 unsigned int temp = 0;
1221
1222 /* write slave address */
1223 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1224 result = i2c_imx_trx_complete(i2c_imx, !use_dma);
1225 if (result)
1226 return result;
1227 result = i2c_imx_acked(i2c_imx);
1228 if (result)
1229 return result;
1230
1231 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1232
1233 /* setup bus to read data */
1234 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1235 temp &= ~I2CR_MTX;
1236
1237 /*
1238 * Reset the I2CR_TXAK flag initially for SMBus block read since the
1239 * length is unknown
1240 */
1241 if (msgs->len - 1)
1242 temp &= ~I2CR_TXAK;
1243 if (use_dma)
1244 temp |= I2CR_DMAEN;
1245
1246 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1247 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1248
1249 return 0;
1250 }
1251
i2c_imx_dma_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)1252 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
1253 struct i2c_msg *msgs, bool is_lastmsg)
1254 {
1255 int result;
1256 unsigned long time_left;
1257 unsigned int temp;
1258 unsigned long orig_jiffies = jiffies;
1259 struct imx_i2c_dma *dma = i2c_imx->dma;
1260 struct device *dev = &i2c_imx->adapter.dev;
1261
1262 i2c_imx->state = IMX_I2C_STATE_DMA;
1263
1264 result = i2c_imx_prepare_read(i2c_imx, msgs, true);
1265 if (result)
1266 return result;
1267
1268 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1269
1270 dma->chan_using = dma->chan_rx;
1271 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
1272 dma->dma_data_dir = DMA_FROM_DEVICE;
1273 /* The last two data bytes must be transferred by the CPU. */
1274 dma->dma_len = msgs->len - 2;
1275 result = i2c_imx_dma_xfer(i2c_imx, msgs);
1276 if (result)
1277 return result;
1278
1279 time_left = wait_for_completion_timeout(
1280 &i2c_imx->dma->cmd_complete,
1281 msecs_to_jiffies(DMA_TIMEOUT));
1282 if (time_left == 0) {
1283 dmaengine_terminate_sync(dma->chan_using);
1284 return -ETIMEDOUT;
1285 }
1286
1287 /* waiting for transfer complete. */
1288 while (1) {
1289 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1290 if (temp & I2SR_ICF)
1291 break;
1292 if (time_after(jiffies, orig_jiffies +
1293 msecs_to_jiffies(DMA_TIMEOUT))) {
1294 dev_dbg(dev, "<%s> Timeout\n", __func__);
1295 return -ETIMEDOUT;
1296 }
1297 schedule();
1298 }
1299
1300 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1301 temp &= ~I2CR_DMAEN;
1302 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1303
1304 /* read n-1 byte data */
1305 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1306 temp |= I2CR_TXAK;
1307 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1308
1309 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1310 /* read n byte data */
1311 result = i2c_imx_trx_complete(i2c_imx, false);
1312 if (result)
1313 return result;
1314
1315 if (is_lastmsg) {
1316 /*
1317 * It must generate STOP before read I2DR to prevent
1318 * controller from generating another clock cycle
1319 */
1320 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
1321 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1322 if (!(temp & I2CR_MSTA))
1323 i2c_imx->stopped = 1;
1324 temp &= ~(I2CR_MSTA | I2CR_MTX);
1325 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1326 if (!i2c_imx->stopped)
1327 i2c_imx_bus_busy(i2c_imx, 0, false);
1328 } else {
1329 /*
1330 * For i2c master receiver repeat restart operation like:
1331 * read -> repeat MSTA -> read/write
1332 * The controller must set MTX before read the last byte in
1333 * the first read operation, otherwise the first read cost
1334 * one extra clock cycle.
1335 */
1336 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1337 temp |= I2CR_MTX;
1338 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1339 }
1340 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1341
1342 return 0;
1343 }
1344
i2c_imx_atomic_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)1345 static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx,
1346 struct i2c_msg *msgs)
1347 {
1348 int i, result;
1349
1350 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1351 __func__, i2c_8bit_addr_from_msg(msgs));
1352
1353 /* write slave address */
1354 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1355 result = i2c_imx_trx_complete(i2c_imx, true);
1356 if (result)
1357 return result;
1358 result = i2c_imx_acked(i2c_imx);
1359 if (result)
1360 return result;
1361 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1362
1363 /* write data */
1364 for (i = 0; i < msgs->len; i++) {
1365 dev_dbg(&i2c_imx->adapter.dev,
1366 "<%s> write byte: B%d=0x%X\n",
1367 __func__, i, msgs->buf[i]);
1368 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1369 result = i2c_imx_trx_complete(i2c_imx, true);
1370 if (result)
1371 return result;
1372 result = i2c_imx_acked(i2c_imx);
1373 if (result)
1374 return result;
1375 }
1376 return 0;
1377 }
1378
i2c_imx_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)1379 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
1380 {
1381 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1382 __func__, i2c_8bit_addr_from_msg(msgs));
1383
1384 i2c_imx->state = IMX_I2C_STATE_WRITE;
1385 i2c_imx->msg = msgs;
1386 i2c_imx->msg_buf_idx = 0;
1387
1388 /*
1389 * By writing the device address we start the state machine in the ISR.
1390 * The ISR will report when it is done or when it fails.
1391 */
1392 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1393 wait_event_timeout(i2c_imx->queue,
1394 i2c_imx->state == IMX_I2C_STATE_DONE ||
1395 i2c_imx->state == IMX_I2C_STATE_FAILED,
1396 (msgs->len + 1) * HZ / 10);
1397 if (i2c_imx->state == IMX_I2C_STATE_FAILED) {
1398 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n",
1399 __func__, i2c_imx->isr_result);
1400 return i2c_imx->isr_result;
1401 }
1402 if (i2c_imx->state != IMX_I2C_STATE_DONE) {
1403 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__);
1404 return -ETIMEDOUT;
1405 }
1406 return 0;
1407 }
1408
i2c_imx_atomic_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)1409 static int i2c_imx_atomic_read(struct imx_i2c_struct *i2c_imx,
1410 struct i2c_msg *msgs, bool is_lastmsg)
1411 {
1412 int i, result;
1413 unsigned int temp;
1414 int block_data = msgs->flags & I2C_M_RECV_LEN;
1415
1416 result = i2c_imx_prepare_read(i2c_imx, msgs, false);
1417 if (result)
1418 return result;
1419
1420 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1421
1422 /* read data */
1423 for (i = 0; i < msgs->len; i++) {
1424 u8 len = 0;
1425
1426 result = i2c_imx_trx_complete(i2c_imx, true);
1427 if (result)
1428 return result;
1429 /*
1430 * First byte is the length of remaining packet
1431 * in the SMBus block data read. Add it to
1432 * msgs->len.
1433 */
1434 if ((!i) && block_data) {
1435 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1436 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
1437 return -EPROTO;
1438 dev_dbg(&i2c_imx->adapter.dev,
1439 "<%s> read length: 0x%X\n",
1440 __func__, len);
1441 msgs->len += len;
1442 }
1443 if (i == (msgs->len - 1)) {
1444 if (is_lastmsg) {
1445 /*
1446 * It must generate STOP before read I2DR to prevent
1447 * controller from generating another clock cycle
1448 */
1449 dev_dbg(&i2c_imx->adapter.dev,
1450 "<%s> clear MSTA\n", __func__);
1451 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1452 if (!(temp & I2CR_MSTA))
1453 i2c_imx->stopped = 1;
1454 temp &= ~(I2CR_MSTA | I2CR_MTX);
1455 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1456 if (!i2c_imx->stopped)
1457 i2c_imx_bus_busy(i2c_imx, 0, true);
1458 } else {
1459 /*
1460 * For i2c master receiver repeat restart operation like:
1461 * read -> repeat MSTA -> read/write
1462 * The controller must set MTX before read the last byte in
1463 * the first read operation, otherwise the first read cost
1464 * one extra clock cycle.
1465 */
1466 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1467 temp |= I2CR_MTX;
1468 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1469 }
1470 } else if (i == (msgs->len - 2)) {
1471 dev_dbg(&i2c_imx->adapter.dev,
1472 "<%s> set TXAK\n", __func__);
1473 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1474 temp |= I2CR_TXAK;
1475 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1476 }
1477 if ((!i) && block_data)
1478 msgs->buf[0] = len;
1479 else
1480 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1481 dev_dbg(&i2c_imx->adapter.dev,
1482 "<%s> read byte: B%d=0x%X\n",
1483 __func__, i, msgs->buf[i]);
1484 }
1485 return 0;
1486 }
1487
i2c_imx_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)1488 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1489 bool is_lastmsg)
1490 {
1491 int block_data = msgs->flags & I2C_M_RECV_LEN;
1492
1493 dev_dbg(&i2c_imx->adapter.dev,
1494 "<%s> write slave address: addr=0x%x\n",
1495 __func__, i2c_8bit_addr_from_msg(msgs));
1496
1497 i2c_imx->is_lastmsg = is_lastmsg;
1498
1499 if (block_data)
1500 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA;
1501 else
1502 i2c_imx->state = IMX_I2C_STATE_READ;
1503 i2c_imx->msg = msgs;
1504 i2c_imx->msg_buf_idx = 0;
1505
1506 /*
1507 * By writing the device address we start the state machine in the ISR.
1508 * The ISR will report when it is done or when it fails.
1509 */
1510 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1511 wait_event_timeout(i2c_imx->queue,
1512 i2c_imx->state == IMX_I2C_STATE_DONE ||
1513 i2c_imx->state == IMX_I2C_STATE_FAILED,
1514 (msgs->len + 1) * HZ / 10);
1515 if (i2c_imx->state == IMX_I2C_STATE_FAILED) {
1516 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n",
1517 __func__, i2c_imx->isr_result);
1518 return i2c_imx->isr_result;
1519 }
1520 if (i2c_imx->state != IMX_I2C_STATE_DONE) {
1521 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__);
1522 return -ETIMEDOUT;
1523 }
1524 if (!i2c_imx->stopped)
1525 return i2c_imx_bus_busy(i2c_imx, 0, false);
1526
1527 return 0;
1528 }
1529
i2c_imx_xfer_common(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,bool atomic)1530 static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
1531 struct i2c_msg *msgs, int num, bool atomic)
1532 {
1533 unsigned int i, temp;
1534 int result;
1535 bool is_lastmsg = false;
1536 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1537 int use_dma = 0;
1538
1539 /* Start I2C transfer */
1540 result = i2c_imx_start(i2c_imx, atomic);
1541 if (result) {
1542 /*
1543 * Bus recovery uses gpiod_get_value_cansleep() which is not
1544 * allowed within atomic context.
1545 */
1546 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1547 i2c_recover_bus(&i2c_imx->adapter);
1548 result = i2c_imx_start(i2c_imx, atomic);
1549 }
1550 }
1551
1552 if (result)
1553 goto fail0;
1554
1555 /* read/write data */
1556 for (i = 0; i < num; i++) {
1557 if (i == num - 1)
1558 is_lastmsg = true;
1559
1560 if (i) {
1561 dev_dbg(&i2c_imx->adapter.dev,
1562 "<%s> repeated start\n", __func__);
1563 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1564 temp |= I2CR_RSTA;
1565 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1566 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
1567 if (result)
1568 goto fail0;
1569 }
1570 dev_dbg(&i2c_imx->adapter.dev,
1571 "<%s> transfer message: %d\n", __func__, i);
1572 /* write/read data */
1573 #ifdef CONFIG_I2C_DEBUG_BUS
1574 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1575 dev_dbg(&i2c_imx->adapter.dev,
1576 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
1577 __func__,
1578 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
1579 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
1580 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
1581 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1582 dev_dbg(&i2c_imx->adapter.dev,
1583 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
1584 __func__,
1585 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
1586 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
1587 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
1588 (temp & I2SR_RXAK ? 1 : 0));
1589 #endif
1590
1591 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1592 msgs[i].flags & I2C_M_DMA_SAFE;
1593 if (msgs[i].flags & I2C_M_RD) {
1594 int block_data = msgs->flags & I2C_M_RECV_LEN;
1595
1596 if (atomic)
1597 result = i2c_imx_atomic_read(i2c_imx, &msgs[i], is_lastmsg);
1598 else if (use_dma && !block_data)
1599 result = i2c_imx_dma_read(i2c_imx, &msgs[i], is_lastmsg);
1600 else
1601 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
1602 } else {
1603 if (atomic)
1604 result = i2c_imx_atomic_write(i2c_imx, &msgs[i]);
1605 else if (use_dma)
1606 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1607 else
1608 result = i2c_imx_write(i2c_imx, &msgs[i]);
1609 }
1610 if (result)
1611 goto fail0;
1612 }
1613
1614 fail0:
1615 /* Stop I2C transfer */
1616 i2c_imx_stop(i2c_imx, atomic);
1617
1618 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1619 (result < 0) ? "error" : "success msg",
1620 (result < 0) ? result : num);
1621 /* After data is transferred, switch to slave mode(as a receiver) */
1622 if (i2c_imx->slave)
1623 i2c_imx_slave_init(i2c_imx);
1624
1625 return (result < 0) ? result : num;
1626 }
1627
i2c_imx_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1628 static int i2c_imx_xfer(struct i2c_adapter *adapter,
1629 struct i2c_msg *msgs, int num)
1630 {
1631 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1632 int result;
1633
1634 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1635 if (result < 0)
1636 return result;
1637
1638 result = i2c_imx_xfer_common(adapter, msgs, num, false);
1639
1640 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1641 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1642
1643 return result;
1644 }
1645
i2c_imx_xfer_atomic(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1646 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1647 struct i2c_msg *msgs, int num)
1648 {
1649 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1650 int result;
1651
1652 result = clk_enable(i2c_imx->clk);
1653 if (result)
1654 return result;
1655
1656 result = i2c_imx_xfer_common(adapter, msgs, num, true);
1657
1658 clk_disable(i2c_imx->clk);
1659
1660 return result;
1661 }
1662
1663 /*
1664 * We switch SCL and SDA to their GPIO function and do some bitbanging
1665 * for bus recovery. These alternative pinmux settings can be
1666 * described in the device tree by a separate pinctrl state "gpio". If
1667 * this is missing this is not a big problem, the only implication is
1668 * that we can't do bus recovery.
1669 */
i2c_imx_init_recovery_info(struct imx_i2c_struct * i2c_imx,struct platform_device * pdev)1670 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1671 struct platform_device *pdev)
1672 {
1673 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo;
1674
1675 bri->pinctrl = devm_pinctrl_get(&pdev->dev);
1676 if (IS_ERR(bri->pinctrl))
1677 return PTR_ERR(bri->pinctrl);
1678
1679 i2c_imx->adapter.bus_recovery_info = bri;
1680
1681 return 0;
1682 }
1683
i2c_imx_func(struct i2c_adapter * adapter)1684 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1685 {
1686 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1687 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1688 }
1689
1690 static const struct i2c_algorithm i2c_imx_algo = {
1691 .xfer = i2c_imx_xfer,
1692 .xfer_atomic = i2c_imx_xfer_atomic,
1693 .functionality = i2c_imx_func,
1694 .reg_slave = i2c_imx_reg_slave,
1695 .unreg_slave = i2c_imx_unreg_slave,
1696 };
1697
i2c_imx_probe(struct platform_device * pdev)1698 static int i2c_imx_probe(struct platform_device *pdev)
1699 {
1700 struct imx_i2c_struct *i2c_imx;
1701 struct resource *res;
1702 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1703 void __iomem *base;
1704 int irq, ret;
1705 dma_addr_t phy_addr;
1706 const struct imx_i2c_hwdata *match;
1707
1708 irq = platform_get_irq(pdev, 0);
1709 if (irq < 0)
1710 return dev_err_probe(&pdev->dev, irq, "can't get IRQ\n");
1711
1712 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1713 if (IS_ERR(base))
1714 return dev_err_probe(&pdev->dev, PTR_ERR(base), "can't get IO memory\n");
1715
1716 phy_addr = (dma_addr_t)res->start;
1717 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1718 if (!i2c_imx)
1719 return -ENOMEM;
1720
1721 spin_lock_init(&i2c_imx->slave_lock);
1722 hrtimer_setup(&i2c_imx->slave_timer, i2c_imx_slave_timeout, CLOCK_MONOTONIC,
1723 HRTIMER_MODE_ABS);
1724
1725 match = device_get_match_data(&pdev->dev);
1726 if (match)
1727 i2c_imx->hwdata = match;
1728 else
1729 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1730 platform_get_device_id(pdev)->driver_data;
1731
1732 /* Setup i2c_imx driver structure */
1733 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1734 i2c_imx->adapter.owner = THIS_MODULE;
1735 i2c_imx->adapter.algo = &i2c_imx_algo;
1736 i2c_imx->adapter.dev.parent = &pdev->dev;
1737 i2c_imx->adapter.nr = pdev->id;
1738 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1739 i2c_imx->base = base;
1740 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1741
1742 /* Get I2C clock */
1743 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1744 if (IS_ERR(i2c_imx->clk))
1745 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1746 "can't get I2C clock\n");
1747
1748 /* Init queue */
1749 init_waitqueue_head(&i2c_imx->queue);
1750
1751 /* Set up adapter data */
1752 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1753
1754 /* Set up platform driver data */
1755 platform_set_drvdata(pdev, i2c_imx);
1756
1757 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1758 pm_runtime_use_autosuspend(&pdev->dev);
1759 pm_runtime_set_active(&pdev->dev);
1760 pm_runtime_enable(&pdev->dev);
1761
1762 ret = pm_runtime_get_sync(&pdev->dev);
1763 if (ret < 0)
1764 goto rpm_disable;
1765
1766 /* Request IRQ */
1767 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED | IRQF_NO_SUSPEND,
1768 pdev->name, i2c_imx);
1769 if (ret) {
1770 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1771 goto rpm_disable;
1772 }
1773
1774 /*
1775 * We use the single-master property for backward compatibility.
1776 * By default multi master mode is enabled.
1777 */
1778 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master");
1779
1780 /* Set up clock divider */
1781 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1782 ret = of_property_read_u32(pdev->dev.of_node,
1783 "clock-frequency", &i2c_imx->bitrate);
1784 if (ret < 0 && pdata && pdata->bitrate)
1785 i2c_imx->bitrate = pdata->bitrate;
1786 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1787 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1788 ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1789 if (ret < 0) {
1790 dev_err(&pdev->dev, "can't get I2C clock\n");
1791 goto clk_notifier_unregister;
1792 }
1793
1794 i2c_imx_reset_regs(i2c_imx);
1795
1796 /* Init optional bus recovery function */
1797 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1798 /* Give it another chance if pinctrl used is not ready yet */
1799 if (ret == -EPROBE_DEFER)
1800 goto clk_notifier_unregister;
1801
1802 /*
1803 * DMA mode should be optional for I2C, when encountering DMA errors,
1804 * no need to exit I2C probe. Only print warning to show DMA error and
1805 * use PIO mode directly to ensure I2C bus available as much as possible.
1806 */
1807 ret = i2c_imx_dma_request(i2c_imx, phy_addr);
1808 if (ret) {
1809 if (ret == -EPROBE_DEFER) {
1810 dev_err_probe(&pdev->dev, ret, "can't get DMA channels\n");
1811 goto clk_notifier_unregister;
1812 } else if (ret == -ENODEV) {
1813 dev_dbg(&pdev->dev, "Only use PIO mode\n");
1814 } else {
1815 dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n",
1816 ERR_PTR(ret));
1817 }
1818 }
1819
1820 /* Add I2C adapter */
1821 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1822 if (ret < 0)
1823 goto clk_notifier_unregister;
1824
1825 pm_runtime_mark_last_busy(&pdev->dev);
1826 pm_runtime_put_autosuspend(&pdev->dev);
1827
1828 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1829 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1830 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1831 i2c_imx->adapter.name);
1832 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1833
1834 return 0; /* Return OK */
1835
1836 clk_notifier_unregister:
1837 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1838 free_irq(irq, i2c_imx);
1839 rpm_disable:
1840 pm_runtime_put_noidle(&pdev->dev);
1841 pm_runtime_disable(&pdev->dev);
1842 pm_runtime_set_suspended(&pdev->dev);
1843 pm_runtime_dont_use_autosuspend(&pdev->dev);
1844 return ret;
1845 }
1846
i2c_imx_remove(struct platform_device * pdev)1847 static void i2c_imx_remove(struct platform_device *pdev)
1848 {
1849 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1850 int irq, ret;
1851
1852 ret = pm_runtime_get_sync(&pdev->dev);
1853
1854 hrtimer_cancel(&i2c_imx->slave_timer);
1855
1856 /* remove adapter */
1857 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1858 i2c_del_adapter(&i2c_imx->adapter);
1859
1860 if (i2c_imx->dma)
1861 i2c_imx_dma_free(i2c_imx);
1862
1863 if (ret >= 0) {
1864 /* setup chip registers to defaults */
1865 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1866 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1867 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1868 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1869 }
1870
1871 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1872 irq = platform_get_irq(pdev, 0);
1873 if (irq >= 0)
1874 free_irq(irq, i2c_imx);
1875
1876 pm_runtime_put_noidle(&pdev->dev);
1877 pm_runtime_disable(&pdev->dev);
1878 }
1879
i2c_imx_runtime_suspend(struct device * dev)1880 static int i2c_imx_runtime_suspend(struct device *dev)
1881 {
1882 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1883
1884 clk_disable(i2c_imx->clk);
1885 return pinctrl_pm_select_sleep_state(dev);
1886 }
1887
i2c_imx_runtime_resume(struct device * dev)1888 static int i2c_imx_runtime_resume(struct device *dev)
1889 {
1890 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1891 int ret;
1892
1893 ret = pinctrl_pm_select_default_state(dev);
1894 if (ret)
1895 return ret;
1896
1897 ret = clk_enable(i2c_imx->clk);
1898 if (ret)
1899 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1900
1901 return ret;
1902 }
1903
i2c_imx_suspend(struct device * dev)1904 static int i2c_imx_suspend(struct device *dev)
1905 {
1906 /*
1907 * Some I2C devices may need the I2C controller to remain active
1908 * during resume_noirq() or suspend_noirq(). If the controller is
1909 * autosuspended, there is no way to wake it up once runtime PM is
1910 * disabled (in suspend_late()).
1911 *
1912 * During system resume, the I2C controller will be available only
1913 * after runtime PM is re-enabled (in resume_early()). However, this
1914 * may be too late for some devices.
1915 *
1916 * Wake up the controller in the suspend() callback while runtime PM
1917 * is still enabled. The I2C controller will remain available until
1918 * the suspend_noirq() callback (pm_runtime_force_suspend()) is
1919 * called. During resume, the I2C controller can be restored by the
1920 * resume_noirq() callback (pm_runtime_force_resume()).
1921 *
1922 * Finally, the resume() callback re-enables autosuspend, ensuring
1923 * the I2C controller remains available until the system enters
1924 * suspend_noirq() and from resume_noirq().
1925 */
1926 return pm_runtime_resume_and_get(dev);
1927 }
1928
i2c_imx_resume(struct device * dev)1929 static int i2c_imx_resume(struct device *dev)
1930 {
1931 pm_runtime_mark_last_busy(dev);
1932 pm_runtime_put_autosuspend(dev);
1933
1934 return 0;
1935 }
1936
1937 static const struct dev_pm_ops i2c_imx_pm_ops = {
1938 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1939 pm_runtime_force_resume)
1940 SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume)
1941 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL)
1942 };
1943
1944 static struct platform_driver i2c_imx_driver = {
1945 .probe = i2c_imx_probe,
1946 .remove = i2c_imx_remove,
1947 .driver = {
1948 .name = DRIVER_NAME,
1949 .pm = pm_ptr(&i2c_imx_pm_ops),
1950 .of_match_table = i2c_imx_dt_ids,
1951 .acpi_match_table = i2c_imx_acpi_ids,
1952 },
1953 .id_table = imx_i2c_devtype,
1954 };
1955
i2c_adap_imx_init(void)1956 static int __init i2c_adap_imx_init(void)
1957 {
1958 return platform_driver_register(&i2c_imx_driver);
1959 }
1960 subsys_initcall(i2c_adap_imx_init);
1961
i2c_adap_imx_exit(void)1962 static void __exit i2c_adap_imx_exit(void)
1963 {
1964 platform_driver_unregister(&i2c_imx_driver);
1965 }
1966 module_exit(i2c_adap_imx_exit);
1967
1968 MODULE_LICENSE("GPL");
1969 MODULE_AUTHOR("Darius Augulis");
1970 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1971 MODULE_ALIAS("platform:" DRIVER_NAME);
1972