1 /*-
2 * Copyright (c) 2005 Poul-Henning Kamp
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_acpi.h"
30
31 #if defined(__amd64__)
32 #define DEV_APIC
33 #else
34 #include "opt_apic.h"
35 #endif
36 #include <sys/param.h>
37 #include <sys/conf.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/proc.h>
42 #include <sys/rman.h>
43 #include <sys/mman.h>
44 #include <sys/time.h>
45 #include <sys/smp.h>
46 #include <sys/sysctl.h>
47 #include <sys/timeet.h>
48 #include <sys/timetc.h>
49 #include <sys/vdso.h>
50
51 #include <contrib/dev/acpica/include/acpi.h>
52 #include <contrib/dev/acpica/include/accommon.h>
53
54 #include <dev/acpica/acpivar.h>
55 #include <dev/acpica/acpi_hpet.h>
56
57 #ifdef DEV_APIC
58 #include "pcib_if.h"
59 #endif
60
61 #define HPET_VENDID_AMD 0x4353
62 #define HPET_VENDID_AMD2 0x1022
63 #define HPET_VENDID_HYGON 0x1d94
64 #define HPET_VENDID_INTEL 0x8086
65 #define HPET_VENDID_NVIDIA 0x10de
66 #define HPET_VENDID_SW 0x1166
67
68 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
69
70 /* ACPI CA debugging */
71 #define _COMPONENT ACPI_TIMER
72 ACPI_MODULE_NAME("HPET")
73
74 struct hpet_softc {
75 device_t dev;
76 int mem_rid;
77 int intr_rid;
78 int irq;
79 int useirq;
80 int legacy_route;
81 int per_cpu;
82 uint32_t allowed_irqs;
83 struct resource *mem_res;
84 struct resource *intr_res;
85 void *intr_handle;
86 ACPI_HANDLE handle;
87 uint32_t acpi_uid;
88 uint64_t freq;
89 uint32_t caps;
90 struct timecounter tc;
91 struct hpet_timer {
92 struct eventtimer et;
93 struct hpet_softc *sc;
94 int num;
95 int mode;
96 #define TIMER_STOPPED 0
97 #define TIMER_PERIODIC 1
98 #define TIMER_ONESHOT 2
99 int intr_rid;
100 int irq;
101 int pcpu_cpu;
102 int pcpu_misrouted;
103 int pcpu_master;
104 int pcpu_slaves[MAXCPU];
105 struct resource *intr_res;
106 void *intr_handle;
107 uint32_t caps;
108 uint32_t vectors;
109 uint32_t div;
110 uint32_t next;
111 char name[8];
112 } t[32];
113 int num_timers;
114 struct cdev *pdev;
115 int mmap_allow;
116 int mmap_allow_write;
117 };
118
119 static d_open_t hpet_open;
120 static d_mmap_t hpet_mmap;
121
122 static struct cdevsw hpet_cdevsw = {
123 .d_version = D_VERSION,
124 .d_name = "hpet",
125 .d_open = hpet_open,
126 .d_mmap = hpet_mmap,
127 };
128
129 static u_int hpet_get_timecount(struct timecounter *tc);
130 static void hpet_test(struct hpet_softc *sc);
131
132 static char *hpet_ids[] = { "PNP0103", NULL };
133
134 static u_int
hpet_get_timecount(struct timecounter * tc)135 hpet_get_timecount(struct timecounter *tc)
136 {
137 struct hpet_softc *sc;
138
139 sc = tc->tc_priv;
140 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
141 }
142
143 uint32_t
hpet_vdso_timehands(struct vdso_timehands * vdso_th,struct timecounter * tc)144 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
145 {
146 struct hpet_softc *sc;
147
148 sc = tc->tc_priv;
149 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET;
150 vdso_th->th_x86_shift = 0;
151 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev);
152 vdso_th->th_x86_pvc_last_systime = 0;
153 vdso_th->th_x86_pvc_stable_mask = 0;
154 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
155 return (sc->mmap_allow != 0);
156 }
157
158 #ifdef COMPAT_FREEBSD32
159 uint32_t
hpet_vdso_timehands32(struct vdso_timehands32 * vdso_th32,struct timecounter * tc)160 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
161 struct timecounter *tc)
162 {
163 struct hpet_softc *sc;
164
165 sc = tc->tc_priv;
166 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET;
167 vdso_th32->th_x86_shift = 0;
168 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev);
169 vdso_th32->th_x86_pvc_last_systime[0] = 0;
170 vdso_th32->th_x86_pvc_last_systime[1] = 0;
171 vdso_th32->th_x86_pvc_stable_mask = 0;
172 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));
173 return (sc->mmap_allow != 0);
174 }
175 #endif
176
177 static void
hpet_enable(struct hpet_softc * sc)178 hpet_enable(struct hpet_softc *sc)
179 {
180 uint32_t val;
181
182 val = bus_read_4(sc->mem_res, HPET_CONFIG);
183 if (sc->legacy_route)
184 val |= HPET_CNF_LEG_RT;
185 else
186 val &= ~HPET_CNF_LEG_RT;
187 val |= HPET_CNF_ENABLE;
188 bus_write_4(sc->mem_res, HPET_CONFIG, val);
189 }
190
191 static void
hpet_disable(struct hpet_softc * sc)192 hpet_disable(struct hpet_softc *sc)
193 {
194 uint32_t val;
195
196 val = bus_read_4(sc->mem_res, HPET_CONFIG);
197 val &= ~HPET_CNF_ENABLE;
198 bus_write_4(sc->mem_res, HPET_CONFIG, val);
199 }
200
201 static int
hpet_start(struct eventtimer * et,sbintime_t first,sbintime_t period)202 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
203 {
204 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
205 struct hpet_timer *t;
206 struct hpet_softc *sc = mt->sc;
207 uint32_t fdiv, now;
208
209 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
210 if (period != 0) {
211 t->mode = TIMER_PERIODIC;
212 t->div = (sc->freq * period) >> 32;
213 } else {
214 t->mode = TIMER_ONESHOT;
215 t->div = 0;
216 }
217 if (first != 0)
218 fdiv = (sc->freq * first) >> 32;
219 else
220 fdiv = t->div;
221 if (t->irq < 0)
222 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
223 t->caps |= HPET_TCNF_INT_ENB;
224 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
225 restart:
226 t->next = now + fdiv;
227 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) {
228 t->caps |= HPET_TCNF_TYPE;
229 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
230 t->caps | HPET_TCNF_VAL_SET);
231 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
232 t->next);
233 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
234 t->div);
235 } else {
236 t->caps &= ~HPET_TCNF_TYPE;
237 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
238 t->caps);
239 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
240 t->next);
241 }
242 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
243 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
244 fdiv *= 2;
245 goto restart;
246 }
247 return (0);
248 }
249
250 static int
hpet_stop(struct eventtimer * et)251 hpet_stop(struct eventtimer *et)
252 {
253 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
254 struct hpet_timer *t;
255 struct hpet_softc *sc = mt->sc;
256
257 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
258 t->mode = TIMER_STOPPED;
259 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
260 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
261 return (0);
262 }
263
264 static int
hpet_intr_single(void * arg)265 hpet_intr_single(void *arg)
266 {
267 struct hpet_timer *t = (struct hpet_timer *)arg;
268 struct hpet_timer *mt;
269 struct hpet_softc *sc = t->sc;
270 uint32_t now;
271
272 if (t->mode == TIMER_STOPPED)
273 return (FILTER_STRAY);
274 /* Check that per-CPU timer interrupt reached right CPU. */
275 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
276 if ((++t->pcpu_misrouted) % 32 == 0) {
277 printf("HPET interrupt routed to the wrong CPU"
278 " (timer %d CPU %d -> %d)!\n",
279 t->num, t->pcpu_cpu, curcpu);
280 }
281
282 /*
283 * Reload timer, hoping that next time may be more lucky
284 * (system will manage proper interrupt binding).
285 */
286 if ((t->mode == TIMER_PERIODIC &&
287 (t->caps & HPET_TCAP_PER_INT) == 0) ||
288 t->mode == TIMER_ONESHOT) {
289 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
290 sc->freq / 8;
291 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
292 t->next);
293 }
294 return (FILTER_HANDLED);
295 }
296 if (t->mode == TIMER_PERIODIC &&
297 (t->caps & HPET_TCAP_PER_INT) == 0) {
298 t->next += t->div;
299 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
300 if ((int32_t)((now + t->div / 2) - t->next) > 0)
301 t->next = now + t->div / 2;
302 bus_write_4(sc->mem_res,
303 HPET_TIMER_COMPARATOR(t->num), t->next);
304 } else if (t->mode == TIMER_ONESHOT)
305 t->mode = TIMER_STOPPED;
306 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
307 if (mt->et.et_active)
308 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
309 return (FILTER_HANDLED);
310 }
311
312 static int
hpet_intr(void * arg)313 hpet_intr(void *arg)
314 {
315 struct hpet_softc *sc = (struct hpet_softc *)arg;
316 int i;
317 uint32_t val;
318
319 val = bus_read_4(sc->mem_res, HPET_ISR);
320 if (val) {
321 bus_write_4(sc->mem_res, HPET_ISR, val);
322 val &= sc->useirq;
323 for (i = 0; i < sc->num_timers; i++) {
324 if ((val & (1 << i)) == 0)
325 continue;
326 hpet_intr_single(&sc->t[i]);
327 }
328 return (FILTER_HANDLED);
329 }
330 return (FILTER_STRAY);
331 }
332
333 uint32_t
hpet_get_uid(device_t dev)334 hpet_get_uid(device_t dev)
335 {
336 struct hpet_softc *sc;
337
338 sc = device_get_softc(dev);
339 return (sc->acpi_uid);
340 }
341
342 static ACPI_STATUS
hpet_find(ACPI_HANDLE handle,UINT32 level,void * context,void ** status)343 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
344 void **status)
345 {
346 char **ids;
347 uint32_t id = (uint32_t)(uintptr_t)context;
348 uint32_t uid = 0;
349
350 for (ids = hpet_ids; *ids != NULL; ids++) {
351 if (acpi_MatchHid(handle, *ids))
352 break;
353 }
354 if (*ids == NULL)
355 return (AE_OK);
356 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
357 id == uid)
358 *status = acpi_get_device(handle);
359 return (AE_OK);
360 }
361
362 /*
363 * Find an existing IRQ resource that matches the requested IRQ range
364 * and return its RID. If one is not found, use a new RID.
365 */
366 static int
hpet_find_irq_rid(device_t dev,u_long start,u_long end)367 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
368 {
369 rman_res_t irq;
370 int error, rid;
371
372 for (rid = 0;; rid++) {
373 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
374 if (error != 0 || (start <= irq && irq <= end))
375 return (rid);
376 }
377 }
378
379 static int
hpet_open(struct cdev * cdev,int oflags,int devtype,struct thread * td)380 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td)
381 {
382 struct hpet_softc *sc;
383
384 sc = cdev->si_drv1;
385 if (!sc->mmap_allow)
386 return (EPERM);
387 else
388 return (0);
389 }
390
391 static int
hpet_mmap(struct cdev * cdev,vm_ooffset_t offset,vm_paddr_t * paddr,int nprot,vm_memattr_t * memattr)392 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,
393 int nprot, vm_memattr_t *memattr)
394 {
395 struct hpet_softc *sc;
396
397 sc = cdev->si_drv1;
398 if (offset >= rman_get_size(sc->mem_res))
399 return (EINVAL);
400 if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
401 return (EPERM);
402 *paddr = rman_get_start(sc->mem_res) + offset;
403 *memattr = VM_MEMATTR_UNCACHEABLE;
404
405 return (0);
406 }
407
408 /* Discover the HPET via the ACPI table of the same name. */
409 static void
hpet_identify(driver_t * driver,device_t parent)410 hpet_identify(driver_t *driver, device_t parent)
411 {
412 ACPI_TABLE_HPET *hpet;
413 ACPI_STATUS status;
414 device_t child;
415 int i;
416
417 /* Only one HPET device can be added. */
418 if (devclass_get_device(devclass_find("hpet"), 0))
419 return;
420 for (i = 1; ; i++) {
421 /* Search for HPET table. */
422 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
423 if (ACPI_FAILURE(status))
424 return;
425 /* Search for HPET device with same ID. */
426 child = NULL;
427 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
428 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence,
429 (void *)&child);
430 /* If found - let it be probed in normal way. */
431 if (child) {
432 if (bus_get_resource(child, SYS_RES_MEMORY, 0,
433 NULL, NULL) != 0)
434 bus_set_resource(child, SYS_RES_MEMORY, 0,
435 hpet->Address.Address, HPET_MEM_WIDTH);
436 continue;
437 }
438 /* If not - create it from table info. */
439 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
440 if (child == NULL) {
441 printf("%s: can't add child\n", __func__);
442 continue;
443 }
444 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
445 HPET_MEM_WIDTH);
446 }
447 }
448
449 static int
hpet_probe(device_t dev)450 hpet_probe(device_t dev)
451 {
452 int rv;
453
454 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
455 if (acpi_disabled("hpet"))
456 return (ENXIO);
457 if (acpi_get_handle(dev) != NULL)
458 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids, NULL);
459 else
460 rv = 0;
461 if (rv <= 0)
462 device_set_desc(dev, "High Precision Event Timer");
463 return (rv);
464 }
465
466 static int
hpet_attach(device_t dev)467 hpet_attach(device_t dev)
468 {
469 struct hpet_softc *sc;
470 struct hpet_timer *t;
471 struct make_dev_args mda;
472 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
473 int pcpu_master, error;
474 rman_res_t hpet_region_size;
475 static int maxhpetet = 0;
476 uint32_t val, val2, cvectors, dvectors;
477 uint16_t vendor, rev;
478
479 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
480
481 sc = device_get_softc(dev);
482 sc->dev = dev;
483 sc->handle = acpi_get_handle(dev);
484
485 sc->mem_rid = 0;
486 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
487 RF_ACTIVE);
488 if (sc->mem_res == NULL)
489 return (ENOMEM);
490
491 hpet_region_size = rman_get_size(sc->mem_res);
492 /* Validate that the region is big enough for the control registers. */
493 if (hpet_region_size < HPET_MEM_MIN_WIDTH) {
494 device_printf(dev, "memory region width %jd too small\n",
495 hpet_region_size);
496 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
497 return (ENXIO);
498 }
499
500 /* Be sure timer is enabled. */
501 hpet_enable(sc);
502
503 /* Read basic statistics about the timer. */
504 val = bus_read_4(sc->mem_res, HPET_PERIOD);
505 if (val == 0) {
506 device_printf(dev, "invalid period\n");
507 hpet_disable(sc);
508 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
509 return (ENXIO);
510 }
511
512 sc->freq = (1000000000000000LL + val / 2) / val;
513 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
514 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
515 rev = sc->caps & HPET_CAP_REV_ID;
516 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
517 /*
518 * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
519 * Specification and provides an off by one number
520 * of timers/comparators.
521 * Additionally, they use unregistered value in VENDOR_ID field.
522 */
523 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
524 num_timers--;
525 /*
526 * Now validate that the region is big enough to address all counters.
527 */
528 if (hpet_region_size < HPET_TIMER_CAP_CNF(num_timers)) {
529 device_printf(dev,
530 "memory region width %jd too small for %d timers\n",
531 hpet_region_size, num_timers);
532 hpet_disable(sc);
533 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
534 return (ENXIO);
535 }
536
537 sc->num_timers = num_timers;
538 if (bootverbose) {
539 device_printf(dev,
540 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
541 vendor, rev, sc->freq,
542 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
543 num_timers,
544 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
545 }
546 for (i = 0; i < num_timers; i++) {
547 t = &sc->t[i];
548 t->sc = sc;
549 t->num = i;
550 t->mode = TIMER_STOPPED;
551 t->intr_rid = -1;
552 t->irq = -1;
553 t->pcpu_cpu = -1;
554 t->pcpu_misrouted = 0;
555 t->pcpu_master = -1;
556 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
557 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
558 if (bootverbose) {
559 device_printf(dev,
560 " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
561 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
562 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
563 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
564 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
565 }
566 }
567 if (testenv("debug.acpi.hpet_test"))
568 hpet_test(sc);
569 /*
570 * Don't attach if the timer never increments. Since the spec
571 * requires it to be at least 10 MHz, it has to change in 1 us.
572 */
573 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
574 DELAY(1);
575 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
576 if (val == val2) {
577 device_printf(dev, "HPET never increments, disabling\n");
578 hpet_disable(sc);
579 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
580 return (ENXIO);
581 }
582 /* Announce first HPET as timecounter. */
583 if (device_get_unit(dev) == 0) {
584 sc->tc.tc_get_timecount = hpet_get_timecount,
585 sc->tc.tc_counter_mask = ~0u,
586 sc->tc.tc_name = "HPET",
587 sc->tc.tc_quality = 950,
588 sc->tc.tc_frequency = sc->freq;
589 sc->tc.tc_priv = sc;
590 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands;
591 #ifdef COMPAT_FREEBSD32
592 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32;
593 #endif
594 tc_init(&sc->tc);
595 }
596 /* If not disabled - setup and announce event timers. */
597 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
598 "clock", &i) == 0 && i == 0)
599 return (0);
600
601 /* Check whether we can and want legacy routing. */
602 sc->legacy_route = 0;
603 resource_int_value(device_get_name(dev), device_get_unit(dev),
604 "legacy_route", &sc->legacy_route);
605 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
606 sc->legacy_route = 0;
607 if (sc->legacy_route) {
608 sc->t[0].vectors = 0;
609 sc->t[1].vectors = 0;
610 }
611
612 /* Check what IRQs we want use. */
613 /* By default allow any PCI IRQs. */
614 sc->allowed_irqs = 0xffff0000;
615 /*
616 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
617 * Lower are also not always working for different reasons.
618 * SB800 fixed it, but seems do not implements level triggering
619 * properly, that makes it very unreliable - it freezes after any
620 * interrupt loss. Avoid legacy IRQs for AMD.
621 */
622 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2 ||
623 vendor == HPET_VENDID_HYGON)
624 sc->allowed_irqs = 0x00000000;
625 /*
626 * NVidia MCP5x chipsets have number of unexplained interrupt
627 * problems. For some reason, using HPET interrupts breaks HDA sound.
628 */
629 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
630 sc->allowed_irqs = 0x00000000;
631 /*
632 * ServerWorks HT1000 reported to have problems with IRQs >= 16.
633 * Lower IRQs are working, but allowed mask is not set correctly.
634 * Legacy_route mode works fine.
635 */
636 if (vendor == HPET_VENDID_SW && rev <= 0x01)
637 sc->allowed_irqs = 0x00000000;
638 /*
639 * Neither QEMU nor VirtualBox report supported IRQs correctly.
640 * The only way to use HPET there is to specify IRQs manually
641 * and/or use legacy_route. Legacy_route mode works on both.
642 */
643 if (vm_guest != VM_GUEST_NO)
644 sc->allowed_irqs = 0x00000000;
645 /* Let user override. */
646 resource_int_value(device_get_name(dev), device_get_unit(dev),
647 "allowed_irqs", &sc->allowed_irqs);
648
649 /* Get how much per-CPU timers we should try to provide. */
650 sc->per_cpu = 1;
651 resource_int_value(device_get_name(dev), device_get_unit(dev),
652 "per_cpu", &sc->per_cpu);
653
654 num_msi = 0;
655 sc->useirq = 0;
656 /* Find IRQ vectors for all timers. */
657 cvectors = sc->allowed_irqs & 0xffff0000;
658 dvectors = sc->allowed_irqs & 0x0000ffff;
659 if (sc->legacy_route)
660 dvectors &= 0x0000fefe;
661 for (i = 0; i < num_timers; i++) {
662 t = &sc->t[i];
663 if (sc->legacy_route && i < 2)
664 t->irq = (i == 0) ? 0 : 8;
665 #ifdef DEV_APIC
666 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
667 if ((j = PCIB_ALLOC_MSIX(
668 device_get_parent(device_get_parent(dev)), dev,
669 &t->irq))) {
670 device_printf(dev,
671 "Can't allocate interrupt for t%d: %d\n",
672 i, j);
673 }
674 }
675 #endif
676 else if (dvectors & t->vectors) {
677 t->irq = ffs(dvectors & t->vectors) - 1;
678 dvectors &= ~(1 << t->irq);
679 }
680 if (t->irq >= 0) {
681 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
682 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
683 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
684 if (t->intr_res == NULL) {
685 t->irq = -1;
686 device_printf(dev,
687 "Can't map interrupt for t%d.\n", i);
688 } else if (bus_setup_intr(dev, t->intr_res,
689 INTR_TYPE_CLK, hpet_intr_single, NULL, t,
690 &t->intr_handle) != 0) {
691 t->irq = -1;
692 device_printf(dev,
693 "Can't setup interrupt for t%d.\n", i);
694 } else {
695 bus_describe_intr(dev, t->intr_res,
696 t->intr_handle, "t%d", i);
697 num_msi++;
698 }
699 }
700 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
701 cvectors &= t->vectors;
702 sc->useirq |= (1 << i);
703 }
704 }
705 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
706 sc->legacy_route = 0;
707 if (sc->legacy_route)
708 hpet_enable(sc);
709 /* Group timers for per-CPU operation. */
710 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
711 num_percpu_t = num_percpu_et * mp_ncpus;
712 pcpu_master = 0;
713 cur_cpu = CPU_FIRST();
714 for (i = 0; i < num_timers; i++) {
715 t = &sc->t[i];
716 if (t->irq >= 0 && num_percpu_t > 0) {
717 if (cur_cpu == CPU_FIRST())
718 pcpu_master = i;
719 t->pcpu_cpu = cur_cpu;
720 t->pcpu_master = pcpu_master;
721 sc->t[pcpu_master].
722 pcpu_slaves[cur_cpu] = i;
723 bus_bind_intr(dev, t->intr_res, cur_cpu);
724 cur_cpu = CPU_NEXT(cur_cpu);
725 num_percpu_t--;
726 } else if (t->irq >= 0)
727 bus_bind_intr(dev, t->intr_res, CPU_FIRST());
728 }
729 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
730 sc->irq = -1;
731 /* If at least one timer needs legacy IRQ - set it up. */
732 if (sc->useirq) {
733 j = i = fls(cvectors) - 1;
734 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
735 j--;
736 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
737 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
738 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
739 if (sc->intr_res == NULL)
740 device_printf(dev, "Can't map interrupt.\n");
741 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
742 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
743 device_printf(dev, "Can't setup interrupt.\n");
744 } else {
745 sc->irq = rman_get_start(sc->intr_res);
746 /* Bind IRQ to BSP to avoid live migration. */
747 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
748 }
749 }
750 /* Program and announce event timers. */
751 for (i = 0; i < num_timers; i++) {
752 t = &sc->t[i];
753 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
754 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
755 t->caps &= ~(HPET_TCNF_INT_TYPE);
756 t->caps |= HPET_TCNF_32MODE;
757 if (t->irq >= 0 && sc->legacy_route && i < 2) {
758 /* Legacy route doesn't need more configuration. */
759 } else
760 #ifdef DEV_APIC
761 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
762 uint64_t addr;
763 uint32_t data;
764
765 if (PCIB_MAP_MSI(
766 device_get_parent(device_get_parent(dev)), dev,
767 t->irq, &addr, &data) == 0) {
768 bus_write_4(sc->mem_res,
769 HPET_TIMER_FSB_ADDR(i), addr);
770 bus_write_4(sc->mem_res,
771 HPET_TIMER_FSB_VAL(i), data);
772 t->caps |= HPET_TCNF_FSB_EN;
773 } else
774 t->irq = -2;
775 } else
776 #endif
777 if (t->irq >= 0)
778 t->caps |= (t->irq << 9);
779 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
780 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
781 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
782 /* Skip event timers without set up IRQ. */
783 if (t->irq < 0 &&
784 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
785 continue;
786 /* Announce the reset. */
787 if (maxhpetet == 0)
788 t->et.et_name = "HPET";
789 else {
790 sprintf(t->name, "HPET%d", maxhpetet);
791 t->et.et_name = t->name;
792 }
793 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
794 t->et.et_quality = 450;
795 if (t->pcpu_master >= 0) {
796 t->et.et_flags |= ET_FLAGS_PERCPU;
797 t->et.et_quality += 100;
798 } else if (mp_ncpus >= 8)
799 t->et.et_quality -= 100;
800 if ((t->caps & HPET_TCAP_PER_INT) == 0)
801 t->et.et_quality -= 10;
802 t->et.et_frequency = sc->freq;
803 t->et.et_min_period =
804 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
805 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
806 t->et.et_start = hpet_start;
807 t->et.et_stop = hpet_stop;
808 t->et.et_priv = &sc->t[i];
809 if (t->pcpu_master < 0 || t->pcpu_master == i) {
810 et_register(&t->et);
811 maxhpetet++;
812 }
813 }
814 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid);
815
816 make_dev_args_init(&mda);
817 mda.mda_devsw = &hpet_cdevsw;
818 mda.mda_uid = UID_ROOT;
819 mda.mda_gid = GID_WHEEL;
820 mda.mda_mode = 0644;
821 mda.mda_si_drv1 = sc;
822 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev));
823 if (error == 0) {
824 sc->mmap_allow = 1;
825 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow",
826 &sc->mmap_allow);
827 sc->mmap_allow_write = 0;
828 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write",
829 &sc->mmap_allow_write);
830 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
831 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
832 OID_AUTO, "mmap_allow",
833 CTLFLAG_RW, &sc->mmap_allow, 0,
834 "Allow userland to memory map HPET");
835 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
836 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
837 OID_AUTO, "mmap_allow_write",
838 CTLFLAG_RW, &sc->mmap_allow_write, 0,
839 "Allow userland write to the HPET register space");
840 } else {
841 device_printf(dev, "could not create /dev/hpet%d, error %d\n",
842 device_get_unit(dev), error);
843 }
844
845 return (0);
846 }
847
848 static int
hpet_detach(device_t dev)849 hpet_detach(device_t dev)
850 {
851 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
852
853 /* XXX Without a tc_remove() function, we can't detach. */
854 return (EBUSY);
855 }
856
857 static int
hpet_suspend(device_t dev)858 hpet_suspend(device_t dev)
859 {
860 // struct hpet_softc *sc;
861
862 /*
863 * Disable the timer during suspend. The timer will not lose
864 * its state in S1 or S2, but we are required to disable
865 * it.
866 */
867 // sc = device_get_softc(dev);
868 // hpet_disable(sc);
869
870 return (0);
871 }
872
873 static int
hpet_resume(device_t dev)874 hpet_resume(device_t dev)
875 {
876 struct hpet_softc *sc;
877 struct hpet_timer *t;
878 int i;
879
880 /* Re-enable the timer after a resume to keep the clock advancing. */
881 sc = device_get_softc(dev);
882 hpet_enable(sc);
883 /* Restart event timers that were running on suspend. */
884 for (i = 0; i < sc->num_timers; i++) {
885 t = &sc->t[i];
886 #ifdef DEV_APIC
887 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
888 uint64_t addr;
889 uint32_t data;
890
891 if (PCIB_MAP_MSI(
892 device_get_parent(device_get_parent(dev)), dev,
893 t->irq, &addr, &data) == 0) {
894 bus_write_4(sc->mem_res,
895 HPET_TIMER_FSB_ADDR(i), addr);
896 bus_write_4(sc->mem_res,
897 HPET_TIMER_FSB_VAL(i), data);
898 }
899 }
900 #endif
901 if (t->mode == TIMER_STOPPED)
902 continue;
903 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
904 if (t->mode == TIMER_PERIODIC &&
905 (t->caps & HPET_TCAP_PER_INT) != 0) {
906 t->caps |= HPET_TCNF_TYPE;
907 t->next += t->div;
908 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
909 t->caps | HPET_TCNF_VAL_SET);
910 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
911 t->next);
912 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
913 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
914 t->div);
915 } else {
916 t->next += sc->freq / 1024;
917 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
918 t->next);
919 }
920 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
921 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
922 }
923 return (0);
924 }
925
926 /* Print some basic latency/rate information to assist in debugging. */
927 static void
hpet_test(struct hpet_softc * sc)928 hpet_test(struct hpet_softc *sc)
929 {
930 int i;
931 uint32_t u1, u2;
932 struct bintime b0, b1, b2;
933 struct timespec ts;
934
935 binuptime(&b0);
936 binuptime(&b0);
937 binuptime(&b1);
938 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
939 for (i = 1; i < 1000; i++)
940 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
941 binuptime(&b2);
942 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
943
944 bintime_sub(&b2, &b1);
945 bintime_sub(&b1, &b0);
946 bintime_sub(&b2, &b1);
947 bintime2timespec(&b2, &ts);
948
949 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
950 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
951
952 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
953 }
954
955 #ifdef DEV_APIC
956 static int
hpet_remap_intr(device_t dev,device_t child,u_int irq)957 hpet_remap_intr(device_t dev, device_t child, u_int irq)
958 {
959 struct hpet_softc *sc = device_get_softc(dev);
960 struct hpet_timer *t;
961 uint64_t addr;
962 uint32_t data;
963 int error, i;
964
965 for (i = 0; i < sc->num_timers; i++) {
966 t = &sc->t[i];
967 if (t->irq != irq)
968 continue;
969 error = PCIB_MAP_MSI(
970 device_get_parent(device_get_parent(dev)), dev,
971 irq, &addr, &data);
972 if (error)
973 return (error);
974 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
975 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
976 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
977 hpet_enable(sc);
978 return (0);
979 }
980 return (ENOENT);
981 }
982 #endif
983
984 static device_method_t hpet_methods[] = {
985 /* Device interface */
986 DEVMETHOD(device_identify, hpet_identify),
987 DEVMETHOD(device_probe, hpet_probe),
988 DEVMETHOD(device_attach, hpet_attach),
989 DEVMETHOD(device_detach, hpet_detach),
990 DEVMETHOD(device_suspend, hpet_suspend),
991 DEVMETHOD(device_resume, hpet_resume),
992
993 #ifdef DEV_APIC
994 DEVMETHOD(bus_remap_intr, hpet_remap_intr),
995 #endif
996
997 DEVMETHOD_END
998 };
999
1000 static driver_t hpet_driver = {
1001 "hpet",
1002 hpet_methods,
1003 sizeof(struct hpet_softc),
1004 };
1005
1006 DRIVER_MODULE(hpet, acpi, hpet_driver, 0, 0);
1007 MODULE_DEPEND(hpet, acpi, 1, 1, 1);
1008