1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * RME HDSPe driver for FreeBSD.
32 * Supported cards: AIO, RayDAT.
33 */
34
35 #include <sys/types.h>
36 #include <sys/sysctl.h>
37
38 #include <dev/sound/pcm/sound.h>
39 #include <dev/sound/pci/hdspe.h>
40
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43
44 #include <mixer_if.h>
45
46 static bool hdspe_unified_pcm = false;
47
48 static SYSCTL_NODE(_hw, OID_AUTO, hdspe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
49 "PCI HDSPe");
50
51 SYSCTL_BOOL(_hw_hdspe, OID_AUTO, unified_pcm, CTLFLAG_RWTUN,
52 &hdspe_unified_pcm, 0, "Combine physical ports in one unified pcm device");
53
54 static struct hdspe_clock_source hdspe_clock_source_table_rd[] = {
55 { "internal", 0 << 1 | 1, HDSPE_STATUS1_CLOCK(15), 0, 0 },
56 { "word", 0 << 1 | 0, HDSPE_STATUS1_CLOCK( 0), 1 << 24, 1 << 25 },
57 { "aes", 1 << 1 | 0, HDSPE_STATUS1_CLOCK( 1), 1 << 0, 1 << 8 },
58 { "spdif", 2 << 1 | 0, HDSPE_STATUS1_CLOCK( 2), 1 << 1, 1 << 9 },
59 { "adat1", 3 << 1 | 0, HDSPE_STATUS1_CLOCK( 3), 1 << 2, 1 << 10 },
60 { "adat2", 4 << 1 | 0, HDSPE_STATUS1_CLOCK( 4), 1 << 3, 1 << 11 },
61 { "adat3", 5 << 1 | 0, HDSPE_STATUS1_CLOCK( 5), 1 << 4, 1 << 12 },
62 { "adat4", 6 << 1 | 0, HDSPE_STATUS1_CLOCK( 6), 1 << 5, 1 << 13 },
63 { "tco", 9 << 1 | 0, HDSPE_STATUS1_CLOCK( 9), 1 << 26, 1 << 27 },
64 { "sync_in", 10 << 1 | 0, HDSPE_STATUS1_CLOCK(10), 0, 0 },
65 { NULL, 0 << 1 | 0, HDSPE_STATUS1_CLOCK( 0), 0, 0 },
66 };
67
68 static struct hdspe_clock_source hdspe_clock_source_table_aio[] = {
69 { "internal", 0 << 1 | 1, HDSPE_STATUS1_CLOCK(15), 0, 0 },
70 { "word", 0 << 1 | 0, HDSPE_STATUS1_CLOCK( 0), 1 << 24, 1 << 25 },
71 { "aes", 1 << 1 | 0, HDSPE_STATUS1_CLOCK( 1), 1 << 0, 1 << 8 },
72 { "spdif", 2 << 1 | 0, HDSPE_STATUS1_CLOCK( 2), 1 << 1, 1 << 9 },
73 { "adat", 3 << 1 | 0, HDSPE_STATUS1_CLOCK( 3), 1 << 2, 1 << 10 },
74 { "tco", 9 << 1 | 0, HDSPE_STATUS1_CLOCK( 9), 1 << 26, 1 << 27 },
75 { "sync_in", 10 << 1 | 0, HDSPE_STATUS1_CLOCK(10), 0, 0 },
76 { NULL, 0 << 1 | 0, HDSPE_STATUS1_CLOCK( 0), 0, 0 },
77 };
78
79 static struct hdspe_channel chan_map_aio[] = {
80 { HDSPE_CHAN_AIO_LINE, "line" },
81 { HDSPE_CHAN_AIO_EXT, "ext" },
82 { HDSPE_CHAN_AIO_PHONE, "phone" },
83 { HDSPE_CHAN_AIO_AES, "aes" },
84 { HDSPE_CHAN_AIO_SPDIF, "s/pdif" },
85 { HDSPE_CHAN_AIO_ADAT, "adat" },
86 { 0, NULL },
87 };
88
89 static struct hdspe_channel chan_map_aio_uni[] = {
90 { HDSPE_CHAN_AIO_ALL, "all" },
91 { 0, NULL },
92 };
93
94 static struct hdspe_channel chan_map_rd[] = {
95 { HDSPE_CHAN_RAY_AES, "aes" },
96 { HDSPE_CHAN_RAY_SPDIF, "s/pdif" },
97 { HDSPE_CHAN_RAY_ADAT1, "adat1" },
98 { HDSPE_CHAN_RAY_ADAT2, "adat2" },
99 { HDSPE_CHAN_RAY_ADAT3, "adat3" },
100 { HDSPE_CHAN_RAY_ADAT4, "adat4" },
101 { 0, NULL },
102 };
103
104 static struct hdspe_channel chan_map_rd_uni[] = {
105 { HDSPE_CHAN_RAY_ALL, "all" },
106 { 0, NULL },
107 };
108
109 static void
hdspe_intr(void * p)110 hdspe_intr(void *p)
111 {
112 struct sc_pcminfo *scp;
113 struct sc_info *sc;
114 unsigned int i;
115 int status;
116
117 sc = (struct sc_info *)p;
118
119 mtx_lock(&sc->lock);
120
121 status = hdspe_read_1(sc, HDSPE_STATUS_REG);
122 if (status & HDSPE_AUDIO_IRQ_PENDING) {
123 for (i = 0; i < HDSPE_MAX_PCMDEV; i++) {
124 scp = sc->pcms[i];
125 if (scp == NULL || sc->pcm_detaching[i] ||
126 scp->ih == NULL)
127 continue;
128 sc->pcm_refs[i]++;
129 scp->ih(scp);
130 if (--sc->pcm_refs[i] == 0 && sc->pcm_detaching[i])
131 cv_broadcast(&sc->pcm_cv);
132 }
133
134 hdspe_write_1(sc, HDSPE_INTERRUPT_ACK, 0);
135 }
136
137 mtx_unlock(&sc->lock);
138 }
139
140 static void
hdspe_dmapsetmap(void * arg,bus_dma_segment_t * segs,int nseg,int error)141 hdspe_dmapsetmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
142 {
143 #if 0
144 device_printf(sc->dev, "hdspe_dmapsetmap()\n");
145 #endif
146 }
147
148 static int
hdspe_alloc_resources(struct sc_info * sc)149 hdspe_alloc_resources(struct sc_info *sc)
150 {
151
152 /* Allocate resource. */
153 sc->csid = PCIR_BAR(0);
154 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
155 &sc->csid, RF_ACTIVE);
156
157 if (!sc->cs) {
158 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n");
159 return (ENXIO);
160 }
161
162 sc->cst = rman_get_bustag(sc->cs);
163 sc->csh = rman_get_bushandle(sc->cs);
164
165 /* Allocate interrupt resource. */
166 sc->irqid = 0;
167 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid,
168 RF_ACTIVE | RF_SHAREABLE);
169
170 if (!sc->irq ||
171 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV,
172 NULL, hdspe_intr, sc, &sc->ih)) {
173 device_printf(sc->dev, "Unable to alloc interrupt resource.\n");
174 return (ENXIO);
175 }
176
177 /* Allocate DMA resources. */
178 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev),
179 /*alignment*/4,
180 /*boundary*/0,
181 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
182 /*highaddr*/BUS_SPACE_MAXADDR,
183 /*filter*/NULL,
184 /*filterarg*/NULL,
185 /*maxsize*/2 * HDSPE_DMASEGSIZE,
186 /*nsegments*/2,
187 /*maxsegsz*/HDSPE_DMASEGSIZE,
188 /*flags*/0,
189 /*lockfunc*/NULL,
190 /*lockarg*/NULL,
191 /*dmatag*/&sc->dmat) != 0) {
192 device_printf(sc->dev, "Unable to create dma tag.\n");
193 return (ENXIO);
194 }
195
196 sc->bufsize = HDSPE_DMASEGSIZE;
197
198 /* pbuf (play buffer). */
199 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, BUS_DMA_WAITOK,
200 &sc->pmap)) {
201 device_printf(sc->dev, "Can't alloc pbuf.\n");
202 return (ENXIO);
203 }
204
205 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize,
206 hdspe_dmapsetmap, sc, BUS_DMA_NOWAIT)) {
207 device_printf(sc->dev, "Can't load pbuf.\n");
208 return (ENXIO);
209 }
210
211 /* rbuf (rec buffer). */
212 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, BUS_DMA_WAITOK,
213 &sc->rmap)) {
214 device_printf(sc->dev, "Can't alloc rbuf.\n");
215 return (ENXIO);
216 }
217
218 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize,
219 hdspe_dmapsetmap, sc, BUS_DMA_NOWAIT)) {
220 device_printf(sc->dev, "Can't load rbuf.\n");
221 return (ENXIO);
222 }
223
224 bzero(sc->pbuf, sc->bufsize);
225 bzero(sc->rbuf, sc->bufsize);
226
227 return (0);
228 }
229
230 static void
hdspe_map_dmabuf(struct sc_info * sc)231 hdspe_map_dmabuf(struct sc_info *sc)
232 {
233 uint32_t paddr, raddr;
234 int i;
235
236 paddr = vtophys(sc->pbuf);
237 raddr = vtophys(sc->rbuf);
238
239 for (i = 0; i < HDSPE_MAX_SLOTS * 16; i++) {
240 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_OUT + 4 * i,
241 paddr + i * 4096);
242 hdspe_write_4(sc, HDSPE_PAGE_ADDR_BUF_IN + 4 * i,
243 raddr + i * 4096);
244 }
245 }
246
247 static const char *
hdspe_settings_input_level(uint32_t settings)248 hdspe_settings_input_level(uint32_t settings)
249 {
250 switch (settings & HDSPE_INPUT_LEVEL_MASK) {
251 case HDSPE_INPUT_LEVEL_LOWGAIN:
252 return ("LowGain");
253 case HDSPE_INPUT_LEVEL_PLUS4DBU:
254 return ("+4dBu");
255 case HDSPE_INPUT_LEVEL_MINUS10DBV:
256 return ("-10dBV");
257 default:
258 return (NULL);
259 }
260 }
261
262 static int
hdspe_sysctl_input_level(SYSCTL_HANDLER_ARGS)263 hdspe_sysctl_input_level(SYSCTL_HANDLER_ARGS)
264 {
265 struct sc_info *sc;
266 const char *label;
267 char buf[16] = "invalid";
268 int error;
269 uint32_t settings;
270
271 sc = oidp->oid_arg1;
272
273 /* Only available on HDSPE AIO. */
274 if (sc->type != HDSPE_AIO)
275 return (ENXIO);
276
277 /* Extract current input level from settings register. */
278 settings = sc->settings_register & HDSPE_INPUT_LEVEL_MASK;
279 label = hdspe_settings_input_level(settings);
280 if (label != NULL)
281 strlcpy(buf, label, sizeof(buf));
282
283 /* Process sysctl string request. */
284 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
285 if (error != 0 || req->newptr == NULL)
286 return (error);
287
288 /* Find input level matching the sysctl string. */
289 label = hdspe_settings_input_level(HDSPE_INPUT_LEVEL_LOWGAIN);
290 if (strncasecmp(buf, label, sizeof(buf)) == 0)
291 settings = HDSPE_INPUT_LEVEL_LOWGAIN;
292 label = hdspe_settings_input_level(HDSPE_INPUT_LEVEL_PLUS4DBU);
293 if (strncasecmp(buf, label, sizeof(buf)) == 0)
294 settings = HDSPE_INPUT_LEVEL_PLUS4DBU;
295 label = hdspe_settings_input_level(HDSPE_INPUT_LEVEL_MINUS10DBV);
296 if (strncasecmp(buf, label, sizeof(buf)) == 0)
297 settings = HDSPE_INPUT_LEVEL_MINUS10DBV;
298
299 /* Set input level in settings register. */
300 settings &= HDSPE_INPUT_LEVEL_MASK;
301 if (settings != (sc->settings_register & HDSPE_INPUT_LEVEL_MASK)) {
302 mtx_lock(&sc->lock);
303 sc->settings_register &= ~HDSPE_INPUT_LEVEL_MASK;
304 sc->settings_register |= settings;
305 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register);
306 mtx_unlock(&sc->lock);
307 }
308 return (0);
309 }
310
311 static const char *
hdspe_settings_output_level(uint32_t settings)312 hdspe_settings_output_level(uint32_t settings)
313 {
314 switch (settings & HDSPE_OUTPUT_LEVEL_MASK) {
315 case HDSPE_OUTPUT_LEVEL_HIGHGAIN:
316 return ("HighGain");
317 case HDSPE_OUTPUT_LEVEL_PLUS4DBU:
318 return ("+4dBu");
319 case HDSPE_OUTPUT_LEVEL_MINUS10DBV:
320 return ("-10dBV");
321 default:
322 return (NULL);
323 }
324 }
325
326 static int
hdspe_sysctl_output_level(SYSCTL_HANDLER_ARGS)327 hdspe_sysctl_output_level(SYSCTL_HANDLER_ARGS)
328 {
329 struct sc_info *sc;
330 const char *label;
331 char buf[16] = "invalid";
332 int error;
333 uint32_t settings;
334
335 sc = oidp->oid_arg1;
336
337 /* Only available on HDSPE AIO. */
338 if (sc->type != HDSPE_AIO)
339 return (ENXIO);
340
341 /* Extract current output level from settings register. */
342 settings = sc->settings_register & HDSPE_OUTPUT_LEVEL_MASK;
343 label = hdspe_settings_output_level(settings);
344 if (label != NULL)
345 strlcpy(buf, label, sizeof(buf));
346
347 /* Process sysctl string request. */
348 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
349 if (error != 0 || req->newptr == NULL)
350 return (error);
351
352 /* Find output level matching the sysctl string. */
353 label = hdspe_settings_output_level(HDSPE_OUTPUT_LEVEL_HIGHGAIN);
354 if (strncasecmp(buf, label, sizeof(buf)) == 0)
355 settings = HDSPE_OUTPUT_LEVEL_HIGHGAIN;
356 label = hdspe_settings_output_level(HDSPE_OUTPUT_LEVEL_PLUS4DBU);
357 if (strncasecmp(buf, label, sizeof(buf)) == 0)
358 settings = HDSPE_OUTPUT_LEVEL_PLUS4DBU;
359 label = hdspe_settings_output_level(HDSPE_OUTPUT_LEVEL_MINUS10DBV);
360 if (strncasecmp(buf, label, sizeof(buf)) == 0)
361 settings = HDSPE_OUTPUT_LEVEL_MINUS10DBV;
362
363 /* Set output level in settings register. */
364 settings &= HDSPE_OUTPUT_LEVEL_MASK;
365 if (settings != (sc->settings_register & HDSPE_OUTPUT_LEVEL_MASK)) {
366 mtx_lock(&sc->lock);
367 sc->settings_register &= ~HDSPE_OUTPUT_LEVEL_MASK;
368 sc->settings_register |= settings;
369 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register);
370 mtx_unlock(&sc->lock);
371 }
372 return (0);
373 }
374
375 static const char *
hdspe_settings_phones_level(uint32_t settings)376 hdspe_settings_phones_level(uint32_t settings)
377 {
378 switch (settings & HDSPE_PHONES_LEVEL_MASK) {
379 case HDSPE_PHONES_LEVEL_HIGHGAIN:
380 return ("HighGain");
381 case HDSPE_PHONES_LEVEL_PLUS4DBU:
382 return ("+4dBu");
383 case HDSPE_PHONES_LEVEL_MINUS10DBV:
384 return ("-10dBV");
385 default:
386 return (NULL);
387 }
388 }
389
390 static int
hdspe_sysctl_phones_level(SYSCTL_HANDLER_ARGS)391 hdspe_sysctl_phones_level(SYSCTL_HANDLER_ARGS)
392 {
393 struct sc_info *sc;
394 const char *label;
395 char buf[16] = "invalid";
396 int error;
397 uint32_t settings;
398
399 sc = oidp->oid_arg1;
400
401 /* Only available on HDSPE AIO. */
402 if (sc->type != HDSPE_AIO)
403 return (ENXIO);
404
405 /* Extract current phones level from settings register. */
406 settings = sc->settings_register & HDSPE_PHONES_LEVEL_MASK;
407 label = hdspe_settings_phones_level(settings);
408 if (label != NULL)
409 strlcpy(buf, label, sizeof(buf));
410
411 /* Process sysctl string request. */
412 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
413 if (error != 0 || req->newptr == NULL)
414 return (error);
415
416 /* Find phones level matching the sysctl string. */
417 label = hdspe_settings_phones_level(HDSPE_PHONES_LEVEL_HIGHGAIN);
418 if (strncasecmp(buf, label, sizeof(buf)) == 0)
419 settings = HDSPE_PHONES_LEVEL_HIGHGAIN;
420 label = hdspe_settings_phones_level(HDSPE_PHONES_LEVEL_PLUS4DBU);
421 if (strncasecmp(buf, label, sizeof(buf)) == 0)
422 settings = HDSPE_PHONES_LEVEL_PLUS4DBU;
423 label = hdspe_settings_phones_level(HDSPE_PHONES_LEVEL_MINUS10DBV);
424 if (strncasecmp(buf, label, sizeof(buf)) == 0)
425 settings = HDSPE_PHONES_LEVEL_MINUS10DBV;
426
427 /* Set phones level in settings register. */
428 settings &= HDSPE_PHONES_LEVEL_MASK;
429 if (settings != (sc->settings_register & HDSPE_PHONES_LEVEL_MASK)) {
430 mtx_lock(&sc->lock);
431 sc->settings_register &= ~HDSPE_PHONES_LEVEL_MASK;
432 sc->settings_register |= settings;
433 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register);
434 mtx_unlock(&sc->lock);
435 }
436 return (0);
437 }
438
439 static int
hdspe_sysctl_sample_rate(SYSCTL_HANDLER_ARGS)440 hdspe_sysctl_sample_rate(SYSCTL_HANDLER_ARGS)
441 {
442 struct sc_info *sc = oidp->oid_arg1;
443 int error;
444 unsigned int speed, multiplier;
445
446 speed = sc->force_speed;
447
448 /* Process sysctl (unsigned) integer request. */
449 error = sysctl_handle_int(oidp, &speed, 0, req);
450 if (error != 0 || req->newptr == NULL)
451 return (error);
452
453 /* Speed from 32000 to 192000, 0 falls back to pcm speed setting. */
454 sc->force_speed = 0;
455 if (speed > 0) {
456 multiplier = 1;
457 if (speed > (96000 + 128000) / 2)
458 multiplier = 4;
459 else if (speed > (48000 + 64000) / 2)
460 multiplier = 2;
461
462 if (speed < ((32000 + 44100) / 2) * multiplier)
463 sc->force_speed = 32000 * multiplier;
464 else if (speed < ((44100 + 48000) / 2) * multiplier)
465 sc->force_speed = 44100 * multiplier;
466 else
467 sc->force_speed = 48000 * multiplier;
468 }
469
470 return (0);
471 }
472
473
474 static int
hdspe_sysctl_period(SYSCTL_HANDLER_ARGS)475 hdspe_sysctl_period(SYSCTL_HANDLER_ARGS)
476 {
477 struct sc_info *sc = oidp->oid_arg1;
478 int error;
479 unsigned int period;
480
481 period = sc->force_period;
482
483 /* Process sysctl (unsigned) integer request. */
484 error = sysctl_handle_int(oidp, &period, 0, req);
485 if (error != 0 || req->newptr == NULL)
486 return (error);
487
488 /* Period is from 2^5 to 2^14, 0 falls back to pcm latency settings. */
489 sc->force_period = 0;
490 if (period > 0) {
491 sc->force_period = 32;
492 while (sc->force_period < period && sc->force_period < 4096)
493 sc->force_period <<= 1;
494 }
495
496 return (0);
497 }
498
499 static int
hdspe_sysctl_clock_preference(SYSCTL_HANDLER_ARGS)500 hdspe_sysctl_clock_preference(SYSCTL_HANDLER_ARGS)
501 {
502 struct sc_info *sc;
503 struct hdspe_clock_source *clock_table, *clock;
504 char buf[16] = "invalid";
505 int error;
506 uint32_t setting;
507
508 sc = oidp->oid_arg1;
509
510 /* Select sync ports table for device type. */
511 if (sc->type == HDSPE_AIO)
512 clock_table = hdspe_clock_source_table_aio;
513 else if (sc->type == HDSPE_RAYDAT)
514 clock_table = hdspe_clock_source_table_rd;
515 else
516 return (ENXIO);
517
518 /* Extract preferred clock source from settings register. */
519 setting = sc->settings_register & HDSPE_SETTING_CLOCK_MASK;
520 for (clock = clock_table; clock->name != NULL; ++clock) {
521 if (clock->setting == setting)
522 break;
523 }
524 if (clock->name != NULL)
525 strlcpy(buf, clock->name, sizeof(buf));
526
527 /* Process sysctl string request. */
528 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
529 if (error != 0 || req->newptr == NULL)
530 return (error);
531
532 /* Find clock source matching the sysctl string. */
533 for (clock = clock_table; clock->name != NULL; ++clock) {
534 if (strncasecmp(buf, clock->name, sizeof(buf)) == 0)
535 break;
536 }
537
538 /* Set preferred clock source in settings register. */
539 if (clock->name != NULL) {
540 setting = clock->setting & HDSPE_SETTING_CLOCK_MASK;
541 mtx_lock(&sc->lock);
542 sc->settings_register &= ~HDSPE_SETTING_CLOCK_MASK;
543 sc->settings_register |= setting;
544 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register);
545 mtx_unlock(&sc->lock);
546 }
547 return (0);
548 }
549
550 static int
hdspe_sysctl_clock_source(SYSCTL_HANDLER_ARGS)551 hdspe_sysctl_clock_source(SYSCTL_HANDLER_ARGS)
552 {
553 struct sc_info *sc;
554 struct hdspe_clock_source *clock_table, *clock;
555 char buf[16] = "invalid";
556 uint32_t status;
557
558 sc = oidp->oid_arg1;
559
560 /* Select sync ports table for device type. */
561 if (sc->type == HDSPE_AIO)
562 clock_table = hdspe_clock_source_table_aio;
563 else if (sc->type == HDSPE_RAYDAT)
564 clock_table = hdspe_clock_source_table_rd;
565 else
566 return (ENXIO);
567
568 /* Read current (autosync) clock source from status register. */
569 mtx_lock(&sc->lock);
570 status = hdspe_read_4(sc, HDSPE_STATUS1_REG);
571 status &= HDSPE_STATUS1_CLOCK_MASK;
572 mtx_unlock(&sc->lock);
573
574 /* Translate status register value to clock source. */
575 for (clock = clock_table; clock->name != NULL; ++clock) {
576 /* In clock master mode, override with internal clock source. */
577 if (sc->settings_register & HDSPE_SETTING_MASTER) {
578 if (clock->setting & HDSPE_SETTING_MASTER)
579 break;
580 } else if (clock->status == status)
581 break;
582 }
583
584 /* Process sysctl string request. */
585 if (clock->name != NULL)
586 strlcpy(buf, clock->name, sizeof(buf));
587 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
588 }
589
590 static int
hdspe_sysctl_clock_list(SYSCTL_HANDLER_ARGS)591 hdspe_sysctl_clock_list(SYSCTL_HANDLER_ARGS)
592 {
593 struct sc_info *sc;
594 struct hdspe_clock_source *clock_table, *clock;
595 char buf[256];
596 int n;
597
598 sc = oidp->oid_arg1;
599 n = 0;
600
601 /* Select clock source table for device type. */
602 if (sc->type == HDSPE_AIO)
603 clock_table = hdspe_clock_source_table_aio;
604 else if (sc->type == HDSPE_RAYDAT)
605 clock_table = hdspe_clock_source_table_rd;
606 else
607 return (ENXIO);
608
609 /* List available clock sources. */
610 buf[0] = 0;
611 for (clock = clock_table; clock->name != NULL; ++clock) {
612 if (n > 0)
613 n += strlcpy(buf + n, ",", sizeof(buf) - n);
614 n += strlcpy(buf + n, clock->name, sizeof(buf) - n);
615 }
616 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
617 }
618
619 static int
hdspe_sysctl_sync_status(SYSCTL_HANDLER_ARGS)620 hdspe_sysctl_sync_status(SYSCTL_HANDLER_ARGS)
621 {
622 struct sc_info *sc;
623 struct hdspe_clock_source *clock_table, *clock;
624 char buf[256];
625 char *state;
626 int n;
627 uint32_t status;
628
629 sc = oidp->oid_arg1;
630 n = 0;
631
632 /* Select sync ports table for device type. */
633 if (sc->type == HDSPE_AIO)
634 clock_table = hdspe_clock_source_table_aio;
635 else if (sc->type == HDSPE_RAYDAT)
636 clock_table = hdspe_clock_source_table_rd;
637 else
638 return (ENXIO);
639
640 /* Read current lock and sync bits from status register. */
641 mtx_lock(&sc->lock);
642 status = hdspe_read_4(sc, HDSPE_STATUS1_REG);
643 mtx_unlock(&sc->lock);
644
645 /* List clock sources with lock and sync state. */
646 for (clock = clock_table; clock->name != NULL; ++clock) {
647 if (clock->sync_bit != 0) {
648 if (n > 0)
649 n += strlcpy(buf + n, ",", sizeof(buf) - n);
650 state = "none";
651 if ((clock->sync_bit & status) != 0)
652 state = "sync";
653 else if ((clock->lock_bit & status) != 0)
654 state = "lock";
655 n += snprintf(buf + n, sizeof(buf) - n, "%s(%s)",
656 clock->name, state);
657 }
658 }
659 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
660 }
661
662 static int
hdspe_probe(device_t dev)663 hdspe_probe(device_t dev)
664 {
665 uint32_t rev;
666
667 if ((pci_get_vendor(dev) == PCI_VENDOR_XILINX ||
668 pci_get_vendor(dev) == PCI_VENDOR_RME) &&
669 pci_get_device(dev) == PCI_DEVICE_XILINX_HDSPE) {
670 rev = pci_get_revid(dev);
671 switch (rev) {
672 case PCI_REVISION_AIO:
673 device_set_desc(dev, "RME HDSPe AIO");
674 return (0);
675 case PCI_REVISION_RAYDAT:
676 device_set_desc(dev, "RME HDSPe RayDAT");
677 return (0);
678 }
679 }
680
681 return (ENXIO);
682 }
683
684 static int
hdspe_init(struct sc_info * sc)685 hdspe_init(struct sc_info *sc)
686 {
687 long long period;
688
689 /* Set latency. */
690 sc->period = 32;
691 /*
692 * The pcm channel latency settings propagate unreliable blocksizes,
693 * different for recording and playback, and skewed due to rounding
694 * and total buffer size limits.
695 * Force period to a consistent default until these issues are fixed.
696 */
697 sc->force_period = 256;
698 sc->ctrl_register = hdspe_encode_latency(7);
699
700 /* Set rate. */
701 sc->speed = HDSPE_SPEED_DEFAULT;
702 sc->force_speed = 0;
703 sc->ctrl_register &= ~HDSPE_FREQ_MASK;
704 sc->ctrl_register |= HDSPE_FREQ_MASK_DEFAULT;
705 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register);
706
707 switch (sc->type) {
708 case HDSPE_RAYDAT:
709 case HDSPE_AIO:
710 period = HDSPE_FREQ_AIO;
711 break;
712 default:
713 return (ENXIO);
714 }
715
716 /* Set DDS value. */
717 period /= sc->speed;
718 hdspe_write_4(sc, HDSPE_FREQ_REG, period);
719
720 /* Other settings. */
721 sc->settings_register = 0;
722
723 /* Default gain levels. */
724 sc->settings_register &= ~HDSPE_INPUT_LEVEL_MASK;
725 sc->settings_register |= HDSPE_INPUT_LEVEL_LOWGAIN;
726 sc->settings_register &= ~HDSPE_OUTPUT_LEVEL_MASK;
727 sc->settings_register |= HDSPE_OUTPUT_LEVEL_MINUS10DBV;
728 sc->settings_register &= ~HDSPE_PHONES_LEVEL_MASK;
729 sc->settings_register |= HDSPE_PHONES_LEVEL_MINUS10DBV;
730
731 hdspe_write_4(sc, HDSPE_SETTINGS_REG, sc->settings_register);
732
733 return (0);
734 }
735
736 static int
hdspe_attach(device_t dev)737 hdspe_attach(device_t dev)
738 {
739 struct hdspe_channel *chan_map;
740 struct sc_pcminfo *scp;
741 struct sc_info *sc;
742 uint32_t rev;
743 int i, err;
744
745 #if 0
746 device_printf(dev, "hdspe_attach()\n");
747 #endif
748
749 sc = device_get_softc(dev);
750 mtx_init(&sc->lock, device_get_nameunit(dev), "snd_hdspe softc",
751 MTX_DEF);
752 sc->dev = dev;
753
754 pci_enable_busmaster(dev);
755 rev = pci_get_revid(dev);
756 switch (rev) {
757 case PCI_REVISION_AIO:
758 sc->type = HDSPE_AIO;
759 chan_map = hdspe_unified_pcm ? chan_map_aio_uni : chan_map_aio;
760 break;
761 case PCI_REVISION_RAYDAT:
762 sc->type = HDSPE_RAYDAT;
763 chan_map = hdspe_unified_pcm ? chan_map_rd_uni : chan_map_rd;
764 break;
765 default:
766 return (ENXIO);
767 }
768
769 /* Allocate resources. */
770 err = hdspe_alloc_resources(sc);
771 if (err) {
772 device_printf(dev, "Unable to allocate system resources.\n");
773 return (ENXIO);
774 }
775
776 if (hdspe_init(sc) != 0)
777 return (ENXIO);
778
779 for (i = 0; i < HDSPE_MAX_CHANS && chan_map[i].descr != NULL; i++) {
780 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_WAITOK | M_ZERO);
781 scp->hc = &chan_map[i];
782 scp->sc = sc;
783 scp->dev = device_add_child(dev, "pcm", DEVICE_UNIT_ANY);
784 device_set_ivars(scp->dev, scp);
785 }
786
787 hdspe_map_dmabuf(sc);
788
789 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
790 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
791 "sync_status", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
792 sc, 0, hdspe_sysctl_sync_status, "A",
793 "List clock source signal lock and sync status");
794
795 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
796 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
797 "clock_source", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
798 sc, 0, hdspe_sysctl_clock_source, "A",
799 "Currently effective clock source");
800
801 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
802 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
803 "clock_preference", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
804 sc, 0, hdspe_sysctl_clock_preference, "A",
805 "Set 'internal' (master) or preferred autosync clock source");
806
807 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
808 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
809 "clock_list", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
810 sc, 0, hdspe_sysctl_clock_list, "A",
811 "List of supported clock sources");
812
813 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
814 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
815 "period", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE,
816 sc, 0, hdspe_sysctl_period, "A",
817 "Force period of samples per interrupt (32, 64, ... 4096)");
818
819 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
820 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
821 "sample_rate", CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE,
822 sc, 0, hdspe_sysctl_sample_rate, "A",
823 "Force sample rate (32000, 44100, 48000, ... 192000)");
824
825 if (sc->type == HDSPE_AIO) {
826 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
827 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
828 "phones_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
829 sc, 0, hdspe_sysctl_phones_level, "A",
830 "Phones output level ('HighGain', '+4dBU', '-10dBV')");
831
832 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
833 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
834 "output_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
835 sc, 0, hdspe_sysctl_output_level, "A",
836 "Analog output level ('HighGain', '+4dBU', '-10dBV')");
837
838 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
839 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
840 "input_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
841 sc, 0, hdspe_sysctl_input_level, "A",
842 "Analog input level ('LowGain', '+4dBU', '-10dBV')");
843 }
844
845 cv_init(&sc->pcm_cv, "snd_hdspe pcm");
846 bus_attach_children(dev);
847 return (0);
848 }
849
850 static void
hdspe_child_deleted(device_t dev,device_t child)851 hdspe_child_deleted(device_t dev, device_t child)
852 {
853 free(device_get_ivars(child), M_DEVBUF);
854 }
855
856 static void
hdspe_dmafree(struct sc_info * sc)857 hdspe_dmafree(struct sc_info *sc)
858 {
859
860 bus_dmamap_unload(sc->dmat, sc->rmap);
861 bus_dmamap_unload(sc->dmat, sc->pmap);
862 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap);
863 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap);
864 sc->rbuf = sc->pbuf = NULL;
865 }
866
867 static int
hdspe_detach(device_t dev)868 hdspe_detach(device_t dev)
869 {
870 struct sc_info *sc;
871 int err;
872
873 sc = device_get_softc(dev);
874 if (sc == NULL) {
875 device_printf(dev,"Can't detach: softc is null.\n");
876 return (0);
877 }
878
879 err = bus_generic_detach(dev);
880 if (err)
881 return (err);
882
883 hdspe_dmafree(sc);
884
885 if (sc->ih)
886 bus_teardown_intr(dev, sc->irq, sc->ih);
887 if (sc->dmat)
888 bus_dma_tag_destroy(sc->dmat);
889 if (sc->irq)
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
891 if (sc->cs)
892 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs);
893 cv_destroy(&sc->pcm_cv);
894 mtx_destroy(&sc->lock);
895
896 return (0);
897 }
898
899 static device_method_t hdspe_methods[] = {
900 DEVMETHOD(device_probe, hdspe_probe),
901 DEVMETHOD(device_attach, hdspe_attach),
902 DEVMETHOD(device_detach, hdspe_detach),
903 DEVMETHOD(bus_child_deleted, hdspe_child_deleted),
904 DEVMETHOD_END
905 };
906
907 static driver_t hdspe_driver = {
908 "hdspe",
909 hdspe_methods,
910 sizeof(struct sc_info),
911 };
912
913 DRIVER_MODULE(snd_hdspe, pci, hdspe_driver, 0, 0);
914