1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 31 #ifndef _EM_H_DEFINED_ 32 #define _EM_H_DEFINED_ 33 34 #include "opt_ddb.h" 35 #include "opt_inet.h" 36 #include "opt_inet6.h" 37 #include "opt_rss.h" 38 39 #ifdef HAVE_KERNEL_OPTION_HEADERS 40 #include "opt_device_polling.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #ifdef DDB 46 #include <sys/types.h> 47 #include <ddb/ddb.h> 48 #endif 49 #include <sys/buf_ring.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 #include <sys/endian.h> 53 #include <sys/kernel.h> 54 #include <sys/kthread.h> 55 #include <sys/malloc.h> 56 #include <sys/mbuf.h> 57 #include <sys/module.h> 58 #include <sys/rman.h> 59 #include <sys/smp.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/sysctl.h> 63 #include <sys/taskqueue.h> 64 #include <sys/eventhandler.h> 65 #include <machine/bus.h> 66 #include <machine/resource.h> 67 68 #include <net/bpf.h> 69 #include <net/ethernet.h> 70 #include <net/if.h> 71 #include <net/if_var.h> 72 #include <net/if_arp.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/iflib.h> 76 #include <net/rss_config.h> 77 #include <netinet/in_rss.h> 78 79 #include <net/if_types.h> 80 #include <net/if_vlan_var.h> 81 82 #include <netinet/in_systm.h> 83 #include <netinet/in.h> 84 #include <netinet/if_ether.h> 85 #include <netinet/ip.h> 86 #include <netinet/ip6.h> 87 #include <netinet/tcp.h> 88 #include <netinet/udp.h> 89 90 #include <machine/in_cksum.h> 91 #include <dev/led/led.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 95 #include "e1000_api.h" 96 #include "e1000_82571.h" 97 #include "ifdi_if.h" 98 99 struct igb_vf; 100 struct igb_vf_mac_filter; 101 102 /* Tunables */ 103 104 /* 105 * EM_MAX_TXD: Maximum number of Transmit Descriptors 106 * Valid Range: 80-256 for 82542 and 82543-based adapters 107 * 80-4096 for others 108 * Default Value: 1024 109 * This value is the number of transmit descriptors allocated by the driver. 110 * Increasing this value allows the driver to queue more transmits. Each 111 * descriptor is 16 bytes. 112 * Since TDLEN should be multiple of 128bytes, the number of transmit 113 * desscriptors should meet the following condition. 114 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 115 */ 116 #define EM_MIN_TXD 128 117 #define EM_MAX_TXD 4096 118 #define EM_DEFAULT_TXD 1024 119 #define EM_DEFAULT_MULTI_TXD 4096 120 #define IGB_MAX_TXD 4096 121 122 /* 123 * EM_MAX_RXD - Maximum number of receive Descriptors 124 * Valid Range: 80-256 for 82542 and 82543-based adapters 125 * 80-4096 for others 126 * Default Value: 1024 127 * This value is the number of receive descriptors allocated by the driver. 128 * Increasing this value allows the driver to buffer more incoming packets. 129 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 130 * descriptor. The maximum MTU size is 16110. 131 * Since TDLEN should be multiple of 128bytes, the number of transmit 132 * desscriptors should meet the following condition. 133 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 134 */ 135 #define EM_MIN_RXD 128 136 #define EM_MAX_RXD 4096 137 #define EM_DEFAULT_RXD 1024 138 #define EM_DEFAULT_MULTI_RXD 4096 139 #define IGB_MAX_RXD 4096 140 #define IGB_MAX_FRAME_SIZE 9234 141 142 /* 143 * EM_TIDV - Transmit Interrupt Delay Value 144 * Valid Range: 0-65535 (0=off) 145 * Default Value: 64 146 * This value delays the generation of transmit interrupts in units of 147 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 148 * efficiency if properly tuned for specific network traffic. If the 149 * system is reporting dropped transmits, this value may be set too high 150 * causing the driver to run out of available transmit descriptors. 151 */ 152 #define EM_TIDV 64 153 154 /* 155 * EM_TADV - Transmit Absolute Interrupt Delay Value 156 * (Not valid for 82542/82543/82544) 157 * Valid Range: 0-65535 (0=off) 158 * Default Value: 64 159 * This value, in units of 1.024 microseconds, limits the delay in which a 160 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 161 * this value ensures that an interrupt is generated after the initial 162 * packet is sent on the wire within the set amount of time. Proper tuning, 163 * along with EM_TIDV, may improve traffic throughput in specific 164 * network conditions. 165 */ 166 #define EM_TADV 64 167 168 /* 169 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 170 * Valid Range: 0-65535 (0=off) 171 * Default Value: 0 172 * This value delays the generation of receive interrupts in units of 1.024 173 * microseconds. Receive interrupt reduction can improve CPU efficiency if 174 * properly tuned for specific network traffic. Increasing this value adds 175 * extra latency to frame reception and can end up decreasing the throughput 176 * of TCP traffic. If the system is reporting dropped receives, this value 177 * may be set too high, causing the driver to run out of available receive 178 * descriptors. 179 * 180 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 181 * may hang (stop transmitting) under certain network conditions. 182 * If this occurs a WATCHDOG message is logged in the system 183 * event log. In addition, the controller is automatically reset, 184 * restoring the network connection. To eliminate the potential 185 * for the hang ensure that EM_RDTR is set to 0. 186 */ 187 #define EM_RDTR 0 188 189 /* 190 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 191 * Valid Range: 0-65535 (0=off) 192 * Default Value: 64 193 * This value, in units of 1.024 microseconds, limits the delay in which a 194 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 195 * this value ensures that an interrupt is generated after the initial 196 * packet is received within the set amount of time. Proper tuning, 197 * along with EM_RDTR, may improve traffic throughput in specific network 198 * conditions. 199 */ 200 #define EM_RADV 64 201 202 /* 203 * This parameter controls whether or not autonegotiation is enabled. 204 * 0 - Disable autonegotiation 205 * 1 - Enable autonegotiation 206 */ 207 #define DO_AUTO_NEG 1 208 209 /* 210 * This parameter control whether or not the driver will wait for 211 * autonegotiation to complete. 212 * 1 - Wait for autonegotiation to complete 213 * 0 - Don't wait for autonegotiation to complete 214 */ 215 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 216 217 /* Tunables -- End */ 218 219 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 220 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 221 ADVERTISE_1000_FULL) 222 223 #define AUTO_ALL_MODES 0 224 225 /* PHY master/slave setting */ 226 #define EM_MASTER_SLAVE e1000_ms_hw_default 227 228 /* 229 * Miscellaneous constants 230 */ 231 #define EM_VENDOR_ID 0x8086 232 #define EM_FLASH 0x0014 233 #define EM_SUBVENDOR_DELL 0x1028 234 #define EM_SUBVENDOR_HP 0x103c 235 #define EM_I350_SUBDEVICE_WOL_1 0x1f52 236 #define EM_I350_SUBDEVICE_WOL_2 0x5001 237 #define EM_I350_SUBDEVICE_WOL_3 0x5002 238 239 #define EM_JUMBO_PBA 0x00000028 240 #define EM_DEFAULT_PBA 0x00000030 241 #define EM_SMARTSPEED_DOWNSHIFT 3 242 #define EM_SMARTSPEED_MAX 15 243 #define EM_MAX_LOOP 10 244 245 #define MAX_NUM_MULTICAST_ADDRESSES 128 246 #define PCI_ANY_ID (~0U) 247 #define ETHER_ALIGN 2 248 #define EM_FC_PAUSE_TIME 0x0680 249 #define EM_EEPROM_APME_HIGH 0x0400 250 #define EM_EEPROM_APME_LOW 0x0004 251 252 /* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 253 #define IGB_MEDIA_RESET (1 << 0) 254 255 /* Define the interrupt rates and ITR helpers */ 256 #define EM_INTS_4K 4000 257 #define EM_INTS_20K 20000 258 #define EM_INTS_70K 70000 259 #define EM_INTS_DEFAULT 8000 260 #define EM_INTS_MULTIPLIER 256 261 #define EM_ITR_DIVIDEND 1000000000 262 #define EM_INTS_TO_ITR(i) (EM_ITR_DIVIDEND/(i * EM_INTS_MULTIPLIER)) 263 #define IGB_EITR_DIVIDEND 1000000 264 #define IGB_EITR_SHIFT 2 265 #define IGB_QVECTOR_MASK 0x7FFC 266 #define IGB_INTS_TO_EITR(i) \ 267 (((IGB_EITR_DIVIDEND / (i)) << IGB_EITR_SHIFT) & IGB_QVECTOR_MASK) 268 #define IGB_EITR_TO_INTS(i) ((IGB_EITR_DIVIDEND << IGB_EITR_SHIFT) / \ 269 ((i) & IGB_QVECTOR_MASK)) 270 271 /* 272 * The average packet size calculation in em_ring_itr() yields an EITR 273 * interval field value. That field is quarter microsecond granular (see 274 * IGB_EITR_SHIFT), so an interval of V is 1000000 / (V / 4) interrupts per 275 * second. 276 */ 277 #define EM_AIM_DIVIDEND (IGB_EITR_DIVIDEND << IGB_EITR_SHIFT) 278 279 #define IGB_LINK_ITR 2000 280 #define I210_LINK_DELAY 1000 281 282 #define IGB_TXPBSIZE 20408 283 #define IGB_HDR_BUF 128 284 #define IGB_PKTTYPE_MASK 0x0000FFF0 285 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 286 287 /* 288 * Driver state logic for the detection of a hung state 289 * in hardware. Set TX_HUNG whenever a TX packet is used 290 * (data is sent) and clear it when txeof() is invoked if 291 * any descriptors from the ring are cleaned/reclaimed. 292 * Increment internal counter if no descriptors are cleaned 293 * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 294 * reset adapter. 295 */ 296 #define EM_TX_IDLE 0x00000000 297 #define EM_TX_BUSY 0x00000001 298 #define EM_TX_HUNG 0x80000000 299 #define EM_TX_MAXTRIES 10 300 301 #define PCICFG_DESC_RING_STATUS 0xe4 302 #define FLUSH_DESC_REQUIRED 0x100 303 304 #define EM_TX_PTHRESH 31 305 #define EM_TX_HTHRESH 1 306 #define EM_TX_WTHRESH 1 307 308 #define EM_RXDCTL_PTHRESH_MASK 0x0000003F 309 #define EM_RXDCTL_HTHRESH_MASK 0x00003F00 310 #define EM_RXDCTL_WTHRESH_MASK 0x003F0000 311 #define EM_RXDCTL_THRESH_MASK (EM_RXDCTL_PTHRESH_MASK | \ 312 EM_RXDCTL_HTHRESH_MASK | \ 313 EM_RXDCTL_WTHRESH_MASK) 314 315 #define EM_JUMBO_RX_PTHRESH 3 316 #define EM_JUMBO_RX_HTHRESH 1 317 #define EM_82574_RX_PTHRESH 32 318 #define EM_82574_RX_HTHRESH 4 319 #define EM_82574_RX_WTHRESH 4 320 321 #define IGB_RXDCTL_PTHRESH_MASK 0x0000001F 322 #define IGB_RXDCTL_HTHRESH_MASK 0x00001F00 323 #define IGB_RXDCTL_WTHRESH_MASK 0x001F0000 324 #define IGB_RXDCTL_THRESH_MASK (IGB_RXDCTL_PTHRESH_MASK | \ 325 IGB_RXDCTL_HTHRESH_MASK | \ 326 IGB_RXDCTL_WTHRESH_MASK) 327 #define IGB_82575_RXDCTL_THRESH_MASK 0x003F3F3F 328 329 #define IGB_RX_PTHRESH 8 330 #define I354_RX_PTHRESH 12 331 #define IGB_RX_HTHRESH 8 332 #define IGB_RX_WTHRESH 4 333 #define IGB_82576_RX_WTHRESH 1 334 335 #define IGB_TX_PTHRESH 8 336 #define I354_TX_PTHRESH 20 337 #define IGB_TX_HTHRESH 1 338 339 /* 340 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 341 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 342 * also optimize cache line size effect. H/W supports up to cache line size 128. 343 */ 344 #define EM_DBA_ALIGN 128 345 346 /* 347 * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 348 */ 349 #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 350 #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 351 #define TARC_MQ_FIX (1 << 23) | \ 352 (1 << 24) | \ 353 (1 << 25) /* Handle errata in MQ mode */ 354 #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 355 356 /* PCI Config defines */ 357 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 358 #define EM_BAR_TYPE_MASK 0x00000001 359 #define EM_BAR_TYPE_MMEM 0x00000000 360 #define EM_BAR_TYPE_IO 0x00000001 361 #define EM_BAR_TYPE_FLASH 0x0014 362 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 363 #define EM_BAR_MEM_TYPE_MASK 0x00000006 364 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 365 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 366 367 /* Defines for printing debug information */ 368 #define DEBUG_INIT 0 369 #define DEBUG_IOCTL 0 370 #define DEBUG_HW 0 371 372 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 373 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 374 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 375 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 376 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 377 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 378 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 379 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 380 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 381 382 #define EM_MAX_SCATTER 40 383 #define EM_VFTA_SIZE 128 384 #define EM_TSO_SIZE 65535 385 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 386 #define ETH_ZLEN 60 387 388 /* Offload bits in mbuf flag */ 389 #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 390 CSUM_IP6_UDP | CSUM_IP6_TCP) 391 #define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 392 CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 393 CSUM_IP6_SCTP) 394 395 #define IGB_PKTTYPE_MASK 0x0000FFF0 396 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 397 398 /* 399 * 82574 has a nonstandard address for EIAC 400 * and since its only used in MSI-X, and in 401 * the em driver only 82574 uses MSI-X we can 402 * solve it just using this define. 403 */ 404 #define EM_EIAC 0x000DC 405 /* 406 * 82574 only reports 3 MSI-X vectors by default; 407 * defines assisting with making it report 5 are 408 * located here. 409 */ 410 #define EM_NVM_PCIE_CTRL 0x1B 411 #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 412 #define EM_NVM_MSIX_N_SHIFT 7 413 414 /* 415 * VFs use 32-bit counter that rolls over. 416 */ 417 #define UPDATE_VF_REG(reg, last, cur) \ 418 do { \ 419 u32 new = E1000_READ_REG(&sc->hw, reg); \ 420 cur += (u32)(new - last); \ 421 last = new; \ 422 } while (0) 423 424 struct e1000_softc; 425 426 struct em_int_delay_info { 427 struct e1000_softc *sc; /* Back-pointer to the sc struct */ 428 int offset; /* Register offset to read/write */ 429 int value; /* Current value in usecs */ 430 }; 431 432 /* 433 * The transmit ring, one per tx queue 434 */ 435 struct tx_ring { 436 struct e1000_softc *sc; 437 struct e1000_tx_desc *tx_base; 438 uint64_t tx_paddr; 439 qidx_t *tx_rsq; 440 bool tx_tso; /* last tx was tso */ 441 uint8_t me; 442 qidx_t tx_rs_cidx; 443 qidx_t tx_rs_pidx; 444 qidx_t tx_cidx_processed; 445 /* Interrupt resources */ 446 void *tag; 447 struct resource *res; 448 449 /* Soft stats */ 450 unsigned long tx_irq; 451 452 /* 453 * Free running AIM counters. The producer updates these while 454 * encapsulating packets, then publishes both together at the TX 455 * doorbell. The interrupt handler samples only the published value, 456 * so it cannot observe one counter without the other. 457 */ 458 u32 tx_packets; 459 u32 tx_bytes; 460 uint64_t tx_aim_snapshot __aligned(8); 461 u32 tx_packets_last; 462 u32 tx_bytes_last; 463 464 /* Saved csum offloading context information */ 465 int csum_flags; 466 int csum_lhlen; 467 int csum_iphlen; 468 469 int csum_thlen; 470 int csum_mss; 471 int csum_pktlen; 472 473 uint32_t csum_txd_upper; 474 uint32_t csum_txd_lower; /* last field */ 475 }; 476 477 static __inline void 478 em_aim_publish(struct tx_ring *txr) 479 { 480 uint64_t snapshot; 481 482 snapshot = ((uint64_t)txr->tx_bytes << 32) | txr->tx_packets; 483 atomic_store_rel_64(&txr->tx_aim_snapshot, snapshot); 484 } 485 486 /* 487 * The Receive ring, one per rx queue 488 */ 489 struct rx_ring { 490 struct e1000_softc *sc; 491 struct em_rx_queue *que; 492 u32 me; 493 u32 payload; 494 union e1000_rx_desc_extended *rx_base; 495 uint64_t rx_paddr; 496 497 /* Interrupt resources */ 498 void *tag; 499 struct resource *res; 500 bool discard; 501 502 /* Soft stats */ 503 unsigned long rx_irq; 504 unsigned long rx_discarded; 505 506 /* 507 * Free running AIM counters. RX publishes both together when iflib 508 * returns descriptors to hardware. The interrupt handler samples only 509 * the published value, so watchdog-driven RX processing cannot expose 510 * one counter without the other. 511 */ 512 u32 rx_packets; 513 u32 rx_bytes; 514 uint64_t rx_aim_snapshot __aligned(8); 515 u32 rx_packets_last; 516 u32 rx_bytes_last; 517 }; 518 519 static __inline void 520 em_aim_publish_rx(struct rx_ring *rxr) 521 { 522 uint64_t snapshot; 523 524 snapshot = ((uint64_t)rxr->rx_bytes << 32) | rxr->rx_packets; 525 atomic_store_rel_64(&rxr->rx_aim_snapshot, snapshot); 526 } 527 528 struct em_tx_queue { 529 struct e1000_softc *sc; 530 u32 msix; 531 u32 eims; /* This queue's EIMS bit */ 532 u32 me; 533 struct tx_ring txr; 534 }; 535 536 struct em_rx_queue { 537 struct e1000_softc *sc; 538 u32 me; 539 u32 msix; 540 u32 eims; 541 u32 itr_setting; 542 struct rx_ring rxr; 543 u64 irqs; 544 struct if_irq que_irq; 545 }; 546 547 /* Driver-observed link state and its publication barrier. */ 548 enum em_link_state { 549 EM_LINK_STATE_DOWN = 0, 550 EM_LINK_STATE_DOWN_RESET_PENDING, 551 EM_LINK_STATE_UP, 552 EM_LINK_STATE_UP_RESET_PENDING, 553 }; 554 555 /* Our softc structure */ 556 struct e1000_softc { 557 struct e1000_hw hw; 558 559 if_softc_ctx_t shared; 560 if_ctx_t ctx; 561 #define tx_num_queues shared->isc_ntxqsets 562 #define rx_num_queues shared->isc_nrxqsets 563 #define intr_type shared->isc_intr 564 /* FreeBSD operating-system-specific structures. */ 565 struct e1000_osdep osdep; 566 device_t dev; 567 struct cdev *led_dev; 568 569 struct em_tx_queue *tx_queues; 570 struct em_rx_queue *rx_queues; 571 struct if_irq irq; 572 573 struct resource *memory; 574 struct resource *flash; 575 struct resource *ioport; 576 577 struct resource *res; 578 void *tag; 579 u32 linkvec; 580 u32 ivars; 581 582 struct ifmedia *media; 583 int msix; 584 int if_flags; 585 int em_insert_vlan_header; 586 u32 ims; 587 bool allow_64bit_dma; 588 bool in_detach; 589 590 u32 flags; 591 /* Task for FAST handling */ 592 struct grouptask link_task; 593 594 u16 num_vlans; 595 u32 txd_cmd; 596 597 u32 rx_mbuf_sz; 598 599 int enable_aim; 600 /* Management and WOL features */ 601 bool wol_phy_wakeup; 602 bool wol_phy_armed; 603 bool suspend_link_powered_down; 604 bool has_manage; 605 bool has_amt; 606 607 /* Multicast array memory */ 608 u8 *mta; 609 610 /* 611 ** Shadow VFTA table, this is needed because 612 ** the real vlan filter table gets cleared during 613 ** a soft reset and the driver needs to be able 614 ** to repopulate it. 615 */ 616 u32 shadow_vfta[EM_VFTA_SIZE]; 617 u32 vf_vfta_stale[EM_VFTA_SIZE]; 618 u32 vf_vfta_retry[EM_VFTA_SIZE]; 619 sbintime_t vf_vlan_retry_deadline; 620 u16 vf_vlan_retry_cursor; 621 622 /* Info about the interface */ 623 enum em_link_state link_state; 624 u16 fc; 625 u16 link_speed; 626 u16 link_duplex; 627 u32 smartspeed; 628 u32 dmac; 629 u32 pba; 630 int link_mask; 631 int tso_automasked; 632 u32 phy_hang_count; 633 u32 promisc_pending; 634 u32 stats_pending; 635 u32 device_reset_state; 636 u32 fatal_error_state; 637 u32 fatal_error_icr; 638 u32 fatal_error_pbeccsts; 639 u32 fatal_error_peind; 640 u32 fatal_error_pcie; 641 u32 fatal_error_pcie_ecc; 642 u32 fatal_error_lan; 643 u32 fatal_error_dma_tx; 644 u32 fatal_error_dma_rx; 645 u32 fatal_error_dma_host; 646 u64 fatal_error_reset_count; 647 u64 fatal_error_lan_count; 648 u64 fatal_error_mng_count; 649 u64 fatal_error_pcie_count; 650 u64 fatal_error_dma_count; 651 u64 fatal_error_unknown_count; 652 u64 corrected_error_dma_count; 653 u64 corrected_error_pcie_tx_data_count; 654 u64 corrected_error_pcie_retry_count; 655 u64 corrected_error_pcie_other_count; 656 u64 corrected_error_packet_buffer_count; 657 u64 corrected_error_lan_mng_fifo_count; 658 u64 uncorrected_error_packet_buffer_count; 659 u64 uncorrected_error_dma_count; 660 u64 uncorrected_error_pcie_count; 661 662 #ifdef PCI_IOV 663 struct igb_vf *vfs; 664 struct igb_vf_mac_filter *vf_mac_filters; 665 struct callout iov_mbx_retry; 666 u32 iov_vfta[EM_VFTA_SIZE]; 667 u32 iov_mdd_cause; 668 u32 iov_pending; 669 u32 iov_spoof_pending; 670 u32 iov_blocked_pending; 671 u32 iov_intr_drain_pending; 672 u32 iov_teardown; 673 struct timeval iov_last_mdd_log; 674 u16 num_vfs; 675 u16 num_vf_mac_filters; 676 u16 pool; 677 bool iov_hw_active; 678 bool iov_mta_valid; 679 bool iov_mbx_retry_initialized; 680 bool iov_pf_mdd_blocked; 681 bool iov_pf_vlan_promisc; 682 bool iov_vfta_valid; 683 #endif 684 685 u64 que_mask; 686 687 /* We need to store this at attach due to e1000 hw/sw locking model */ 688 struct e1000_fw_version fw_ver; 689 690 struct em_int_delay_info tx_int_delay; 691 struct em_int_delay_info tx_abs_int_delay; 692 struct em_int_delay_info rx_int_delay; 693 struct em_int_delay_info rx_abs_int_delay; 694 struct em_int_delay_info tx_itr; 695 696 /* Misc stats maintained by the driver */ 697 unsigned long dropped_pkts; 698 unsigned long link_irq; 699 unsigned long rx_overruns; 700 u64 rx_csum_good; 701 u64 rx_csum_errors; 702 703 union { 704 struct e1000_hw_stats stats; /* !sc->vf_ifp */ 705 struct e1000_vf_stats vf_stats; /* sc->vf_ifp */ 706 } ustats; 707 708 struct callout vf_queue_retry; 709 struct callout vf_mbx_retry; 710 struct timeval vf_last_queue_log; 711 struct timeval vf_last_mbx_log; 712 u32 vf_queue_retry_new_epoch; 713 u32 vf_queue_retry_pending; 714 u32 vf_mbx_ready; 715 u32 vf_mbx_retry_pending; 716 u16 vf_ifp; 717 u8 vf_queue_failures; 718 u8 vf_mbx_retry_stage; 719 bool vf_queue_gave_up; 720 bool vf_queue_retry_initialized; 721 bool vf_mbx_retry_initialized; 722 bool vf_queues_sanitized; 723 bool vf_reset_pending; 724 bool vf_stats_valid; 725 /* A PF can retain auxiliary filters across a VF reset. */ 726 bool vf_uc_filters_set; 727 }; 728 729 static inline bool 730 igbv_is_hyperv(const struct e1000_softc *sc) 731 { 732 733 return (sc->vf_ifp && 734 (sc->hw.device_id == E1000_DEV_ID_82576_VF_HV || 735 sc->hw.device_id == E1000_DEV_ID_I350_VF_HV)); 736 } 737 738 /* 739 * Shared PF/VF mechanisms and VF policy entry points. The latter live in 740 * if_igbv.c so the VF method table cannot accidentally select PF policy. 741 */ 742 int em_if_attach_pre(if_ctx_t); 743 int em_if_attach_post(if_ctx_t); 744 void em_add_device_sysctls(struct e1000_softc *); 745 int em_if_set_promisc_impl(if_ctx_t, int); 746 bool em_is_valid_ether_addr(const u8 *); 747 void em_initialize_transmit_rings(if_ctx_t); 748 void em_update_stats_counters(struct e1000_softc *); 749 void igb_initialize_receive_rings(if_ctx_t, bool); 750 751 int igbv_get_regs(SYSCTL_HANDLER_ARGS); 752 int igbv_if_attach_pre(if_ctx_t); 753 int igbv_if_attach_post(if_ctx_t); 754 int igbv_if_media_change(if_ctx_t); 755 void igbv_init_hv_ops(struct e1000_hw *); 756 void igbv_if_intr_enable(if_ctx_t); 757 void igbv_if_intr_disable(if_ctx_t); 758 void igbv_if_update_admin_status(if_ctx_t); 759 void igbv_initialize_receive_unit(if_ctx_t); 760 void igbv_initialize_transmit_unit(if_ctx_t); 761 void igbv_mbx_retry_detach(struct e1000_softc *); 762 void igbv_mbx_retry_failed(if_ctx_t); 763 void igbv_mbx_retry_prepare(struct e1000_softc *); 764 void igbv_mbx_retry_stop(struct e1000_softc *); 765 void igbv_queue_retry_detach(struct e1000_softc *); 766 void igbv_queue_retry_failed(if_ctx_t); 767 void igbv_queue_retry_prepare(struct e1000_softc *); 768 void igbv_queue_retry_stop(struct e1000_softc *); 769 void igbv_reconcile_mac(struct e1000_softc *, if_t); 770 bool igbv_reset(if_ctx_t); 771 bool igbv_sanitize_queues(struct e1000_softc *); 772 void igbv_log_reset_failure(struct e1000_softc *, s32, bool); 773 void igbv_update_uc_addr_list(struct e1000_softc *, if_t); 774 void igbv_vlan_retry_add(struct e1000_softc *, u16); 775 void igbv_vlan_retry_clear(struct e1000_softc *, u16); 776 777 /******************************************************************************** 778 * vendor_info_array 779 * 780 * This array contains the list of Subvendor/Subdevice IDs on which the driver 781 * should load. 782 * 783 ********************************************************************************/ 784 typedef struct _em_vendor_info_t { 785 unsigned int vendor_id; 786 unsigned int device_id; 787 unsigned int subvendor_id; 788 unsigned int subdevice_id; 789 unsigned int index; 790 } em_vendor_info_t; 791 792 void em_dump_rs(struct e1000_softc *); 793 794 #endif /* _EM_H_DEFINED_ */ 795