1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2
3 /* MDIO support for Mellanox Gigabit Ethernet driver
4 *
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/ioport.h>
16 #include <linux/irqreturn.h>
17 #include <linux/jiffies.h>
18 #include <linux/module.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22
23 #include "mlxbf_gige.h"
24 #include "mlxbf_gige_regs.h"
25 #include "mlxbf_gige_mdio_bf2.h"
26 #include "mlxbf_gige_mdio_bf3.h"
27
28 static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = {
29 [MLXBF_GIGE_VERSION_BF2] = {
30 .gw_address = MLXBF2_GIGE_MDIO_GW_OFFSET,
31 .read_data_address = MLXBF2_GIGE_MDIO_GW_OFFSET,
32 .busy = {
33 .mask = MLXBF2_GIGE_MDIO_GW_BUSY_MASK,
34 .shift = MLXBF2_GIGE_MDIO_GW_BUSY_SHIFT,
35 },
36 .read_data = {
37 .mask = MLXBF2_GIGE_MDIO_GW_AD_MASK,
38 .shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
39 },
40 .write_data = {
41 .mask = MLXBF2_GIGE_MDIO_GW_AD_MASK,
42 .shift = MLXBF2_GIGE_MDIO_GW_AD_SHIFT,
43 },
44 .devad = {
45 .mask = MLXBF2_GIGE_MDIO_GW_DEVAD_MASK,
46 .shift = MLXBF2_GIGE_MDIO_GW_DEVAD_SHIFT,
47 },
48 .partad = {
49 .mask = MLXBF2_GIGE_MDIO_GW_PARTAD_MASK,
50 .shift = MLXBF2_GIGE_MDIO_GW_PARTAD_SHIFT,
51 },
52 .opcode = {
53 .mask = MLXBF2_GIGE_MDIO_GW_OPCODE_MASK,
54 .shift = MLXBF2_GIGE_MDIO_GW_OPCODE_SHIFT,
55 },
56 .st1 = {
57 .mask = MLXBF2_GIGE_MDIO_GW_ST1_MASK,
58 .shift = MLXBF2_GIGE_MDIO_GW_ST1_SHIFT,
59 },
60 },
61 [MLXBF_GIGE_VERSION_BF3] = {
62 .gw_address = MLXBF3_GIGE_MDIO_GW_OFFSET,
63 .read_data_address = MLXBF3_GIGE_MDIO_DATA_READ,
64 .busy = {
65 .mask = MLXBF3_GIGE_MDIO_GW_BUSY_MASK,
66 .shift = MLXBF3_GIGE_MDIO_GW_BUSY_SHIFT,
67 },
68 .read_data = {
69 .mask = MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK,
70 .shift = MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT,
71 },
72 .write_data = {
73 .mask = MLXBF3_GIGE_MDIO_GW_DATA_MASK,
74 .shift = MLXBF3_GIGE_MDIO_GW_DATA_SHIFT,
75 },
76 .devad = {
77 .mask = MLXBF3_GIGE_MDIO_GW_DEVAD_MASK,
78 .shift = MLXBF3_GIGE_MDIO_GW_DEVAD_SHIFT,
79 },
80 .partad = {
81 .mask = MLXBF3_GIGE_MDIO_GW_PARTAD_MASK,
82 .shift = MLXBF3_GIGE_MDIO_GW_PARTAD_SHIFT,
83 },
84 .opcode = {
85 .mask = MLXBF3_GIGE_MDIO_GW_OPCODE_MASK,
86 .shift = MLXBF3_GIGE_MDIO_GW_OPCODE_SHIFT,
87 },
88 .st1 = {
89 .mask = MLXBF3_GIGE_MDIO_GW_ST1_MASK,
90 .shift = MLXBF3_GIGE_MDIO_GW_ST1_SHIFT,
91 },
92 },
93 };
94
95 #define MLXBF_GIGE_MDIO_FREQ_REFERENCE 156250000ULL
96 #define MLXBF_GIGE_MDIO_COREPLL_CONST 16384ULL
97 #define MLXBF_GIGE_MDC_CLK_NS 400
98 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG1 0x4
99 #define MLXBF_GIGE_MDIO_PLL_I1CLK_REG2 0x8
100 #define MLXBF_GIGE_MDIO_CORE_F_SHIFT 0
101 #define MLXBF_GIGE_MDIO_CORE_F_MASK GENMASK(25, 0)
102 #define MLXBF_GIGE_MDIO_CORE_R_SHIFT 26
103 #define MLXBF_GIGE_MDIO_CORE_R_MASK GENMASK(31, 26)
104 #define MLXBF_GIGE_MDIO_CORE_OD_SHIFT 0
105 #define MLXBF_GIGE_MDIO_CORE_OD_MASK GENMASK(3, 0)
106
107 /* Support clause 22 */
108 #define MLXBF_GIGE_MDIO_CL22_ST1 0x1
109 #define MLXBF_GIGE_MDIO_CL22_WRITE 0x1
110 #define MLXBF_GIGE_MDIO_CL22_READ 0x2
111
112 /* Busy bit is set by software and cleared by hardware */
113 #define MLXBF_GIGE_MDIO_SET_BUSY 0x1
114
115 #define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30
116 #define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c
117 #define MLXBF_GIGE_BF3_COREPLL_ADDR 0x13409824
118 #define MLXBF_GIGE_BF3_COREPLL_SIZE 0x00000010
119
120 static struct resource corepll_params[] = {
121 [MLXBF_GIGE_VERSION_BF2] = {
122 .start = MLXBF_GIGE_BF2_COREPLL_ADDR,
123 .end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1,
124 .name = "COREPLL_RES"
125 },
126 [MLXBF_GIGE_VERSION_BF3] = {
127 .start = MLXBF_GIGE_BF3_COREPLL_ADDR,
128 .end = MLXBF_GIGE_BF3_COREPLL_ADDR + MLXBF_GIGE_BF3_COREPLL_SIZE - 1,
129 .name = "COREPLL_RES"
130 }
131 };
132
133 /* Returns core clock i1clk in Hz */
calculate_i1clk(struct mlxbf_gige * priv)134 static u64 calculate_i1clk(struct mlxbf_gige *priv)
135 {
136 u8 core_od, core_r;
137 u64 freq_output;
138 u32 reg1, reg2;
139 u32 core_f;
140
141 reg1 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1);
142 reg2 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG2);
143
144 core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >>
145 MLXBF_GIGE_MDIO_CORE_F_SHIFT;
146 core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >>
147 MLXBF_GIGE_MDIO_CORE_R_SHIFT;
148 core_od = (reg2 & MLXBF_GIGE_MDIO_CORE_OD_MASK) >>
149 MLXBF_GIGE_MDIO_CORE_OD_SHIFT;
150
151 /* Compute PLL output frequency as follow:
152 *
153 * CORE_F / 16384
154 * freq_output = freq_reference * ----------------------------
155 * (CORE_R + 1) * (CORE_OD + 1)
156 */
157 freq_output = div_u64((MLXBF_GIGE_MDIO_FREQ_REFERENCE * core_f),
158 MLXBF_GIGE_MDIO_COREPLL_CONST);
159 freq_output = div_u64(freq_output, (core_r + 1) * (core_od + 1));
160
161 return freq_output;
162 }
163
164 /* Formula for encoding the MDIO period. The encoded value is
165 * passed to the MDIO config register.
166 *
167 * mdc_clk = 2*(val + 1)*(core clock in sec)
168 *
169 * i1clk is in Hz:
170 * 400 ns = 2*(val + 1)*(1/i1clk)
171 *
172 * val = (((400/10^9) / (1/i1clk) / 2) - 1)
173 * val = (400/2 * i1clk)/10^9 - 1
174 */
mdio_period_map(struct mlxbf_gige * priv)175 static u8 mdio_period_map(struct mlxbf_gige *priv)
176 {
177 u8 mdio_period;
178 u64 i1clk;
179
180 i1clk = calculate_i1clk(priv);
181
182 mdio_period = div_u64((MLXBF_GIGE_MDC_CLK_NS >> 1) * i1clk, 1000000000) - 1;
183
184 return mdio_period;
185 }
186
mlxbf_gige_mdio_create_cmd(struct mlxbf_gige_mdio_gw * mdio_gw,u16 data,int phy_add,int phy_reg,u32 opcode)187 static u32 mlxbf_gige_mdio_create_cmd(struct mlxbf_gige_mdio_gw *mdio_gw, u16 data, int phy_add,
188 int phy_reg, u32 opcode)
189 {
190 u32 gw_reg = 0;
191
192 gw_reg |= ((data << mdio_gw->write_data.shift) &
193 mdio_gw->write_data.mask);
194 gw_reg |= ((phy_reg << mdio_gw->devad.shift) &
195 mdio_gw->devad.mask);
196 gw_reg |= ((phy_add << mdio_gw->partad.shift) &
197 mdio_gw->partad.mask);
198 gw_reg |= ((opcode << mdio_gw->opcode.shift) &
199 mdio_gw->opcode.mask);
200 gw_reg |= ((MLXBF_GIGE_MDIO_CL22_ST1 << mdio_gw->st1.shift) &
201 mdio_gw->st1.mask);
202 gw_reg |= ((MLXBF_GIGE_MDIO_SET_BUSY << mdio_gw->busy.shift) &
203 mdio_gw->busy.mask);
204
205 return gw_reg;
206 }
207
mlxbf_gige_mdio_read(struct mii_bus * bus,int phy_add,int phy_reg)208 static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
209 {
210 struct mlxbf_gige *priv = bus->priv;
211 u32 cmd;
212 int ret;
213 u32 val;
214
215 /* Send mdio read request */
216 cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, 0, phy_add, phy_reg,
217 MLXBF_GIGE_MDIO_CL22_READ);
218
219 writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
220
221 ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address,
222 val, !(val & priv->mdio_gw->busy.mask),
223 5, 1000000);
224
225 if (ret) {
226 writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
227 return ret;
228 }
229
230 ret = readl(priv->mdio_io + priv->mdio_gw->read_data_address);
231 /* Only return ad bits of the gw register */
232 ret &= priv->mdio_gw->read_data.mask;
233
234 /* The MDIO lock is set on read. To release it, clear gw register */
235 writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
236
237 return ret;
238 }
239
mlxbf_gige_mdio_write(struct mii_bus * bus,int phy_add,int phy_reg,u16 val)240 static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
241 int phy_reg, u16 val)
242 {
243 struct mlxbf_gige *priv = bus->priv;
244 u32 temp;
245 u32 cmd;
246 int ret;
247
248 /* Send mdio write request */
249 cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, val, phy_add, phy_reg,
250 MLXBF_GIGE_MDIO_CL22_WRITE);
251 writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
252
253 /* If the poll timed out, drop the request */
254 ret = readl_poll_timeout_atomic(priv->mdio_io + priv->mdio_gw->gw_address,
255 temp, !(temp & priv->mdio_gw->busy.mask),
256 5, 1000000);
257
258 /* The MDIO lock is set on read. To release it, clear gw register */
259 writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
260
261 return ret;
262 }
263
mlxbf_gige_mdio_cfg(struct mlxbf_gige * priv)264 static void mlxbf_gige_mdio_cfg(struct mlxbf_gige *priv)
265 {
266 u8 mdio_period;
267 u32 val;
268
269 mdio_period = mdio_period_map(priv);
270
271 if (priv->hw_version == MLXBF_GIGE_VERSION_BF2) {
272 val = MLXBF2_GIGE_MDIO_CFG_VAL;
273 val |= FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
274 writel(val, priv->mdio_io + MLXBF2_GIGE_MDIO_CFG_OFFSET);
275 } else {
276 val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) |
277 FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1);
278 writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG0);
279 val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK, mdio_period);
280 writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG1);
281 val = FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) |
282 FIELD_PREP(MLXBF3_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13);
283 writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG2);
284 }
285 }
286
mlxbf_gige_mdio_probe(struct platform_device * pdev,struct mlxbf_gige * priv)287 int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv)
288 {
289 struct device *dev = &pdev->dev;
290 struct resource *res;
291 int ret;
292
293 if (priv->hw_version > MLXBF_GIGE_VERSION_BF3)
294 return -ENODEV;
295
296 priv->mdio_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MDIO9);
297 if (IS_ERR(priv->mdio_io))
298 return PTR_ERR(priv->mdio_io);
299
300 /* clk resource shared with other drivers so cannot use
301 * devm_platform_ioremap_resource
302 */
303 res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK);
304 if (!res) {
305 /* For backward compatibility with older ACPI tables, also keep
306 * CLK resource internal to the driver.
307 */
308 res = &corepll_params[priv->hw_version];
309 }
310
311 priv->clk_io = devm_ioremap(dev, res->start, resource_size(res));
312 if (!priv->clk_io)
313 return -ENOMEM;
314
315 priv->mdio_gw = &mlxbf_gige_mdio_gw_t[priv->hw_version];
316
317 mlxbf_gige_mdio_cfg(priv);
318
319 priv->mdiobus = devm_mdiobus_alloc(dev);
320 if (!priv->mdiobus) {
321 dev_err(dev, "Failed to alloc MDIO bus\n");
322 return -ENOMEM;
323 }
324
325 priv->mdiobus->name = "mlxbf-mdio";
326 priv->mdiobus->read = mlxbf_gige_mdio_read;
327 priv->mdiobus->write = mlxbf_gige_mdio_write;
328 priv->mdiobus->parent = dev;
329 priv->mdiobus->priv = priv;
330 snprintf(priv->mdiobus->id, MII_BUS_ID_SIZE, "%s",
331 dev_name(dev));
332
333 ret = mdiobus_register(priv->mdiobus);
334 if (ret)
335 dev_err(dev, "Failed to register MDIO bus\n");
336
337 return ret;
338 }
339
mlxbf_gige_mdio_remove(struct mlxbf_gige * priv)340 void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv)
341 {
342 mdiobus_unregister(priv->mdiobus);
343 }
344