1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r9a06g032-sysctrl.h> 11 12/ { 13 compatible = "renesas,r9a06g032"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 interrupt-parent = <&gic>; 17 18 /* 19 * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor) 20 * with x1, x2 or x4 ratio between the CPUs clock frequency and this 21 * 'ref' clock frequency. 22 * 23 * The table below is built on the assumption that the 'ref' clock 24 * frequency is set to 500MHz which is its default value. 25 * 26 * The table should be overridden in the board device-tree file based 27 * on the 'ref' clock frequency if this frequency value is not the 28 * default one. 29 */ 30 cpu_opp_table: opp-table-cpu { 31 compatible = "operating-points-v2"; 32 opp-shared; 33 34 opp-125000000 { 35 opp-hz = /bits/ 64 <125000000>; 36 /* ~35 clocks cycles at 125mhz */ 37 clock-latency-ns = <300>; 38 }; 39 40 opp-250000000 { 41 opp-hz = /bits/ 64 <250000000>; 42 clock-latency-ns = <300>; 43 }; 44 45 opp-500000000 { 46 opp-hz = /bits/ 64 <500000000>; 47 clock-latency-ns = <300>; 48 }; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu@0 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a7"; 58 reg = <0>; 59 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 63 cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a7"; 66 reg = <1>; 67 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 68 enable-method = "renesas,r9a06g032-smp"; 69 cpu-release-addr = <0 0x4000c204>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 }; 73 74 ext_jtag_clk: extjtagclk { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <0>; 78 }; 79 80 ext_mclk: extmclk { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <40000000>; 84 }; 85 86 ext_rgmii_ref: extrgmiiref { 87 #clock-cells = <0>; 88 compatible = "fixed-clock"; 89 clock-frequency = <0>; 90 }; 91 92 ext_rtc_clk: extrtcclk { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 clock-frequency = <0>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges; 103 104 qspi0: spi@40005000 { 105 compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; 106 reg = <0x40005000 0x1000>, <0x10000000 0x10000000>; 107 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>, 109 <&sysctrl R9A06G032_HCLK_QSPI0>; 110 clock-names = "ref", "ahb", "apb"; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 status = "disabled"; 114 }; 115 116 rtc0: rtc@40006000 { 117 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; 118 reg = <0x40006000 0x1000>; 119 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 120 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 121 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 122 interrupt-names = "alarm", "timer", "pps"; 123 clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>; 124 clock-names = "hclk", "xtal"; 125 power-domains = <&sysctrl>; 126 status = "disabled"; 127 }; 128 129 wdt0: watchdog@40008000 { 130 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 131 reg = <0x40008000 0x1000>; 132 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 133 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 134 status = "disabled"; 135 }; 136 137 wdt1: watchdog@40009000 { 138 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 139 reg = <0x40009000 0x1000>; 140 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; 141 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 142 status = "disabled"; 143 }; 144 145 sysctrl: system-controller@4000c000 { 146 compatible = "renesas,r9a06g032-sysctrl"; 147 reg = <0x4000c000 0x1000>; 148 status = "okay"; 149 #clock-cells = <1>; 150 #power-domain-cells = <0>; 151 152 clocks = <&ext_mclk>, <&ext_rtc_clk>, 153 <&ext_jtag_clk>, <&ext_rgmii_ref>; 154 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 158 dmamux: dma-router@a0 { 159 compatible = "renesas,rzn1-dmamux"; 160 reg = <0xa0 4>; 161 #dma-cells = <6>; 162 dma-requests = <32>; 163 dma-masters = <&dma0 &dma1>; 164 }; 165 }; 166 167 udc: usb@4001e000 { 168 compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; 169 reg = <0x4001e000 0x2000>; 170 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&sysctrl R9A06G032_HCLK_USBF>, 173 <&sysctrl R9A06G032_HCLK_USBPM>; 174 clock-names = "hclkf", "hclkpm"; 175 power-domains = <&sysctrl>; 176 status = "disabled"; 177 }; 178 179 pci_usb: pci@40030000 { 180 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; 181 device_type = "pci"; 182 clocks = <&sysctrl R9A06G032_HCLK_USBH>, 183 <&sysctrl R9A06G032_HCLK_USBPM>, 184 <&sysctrl R9A06G032_CLK_PCI_USB>; 185 clock-names = "hclkh", "hclkpm", "pciclk"; 186 power-domains = <&sysctrl>; 187 reg = <0x40030000 0xc00>, 188 <0x40020000 0x1100>; 189 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 190 status = "disabled"; 191 192 bus-range = <0 0>; 193 #address-cells = <3>; 194 #size-cells = <2>; 195 #interrupt-cells = <1>; 196 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; 197 /* Should map all possible DDR as inbound ranges, but 198 * the IP only supports a 256MB, 512MB, or 1GB window. 199 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) 200 */ 201 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; 202 interrupt-map-mask = <0xf800 0 0 0x7>; 203 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 204 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 205 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 206 207 usb@1,0 { 208 reg = <0x800 0 0 0 0>; 209 phys = <&usbphy>; 210 phy-names = "usb"; 211 }; 212 213 usb@2,0 { 214 reg = <0x1000 0 0 0 0>; 215 phys = <&usbphy>; 216 phy-names = "usb"; 217 }; 218 }; 219 220 uart0: serial@40060000 { 221 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 222 reg = <0x40060000 0x400>; 223 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 224 reg-shift = <2>; 225 reg-io-width = <4>; 226 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 227 clock-names = "baudclk", "apb_pclk"; 228 status = "disabled"; 229 }; 230 231 uart1: serial@40061000 { 232 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 233 reg = <0x40061000 0x400>; 234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 235 reg-shift = <2>; 236 reg-io-width = <4>; 237 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; 238 clock-names = "baudclk", "apb_pclk"; 239 status = "disabled"; 240 }; 241 242 uart2: serial@40062000 { 243 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 244 reg = <0x40062000 0x400>; 245 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; 249 clock-names = "baudclk", "apb_pclk"; 250 status = "disabled"; 251 }; 252 253 uart3: serial@50000000 { 254 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 255 reg = <0x50000000 0x400>; 256 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 257 reg-shift = <2>; 258 reg-io-width = <4>; 259 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; 260 clock-names = "baudclk", "apb_pclk"; 261 dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; 262 dma-names = "tx", "rx"; 263 status = "disabled"; 264 }; 265 266 uart4: serial@50001000 { 267 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 268 reg = <0x50001000 0x400>; 269 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 270 reg-shift = <2>; 271 reg-io-width = <4>; 272 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; 273 clock-names = "baudclk", "apb_pclk"; 274 dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; 275 dma-names = "tx", "rx"; 276 status = "disabled"; 277 }; 278 279 uart5: serial@50002000 { 280 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 281 reg = <0x50002000 0x400>; 282 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; 286 clock-names = "baudclk", "apb_pclk"; 287 dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; 288 dma-names = "tx", "rx"; 289 status = "disabled"; 290 }; 291 292 uart6: serial@50003000 { 293 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 294 reg = <0x50003000 0x400>; 295 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; 299 clock-names = "baudclk", "apb_pclk"; 300 dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; 301 dma-names = "tx", "rx"; 302 status = "disabled"; 303 }; 304 305 uart7: serial@50004000 { 306 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 307 reg = <0x50004000 0x400>; 308 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; 312 clock-names = "baudclk", "apb_pclk"; 313 dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; 314 dma-names = "tx", "rx"; 315 status = "disabled"; 316 }; 317 318 i2c1: i2c@40063000 { 319 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; 320 reg = <0x40063000 0x100>; 321 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>; 323 clock-names = "ref", "pclk"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 status = "disabled"; 327 }; 328 329 i2c2: i2c@40064000 { 330 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; 331 reg = <0x40064000 0x100>; 332 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>; 334 clock-names = "ref", "pclk"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 status = "disabled"; 338 }; 339 340 adc: adc@40065000 { 341 compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc"; 342 reg = <0x40065000 0x200>; 343 clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; 344 clock-names = "pclk", "adc"; 345 power-domains = <&sysctrl>; 346 #io-channel-cells = <1>; 347 status = "disabled"; 348 }; 349 350 pinctrl: pinctrl@40067000 { 351 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 352 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 353 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; 354 clock-names = "bus"; 355 status = "okay"; 356 }; 357 358 sdio1: mmc@40100000 { 359 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; 360 reg = <0x40100000 0x1000>; 361 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 363 interrupt-names = "int", "wakeup"; 364 clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>; 365 clock-names = "clk_xin", "clk_ahb"; 366 no-1-8-v; 367 status = "disabled"; 368 }; 369 370 sdio2: mmc@40101000 { 371 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; 372 reg = <0x40101000 0x1000>; 373 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-names = "int", "wakeup"; 376 clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>; 377 clock-names = "clk_xin", "clk_ahb"; 378 no-1-8-v; 379 status = "disabled"; 380 }; 381 382 nand_controller: nand-controller@40102000 { 383 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; 384 reg = <0x40102000 0x2000>; 385 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; 387 clock-names = "hclk", "eclk"; 388 power-domains = <&sysctrl>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 status = "disabled"; 392 }; 393 394 dma0: dma-controller@40104000 { 395 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 396 reg = <0x40104000 0x1000>; 397 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 398 clock-names = "hclk"; 399 clocks = <&sysctrl R9A06G032_HCLK_DMA0>; 400 dma-channels = <8>; 401 dma-requests = <16>; 402 dma-masters = <1>; 403 #dma-cells = <3>; 404 block_size = <0xfff>; 405 data-width = <8>; 406 }; 407 408 dma1: dma-controller@40105000 { 409 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 410 reg = <0x40105000 0x1000>; 411 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 412 clock-names = "hclk"; 413 clocks = <&sysctrl R9A06G032_HCLK_DMA1>; 414 dma-channels = <8>; 415 dma-requests = <16>; 416 dma-masters = <1>; 417 #dma-cells = <3>; 418 block_size = <0xfff>; 419 data-width = <8>; 420 }; 421 422 gmac1: ethernet@44000000 { 423 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 424 reg = <0x44000000 0x2000>; 425 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 429 clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; 430 clock-names = "stmmaceth"; 431 power-domains = <&sysctrl>; 432 snps,multicast-filter-bins = <256>; 433 snps,perfect-filter-entries = <128>; 434 tx-fifo-depth = <2048>; 435 rx-fifo-depth = <4096>; 436 pcs-handle = <&mii_conv1>; 437 status = "disabled"; 438 }; 439 440 gmac2: ethernet@44002000 { 441 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 442 reg = <0x44002000 0x2000>; 443 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 447 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; 448 clock-names = "stmmaceth"; 449 power-domains = <&sysctrl>; 450 snps,multicast-filter-bins = <256>; 451 snps,perfect-filter-entries = <128>; 452 tx-fifo-depth = <2048>; 453 rx-fifo-depth = <4096>; 454 status = "disabled"; 455 }; 456 457 eth_miic: eth-miic@44030000 { 458 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0x44030000 0x10000>; 462 clocks = <&sysctrl R9A06G032_CLK_MII_REF>, 463 <&sysctrl R9A06G032_CLK_RGMII_REF>, 464 <&sysctrl R9A06G032_CLK_RMII_REF>, 465 <&sysctrl R9A06G032_HCLK_SWITCH_RG>; 466 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 467 power-domains = <&sysctrl>; 468 status = "disabled"; 469 470 mii_conv1: mii-conv@1 { 471 reg = <1>; 472 status = "disabled"; 473 }; 474 475 mii_conv2: mii-conv@2 { 476 reg = <2>; 477 status = "disabled"; 478 }; 479 480 mii_conv3: mii-conv@3 { 481 reg = <3>; 482 status = "disabled"; 483 }; 484 485 mii_conv4: mii-conv@4 { 486 reg = <4>; 487 status = "disabled"; 488 }; 489 490 mii_conv5: mii-conv@5 { 491 reg = <5>; 492 status = "disabled"; 493 }; 494 }; 495 496 switch: switch@44050000 { 497 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; 498 reg = <0x44050000 0x10000>; 499 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, 500 <&sysctrl R9A06G032_CLK_SWITCH>; 501 clock-names = "hclk", "clk"; 502 power-domains = <&sysctrl>; 503 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-names = "dlr", "switch", "prp", "hub", "ptrn"; 509 status = "disabled"; 510 511 ethernet-ports { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 switch_port0: port@0 { 516 reg = <0>; 517 pcs-handle = <&mii_conv5>; 518 status = "disabled"; 519 }; 520 521 switch_port1: port@1 { 522 reg = <1>; 523 pcs-handle = <&mii_conv4>; 524 status = "disabled"; 525 }; 526 527 switch_port2: port@2 { 528 reg = <2>; 529 pcs-handle = <&mii_conv3>; 530 status = "disabled"; 531 }; 532 533 switch_port3: port@3 { 534 reg = <3>; 535 pcs-handle = <&mii_conv2>; 536 status = "disabled"; 537 }; 538 539 switch_port4: port@4 { 540 reg = <4>; 541 ethernet = <&gmac2>; 542 label = "cpu"; 543 phy-mode = "internal"; 544 status = "disabled"; 545 fixed-link { 546 speed = <1000>; 547 full-duplex; 548 }; 549 }; 550 }; 551 }; 552 553 gic: interrupt-controller@44101000 { 554 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 555 interrupt-controller; 556 #interrupt-cells = <3>; 557 #address-cells = <0>; 558 reg = <0x44101000 0x1000>, /* Distributer */ 559 <0x44102000 0x2000>, /* CPU interface */ 560 <0x44104000 0x2000>, /* Virt interface control */ 561 <0x44106000 0x2000>; /* Virt CPU interface */ 562 interrupts = 563 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 564 }; 565 566 /* 567 * The GPIO mapping to the corresponding pins is not obvious. 568 * See the hardware documentation for details. 569 */ 570 gpio0: gpio@5000b000 { 571 compatible = "snps,dw-apb-gpio"; 572 reg = <0x5000b000 0x80>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&sysctrl R9A06G032_HCLK_GPIO0>; 576 clock-names = "bus"; 577 578 /* GPIO0a[0] connected to pin GPIO0 */ 579 /* GPIO0a[1..2] connected to pins GPIO3..4 */ 580 /* GPIO0a[3..4] connected to pins GPIO9..10 */ 581 /* GPIO0a[5] connected to pin GPIO12 */ 582 /* GPIO0a[6..7] connected to pins GPIO15..16 */ 583 /* GPIO0a[8..9] connected to pins GPIO21..22 */ 584 /* GPIO0a[10] connected to pin GPIO24 */ 585 /* GPIO0a[11..12] connected to pins GPIO27..28 */ 586 /* GPIO0a[13..14] connected to pins GPIO33..34 */ 587 /* GPIO0a[15] connected to pin GPIO36 */ 588 /* GPIO0a[16..17] connected to pins GPIO39..40 */ 589 /* GPIO0a[18..19] connected to pins GPIO45..46 */ 590 /* GPIO0a[20] connected to pin GPIO48 */ 591 /* GPIO0a[21..22] connected to pins GPIO51..52 */ 592 /* GPIO0a[23..24] connected to pins GPIO57..58 */ 593 /* GPIO0a[25..31] connected to pins GPIO62..68 */ 594 gpio0a: gpio-port@0 { 595 compatible = "snps,dw-apb-gpio-port"; 596 reg = <0>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 snps,nr-gpios = <32>; 600 601 interrupt-controller; 602 interrupt-parent = <&gpioirqmux>; 603 interrupts = < 0 1 2 3 4 5 6 7 604 8 9 10 11 12 13 14 15 605 16 17 18 19 20 21 22 23 606 24 25 26 27 28 29 30 31>; 607 #interrupt-cells = <2>; 608 }; 609 610 /* GPIO0b[0..1] connected to pins GPIO1..2 */ 611 /* GPIO0b[2..5] connected to pins GPIO5..8 */ 612 /* GPIO0b[6] connected to pin GPIO11 */ 613 /* GPIO0b[7..8] connected to pins GPIO13..14 */ 614 /* GPIO0b[9..12] connected to pins GPIO17..20 */ 615 /* GPIO0b[13] connected to pin GPIO23 */ 616 /* GPIO0b[14..15] connected to pins GPIO25..26 */ 617 /* GPIO0b[16..19] connected to pins GPIO29..32 */ 618 /* GPIO0b[20] connected to pin GPIO35 */ 619 /* GPIO0b[21..22] connected to pins GPIO37..38 */ 620 /* GPIO0b[23..26] connected to pins GPIO41..44 */ 621 /* GPIO0b[27] connected to pin GPIO47 */ 622 /* GPIO0b[28..29] connected to pins GPIO49..50 */ 623 /* GPIO0b[30..31] connected to pins GPIO53..54 */ 624 gpio0b: gpio-port@1 { 625 compatible = "snps,dw-apb-gpio-port"; 626 reg = <1>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 snps,nr-gpios = <32>; 630 }; 631 }; 632 633 gpio1: gpio@5000c000 { 634 compatible = "snps,dw-apb-gpio"; 635 reg = <0x5000c000 0x80>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&sysctrl R9A06G032_HCLK_GPIO1>; 639 clock-names = "bus"; 640 641 /* GPIO1a[0..4] connected to pins GPIO69..73 */ 642 /* GPIO1a[5..31] connected to pins GPIO95..121 */ 643 gpio1a: gpio-port@0 { 644 compatible = "snps,dw-apb-gpio-port"; 645 reg = <0>; 646 gpio-controller; 647 #gpio-cells = <2>; 648 snps,nr-gpios = <32>; 649 650 interrupt-controller; 651 interrupt-parent = <&gpioirqmux>; 652 interrupts = <32 33 34 35 36 37 38 39 653 40 41 42 43 44 45 46 47 654 48 49 50 51 52 53 54 55 655 56 57 58 59 60 61 62 63>; 656 #interrupt-cells = <2>; 657 }; 658 659 /* GPIO1b[0..1] connected to pins GPIO55..56 */ 660 /* GPIO1b[2..4] connected to pins GPIO59..61 */ 661 /* GPIO1b[5..25] connected to pins GPIO74..94 */ 662 /* GPIO1b[26..31] connected to pins GPIO150..155 */ 663 gpio1b: gpio-port@1 { 664 compatible = "snps,dw-apb-gpio-port"; 665 reg = <1>; 666 gpio-controller; 667 #gpio-cells = <2>; 668 snps,nr-gpios = <32>; 669 }; 670 }; 671 672 gpio2: gpio@5000d000 { 673 compatible = "snps,dw-apb-gpio"; 674 reg = <0x5000d000 0x80>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 clocks = <&sysctrl R9A06G032_HCLK_GPIO2>; 678 clock-names = "bus"; 679 680 /* GPIO2a[0..27] connected to pins GPIO122..149 */ 681 /* GPIO2a[28..31] connected to pins GPIO156..159 */ 682 gpio2a: gpio-port@0 { 683 compatible = "snps,dw-apb-gpio-port"; 684 reg = <0>; 685 gpio-controller; 686 #gpio-cells = <2>; 687 snps,nr-gpios = <32>; 688 689 interrupt-controller; 690 interrupt-parent = <&gpioirqmux>; 691 interrupts = <64 65 66 67 68 69 70 71 692 72 73 74 75 76 77 78 79 693 80 81 82 83 84 85 86 87 694 88 89 90 91 92 93 94 95>; 695 #interrupt-cells = <2>; 696 }; 697 698 /* GPIO2b[0..9] connected to pins GPIO160..169 */ 699 gpio2b: gpio-port@1 { 700 compatible = "snps,dw-apb-gpio-port"; 701 reg = <1>; 702 gpio-controller; 703 #gpio-cells = <2>; 704 snps,nr-gpios = <10>; 705 }; 706 }; 707 708 gpioirqmux: interrupt-controller@51000480 { 709 compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; 710 reg = <0x51000480 0x20>; 711 #interrupt-cells = <1>; 712 #address-cells = <0>; 713 interrupt-map-mask = <0x7f>; 714 715 /* 716 * Example mapping entry. Board DTs need to overwrite 717 * 'interrupt-map' with their specific mapping. Check 718 * the irqmux binding documentation for details. 719 */ 720 interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 721 722 status = "disabled"; 723 }; 724 725 can0: can@52104000 { 726 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 727 reg = <0x52104000 0x800>; 728 reg-io-width = <4>; 729 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&sysctrl R9A06G032_HCLK_CAN0>; 731 power-domains = <&sysctrl>; 732 status = "disabled"; 733 }; 734 735 can1: can@52105000 { 736 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 737 reg = <0x52105000 0x800>; 738 reg-io-width = <4>; 739 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&sysctrl R9A06G032_HCLK_CAN1>; 741 power-domains = <&sysctrl>; 742 status = "disabled"; 743 }; 744 }; 745 746 timer { 747 compatible = "arm,armv7-timer"; 748 arm,cpu-registers-not-fw-configured; 749 always-on; 750 interrupts = 751 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 752 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 753 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 754 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 755 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 756 }; 757 758 usbphy: usb-phy { 759 #phy-cells = <0>; 760 compatible = "usb-nop-xceiv"; 761 status = "disabled"; 762 }; 763}; 764