1 /*-
2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "opt_wlan.h"
18
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
22 #include <sys/lock.h>
23 #include <sys/mutex.h>
24 #include <sys/mbuf.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
30 #include <sys/bus.h>
31 #include <sys/endian.h>
32 #include <sys/kdb.h>
33
34 #include <net/if.h>
35 #include <net/if_var.h>
36 #include <net/if_arp.h>
37 #include <net/ethernet.h>
38 #include <net/if_dl.h>
39 #include <net/if_media.h>
40 #include <net/if_types.h>
41
42 #ifdef INET
43 #include <netinet/in.h>
44 #include <netinet/in_systm.h>
45 #include <netinet/in_var.h>
46 #include <netinet/if_ether.h>
47 #include <netinet/ip.h>
48 #endif
49
50 #include <net80211/ieee80211_var.h>
51 #include <net80211/ieee80211_regdomain.h>
52 #include <net80211/ieee80211_radiotap.h>
53
54 #include <dev/usb/usb.h>
55 #include <dev/usb/usbdi.h>
56 #include "usbdevs.h"
57
58 #include <dev/usb/wlan/if_urtwreg.h>
59 #include <dev/usb/wlan/if_urtwvar.h>
60
61 /* copy some rate indices from if_rtwn_ridx.h */
62 #define URTW_RIDX_CCK5 2
63 #define URTW_RIDX_CCK11 3
64 #define URTW_RIDX_OFDM6 4
65 #define URTW_RIDX_OFDM24 8
66
67 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
68 "USB Realtek 8187L");
69 #ifdef URTW_DEBUG
70 int urtw_debug = 0;
71 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0,
72 "control debugging printfs");
73 enum {
74 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
75 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
76 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
77 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
78 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
79 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
80 URTW_DEBUG_STAT = 0x00000040, /* statistic */
81 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
82 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
83 URTW_DEBUG_ANY = 0xffffffff
84 };
85 #define DPRINTF(sc, m, fmt, ...) do { \
86 if (sc->sc_debug & (m)) \
87 printf(fmt, __VA_ARGS__); \
88 } while (0)
89 #else
90 #define DPRINTF(sc, m, fmt, ...) do { \
91 (void) sc; \
92 } while (0)
93 #endif
94 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
95 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN,
96 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
97
98 /* recognized device vendors/products */
99 #define urtw_lookup(v, p) \
100 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
101 #define URTW_DEV_B(v,p) \
102 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
103 #define URTW_DEV_L(v,p) \
104 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
105 #define URTW_REV_RTL8187B 0
106 #define URTW_REV_RTL8187L 1
107 static const STRUCT_USB_HOST_ID urtw_devs[] = {
108 URTW_DEV_B(NETGEAR, WG111V3),
109 URTW_DEV_B(REALTEK, RTL8187B_0),
110 URTW_DEV_B(REALTEK, RTL8187B_1),
111 URTW_DEV_B(REALTEK, RTL8187B_2),
112 URTW_DEV_B(SITECOMEU, WL168V4),
113 URTW_DEV_L(ASUS, P5B_WIFI),
114 URTW_DEV_L(BELKIN, F5D7050E),
115 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
116 URTW_DEV_L(NETGEAR, WG111V2),
117 URTW_DEV_L(REALTEK, RTL8187),
118 URTW_DEV_L(SITECOMEU, WL168V1),
119 URTW_DEV_L(SURECOM, EP9001G2A),
120 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
125 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
126 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
127 #undef URTW_DEV_L
128 #undef URTW_DEV_B
129 };
130
131 #define urtw_read8_m(sc, val, data) do { \
132 error = urtw_read8_c(sc, val, data); \
133 if (error != 0) \
134 goto fail; \
135 } while (0)
136 #define urtw_write8_m(sc, val, data) do { \
137 error = urtw_write8_c(sc, val, data); \
138 if (error != 0) \
139 goto fail; \
140 } while (0)
141 #define urtw_read16_m(sc, val, data) do { \
142 error = urtw_read16_c(sc, val, data); \
143 if (error != 0) \
144 goto fail; \
145 } while (0)
146 #define urtw_write16_m(sc, val, data) do { \
147 error = urtw_write16_c(sc, val, data); \
148 if (error != 0) \
149 goto fail; \
150 } while (0)
151 #define urtw_read32_m(sc, val, data) do { \
152 error = urtw_read32_c(sc, val, data); \
153 if (error != 0) \
154 goto fail; \
155 } while (0)
156 #define urtw_write32_m(sc, val, data) do { \
157 error = urtw_write32_c(sc, val, data); \
158 if (error != 0) \
159 goto fail; \
160 } while (0)
161 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
162 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
163 if (error != 0) \
164 goto fail; \
165 } while (0)
166 #define urtw_8187_write_phy_cck(sc, val, data) do { \
167 error = urtw_8187_write_phy_cck_c(sc, val, data); \
168 if (error != 0) \
169 goto fail; \
170 } while (0)
171 #define urtw_8225_write(sc, val, data) do { \
172 error = urtw_8225_write_c(sc, val, data); \
173 if (error != 0) \
174 goto fail; \
175 } while (0)
176
177 struct urtw_pair {
178 uint32_t reg;
179 uint32_t val;
180 };
181
182 static uint8_t urtw_8225_agc[] = {
183 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
184 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
185 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
186 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
187 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
188 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
189 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
190 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
191 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
192 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
193 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
194 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
195 };
196
197 static uint8_t urtw_8225z2_agc[] = {
198 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
199 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
200 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
201 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
202 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
203 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
204 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
205 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
206 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
207 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
208 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
209 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
210 };
211
212 static uint32_t urtw_8225_channel[] = {
213 0x0000, /* dummy channel 0 */
214 0x085c, /* 1 */
215 0x08dc, /* 2 */
216 0x095c, /* 3 */
217 0x09dc, /* 4 */
218 0x0a5c, /* 5 */
219 0x0adc, /* 6 */
220 0x0b5c, /* 7 */
221 0x0bdc, /* 8 */
222 0x0c5c, /* 9 */
223 0x0cdc, /* 10 */
224 0x0d5c, /* 11 */
225 0x0ddc, /* 12 */
226 0x0e5c, /* 13 */
227 0x0f72, /* 14 */
228 };
229
230 static uint8_t urtw_8225_gain[] = {
231 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
232 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
233 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
234 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
235 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
236 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
237 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
238 };
239
240 static struct urtw_pair urtw_8225_rf_part1[] = {
241 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
242 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
243 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
244 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
245 };
246
247 static struct urtw_pair urtw_8225_rf_part2[] = {
248 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
249 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
250 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
251 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
252 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
253 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
254 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
255 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
256 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
257 { 0x27, 0x88 }
258 };
259
260 static struct urtw_pair urtw_8225_rf_part3[] = {
261 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
262 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
263 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
264 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
265 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
266 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
267 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
268 };
269
270 static uint16_t urtw_8225_rxgain[] = {
271 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
272 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
273 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
274 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
275 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
276 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
277 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
278 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
279 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
280 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
281 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
282 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
283 };
284
285 static uint8_t urtw_8225_threshold[] = {
286 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
287 };
288
289 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
290 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
291 };
292
293 static uint8_t urtw_8225_txpwr_cck[] = {
294 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
295 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
296 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
297 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
298 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
299 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
300 };
301
302 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
303 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
304 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
305 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
306 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
307 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
308 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
309 };
310
311 static uint8_t urtw_8225_txpwr_ofdm[]={
312 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
313 };
314
315 static uint8_t urtw_8225v2_gain_bg[]={
316 0x23, 0x15, 0xa5, /* -82-1dbm */
317 0x23, 0x15, 0xb5, /* -82-2dbm */
318 0x23, 0x15, 0xc5, /* -82-3dbm */
319 0x33, 0x15, 0xc5, /* -78dbm */
320 0x43, 0x15, 0xc5, /* -74dbm */
321 0x53, 0x15, 0xc5, /* -70dbm */
322 0x63, 0x15, 0xc5, /* -66dbm */
323 };
324
325 static struct urtw_pair urtw_8225v2_rf_part1[] = {
326 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
327 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
328 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
329 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
330 };
331
332 static struct urtw_pair urtw_8225v2b_rf_part0[] = {
333 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
334 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
335 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
336 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
337 };
338
339 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
340 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
341 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
342 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
343 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
344 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
345 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
346 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
347 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
348 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
349 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
350 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
351 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
352 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
353 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
354 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
355 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
356 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
357 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
358 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
359 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
360 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
361 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
362 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
363 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
364 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
365 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
366 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
367 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
368 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
369 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
370 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
371 };
372
373 static struct urtw_pair urtw_8225v2_rf_part2[] = {
374 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
375 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
376 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
377 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
378 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
379 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
380 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
381 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
382 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
383 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
384 };
385
386 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
387 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
388 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
389 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
390 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
391 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
392 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
393 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
394 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
395 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
396 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
397 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
398 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
399 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
400 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
401 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
402 };
403
404 static struct urtw_pair urtw_8225v2_rf_part3[] = {
405 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
406 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
407 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
408 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
409 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
410 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
411 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
412 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
413 };
414
415 static uint16_t urtw_8225v2_rxgain[] = {
416 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
417 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
418 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
419 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
420 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
421 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
422 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
423 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
424 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
425 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
426 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
427 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
428 };
429
430 static uint16_t urtw_8225v2b_rxgain[] = {
431 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
432 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
433 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
434 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
435 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
436 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
437 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
438 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
439 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
440 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
441 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
442 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
443 };
444
445 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
446 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
447 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
448 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
449 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
450 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
451 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
452 };
453
454 static uint8_t urtw_8225v2_txpwr_cck[] = {
455 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
456 };
457
458 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
459 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
460 };
461
462 static uint8_t urtw_8225v2b_txpwr_cck[] = {
463 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
464 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
465 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
466 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
467 };
468
469 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
470 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
472 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
474 };
475
476 static struct urtw_pair urtw_ratetable[] = {
477 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
478 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
479 { 96, 10 }, { 108, 11 }
480 };
481
482 #if 0
483 static const uint8_t urtw_8187b_reg_table[][3] = {
484 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
485 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
486 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
487 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
488 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
489 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
490 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
491 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
492 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
493 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
494 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
495 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
496 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
497 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
498 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
499 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
500 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
501 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
502 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
503 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
504 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
505 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
506 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
507 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
508 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
509 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
510 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
511 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
512 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
513 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
514 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
515 };
516 #endif
517
518 static usb_callback_t urtw_bulk_rx_callback;
519 static usb_callback_t urtw_bulk_tx_callback;
520 static usb_callback_t urtw_bulk_tx_status_callback;
521
522 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
523 [URTW_8187B_BULK_RX] = {
524 .type = UE_BULK,
525 .endpoint = 0x83,
526 .direction = UE_DIR_IN,
527 .bufsize = MCLBYTES,
528 .flags = {
529 .ext_buffer = 1,
530 .pipe_bof = 1,
531 .short_xfer_ok = 1
532 },
533 .callback = urtw_bulk_rx_callback
534 },
535 [URTW_8187B_BULK_TX_STATUS] = {
536 .type = UE_BULK,
537 .endpoint = 0x89,
538 .direction = UE_DIR_IN,
539 .bufsize = sizeof(uint64_t),
540 .flags = {
541 .pipe_bof = 1,
542 .short_xfer_ok = 1
543 },
544 .callback = urtw_bulk_tx_status_callback
545 },
546 [URTW_8187B_BULK_TX_BE] = {
547 .type = UE_BULK,
548 .endpoint = URTW_8187B_TXPIPE_BE,
549 .direction = UE_DIR_OUT,
550 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
551 .flags = {
552 .force_short_xfer = 1,
553 .pipe_bof = 1,
554 },
555 .callback = urtw_bulk_tx_callback,
556 .timeout = URTW_DATA_TIMEOUT
557 },
558 [URTW_8187B_BULK_TX_BK] = {
559 .type = UE_BULK,
560 .endpoint = URTW_8187B_TXPIPE_BK,
561 .direction = UE_DIR_OUT,
562 .bufsize = URTW_TX_MAXSIZE,
563 .flags = {
564 .ext_buffer = 1,
565 .force_short_xfer = 1,
566 .pipe_bof = 1,
567 },
568 .callback = urtw_bulk_tx_callback,
569 .timeout = URTW_DATA_TIMEOUT
570 },
571 [URTW_8187B_BULK_TX_VI] = {
572 .type = UE_BULK,
573 .endpoint = URTW_8187B_TXPIPE_VI,
574 .direction = UE_DIR_OUT,
575 .bufsize = URTW_TX_MAXSIZE,
576 .flags = {
577 .ext_buffer = 1,
578 .force_short_xfer = 1,
579 .pipe_bof = 1,
580 },
581 .callback = urtw_bulk_tx_callback,
582 .timeout = URTW_DATA_TIMEOUT
583 },
584 [URTW_8187B_BULK_TX_VO] = {
585 .type = UE_BULK,
586 .endpoint = URTW_8187B_TXPIPE_VO,
587 .direction = UE_DIR_OUT,
588 .bufsize = URTW_TX_MAXSIZE,
589 .flags = {
590 .ext_buffer = 1,
591 .force_short_xfer = 1,
592 .pipe_bof = 1,
593 },
594 .callback = urtw_bulk_tx_callback,
595 .timeout = URTW_DATA_TIMEOUT
596 },
597 [URTW_8187B_BULK_TX_EP12] = {
598 .type = UE_BULK,
599 .endpoint = 0xc,
600 .direction = UE_DIR_OUT,
601 .bufsize = URTW_TX_MAXSIZE,
602 .flags = {
603 .ext_buffer = 1,
604 .force_short_xfer = 1,
605 .pipe_bof = 1,
606 },
607 .callback = urtw_bulk_tx_callback,
608 .timeout = URTW_DATA_TIMEOUT
609 }
610 };
611
612 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
613 [URTW_8187L_BULK_RX] = {
614 .type = UE_BULK,
615 .endpoint = 0x81,
616 .direction = UE_DIR_IN,
617 .bufsize = MCLBYTES,
618 .flags = {
619 .ext_buffer = 1,
620 .pipe_bof = 1,
621 .short_xfer_ok = 1
622 },
623 .callback = urtw_bulk_rx_callback
624 },
625 [URTW_8187L_BULK_TX_LOW] = {
626 .type = UE_BULK,
627 .endpoint = 0x2,
628 .direction = UE_DIR_OUT,
629 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
630 .flags = {
631 .force_short_xfer = 1,
632 .pipe_bof = 1,
633 },
634 .callback = urtw_bulk_tx_callback,
635 .timeout = URTW_DATA_TIMEOUT
636 },
637 [URTW_8187L_BULK_TX_NORMAL] = {
638 .type = UE_BULK,
639 .endpoint = 0x3,
640 .direction = UE_DIR_OUT,
641 .bufsize = URTW_TX_MAXSIZE,
642 .flags = {
643 .ext_buffer = 1,
644 .force_short_xfer = 1,
645 .pipe_bof = 1,
646 },
647 .callback = urtw_bulk_tx_callback,
648 .timeout = URTW_DATA_TIMEOUT
649 },
650 };
651
652 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
653 const char [IFNAMSIZ], int, enum ieee80211_opmode,
654 int, const uint8_t [IEEE80211_ADDR_LEN],
655 const uint8_t [IEEE80211_ADDR_LEN]);
656 static void urtw_vap_delete(struct ieee80211vap *);
657 static void urtw_init(struct urtw_softc *);
658 static void urtw_stop(struct urtw_softc *);
659 static void urtw_parent(struct ieee80211com *);
660 static int urtw_transmit(struct ieee80211com *, struct mbuf *);
661 static void urtw_start(struct urtw_softc *);
662 static int urtw_alloc_rx_data_list(struct urtw_softc *);
663 static int urtw_alloc_tx_data_list(struct urtw_softc *);
664 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
665 const struct ieee80211_bpf_params *);
666 static void urtw_scan_start(struct ieee80211com *);
667 static void urtw_scan_end(struct ieee80211com *);
668 static void urtw_getradiocaps(struct ieee80211com *, int, int *,
669 struct ieee80211_channel[]);
670 static void urtw_set_channel(struct ieee80211com *);
671 static void urtw_update_promisc(struct ieee80211com *);
672 static void urtw_update_mcast(struct ieee80211com *);
673 static int urtw_tx_start(struct urtw_softc *,
674 struct ieee80211_node *, struct mbuf *,
675 struct urtw_data *, int);
676 static int urtw_newstate(struct ieee80211vap *,
677 enum ieee80211_state, int);
678 static void urtw_led_ch(void *);
679 static void urtw_ledtask(void *, int);
680 static void urtw_watchdog(void *);
681 static void urtw_set_multi(void *);
682 static int urtw_isbmode(uint16_t);
683 static uint16_t urtw_rtl2rate(uint32_t);
684 static usb_error_t urtw_set_rate(struct urtw_softc *);
685 static usb_error_t urtw_update_msr(struct urtw_softc *);
686 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
687 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
688 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
689 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
690 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
691 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
692 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
693 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
694 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
695 int);
696 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
697 uint32_t *);
698 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
699 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
700 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
701 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
702 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
703 static usb_error_t urtw_led_init(struct urtw_softc *);
704 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
705 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
706 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
707 uint32_t);
708 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
709 uint8_t, uint32_t);
710 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
711 uint32_t);
712 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
713 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
714 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
715 uint16_t);
716 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
717 uint16_t *);
718 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
719 uint32_t *);
720 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
721 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
722 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
723 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
724 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
725 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
726 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
727 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
728 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
729 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
730 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
731 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
732 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
733 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
734 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
735 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
736 static usb_error_t urtw_intr_enable(struct urtw_softc *);
737 static usb_error_t urtw_intr_disable(struct urtw_softc *);
738 static usb_error_t urtw_reset(struct urtw_softc *);
739 static usb_error_t urtw_led_on(struct urtw_softc *, int);
740 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
741 static usb_error_t urtw_led_blink(struct urtw_softc *);
742 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
743 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
744 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
745 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
746 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
747 static usb_error_t urtw_rx_enable(struct urtw_softc *);
748 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
749 static void urtw_free_tx_data_list(struct urtw_softc *);
750 static void urtw_free_rx_data_list(struct urtw_softc *);
751 static void urtw_free_data_list(struct urtw_softc *,
752 struct urtw_data data[], int, int);
753 static usb_error_t urtw_set_macaddr(struct urtw_softc *, const uint8_t *);
754 static usb_error_t urtw_adapter_start(struct urtw_softc *);
755 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
756 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
757 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
758 static usb_error_t urtw_do_request(struct urtw_softc *,
759 struct usb_device_request *, void *);
760 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
761 static usb_error_t urtw_led_off(struct urtw_softc *, int);
762 static void urtw_abort_xfers(struct urtw_softc *);
763 static struct urtw_data *
764 urtw_getbuf(struct urtw_softc *sc);
765 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t,
766 uint8_t);
767 static void urtw_updateslot(struct ieee80211com *);
768 static void urtw_updateslottask(void *, int);
769 static void urtw_sysctl_node(struct urtw_softc *);
770
771 static int
urtw_match(device_t dev)772 urtw_match(device_t dev)
773 {
774 struct usb_attach_arg *uaa = device_get_ivars(dev);
775
776 if (uaa->usb_mode != USB_MODE_HOST)
777 return (ENXIO);
778 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
779 return (ENXIO);
780 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
781 return (ENXIO);
782
783 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
784 }
785
786 static int
urtw_attach(device_t dev)787 urtw_attach(device_t dev)
788 {
789 const struct usb_config *setup_start;
790 int ret = ENXIO;
791 struct urtw_softc *sc = device_get_softc(dev);
792 struct usb_attach_arg *uaa = device_get_ivars(dev);
793 struct ieee80211com *ic = &sc->sc_ic;
794 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */
795 uint16_t n_setup;
796 uint32_t data;
797 usb_error_t error;
798
799 device_set_usb_desc(dev);
800
801 sc->sc_dev = dev;
802 sc->sc_udev = uaa->device;
803 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
804 sc->sc_flags |= URTW_RTL8187B;
805 #ifdef URTW_DEBUG
806 sc->sc_debug = urtw_debug;
807 #endif
808
809 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
810 MTX_DEF);
811 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
812 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
813 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc);
814 callout_init(&sc->sc_watchdog_ch, 0);
815 mbufq_init(&sc->sc_snd, ifqmaxlen);
816
817 if (sc->sc_flags & URTW_RTL8187B) {
818 setup_start = urtw_8187b_usbconfig;
819 n_setup = URTW_8187B_N_XFERS;
820 } else {
821 setup_start = urtw_8187l_usbconfig;
822 n_setup = URTW_8187L_N_XFERS;
823 }
824
825 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
826 setup_start, n_setup, sc, &sc->sc_mtx);
827 if (error) {
828 device_printf(dev, "could not allocate USB transfers, "
829 "err=%s\n", usbd_errstr(error));
830 ret = ENXIO;
831 goto fail0;
832 }
833
834 if (sc->sc_flags & URTW_RTL8187B) {
835 sc->sc_tx_dma_buf =
836 usbd_xfer_get_frame_buffer(sc->sc_xfer[
837 URTW_8187B_BULK_TX_BE], 0);
838 } else {
839 sc->sc_tx_dma_buf =
840 usbd_xfer_get_frame_buffer(sc->sc_xfer[
841 URTW_8187L_BULK_TX_LOW], 0);
842 }
843
844 URTW_LOCK(sc);
845
846 urtw_read32_m(sc, URTW_RX, &data);
847 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
848 URTW_EEPROM_93C46;
849
850 error = urtw_get_rfchip(sc);
851 if (error != 0)
852 goto fail;
853 error = urtw_get_macaddr(sc);
854 if (error != 0)
855 goto fail;
856 error = urtw_get_txpwr(sc);
857 if (error != 0)
858 goto fail;
859 error = urtw_led_init(sc);
860 if (error != 0)
861 goto fail;
862
863 URTW_UNLOCK(sc);
864
865 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
866 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
867 sc->sc_currate = URTW_RIDX_CCK11;
868 sc->sc_preamble_mode = urtw_preamble_mode;
869
870 ic->ic_softc = sc;
871 ic->ic_name = device_get_nameunit(dev);
872 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
873 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
874
875 /* set device capabilities */
876 ic->ic_caps =
877 IEEE80211_C_STA | /* station mode */
878 IEEE80211_C_MONITOR | /* monitor mode supported */
879 IEEE80211_C_TXPMGT | /* tx power management */
880 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
881 IEEE80211_C_SHSLOT | /* short slot time supported */
882 IEEE80211_C_BGSCAN | /* capable of bg scanning */
883 IEEE80211_C_WPA; /* 802.11i */
884
885 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/
886
887 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
888 ic->ic_channels);
889
890 ieee80211_ifattach(ic);
891 ic->ic_raw_xmit = urtw_raw_xmit;
892 ic->ic_scan_start = urtw_scan_start;
893 ic->ic_scan_end = urtw_scan_end;
894 ic->ic_getradiocaps = urtw_getradiocaps;
895 ic->ic_set_channel = urtw_set_channel;
896 ic->ic_updateslot = urtw_updateslot;
897 ic->ic_vap_create = urtw_vap_create;
898 ic->ic_vap_delete = urtw_vap_delete;
899 ic->ic_update_promisc = urtw_update_promisc;
900 ic->ic_update_mcast = urtw_update_mcast;
901 ic->ic_parent = urtw_parent;
902 ic->ic_transmit = urtw_transmit;
903
904 ieee80211_radiotap_attach(ic,
905 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
906 URTW_TX_RADIOTAP_PRESENT,
907 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
908 URTW_RX_RADIOTAP_PRESENT);
909
910 urtw_sysctl_node(sc);
911
912 if (bootverbose)
913 ieee80211_announce(ic);
914 return (0);
915
916 fail:
917 URTW_UNLOCK(sc);
918 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
919 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
920 fail0:
921 return (ret);
922 }
923
924 static int
urtw_detach(device_t dev)925 urtw_detach(device_t dev)
926 {
927 struct urtw_softc *sc = device_get_softc(dev);
928 struct ieee80211com *ic = &sc->sc_ic;
929 unsigned x;
930 unsigned n_xfers;
931
932 /* Prevent further ioctls */
933 URTW_LOCK(sc);
934 sc->sc_flags |= URTW_DETACHED;
935 urtw_stop(sc);
936 URTW_UNLOCK(sc);
937
938 ieee80211_draintask(ic, &sc->sc_updateslot_task);
939 ieee80211_draintask(ic, &sc->sc_led_task);
940
941 usb_callout_drain(&sc->sc_led_ch);
942 callout_drain(&sc->sc_watchdog_ch);
943
944 n_xfers = (sc->sc_flags & URTW_RTL8187B) ?
945 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS;
946
947 /* prevent further allocations from RX/TX data lists */
948 URTW_LOCK(sc);
949 STAILQ_INIT(&sc->sc_tx_active);
950 STAILQ_INIT(&sc->sc_tx_inactive);
951 STAILQ_INIT(&sc->sc_tx_pending);
952
953 STAILQ_INIT(&sc->sc_rx_active);
954 STAILQ_INIT(&sc->sc_rx_inactive);
955 URTW_UNLOCK(sc);
956
957 /* drain USB transfers */
958 for (x = 0; x != n_xfers; x++)
959 usbd_transfer_drain(sc->sc_xfer[x]);
960
961 /* free data buffers */
962 URTW_LOCK(sc);
963 urtw_free_tx_data_list(sc);
964 urtw_free_rx_data_list(sc);
965 URTW_UNLOCK(sc);
966
967 /* free USB transfers and some data buffers */
968 usbd_transfer_unsetup(sc->sc_xfer, n_xfers);
969
970 ieee80211_ifdetach(ic);
971 mbufq_drain(&sc->sc_snd);
972 mtx_destroy(&sc->sc_mtx);
973 return (0);
974 }
975
976 static void
urtw_free_tx_data_list(struct urtw_softc * sc)977 urtw_free_tx_data_list(struct urtw_softc *sc)
978 {
979 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
980 }
981
982 static void
urtw_free_rx_data_list(struct urtw_softc * sc)983 urtw_free_rx_data_list(struct urtw_softc *sc)
984 {
985 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
986 }
987
988 static void
urtw_free_data_list(struct urtw_softc * sc,struct urtw_data data[],int ndata,int fillmbuf)989 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
990 int fillmbuf)
991 {
992 int i;
993
994 for (i = 0; i < ndata; i++) {
995 struct urtw_data *dp = &data[i];
996
997 if (fillmbuf == 1) {
998 if (dp->m != NULL) {
999 m_freem(dp->m);
1000 dp->m = NULL;
1001 dp->buf = NULL;
1002 }
1003 } else {
1004 dp->buf = NULL;
1005 }
1006 if (dp->ni != NULL) {
1007 ieee80211_free_node(dp->ni);
1008 dp->ni = NULL;
1009 }
1010 }
1011 }
1012
1013 static struct ieee80211vap *
urtw_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])1014 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1015 enum ieee80211_opmode opmode, int flags,
1016 const uint8_t bssid[IEEE80211_ADDR_LEN],
1017 const uint8_t mac[IEEE80211_ADDR_LEN])
1018 {
1019 struct urtw_vap *uvp;
1020 struct ieee80211vap *vap;
1021
1022 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1023 return (NULL);
1024 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1025 vap = &uvp->vap;
1026 /* enable s/w bmiss handling for sta mode */
1027
1028 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
1029 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
1030 /* out of memory */
1031 free(uvp, M_80211_VAP);
1032 return (NULL);
1033 }
1034
1035 /* override state transition machine */
1036 uvp->newstate = vap->iv_newstate;
1037 vap->iv_newstate = urtw_newstate;
1038
1039 /* complete setup */
1040 ieee80211_vap_attach(vap, ieee80211_media_change,
1041 ieee80211_media_status, mac);
1042 ic->ic_opmode = opmode;
1043 return (vap);
1044 }
1045
1046 static void
urtw_vap_delete(struct ieee80211vap * vap)1047 urtw_vap_delete(struct ieee80211vap *vap)
1048 {
1049 struct urtw_vap *uvp = URTW_VAP(vap);
1050
1051 ieee80211_vap_detach(vap);
1052 free(uvp, M_80211_VAP);
1053 }
1054
1055 static void
urtw_init(struct urtw_softc * sc)1056 urtw_init(struct urtw_softc *sc)
1057 {
1058 usb_error_t error;
1059 int ret;
1060
1061 URTW_ASSERT_LOCKED(sc);
1062
1063 if (sc->sc_flags & URTW_RUNNING)
1064 urtw_stop(sc);
1065
1066 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
1067 urtw_adapter_start(sc);
1068 if (error != 0)
1069 goto fail;
1070
1071 /* reset softc variables */
1072 sc->sc_txtimer = 0;
1073
1074 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1075 ret = urtw_alloc_rx_data_list(sc);
1076 if (ret != 0)
1077 goto fail;
1078 ret = urtw_alloc_tx_data_list(sc);
1079 if (ret != 0)
1080 goto fail;
1081 sc->sc_flags |= URTW_INIT_ONCE;
1082 }
1083
1084 error = urtw_rx_enable(sc);
1085 if (error != 0)
1086 goto fail;
1087 error = urtw_tx_enable(sc);
1088 if (error != 0)
1089 goto fail;
1090
1091 if (sc->sc_flags & URTW_RTL8187B)
1092 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]);
1093
1094 sc->sc_flags |= URTW_RUNNING;
1095
1096 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1097 fail:
1098 return;
1099 }
1100
1101 static usb_error_t
urtw_adapter_start_b(struct urtw_softc * sc)1102 urtw_adapter_start_b(struct urtw_softc *sc)
1103 {
1104 uint8_t data8;
1105 usb_error_t error;
1106
1107 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1108 if (error)
1109 goto fail;
1110
1111 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1112 urtw_write8_m(sc, URTW_CONFIG3,
1113 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1114 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1115 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1116 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1117
1118 urtw_write8_m(sc, 0x61, 0x10);
1119 urtw_read8_m(sc, 0x62, &data8);
1120 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1121 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1122
1123 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1124 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1125 urtw_write8_m(sc, URTW_CONFIG3, data8);
1126
1127 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1128 if (error)
1129 goto fail;
1130
1131 error = urtw_8187b_cmd_reset(sc);
1132 if (error)
1133 goto fail;
1134
1135 error = sc->sc_rf_init(sc);
1136 if (error != 0)
1137 goto fail;
1138 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1139
1140 /* fix RTL8187B RX stall */
1141 error = urtw_intr_enable(sc);
1142 if (error)
1143 goto fail;
1144
1145 error = urtw_write8e(sc, 0x41, 0xf4);
1146 if (error)
1147 goto fail;
1148 error = urtw_write8e(sc, 0x40, 0x00);
1149 if (error)
1150 goto fail;
1151 error = urtw_write8e(sc, 0x42, 0x00);
1152 if (error)
1153 goto fail;
1154 error = urtw_write8e(sc, 0x42, 0x01);
1155 if (error)
1156 goto fail;
1157 error = urtw_write8e(sc, 0x40, 0x0f);
1158 if (error)
1159 goto fail;
1160 error = urtw_write8e(sc, 0x42, 0x00);
1161 if (error)
1162 goto fail;
1163 error = urtw_write8e(sc, 0x42, 0x01);
1164 if (error)
1165 goto fail;
1166
1167 urtw_read8_m(sc, 0xdb, &data8);
1168 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1169 urtw_write16_m(sc, 0x372, 0x59fa);
1170 urtw_write16_m(sc, 0x374, 0x59d2);
1171 urtw_write16_m(sc, 0x376, 0x59d2);
1172 urtw_write16_m(sc, 0x378, 0x19fa);
1173 urtw_write16_m(sc, 0x37a, 0x19fa);
1174 urtw_write16_m(sc, 0x37c, 0x00d0);
1175 urtw_write8_m(sc, 0x61, 0);
1176
1177 urtw_write8_m(sc, 0x180, 0x0f);
1178 urtw_write8_m(sc, 0x183, 0x03);
1179 urtw_write8_m(sc, 0xda, 0x10);
1180 urtw_write8_m(sc, 0x24d, 0x08);
1181 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
1182
1183 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */
1184 fail:
1185 return (error);
1186 }
1187
1188 static usb_error_t
urtw_set_macaddr(struct urtw_softc * sc,const uint8_t * macaddr)1189 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *macaddr)
1190 {
1191 usb_error_t error;
1192
1193 urtw_write32_m(sc, URTW_MAC0, ((const uint32_t *)macaddr)[0]);
1194 urtw_write16_m(sc, URTW_MAC4, ((const uint32_t *)macaddr)[1] & 0xffff);
1195
1196 fail:
1197 return (error);
1198 }
1199
1200 static usb_error_t
urtw_adapter_start(struct urtw_softc * sc)1201 urtw_adapter_start(struct urtw_softc *sc)
1202 {
1203 struct ieee80211com *ic = &sc->sc_ic;
1204 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1205 const uint8_t *macaddr;
1206 usb_error_t error;
1207
1208 error = urtw_reset(sc);
1209 if (error)
1210 goto fail;
1211
1212 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1213 urtw_write8_m(sc, URTW_GPIO, 0);
1214
1215 /* for led */
1216 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1217 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1218 if (error != 0)
1219 goto fail;
1220
1221 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1222 if (error)
1223 goto fail;
1224 /* applying MAC address again. */
1225 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
1226 urtw_set_macaddr(sc, macaddr);
1227 if (error)
1228 goto fail;
1229
1230 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1231 if (error)
1232 goto fail;
1233
1234 error = urtw_update_msr(sc);
1235 if (error)
1236 goto fail;
1237
1238 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1239 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1240 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1241 error = urtw_set_rate(sc);
1242 if (error != 0)
1243 goto fail;
1244
1245 error = sc->sc_rf_init(sc);
1246 if (error != 0)
1247 goto fail;
1248 if (sc->sc_rf_set_sens != NULL)
1249 sc->sc_rf_set_sens(sc, sc->sc_sens);
1250
1251 /* XXX correct? to call write16 */
1252 urtw_write16_m(sc, URTW_PSR, 1);
1253 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1254 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1255 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1256 /* XXX correct? to call write16 */
1257 urtw_write16_m(sc, URTW_PSR, 0);
1258 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1259
1260 error = urtw_intr_enable(sc);
1261 if (error != 0)
1262 goto fail;
1263
1264 fail:
1265 return (error);
1266 }
1267
1268 static usb_error_t
urtw_set_mode(struct urtw_softc * sc,uint32_t mode)1269 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1270 {
1271 uint8_t data;
1272 usb_error_t error;
1273
1274 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1275 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1276 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1277 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1278 fail:
1279 return (error);
1280 }
1281
1282 static void
urtw_pause_ms(struct urtw_softc * sc,int delay)1283 urtw_pause_ms(struct urtw_softc *sc, int delay)
1284 {
1285 usb_pause_mtx(&sc->sc_mtx, USB_MS_TO_TICKS(delay));
1286 }
1287
1288 static usb_error_t
urtw_8187b_cmd_reset(struct urtw_softc * sc)1289 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1290 {
1291 int i;
1292 uint8_t data8;
1293 usb_error_t error;
1294
1295 /* XXX the code can be duplicate with urtw_reset(). */
1296 urtw_read8_m(sc, URTW_CMD, &data8);
1297 data8 = (data8 & 0x2) | URTW_CMD_RST;
1298 urtw_write8_m(sc, URTW_CMD, data8);
1299
1300 for (i = 0; i < 20; i++) {
1301 urtw_pause_ms(sc, 2);
1302 urtw_read8_m(sc, URTW_CMD, &data8);
1303 if (!(data8 & URTW_CMD_RST))
1304 break;
1305 }
1306 if (i >= 20) {
1307 device_printf(sc->sc_dev, "reset timeout\n");
1308 goto fail;
1309 }
1310 fail:
1311 return (error);
1312 }
1313
1314 static usb_error_t
urtw_do_request(struct urtw_softc * sc,struct usb_device_request * req,void * data)1315 urtw_do_request(struct urtw_softc *sc,
1316 struct usb_device_request *req, void *data)
1317 {
1318 usb_error_t err;
1319 int ntries = 10;
1320
1321 URTW_ASSERT_LOCKED(sc);
1322
1323 while (ntries--) {
1324 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1325 req, data, 0, NULL, 250 /* ms */);
1326 if (err == 0)
1327 break;
1328
1329 DPRINTF(sc, URTW_DEBUG_INIT,
1330 "Control request failed, %s (retrying)\n",
1331 usbd_errstr(err));
1332 urtw_pause_ms(sc, 10);
1333 }
1334 return (err);
1335 }
1336
1337 static void
urtw_stop(struct urtw_softc * sc)1338 urtw_stop(struct urtw_softc *sc)
1339 {
1340 uint8_t data8;
1341 usb_error_t error;
1342
1343 URTW_ASSERT_LOCKED(sc);
1344
1345 sc->sc_flags &= ~URTW_RUNNING;
1346
1347 error = urtw_intr_disable(sc);
1348 if (error)
1349 goto fail;
1350 urtw_read8_m(sc, URTW_CMD, &data8);
1351 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1352 urtw_write8_m(sc, URTW_CMD, data8);
1353
1354 error = sc->sc_rf_stop(sc);
1355 if (error != 0)
1356 goto fail;
1357
1358 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1359 if (error)
1360 goto fail;
1361 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1362 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1363 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1364 if (error)
1365 goto fail;
1366 fail:
1367 if (error)
1368 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1369 usbd_errstr(error));
1370
1371 usb_callout_stop(&sc->sc_led_ch);
1372 callout_stop(&sc->sc_watchdog_ch);
1373
1374 urtw_abort_xfers(sc);
1375 }
1376
1377 static void
urtw_abort_xfers(struct urtw_softc * sc)1378 urtw_abort_xfers(struct urtw_softc *sc)
1379 {
1380 int i, max;
1381
1382 URTW_ASSERT_LOCKED(sc);
1383
1384 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1385 URTW_8187L_N_XFERS;
1386
1387 /* abort any pending transfers */
1388 for (i = 0; i < max; i++)
1389 usbd_transfer_stop(sc->sc_xfer[i]);
1390 }
1391
1392 static void
urtw_parent(struct ieee80211com * ic)1393 urtw_parent(struct ieee80211com *ic)
1394 {
1395 struct urtw_softc *sc = ic->ic_softc;
1396 int startall = 0;
1397
1398 URTW_LOCK(sc);
1399 if (sc->sc_flags & URTW_DETACHED) {
1400 URTW_UNLOCK(sc);
1401 return;
1402 }
1403
1404 if (ic->ic_nrunning > 0) {
1405 if (sc->sc_flags & URTW_RUNNING) {
1406 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0)
1407 urtw_set_multi(sc);
1408 } else {
1409 urtw_init(sc);
1410 startall = 1;
1411 }
1412 } else if (sc->sc_flags & URTW_RUNNING)
1413 urtw_stop(sc);
1414 URTW_UNLOCK(sc);
1415 if (startall)
1416 ieee80211_start_all(ic);
1417 }
1418
1419 static int
urtw_transmit(struct ieee80211com * ic,struct mbuf * m)1420 urtw_transmit(struct ieee80211com *ic, struct mbuf *m)
1421 {
1422 struct urtw_softc *sc = ic->ic_softc;
1423 int error;
1424
1425 URTW_LOCK(sc);
1426 if ((sc->sc_flags & URTW_RUNNING) == 0) {
1427 URTW_UNLOCK(sc);
1428 return (ENXIO);
1429 }
1430 error = mbufq_enqueue(&sc->sc_snd, m);
1431 if (error) {
1432 URTW_UNLOCK(sc);
1433 return (error);
1434 }
1435 urtw_start(sc);
1436 URTW_UNLOCK(sc);
1437
1438 return (0);
1439 }
1440
1441 static void
urtw_start(struct urtw_softc * sc)1442 urtw_start(struct urtw_softc *sc)
1443 {
1444 struct urtw_data *bf;
1445 struct ieee80211_node *ni;
1446 struct mbuf *m;
1447
1448 URTW_ASSERT_LOCKED(sc);
1449
1450 if ((sc->sc_flags & URTW_RUNNING) == 0)
1451 return;
1452
1453 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1454 bf = urtw_getbuf(sc);
1455 if (bf == NULL) {
1456 mbufq_prepend(&sc->sc_snd, m);
1457 break;
1458 }
1459
1460 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1461 m->m_pkthdr.rcvif = NULL;
1462
1463 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1464 if_inc_counter(ni->ni_vap->iv_ifp,
1465 IFCOUNTER_OERRORS, 1);
1466 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1467 ieee80211_free_node(ni);
1468 break;
1469 }
1470
1471 sc->sc_txtimer = 5;
1472 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1473 }
1474 }
1475
1476 static int
urtw_alloc_data_list(struct urtw_softc * sc,struct urtw_data data[],int ndata,int maxsz,void * dma_buf)1477 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1478 int ndata, int maxsz, void *dma_buf)
1479 {
1480 int i, error;
1481
1482 for (i = 0; i < ndata; i++) {
1483 struct urtw_data *dp = &data[i];
1484
1485 dp->sc = sc;
1486 if (dma_buf == NULL) {
1487 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1488 if (dp->m == NULL) {
1489 device_printf(sc->sc_dev,
1490 "could not allocate rx mbuf\n");
1491 error = ENOMEM;
1492 goto fail;
1493 }
1494 dp->buf = mtod(dp->m, uint8_t *);
1495 } else {
1496 dp->m = NULL;
1497 dp->buf = ((uint8_t *)dma_buf) +
1498 (i * maxsz);
1499 }
1500 dp->ni = NULL;
1501 }
1502 return (0);
1503
1504 fail: urtw_free_data_list(sc, data, ndata, 1);
1505 return (error);
1506 }
1507
1508 static int
urtw_alloc_rx_data_list(struct urtw_softc * sc)1509 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1510 {
1511 int error, i;
1512
1513 error = urtw_alloc_data_list(sc,
1514 sc->sc_rx, URTW_RX_DATA_LIST_COUNT,
1515 MCLBYTES, NULL /* mbufs */);
1516 if (error != 0)
1517 return (error);
1518
1519 STAILQ_INIT(&sc->sc_rx_active);
1520 STAILQ_INIT(&sc->sc_rx_inactive);
1521
1522 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1523 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1524
1525 return (0);
1526 }
1527
1528 static int
urtw_alloc_tx_data_list(struct urtw_softc * sc)1529 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1530 {
1531 int error, i;
1532
1533 error = urtw_alloc_data_list(sc,
1534 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1535 sc->sc_tx_dma_buf /* no mbufs */);
1536 if (error != 0)
1537 return (error);
1538
1539 STAILQ_INIT(&sc->sc_tx_active);
1540 STAILQ_INIT(&sc->sc_tx_inactive);
1541 STAILQ_INIT(&sc->sc_tx_pending);
1542
1543 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1544 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1545 next);
1546
1547 return (0);
1548 }
1549
1550 static int
urtw_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1551 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1552 const struct ieee80211_bpf_params *params)
1553 {
1554 struct ieee80211com *ic = ni->ni_ic;
1555 struct urtw_softc *sc = ic->ic_softc;
1556 struct urtw_data *bf;
1557
1558 /* prevent management frames from being sent if we're not ready */
1559 if (!(sc->sc_flags & URTW_RUNNING)) {
1560 m_freem(m);
1561 return ENETDOWN;
1562 }
1563 URTW_LOCK(sc);
1564 bf = urtw_getbuf(sc);
1565 if (bf == NULL) {
1566 m_freem(m);
1567 URTW_UNLOCK(sc);
1568 return (ENOBUFS); /* XXX */
1569 }
1570
1571 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1572 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1573 URTW_UNLOCK(sc);
1574 return (EIO);
1575 }
1576 URTW_UNLOCK(sc);
1577
1578 sc->sc_txtimer = 5;
1579 return (0);
1580 }
1581
1582 static void
urtw_scan_start(struct ieee80211com * ic)1583 urtw_scan_start(struct ieee80211com *ic)
1584 {
1585
1586 /* XXX do nothing? */
1587 }
1588
1589 static void
urtw_scan_end(struct ieee80211com * ic)1590 urtw_scan_end(struct ieee80211com *ic)
1591 {
1592
1593 /* XXX do nothing? */
1594 }
1595
1596 static void
urtw_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1597 urtw_getradiocaps(struct ieee80211com *ic,
1598 int maxchans, int *nchans, struct ieee80211_channel chans[])
1599 {
1600 uint8_t bands[IEEE80211_MODE_BYTES];
1601
1602 memset(bands, 0, sizeof(bands));
1603 setbit(bands, IEEE80211_MODE_11B);
1604 setbit(bands, IEEE80211_MODE_11G);
1605 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1606 }
1607
1608 static void
urtw_set_channel(struct ieee80211com * ic)1609 urtw_set_channel(struct ieee80211com *ic)
1610 {
1611 struct urtw_softc *sc = ic->ic_softc;
1612 uint32_t data, orig;
1613 usb_error_t error;
1614
1615 /*
1616 * if the user set a channel explicitly using ifconfig(8) this function
1617 * can be called earlier than we're expected that in some cases the
1618 * initialization would be failed if setting a channel is called before
1619 * the init have done.
1620 */
1621 if (!(sc->sc_flags & URTW_RUNNING))
1622 return;
1623
1624 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1625 return;
1626
1627 URTW_LOCK(sc);
1628
1629 /*
1630 * during changing th channel we need to temporarily be disable
1631 * TX.
1632 */
1633 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1634 data = orig & ~URTW_TX_LOOPBACK_MASK;
1635 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1636
1637 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1638 if (error != 0)
1639 goto fail;
1640 urtw_pause_ms(sc, 10);
1641 urtw_write32_m(sc, URTW_TX_CONF, orig);
1642
1643 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1644 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1645 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1646 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1647
1648 fail:
1649 URTW_UNLOCK(sc);
1650
1651 sc->sc_curchan = ic->ic_curchan;
1652
1653 if (error != 0)
1654 device_printf(sc->sc_dev, "could not change the channel\n");
1655 }
1656
1657 static void
urtw_update_promisc(struct ieee80211com * ic)1658 urtw_update_promisc(struct ieee80211com *ic)
1659 {
1660 struct urtw_softc *sc = ic->ic_softc;
1661
1662 URTW_LOCK(sc);
1663 if (sc->sc_flags & URTW_RUNNING)
1664 urtw_rx_setconf(sc);
1665 URTW_UNLOCK(sc);
1666 }
1667
1668 static void
urtw_update_mcast(struct ieee80211com * ic)1669 urtw_update_mcast(struct ieee80211com *ic)
1670 {
1671
1672 /* XXX do nothing? */
1673 }
1674
1675 static int
urtw_tx_start(struct urtw_softc * sc,struct ieee80211_node * ni,struct mbuf * m0,struct urtw_data * data,int prior)1676 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1677 struct urtw_data *data, int prior)
1678 {
1679 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1680 struct ieee80211_key *k;
1681 const struct ieee80211_txparam *tp = ni->ni_txparms;
1682 struct ieee80211com *ic = &sc->sc_ic;
1683 struct ieee80211vap *vap = ni->ni_vap;
1684 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1685 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1686 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1687 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1688 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1689 };
1690 struct usb_xfer *xfer;
1691 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type,
1692 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast;
1693 uint16_t acktime, rtstime, ctstime;
1694 uint32_t flags;
1695 usb_error_t error;
1696
1697 URTW_ASSERT_LOCKED(sc);
1698
1699 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1700 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1701
1702 /*
1703 * Software crypto.
1704 */
1705 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1706 k = ieee80211_crypto_encap(ni, m0);
1707 if (k == NULL) {
1708 device_printf(sc->sc_dev,
1709 "ieee80211_crypto_encap returns NULL.\n");
1710 /* XXX we don't expect the fragmented frames */
1711 m_freem(m0);
1712 return (ENOBUFS);
1713 }
1714
1715 /* in case packet header moved, reset pointer */
1716 wh = mtod(m0, struct ieee80211_frame *);
1717 }
1718
1719 if (ieee80211_radiotap_active_vap(vap)) {
1720 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1721
1722 tap->wt_flags = 0;
1723 ieee80211_radiotap_tx(vap, m0);
1724 }
1725
1726 if (IEEE80211_IS_MGMT(wh) || IEEE80211_IS_CTL(wh) ||
1727 (m0->m_flags & M_EAPOL) != 0) {
1728 rate = tp->mgmtrate;
1729 } else {
1730 /* for data frames */
1731 if (ismcast)
1732 rate = tp->mcastrate;
1733 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1734 rate = tp->ucastrate;
1735 else
1736 rate = urtw_rtl2rate(sc->sc_currate);
1737 }
1738
1739 sc->sc_stats.txrates[sc->sc_currate]++;
1740
1741 if (ismcast)
1742 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1743 IEEE80211_CRC_LEN, rate, 0, 0);
1744 else {
1745 acktime = urtw_compute_txtime(14, 2,0, 0);
1746 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1747 rtsenable = 1;
1748 ctsenable = 0;
1749 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1750 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1751 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1752 IEEE80211_CRC_LEN, rate, 0, isshort);
1753 rtsdur = ctstime + pkttime + acktime +
1754 3 * URTW_ASIFS_TIME;
1755 txdur = rtstime + rtsdur;
1756 } else {
1757 rtsenable = ctsenable = rtsdur = 0;
1758 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1759 IEEE80211_CRC_LEN, rate, 0, isshort);
1760 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1761 }
1762
1763 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1764 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1765 IEEE80211_CRC_LEN, rate, 0, isshort) +
1766 3 * URTW_ASIFS_TIME +
1767 2 * acktime;
1768 else
1769 dur = URTW_ASIFS_TIME + acktime;
1770 }
1771 USETW(wh->i_dur, dur);
1772
1773 xferlen = m0->m_pkthdr.len;
1774 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1775 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1776 xferlen += 1;
1777
1778 memset(data->buf, 0, URTW_TX_MAXSIZE);
1779 flags = m0->m_pkthdr.len & 0xfff;
1780 flags |= URTW_TX_FLAG_NO_ENC;
1781 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1782 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1783 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1784 (sc->sc_currate != 0))
1785 flags |= URTW_TX_FLAG_SPLCP;
1786 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1787 flags |= URTW_TX_FLAG_MOREFRAG;
1788
1789 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1790
1791 if (sc->sc_flags & URTW_RTL8187B) {
1792 struct urtw_8187b_txhdr *tx;
1793
1794 tx = (struct urtw_8187b_txhdr *)data->buf;
1795 if (ctsenable)
1796 flags |= URTW_TX_FLAG_CTS;
1797 if (rtsenable) {
1798 flags |= URTW_TX_FLAG_RTS;
1799 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT;
1800 tx->rtsdur = rtsdur;
1801 }
1802 tx->flag = htole32(flags);
1803 tx->txdur = txdur;
1804 if (IEEE80211_IS_MGMT_PROBE_RESP(wh))
1805 tx->retry = 1;
1806 else
1807 tx->retry = URTW_TX_MAXRETRY;
1808 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1809 } else {
1810 struct urtw_8187l_txhdr *tx;
1811
1812 tx = (struct urtw_8187l_txhdr *)data->buf;
1813 if (rtsenable) {
1814 flags |= URTW_TX_FLAG_RTS;
1815 tx->rtsdur = rtsdur;
1816 }
1817 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT;
1818 tx->flag = htole32(flags);
1819 tx->retry = 3; /* CW minimum */
1820 tx->retry |= 7 << 4; /* CW maximum */
1821 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */
1822 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1823 }
1824
1825 data->buflen = xferlen;
1826 data->ni = ni;
1827 data->m = m0;
1828
1829 if (sc->sc_flags & URTW_RTL8187B) {
1830 switch (type) {
1831 case IEEE80211_FC0_TYPE_CTL:
1832 case IEEE80211_FC0_TYPE_MGT:
1833 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1834 break;
1835 default:
1836 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1837 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1838 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1839 break;
1840 }
1841 } else
1842 xfer = (prior == URTW_PRIORITY_LOW) ?
1843 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1844 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1845
1846 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1847 usbd_transfer_start(xfer);
1848
1849 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1850 if (error != 0)
1851 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1852 error);
1853 return (0);
1854 }
1855
1856 static int
urtw_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1857 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1858 {
1859 struct ieee80211com *ic = vap->iv_ic;
1860 struct urtw_softc *sc = ic->ic_softc;
1861 struct urtw_vap *uvp = URTW_VAP(vap);
1862 struct ieee80211_node *ni;
1863 usb_error_t error = 0;
1864
1865 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1866 ieee80211_state_name[vap->iv_state],
1867 ieee80211_state_name[nstate]);
1868
1869 sc->sc_state = nstate;
1870
1871 IEEE80211_UNLOCK(ic);
1872 URTW_LOCK(sc);
1873 usb_callout_stop(&sc->sc_led_ch);
1874 callout_stop(&sc->sc_watchdog_ch);
1875
1876 switch (nstate) {
1877 case IEEE80211_S_INIT:
1878 case IEEE80211_S_SCAN:
1879 case IEEE80211_S_AUTH:
1880 case IEEE80211_S_ASSOC:
1881 break;
1882 case IEEE80211_S_RUN:
1883 ni = ieee80211_ref_node(vap->iv_bss);
1884 /* setting bssid. */
1885 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1886 urtw_write16_m(sc, URTW_BSSID + 4,
1887 ((uint16_t *)ni->ni_bssid)[2]);
1888 urtw_update_msr(sc);
1889 /* XXX maybe the below would be incorrect. */
1890 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1891 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1892 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1893 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1894 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1895 if (error != 0)
1896 device_printf(sc->sc_dev,
1897 "could not control LED (%d)\n", error);
1898 ieee80211_free_node(ni);
1899 break;
1900 default:
1901 break;
1902 }
1903 fail:
1904 URTW_UNLOCK(sc);
1905 IEEE80211_LOCK(ic);
1906 return (uvp->newstate(vap, nstate, arg));
1907 }
1908
1909 static void
urtw_watchdog(void * arg)1910 urtw_watchdog(void *arg)
1911 {
1912 struct urtw_softc *sc = arg;
1913 struct ieee80211com *ic = &sc->sc_ic;
1914
1915 if (sc->sc_txtimer > 0) {
1916 if (--sc->sc_txtimer == 0) {
1917 device_printf(sc->sc_dev, "device timeout\n");
1918 counter_u64_add(ic->ic_oerrors, 1);
1919 ieee80211_restart_all(ic);
1920 return;
1921 }
1922 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1923 }
1924 }
1925
1926 static void
urtw_set_multi(void * arg)1927 urtw_set_multi(void *arg)
1928 {
1929 /* XXX don't know how to set a device. Lack of docs. */
1930 }
1931
1932 static usb_error_t
urtw_set_rate(struct urtw_softc * sc)1933 urtw_set_rate(struct urtw_softc *sc)
1934 {
1935 int i, basic_rate, min_rr_rate, max_rr_rate;
1936 uint16_t data;
1937 usb_error_t error;
1938
1939 basic_rate = URTW_RIDX_OFDM24;
1940 min_rr_rate = URTW_RIDX_OFDM6;
1941 max_rr_rate = URTW_RIDX_OFDM24;
1942
1943 urtw_write8_m(sc, URTW_RESP_RATE,
1944 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1945 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1946
1947 urtw_read16_m(sc, URTW_BRSR, &data);
1948 data &= ~URTW_BRSR_MBR_8185;
1949
1950 for (i = 0; i <= basic_rate; i++)
1951 data |= (1 << i);
1952
1953 urtw_write16_m(sc, URTW_BRSR, data);
1954 fail:
1955 return (error);
1956 }
1957
1958 static uint16_t
urtw_rtl2rate(uint32_t rate)1959 urtw_rtl2rate(uint32_t rate)
1960 {
1961 unsigned i;
1962
1963 for (i = 0; i < nitems(urtw_ratetable); i++) {
1964 if (rate == urtw_ratetable[i].val)
1965 return urtw_ratetable[i].reg;
1966 }
1967
1968 return (0);
1969 }
1970
1971 static usb_error_t
urtw_update_msr(struct urtw_softc * sc)1972 urtw_update_msr(struct urtw_softc *sc)
1973 {
1974 struct ieee80211com *ic = &sc->sc_ic;
1975 uint8_t data;
1976 usb_error_t error;
1977
1978 urtw_read8_m(sc, URTW_MSR, &data);
1979 data &= ~URTW_MSR_LINK_MASK;
1980
1981 if (sc->sc_state == IEEE80211_S_RUN) {
1982 switch (ic->ic_opmode) {
1983 case IEEE80211_M_STA:
1984 case IEEE80211_M_MONITOR:
1985 data |= URTW_MSR_LINK_STA;
1986 if (sc->sc_flags & URTW_RTL8187B)
1987 data |= URTW_MSR_LINK_ENEDCA;
1988 break;
1989 case IEEE80211_M_IBSS:
1990 data |= URTW_MSR_LINK_ADHOC;
1991 break;
1992 case IEEE80211_M_HOSTAP:
1993 data |= URTW_MSR_LINK_HOSTAP;
1994 break;
1995 default:
1996 DPRINTF(sc, URTW_DEBUG_STATE,
1997 "unsupported operation mode 0x%x\n",
1998 ic->ic_opmode);
1999 error = USB_ERR_INVAL;
2000 goto fail;
2001 }
2002 } else
2003 data |= URTW_MSR_LINK_NONE;
2004
2005 urtw_write8_m(sc, URTW_MSR, data);
2006 fail:
2007 return (error);
2008 }
2009
2010 static usb_error_t
urtw_read8_c(struct urtw_softc * sc,int val,uint8_t * data)2011 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2012 {
2013 struct usb_device_request req;
2014 usb_error_t error;
2015
2016 URTW_ASSERT_LOCKED(sc);
2017
2018 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2019 req.bRequest = URTW_8187_GETREGS_REQ;
2020 USETW(req.wValue, (val & 0xff) | 0xff00);
2021 USETW(req.wIndex, (val >> 8) & 0x3);
2022 USETW(req.wLength, sizeof(uint8_t));
2023
2024 error = urtw_do_request(sc, &req, data);
2025 return (error);
2026 }
2027
2028 static usb_error_t
urtw_read16_c(struct urtw_softc * sc,int val,uint16_t * data)2029 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2030 {
2031 struct usb_device_request req;
2032 usb_error_t error;
2033
2034 URTW_ASSERT_LOCKED(sc);
2035
2036 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2037 req.bRequest = URTW_8187_GETREGS_REQ;
2038 USETW(req.wValue, (val & 0xff) | 0xff00);
2039 USETW(req.wIndex, (val >> 8) & 0x3);
2040 USETW(req.wLength, sizeof(uint16_t));
2041
2042 error = urtw_do_request(sc, &req, data);
2043 return (error);
2044 }
2045
2046 static usb_error_t
urtw_read32_c(struct urtw_softc * sc,int val,uint32_t * data)2047 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2048 {
2049 struct usb_device_request req;
2050 usb_error_t error;
2051
2052 URTW_ASSERT_LOCKED(sc);
2053
2054 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2055 req.bRequest = URTW_8187_GETREGS_REQ;
2056 USETW(req.wValue, (val & 0xff) | 0xff00);
2057 USETW(req.wIndex, (val >> 8) & 0x3);
2058 USETW(req.wLength, sizeof(uint32_t));
2059
2060 error = urtw_do_request(sc, &req, data);
2061 return (error);
2062 }
2063
2064 static usb_error_t
urtw_write8_c(struct urtw_softc * sc,int val,uint8_t data)2065 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2066 {
2067 struct usb_device_request req;
2068
2069 URTW_ASSERT_LOCKED(sc);
2070
2071 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2072 req.bRequest = URTW_8187_SETREGS_REQ;
2073 USETW(req.wValue, (val & 0xff) | 0xff00);
2074 USETW(req.wIndex, (val >> 8) & 0x3);
2075 USETW(req.wLength, sizeof(uint8_t));
2076
2077 return (urtw_do_request(sc, &req, &data));
2078 }
2079
2080 static usb_error_t
urtw_write16_c(struct urtw_softc * sc,int val,uint16_t data)2081 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2082 {
2083 struct usb_device_request req;
2084
2085 URTW_ASSERT_LOCKED(sc);
2086
2087 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2088 req.bRequest = URTW_8187_SETREGS_REQ;
2089 USETW(req.wValue, (val & 0xff) | 0xff00);
2090 USETW(req.wIndex, (val >> 8) & 0x3);
2091 USETW(req.wLength, sizeof(uint16_t));
2092
2093 return (urtw_do_request(sc, &req, &data));
2094 }
2095
2096 static usb_error_t
urtw_write32_c(struct urtw_softc * sc,int val,uint32_t data)2097 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2098 {
2099 struct usb_device_request req;
2100
2101 URTW_ASSERT_LOCKED(sc);
2102
2103 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2104 req.bRequest = URTW_8187_SETREGS_REQ;
2105 USETW(req.wValue, (val & 0xff) | 0xff00);
2106 USETW(req.wIndex, (val >> 8) & 0x3);
2107 USETW(req.wLength, sizeof(uint32_t));
2108
2109 return (urtw_do_request(sc, &req, &data));
2110 }
2111
2112 static usb_error_t
urtw_get_macaddr(struct urtw_softc * sc)2113 urtw_get_macaddr(struct urtw_softc *sc)
2114 {
2115 struct ieee80211com *ic = &sc->sc_ic;
2116 uint32_t data;
2117 usb_error_t error;
2118
2119 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2120 if (error != 0)
2121 goto fail;
2122 ic->ic_macaddr[0] = data & 0xff;
2123 ic->ic_macaddr[1] = (data & 0xff00) >> 8;
2124 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2125 if (error != 0)
2126 goto fail;
2127 ic->ic_macaddr[2] = data & 0xff;
2128 ic->ic_macaddr[3] = (data & 0xff00) >> 8;
2129 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2130 if (error != 0)
2131 goto fail;
2132 ic->ic_macaddr[4] = data & 0xff;
2133 ic->ic_macaddr[5] = (data & 0xff00) >> 8;
2134 fail:
2135 return (error);
2136 }
2137
2138 static usb_error_t
urtw_eprom_read32(struct urtw_softc * sc,uint32_t addr,uint32_t * data)2139 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2140 {
2141 #define URTW_READCMD_LEN 3
2142 int addrlen, i;
2143 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2144 usb_error_t error;
2145
2146 /* NB: make sure the buffer is initialized */
2147 *data = 0;
2148
2149 /* enable EPROM programming */
2150 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2151 DELAY(URTW_EPROM_DELAY);
2152
2153 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2154 if (error != 0)
2155 goto fail;
2156 error = urtw_eprom_ck(sc);
2157 if (error != 0)
2158 goto fail;
2159 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2160 if (error != 0)
2161 goto fail;
2162 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2163 addrlen = 8;
2164 addrstr[0] = addr & (1 << 7);
2165 addrstr[1] = addr & (1 << 6);
2166 addrstr[2] = addr & (1 << 5);
2167 addrstr[3] = addr & (1 << 4);
2168 addrstr[4] = addr & (1 << 3);
2169 addrstr[5] = addr & (1 << 2);
2170 addrstr[6] = addr & (1 << 1);
2171 addrstr[7] = addr & (1 << 0);
2172 } else {
2173 addrlen=6;
2174 addrstr[0] = addr & (1 << 5);
2175 addrstr[1] = addr & (1 << 4);
2176 addrstr[2] = addr & (1 << 3);
2177 addrstr[3] = addr & (1 << 2);
2178 addrstr[4] = addr & (1 << 1);
2179 addrstr[5] = addr & (1 << 0);
2180 }
2181 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2182 if (error != 0)
2183 goto fail;
2184
2185 error = urtw_eprom_writebit(sc, 0);
2186 if (error != 0)
2187 goto fail;
2188
2189 for (i = 0; i < 16; i++) {
2190 error = urtw_eprom_ck(sc);
2191 if (error != 0)
2192 goto fail;
2193 error = urtw_eprom_readbit(sc, &data16);
2194 if (error != 0)
2195 goto fail;
2196
2197 (*data) |= (data16 << (15 - i));
2198 }
2199
2200 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2201 if (error != 0)
2202 goto fail;
2203 error = urtw_eprom_ck(sc);
2204 if (error != 0)
2205 goto fail;
2206
2207 /* now disable EPROM programming */
2208 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2209 fail:
2210 return (error);
2211 #undef URTW_READCMD_LEN
2212 }
2213
2214 static usb_error_t
urtw_eprom_cs(struct urtw_softc * sc,int able)2215 urtw_eprom_cs(struct urtw_softc *sc, int able)
2216 {
2217 uint8_t data;
2218 usb_error_t error;
2219
2220 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2221 if (able == URTW_EPROM_ENABLE)
2222 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2223 else
2224 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2225 DELAY(URTW_EPROM_DELAY);
2226 fail:
2227 return (error);
2228 }
2229
2230 static usb_error_t
urtw_eprom_ck(struct urtw_softc * sc)2231 urtw_eprom_ck(struct urtw_softc *sc)
2232 {
2233 uint8_t data;
2234 usb_error_t error;
2235
2236 /* masking */
2237 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2238 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2239 DELAY(URTW_EPROM_DELAY);
2240 /* unmasking */
2241 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2242 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2243 DELAY(URTW_EPROM_DELAY);
2244 fail:
2245 return (error);
2246 }
2247
2248 static usb_error_t
urtw_eprom_readbit(struct urtw_softc * sc,int16_t * data)2249 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2250 {
2251 uint8_t data8;
2252 usb_error_t error;
2253
2254 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2255 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2256 DELAY(URTW_EPROM_DELAY);
2257
2258 fail:
2259 return (error);
2260 }
2261
2262 static usb_error_t
urtw_eprom_writebit(struct urtw_softc * sc,int16_t bit)2263 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2264 {
2265 uint8_t data;
2266 usb_error_t error;
2267
2268 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2269 if (bit != 0)
2270 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2271 else
2272 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2273 DELAY(URTW_EPROM_DELAY);
2274 fail:
2275 return (error);
2276 }
2277
2278 static usb_error_t
urtw_eprom_sendbits(struct urtw_softc * sc,int16_t * buf,int buflen)2279 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2280 {
2281 int i = 0;
2282 usb_error_t error = 0;
2283
2284 for (i = 0; i < buflen; i++) {
2285 error = urtw_eprom_writebit(sc, buf[i]);
2286 if (error != 0)
2287 goto fail;
2288 error = urtw_eprom_ck(sc);
2289 if (error != 0)
2290 goto fail;
2291 }
2292 fail:
2293 return (error);
2294 }
2295
2296 static usb_error_t
urtw_get_txpwr(struct urtw_softc * sc)2297 urtw_get_txpwr(struct urtw_softc *sc)
2298 {
2299 int i, j;
2300 uint32_t data;
2301 usb_error_t error;
2302
2303 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2304 if (error != 0)
2305 goto fail;
2306 sc->sc_txpwr_cck_base = data & 0xf;
2307 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2308
2309 for (i = 1, j = 0; i < 6; i += 2, j++) {
2310 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2311 if (error != 0)
2312 goto fail;
2313 sc->sc_txpwr_cck[i] = data & 0xf;
2314 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2315 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2316 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2317 }
2318 for (i = 1, j = 0; i < 4; i += 2, j++) {
2319 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2320 if (error != 0)
2321 goto fail;
2322 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2323 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2324 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2325 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2326 }
2327 if (sc->sc_flags & URTW_RTL8187B) {
2328 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2329 if (error != 0)
2330 goto fail;
2331 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2332 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2333 error = urtw_eprom_read32(sc, 0x0a, &data);
2334 if (error != 0)
2335 goto fail;
2336 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2337 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2338 error = urtw_eprom_read32(sc, 0x1c, &data);
2339 if (error != 0)
2340 goto fail;
2341 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2342 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2343 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2344 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2345 } else {
2346 for (i = 1, j = 0; i < 4; i += 2, j++) {
2347 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2348 &data);
2349 if (error != 0)
2350 goto fail;
2351 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2352 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2353 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2354 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2355 }
2356 }
2357 fail:
2358 return (error);
2359 }
2360
2361 static usb_error_t
urtw_get_rfchip(struct urtw_softc * sc)2362 urtw_get_rfchip(struct urtw_softc *sc)
2363 {
2364 int ret;
2365 uint8_t data8;
2366 uint32_t data;
2367 usb_error_t error;
2368
2369 if (sc->sc_flags & URTW_RTL8187B) {
2370 urtw_read8_m(sc, 0xe1, &data8);
2371 switch (data8) {
2372 case 0:
2373 sc->sc_flags |= URTW_RTL8187B_REV_B;
2374 break;
2375 case 1:
2376 sc->sc_flags |= URTW_RTL8187B_REV_D;
2377 break;
2378 case 2:
2379 sc->sc_flags |= URTW_RTL8187B_REV_E;
2380 break;
2381 default:
2382 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2383 sc->sc_flags |= URTW_RTL8187B_REV_B;
2384 break;
2385 }
2386 } else {
2387 urtw_read32_m(sc, URTW_TX_CONF, &data);
2388 switch (data & URTW_TX_HWMASK) {
2389 case URTW_TX_R8187vD_B:
2390 sc->sc_flags |= URTW_RTL8187B;
2391 break;
2392 case URTW_TX_R8187vD:
2393 break;
2394 default:
2395 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2396 data & URTW_TX_HWMASK);
2397 break;
2398 }
2399 }
2400
2401 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2402 if (error != 0)
2403 goto fail;
2404 switch (data & 0xff) {
2405 case URTW_EPROM_RFCHIPID_RTL8225U:
2406 error = urtw_8225_isv2(sc, &ret);
2407 if (error != 0)
2408 goto fail;
2409 if (ret == 0) {
2410 sc->sc_rf_init = urtw_8225_rf_init;
2411 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2412 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2413 sc->sc_rf_stop = urtw_8225_rf_stop;
2414 } else {
2415 sc->sc_rf_init = urtw_8225v2_rf_init;
2416 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2417 sc->sc_rf_stop = urtw_8225_rf_stop;
2418 }
2419 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2420 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2421 break;
2422 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2423 sc->sc_rf_init = urtw_8225v2b_rf_init;
2424 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2425 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2426 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2427 sc->sc_rf_stop = urtw_8225_rf_stop;
2428 break;
2429 default:
2430 DPRINTF(sc, URTW_DEBUG_STATE,
2431 "unsupported RF chip %d\n", data & 0xff);
2432 error = USB_ERR_INVAL;
2433 goto fail;
2434 }
2435
2436 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2437 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2438 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2439 "rtl8225z2",
2440 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2441 (data8 == 1) ? "d" : "e") : "none");
2442
2443 fail:
2444 return (error);
2445 }
2446
2447 static usb_error_t
urtw_led_init(struct urtw_softc * sc)2448 urtw_led_init(struct urtw_softc *sc)
2449 {
2450 uint32_t rev;
2451 usb_error_t error;
2452
2453 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2454 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2455 if (error != 0)
2456 goto fail;
2457
2458 switch (rev & URTW_EPROM_CID_MASK) {
2459 case URTW_EPROM_CID_ALPHA0:
2460 sc->sc_strategy = URTW_SW_LED_MODE1;
2461 break;
2462 case URTW_EPROM_CID_SERCOMM_PS:
2463 sc->sc_strategy = URTW_SW_LED_MODE3;
2464 break;
2465 case URTW_EPROM_CID_HW_LED:
2466 sc->sc_strategy = URTW_HW_LED;
2467 break;
2468 case URTW_EPROM_CID_RSVD0:
2469 case URTW_EPROM_CID_RSVD1:
2470 default:
2471 sc->sc_strategy = URTW_SW_LED_MODE0;
2472 break;
2473 }
2474
2475 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2476
2477 fail:
2478 return (error);
2479 }
2480
2481 static usb_error_t
urtw_8225_rf_init(struct urtw_softc * sc)2482 urtw_8225_rf_init(struct urtw_softc *sc)
2483 {
2484 unsigned i;
2485 uint16_t data;
2486 usb_error_t error;
2487
2488 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2489 if (error)
2490 goto fail;
2491
2492 error = urtw_8225_usb_init(sc);
2493 if (error)
2494 goto fail;
2495
2496 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2497 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2498 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2499 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2500
2501 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2502 if (error)
2503 goto fail;
2504 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2505 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2506 if (error)
2507 goto fail;
2508
2509 error = urtw_8185_rf_pins_enable(sc);
2510 if (error)
2511 goto fail;
2512 urtw_pause_ms(sc, 1000);
2513
2514 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) {
2515 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2516 urtw_8225_rf_part1[i].val);
2517 urtw_pause_ms(sc, 1);
2518 }
2519 urtw_pause_ms(sc, 100);
2520 urtw_8225_write(sc,
2521 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2522 urtw_pause_ms(sc, 200);
2523 urtw_8225_write(sc,
2524 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2525 urtw_pause_ms(sc, 200);
2526 urtw_8225_write(sc,
2527 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2528
2529 for (i = 0; i < 95; i++) {
2530 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2531 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2532 }
2533
2534 urtw_8225_write(sc,
2535 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2536 urtw_8225_write(sc,
2537 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2538
2539 for (i = 0; i < 128; i++) {
2540 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2541 urtw_pause_ms(sc, 1);
2542 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2543 urtw_pause_ms(sc, 1);
2544 }
2545
2546 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) {
2547 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2548 urtw_8225_rf_part2[i].val);
2549 urtw_pause_ms(sc, 1);
2550 }
2551
2552 error = urtw_8225_setgain(sc, 4);
2553 if (error)
2554 goto fail;
2555
2556 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) {
2557 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2558 urtw_8225_rf_part3[i].val);
2559 urtw_pause_ms(sc, 1);
2560 }
2561
2562 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2563
2564 error = urtw_8225_set_txpwrlvl(sc, 1);
2565 if (error)
2566 goto fail;
2567
2568 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2569 urtw_pause_ms(sc, 1);
2570 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2571 urtw_pause_ms(sc, 1);
2572
2573 /* TX ant A, 0x0 for B */
2574 error = urtw_8185_tx_antenna(sc, 0x3);
2575 if (error)
2576 goto fail;
2577 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2578
2579 error = urtw_8225_rf_set_chan(sc, 1);
2580 fail:
2581 return (error);
2582 }
2583
2584 static usb_error_t
urtw_8185_rf_pins_enable(struct urtw_softc * sc)2585 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2586 {
2587 usb_error_t error = 0;
2588
2589 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2590 fail:
2591 return (error);
2592 }
2593
2594 static usb_error_t
urtw_8185_tx_antenna(struct urtw_softc * sc,uint8_t ant)2595 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2596 {
2597 usb_error_t error;
2598
2599 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2600 urtw_pause_ms(sc, 1);
2601 fail:
2602 return (error);
2603 }
2604
2605 static usb_error_t
urtw_8187_write_phy_ofdm_c(struct urtw_softc * sc,uint8_t addr,uint32_t data)2606 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2607 {
2608
2609 data = data & 0xff;
2610 return urtw_8187_write_phy(sc, addr, data);
2611 }
2612
2613 static usb_error_t
urtw_8187_write_phy_cck_c(struct urtw_softc * sc,uint8_t addr,uint32_t data)2614 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2615 {
2616
2617 data = data & 0xff;
2618 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2619 }
2620
2621 static usb_error_t
urtw_8187_write_phy(struct urtw_softc * sc,uint8_t addr,uint32_t data)2622 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2623 {
2624 uint32_t phyw;
2625 usb_error_t error;
2626
2627 phyw = ((data << 8) | (addr | 0x80));
2628 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2629 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2630 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2631 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2632 urtw_pause_ms(sc, 1);
2633 fail:
2634 return (error);
2635 }
2636
2637 static usb_error_t
urtw_8225_setgain(struct urtw_softc * sc,int16_t gain)2638 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2639 {
2640 usb_error_t error;
2641
2642 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2643 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2644 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2645 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2646 fail:
2647 return (error);
2648 }
2649
2650 static usb_error_t
urtw_8225_usb_init(struct urtw_softc * sc)2651 urtw_8225_usb_init(struct urtw_softc *sc)
2652 {
2653 uint8_t data;
2654 usb_error_t error;
2655
2656 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2657 urtw_write8_m(sc, URTW_GPIO, 0);
2658 error = urtw_read8e(sc, 0x53, &data);
2659 if (error)
2660 goto fail;
2661 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2662 if (error)
2663 goto fail;
2664 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2665 urtw_write8_m(sc, URTW_GPIO, 0x20);
2666 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2667
2668 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2669 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2670 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2671
2672 urtw_pause_ms(sc, 500);
2673 fail:
2674 return (error);
2675 }
2676
2677 static usb_error_t
urtw_8225_write_c(struct urtw_softc * sc,uint8_t addr,uint16_t data)2678 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2679 {
2680 uint16_t d80, d82, d84;
2681 usb_error_t error;
2682
2683 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2684 d80 &= URTW_RF_PINS_MAGIC1;
2685 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2686 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2687 d84 &= URTW_RF_PINS_MAGIC2;
2688 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2689 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2690 DELAY(10);
2691
2692 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2693 DELAY(2);
2694 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2695 DELAY(10);
2696
2697 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2698 if (error != 0)
2699 goto fail;
2700
2701 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2702 DELAY(10);
2703 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2704 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2705 urtw_pause_ms(sc, 2);
2706 fail:
2707 return (error);
2708 }
2709
2710 static usb_error_t
urtw_8225_write_s16(struct urtw_softc * sc,uint8_t addr,int index,uint16_t * data)2711 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2712 uint16_t *data)
2713 {
2714 uint8_t buf[2];
2715 uint16_t data16;
2716 struct usb_device_request req;
2717 usb_error_t error = 0;
2718
2719 data16 = *data;
2720
2721 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2722 req.bRequest = URTW_8187_SETREGS_REQ;
2723 USETW(req.wValue, addr);
2724 USETW(req.wIndex, index);
2725 USETW(req.wLength, sizeof(uint16_t));
2726 buf[0] = (data16 & 0x00ff);
2727 buf[1] = (data16 & 0xff00) >> 8;
2728
2729 error = urtw_do_request(sc, &req, buf);
2730
2731 return (error);
2732 }
2733
2734 static usb_error_t
urtw_8225_rf_set_chan(struct urtw_softc * sc,int chan)2735 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2736 {
2737 usb_error_t error;
2738
2739 error = urtw_8225_set_txpwrlvl(sc, chan);
2740 if (error)
2741 goto fail;
2742 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2743 urtw_pause_ms(sc, 10);
2744 fail:
2745 return (error);
2746 }
2747
2748 static usb_error_t
urtw_8225_rf_set_sens(struct urtw_softc * sc,int sens)2749 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2750 {
2751 usb_error_t error;
2752
2753 if (sens < 0 || sens > 6)
2754 return -1;
2755
2756 if (sens > 4)
2757 urtw_8225_write(sc,
2758 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2759 else
2760 urtw_8225_write(sc,
2761 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2762
2763 sens = 6 - sens;
2764 error = urtw_8225_setgain(sc, sens);
2765 if (error)
2766 goto fail;
2767
2768 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2769
2770 fail:
2771 return (error);
2772 }
2773
2774 static usb_error_t
urtw_8225_set_txpwrlvl(struct urtw_softc * sc,int chan)2775 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2776 {
2777 int i, idx, set;
2778 uint8_t *cck_pwltable;
2779 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2780 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2781 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2782 usb_error_t error;
2783
2784 cck_pwrlvl_max = 11;
2785 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2786 ofdm_pwrlvl_min = 10;
2787
2788 /* CCK power setting */
2789 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2790 idx = cck_pwrlvl % 6;
2791 set = cck_pwrlvl / 6;
2792 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2793 urtw_8225_txpwr_cck;
2794
2795 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2796 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2797 for (i = 0; i < 8; i++) {
2798 urtw_8187_write_phy_cck(sc, 0x44 + i,
2799 cck_pwltable[idx * 8 + i]);
2800 }
2801 urtw_pause_ms(sc, 1);
2802
2803 /* OFDM power setting */
2804 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2805 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2806 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2807
2808 idx = ofdm_pwrlvl % 6;
2809 set = ofdm_pwrlvl / 6;
2810
2811 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2812 if (error)
2813 goto fail;
2814 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2815 urtw_8187_write_phy_ofdm(sc, 6, 0);
2816 urtw_8187_write_phy_ofdm(sc, 8, 0);
2817
2818 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2819 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2820 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2821 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2822 urtw_pause_ms(sc, 1);
2823 fail:
2824 return (error);
2825 }
2826
2827 static usb_error_t
urtw_8225_rf_stop(struct urtw_softc * sc)2828 urtw_8225_rf_stop(struct urtw_softc *sc)
2829 {
2830 uint8_t data;
2831 usb_error_t error;
2832
2833 urtw_8225_write(sc, 0x4, 0x1f);
2834
2835 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2836 if (error)
2837 goto fail;
2838
2839 urtw_read8_m(sc, URTW_CONFIG3, &data);
2840 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2841 if (sc->sc_flags & URTW_RTL8187B) {
2842 urtw_write32_m(sc, URTW_ANAPARAM2,
2843 URTW_8187B_8225_ANAPARAM2_OFF);
2844 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2845 urtw_write32_m(sc, URTW_ANAPARAM3,
2846 URTW_8187B_8225_ANAPARAM3_OFF);
2847 } else {
2848 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2849 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2850 }
2851
2852 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2853 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2854 if (error)
2855 goto fail;
2856
2857 fail:
2858 return (error);
2859 }
2860
2861 static usb_error_t
urtw_8225v2_rf_init(struct urtw_softc * sc)2862 urtw_8225v2_rf_init(struct urtw_softc *sc)
2863 {
2864 unsigned i;
2865 uint16_t data;
2866 uint32_t data32;
2867 usb_error_t error;
2868
2869 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2870 if (error)
2871 goto fail;
2872
2873 error = urtw_8225_usb_init(sc);
2874 if (error)
2875 goto fail;
2876
2877 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2878 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2879 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2880 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2881
2882 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2883 if (error)
2884 goto fail;
2885 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2886 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2887 if (error)
2888 goto fail;
2889
2890 error = urtw_8185_rf_pins_enable(sc);
2891 if (error)
2892 goto fail;
2893
2894 urtw_pause_ms(sc, 500);
2895
2896 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) {
2897 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2898 urtw_8225v2_rf_part1[i].val);
2899 }
2900 urtw_pause_ms(sc, 50);
2901
2902 urtw_8225_write(sc,
2903 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2904
2905 for (i = 0; i < 95; i++) {
2906 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2907 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2908 urtw_8225v2_rxgain[i]);
2909 }
2910
2911 urtw_8225_write(sc,
2912 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2913 urtw_8225_write(sc,
2914 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2915 urtw_8225_write(sc,
2916 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2917 urtw_8225_write(sc,
2918 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2919 urtw_pause_ms(sc, 100);
2920 urtw_8225_write(sc,
2921 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2922 urtw_pause_ms(sc, 100);
2923
2924 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2925 if (error != 0)
2926 goto fail;
2927 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2928 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2929 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2930 urtw_8225_write(sc,
2931 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2932 urtw_pause_ms(sc, 100);
2933 urtw_8225_write(sc,
2934 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2935 urtw_pause_ms(sc, 50);
2936 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2937 if (error != 0)
2938 goto fail;
2939 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2940 device_printf(sc->sc_dev, "RF calibration failed\n");
2941 }
2942 urtw_pause_ms(sc, 100);
2943
2944 urtw_8225_write(sc,
2945 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2946 for (i = 0; i < 128; i++) {
2947 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2948 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2949 }
2950
2951 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) {
2952 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2953 urtw_8225v2_rf_part2[i].val);
2954 }
2955
2956 error = urtw_8225v2_setgain(sc, 4);
2957 if (error)
2958 goto fail;
2959
2960 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) {
2961 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2962 urtw_8225v2_rf_part3[i].val);
2963 }
2964
2965 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2966
2967 error = urtw_8225v2_set_txpwrlvl(sc, 1);
2968 if (error)
2969 goto fail;
2970
2971 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2972 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2973
2974 /* TX ant A, 0x0 for B */
2975 error = urtw_8185_tx_antenna(sc, 0x3);
2976 if (error)
2977 goto fail;
2978 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2979
2980 error = urtw_8225_rf_set_chan(sc, 1);
2981 fail:
2982 return (error);
2983 }
2984
2985 static usb_error_t
urtw_8225v2_rf_set_chan(struct urtw_softc * sc,int chan)2986 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
2987 {
2988 usb_error_t error;
2989
2990 error = urtw_8225v2_set_txpwrlvl(sc, chan);
2991 if (error)
2992 goto fail;
2993
2994 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2995 urtw_pause_ms(sc, 10);
2996 fail:
2997 return (error);
2998 }
2999
3000 static usb_error_t
urtw_8225_read(struct urtw_softc * sc,uint8_t addr,uint32_t * data)3001 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3002 {
3003 int i;
3004 int16_t bit;
3005 uint8_t rlen = 12, wlen = 6;
3006 uint16_t o1, o2, o3, tmp;
3007 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3008 uint32_t mask = 0x80000000, value = 0;
3009 usb_error_t error;
3010
3011 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3012 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3013 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3014 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3015 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3016 o1 &= ~URTW_RF_PINS_MAGIC4;
3017 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3018 DELAY(5);
3019 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3020 DELAY(5);
3021
3022 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3023 bit = ((d2w & mask) != 0) ? 1 : 0;
3024
3025 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3026 DELAY(2);
3027 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3028 URTW_BB_HOST_BANG_CLK);
3029 DELAY(2);
3030 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3031 URTW_BB_HOST_BANG_CLK);
3032 DELAY(2);
3033 mask = mask >> 1;
3034 if (i == 2)
3035 break;
3036 bit = ((d2w & mask) != 0) ? 1 : 0;
3037 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3038 URTW_BB_HOST_BANG_CLK);
3039 DELAY(2);
3040 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3041 URTW_BB_HOST_BANG_CLK);
3042 DELAY(2);
3043 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3044 DELAY(1);
3045 }
3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3047 URTW_BB_HOST_BANG_CLK);
3048 DELAY(2);
3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3050 DELAY(2);
3051 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3052 DELAY(2);
3053
3054 mask = 0x800;
3055 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3056 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3057 o1 | URTW_BB_HOST_BANG_RW);
3058 DELAY(2);
3059 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3060 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3061 DELAY(2);
3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3063 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3064 DELAY(2);
3065 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3066 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3067 DELAY(2);
3068
3069 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3070 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3071 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3072 o1 | URTW_BB_HOST_BANG_RW);
3073 DELAY(2);
3074 }
3075
3076 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3077 URTW_BB_HOST_BANG_RW);
3078 DELAY(2);
3079
3080 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3081 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3082 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3083
3084 if (data != NULL)
3085 *data = value;
3086 fail:
3087 return (error);
3088 }
3089
3090 static usb_error_t
urtw_8225v2_set_txpwrlvl(struct urtw_softc * sc,int chan)3091 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3092 {
3093 int i;
3094 uint8_t *cck_pwrtable;
3095 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3096 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3097 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3098 usb_error_t error;
3099
3100 /* CCK power setting */
3101 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3102 cck_pwrlvl += sc->sc_txpwr_cck_base;
3103 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3104 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3105 urtw_8225v2_txpwr_cck;
3106
3107 for (i = 0; i < 8; i++)
3108 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3109
3110 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3111 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3112 urtw_pause_ms(sc, 1);
3113
3114 /* OFDM power setting */
3115 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3116 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3117 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3118 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3119
3120 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3121 if (error)
3122 goto fail;
3123
3124 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3125 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3126 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3127 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3128 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3129
3130 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3131 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3132 urtw_pause_ms(sc, 1);
3133 fail:
3134 return (error);
3135 }
3136
3137 static usb_error_t
urtw_8225v2_setgain(struct urtw_softc * sc,int16_t gain)3138 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3139 {
3140 uint8_t *gainp;
3141 usb_error_t error;
3142
3143 /* XXX for A? */
3144 gainp = urtw_8225v2_gain_bg;
3145 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3146 urtw_pause_ms(sc, 1);
3147 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3148 urtw_pause_ms(sc, 1);
3149 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3150 urtw_pause_ms(sc, 1);
3151 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3152 urtw_pause_ms(sc, 1);
3153 fail:
3154 return (error);
3155 }
3156
3157 static usb_error_t
urtw_8225_isv2(struct urtw_softc * sc,int * ret)3158 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3159 {
3160 uint32_t data;
3161 usb_error_t error;
3162
3163 *ret = 1;
3164
3165 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3166 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3167 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3168 urtw_pause_ms(sc, 500);
3169
3170 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3171 URTW_8225_ADDR_0_DATA_MAGIC1);
3172
3173 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3174 if (error != 0)
3175 goto fail;
3176 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3177 *ret = 0;
3178 else {
3179 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3180 if (error != 0)
3181 goto fail;
3182 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3183 *ret = 0;
3184 }
3185
3186 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3187 URTW_8225_ADDR_0_DATA_MAGIC2);
3188 fail:
3189 return (error);
3190 }
3191
3192 static usb_error_t
urtw_8225v2b_rf_init(struct urtw_softc * sc)3193 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3194 {
3195 struct ieee80211com *ic = &sc->sc_ic;
3196 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3197 const uint8_t *macaddr;
3198 unsigned i;
3199 uint8_t data8;
3200 usb_error_t error;
3201
3202 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3203 if (error)
3204 goto fail;
3205
3206 /*
3207 * initialize extra registers on 8187
3208 */
3209 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3210
3211 /* retry limit */
3212 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3213 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3214 urtw_write8_m(sc, URTW_CW_CONF, data8);
3215
3216 /* TX AGC */
3217 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3218 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3219 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3220
3221 /* Auto Rate Fallback Control */
3222 #define URTW_ARFR 0x1e0
3223 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3224 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3225 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3226 data8 | URTW_RATE_FALLBACK_ENABLE);
3227
3228 urtw_read8_m(sc, URTW_MSR, &data8);
3229 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3230 urtw_read8_m(sc, URTW_MSR, &data8);
3231 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3232 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3233
3234 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3235 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3236 #define URTW_FEMR_FOR_8187B 0x1d4
3237 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3238
3239 /* led type */
3240 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3241 data8 = (data8 & 0x3f) | 0x80;
3242 urtw_write8_m(sc, URTW_CONFIG1, data8);
3243
3244 /* applying MAC address again. */
3245 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
3246 error = urtw_set_macaddr(sc, macaddr);
3247 if (error)
3248 goto fail;
3249
3250 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3251 if (error)
3252 goto fail;
3253
3254 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3255
3256 /*
3257 * MAC configuration
3258 */
3259 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++)
3260 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3261 urtw_8225v2b_rf_part1[i].val);
3262 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3263 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3264 urtw_write32_m(sc, 0x1f0, 0);
3265 urtw_write32_m(sc, 0x1f4, 0);
3266 urtw_write8_m(sc, 0x1f8, 0);
3267 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3268
3269 #define URTW_RFSW_CTRL 0x272
3270 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3271
3272 /*
3273 * initialize PHY
3274 */
3275 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3276 if (error)
3277 goto fail;
3278 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3279 urtw_write8_m(sc, URTW_CONFIG3,
3280 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3281
3282 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3283 if (error)
3284 goto fail;
3285
3286 /* setup RFE initial timing */
3287 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3288 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3289 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3290 urtw_pause_ms(sc, 1100);
3291
3292 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) {
3293 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3294 urtw_8225v2b_rf_part0[i].val);
3295 urtw_pause_ms(sc, 1);
3296 }
3297 urtw_8225_write(sc, 0x00, 0x01b7);
3298
3299 for (i = 0; i < 95; i++) {
3300 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3301 urtw_pause_ms(sc, 1);
3302 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3303 urtw_8225v2b_rxgain[i]);
3304 urtw_pause_ms(sc, 1);
3305 }
3306
3307 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3308 urtw_pause_ms(sc, 1);
3309 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3310 urtw_pause_ms(sc, 1);
3311 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3312 urtw_pause_ms(sc, 1);
3313 urtw_pause_ms(sc, 3000);
3314 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3315 urtw_pause_ms(sc, 2000);
3316 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3317 urtw_pause_ms(sc, 1);
3318 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3319 urtw_pause_ms(sc, 1);
3320
3321 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3322 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3323 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3324
3325 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3326 for (i = 0; i < 128; i++) {
3327 uint32_t addr, data;
3328
3329 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3330 addr = ((i + 0x80) << 8) | 0x0000008e;
3331
3332 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3333 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3334 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3335 }
3336 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3337
3338 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++)
3339 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3340
3341 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3342 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3343 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3344 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3345
3346 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3347 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3348 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3349 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3350
3351 fail:
3352 return (error);
3353 }
3354
3355 static usb_error_t
urtw_8225v2b_rf_set_chan(struct urtw_softc * sc,int chan)3356 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3357 {
3358 usb_error_t error;
3359
3360 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3361 if (error)
3362 goto fail;
3363
3364 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3365 urtw_pause_ms(sc, 10);
3366 fail:
3367 return (error);
3368 }
3369
3370 static usb_error_t
urtw_8225v2b_set_txpwrlvl(struct urtw_softc * sc,int chan)3371 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3372 {
3373 int i;
3374 uint8_t *cck_pwrtable;
3375 uint8_t cck_pwrlvl_max = 15;
3376 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3377 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3378 usb_error_t error;
3379
3380 /* CCK power setting */
3381 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3382 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3383 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3384 cck_pwrlvl += sc->sc_txpwr_cck_base;
3385 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3386 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3387 urtw_8225v2b_txpwr_cck;
3388
3389 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3390 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3391 ((cck_pwrlvl <= 11) ? 8 : 16);
3392 else
3393 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3394 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3395
3396 for (i = 0; i < 8; i++)
3397 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3398
3399 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3400 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3401 urtw_pause_ms(sc, 1);
3402
3403 /* OFDM power setting */
3404 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3405 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3406 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3407 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3408 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3409
3410 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3411 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3412
3413 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3414 if (ofdm_pwrlvl <= 11) {
3415 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3416 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3417 } else {
3418 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3419 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3420 }
3421 } else {
3422 if (ofdm_pwrlvl <= 11) {
3423 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3424 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3425 } else if (ofdm_pwrlvl <= 17) {
3426 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3427 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3428 } else {
3429 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3430 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3431 }
3432 }
3433 urtw_pause_ms(sc, 1);
3434 fail:
3435 return (error);
3436 }
3437
3438 static usb_error_t
urtw_read8e(struct urtw_softc * sc,int val,uint8_t * data)3439 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3440 {
3441 struct usb_device_request req;
3442 usb_error_t error;
3443
3444 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3445 req.bRequest = URTW_8187_GETREGS_REQ;
3446 USETW(req.wValue, val | 0xfe00);
3447 USETW(req.wIndex, 0);
3448 USETW(req.wLength, sizeof(uint8_t));
3449
3450 error = urtw_do_request(sc, &req, data);
3451 return (error);
3452 }
3453
3454 static usb_error_t
urtw_write8e(struct urtw_softc * sc,int val,uint8_t data)3455 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3456 {
3457 struct usb_device_request req;
3458
3459 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3460 req.bRequest = URTW_8187_SETREGS_REQ;
3461 USETW(req.wValue, val | 0xfe00);
3462 USETW(req.wIndex, 0);
3463 USETW(req.wLength, sizeof(uint8_t));
3464
3465 return (urtw_do_request(sc, &req, &data));
3466 }
3467
3468 static usb_error_t
urtw_8180_set_anaparam(struct urtw_softc * sc,uint32_t val)3469 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3470 {
3471 uint8_t data;
3472 usb_error_t error;
3473
3474 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3475 if (error)
3476 goto fail;
3477
3478 urtw_read8_m(sc, URTW_CONFIG3, &data);
3479 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3480 urtw_write32_m(sc, URTW_ANAPARAM, val);
3481 urtw_read8_m(sc, URTW_CONFIG3, &data);
3482 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3483
3484 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3485 if (error)
3486 goto fail;
3487 fail:
3488 return (error);
3489 }
3490
3491 static usb_error_t
urtw_8185_set_anaparam2(struct urtw_softc * sc,uint32_t val)3492 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3493 {
3494 uint8_t data;
3495 usb_error_t error;
3496
3497 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3498 if (error)
3499 goto fail;
3500
3501 urtw_read8_m(sc, URTW_CONFIG3, &data);
3502 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3503 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3504 urtw_read8_m(sc, URTW_CONFIG3, &data);
3505 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3506
3507 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3508 if (error)
3509 goto fail;
3510 fail:
3511 return (error);
3512 }
3513
3514 static usb_error_t
urtw_intr_enable(struct urtw_softc * sc)3515 urtw_intr_enable(struct urtw_softc *sc)
3516 {
3517 usb_error_t error;
3518
3519 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3520 fail:
3521 return (error);
3522 }
3523
3524 static usb_error_t
urtw_intr_disable(struct urtw_softc * sc)3525 urtw_intr_disable(struct urtw_softc *sc)
3526 {
3527 usb_error_t error;
3528
3529 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3530 fail:
3531 return (error);
3532 }
3533
3534 static usb_error_t
urtw_reset(struct urtw_softc * sc)3535 urtw_reset(struct urtw_softc *sc)
3536 {
3537 uint8_t data;
3538 usb_error_t error;
3539
3540 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3541 if (error)
3542 goto fail;
3543 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3544 if (error)
3545 goto fail;
3546
3547 error = urtw_intr_disable(sc);
3548 if (error)
3549 goto fail;
3550 urtw_pause_ms(sc, 100);
3551
3552 error = urtw_write8e(sc, 0x18, 0x10);
3553 if (error != 0)
3554 goto fail;
3555 error = urtw_write8e(sc, 0x18, 0x11);
3556 if (error != 0)
3557 goto fail;
3558 error = urtw_write8e(sc, 0x18, 0x00);
3559 if (error != 0)
3560 goto fail;
3561 urtw_pause_ms(sc, 100);
3562
3563 urtw_read8_m(sc, URTW_CMD, &data);
3564 data = (data & 0x2) | URTW_CMD_RST;
3565 urtw_write8_m(sc, URTW_CMD, data);
3566 urtw_pause_ms(sc, 100);
3567
3568 urtw_read8_m(sc, URTW_CMD, &data);
3569 if (data & URTW_CMD_RST) {
3570 device_printf(sc->sc_dev, "reset timeout\n");
3571 goto fail;
3572 }
3573
3574 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3575 if (error)
3576 goto fail;
3577 urtw_pause_ms(sc, 100);
3578
3579 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3580 if (error)
3581 goto fail;
3582 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3583 if (error)
3584 goto fail;
3585 fail:
3586 return (error);
3587 }
3588
3589 static usb_error_t
urtw_led_ctl(struct urtw_softc * sc,int mode)3590 urtw_led_ctl(struct urtw_softc *sc, int mode)
3591 {
3592 usb_error_t error = 0;
3593
3594 switch (sc->sc_strategy) {
3595 case URTW_SW_LED_MODE0:
3596 error = urtw_led_mode0(sc, mode);
3597 break;
3598 case URTW_SW_LED_MODE1:
3599 error = urtw_led_mode1(sc, mode);
3600 break;
3601 case URTW_SW_LED_MODE2:
3602 error = urtw_led_mode2(sc, mode);
3603 break;
3604 case URTW_SW_LED_MODE3:
3605 error = urtw_led_mode3(sc, mode);
3606 break;
3607 default:
3608 DPRINTF(sc, URTW_DEBUG_STATE,
3609 "unsupported LED mode %d\n", sc->sc_strategy);
3610 error = USB_ERR_INVAL;
3611 break;
3612 }
3613
3614 return (error);
3615 }
3616
3617 static usb_error_t
urtw_led_mode0(struct urtw_softc * sc,int mode)3618 urtw_led_mode0(struct urtw_softc *sc, int mode)
3619 {
3620
3621 switch (mode) {
3622 case URTW_LED_CTL_POWER_ON:
3623 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3624 break;
3625 case URTW_LED_CTL_TX:
3626 if (sc->sc_gpio_ledinprogress == 1)
3627 return (0);
3628
3629 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3630 sc->sc_gpio_blinktime = 2;
3631 break;
3632 case URTW_LED_CTL_LINK:
3633 sc->sc_gpio_ledstate = URTW_LED_ON;
3634 break;
3635 default:
3636 DPRINTF(sc, URTW_DEBUG_STATE,
3637 "unsupported LED mode 0x%x", mode);
3638 return (USB_ERR_INVAL);
3639 }
3640
3641 switch (sc->sc_gpio_ledstate) {
3642 case URTW_LED_ON:
3643 if (sc->sc_gpio_ledinprogress != 0)
3644 break;
3645 urtw_led_on(sc, URTW_LED_GPIO);
3646 break;
3647 case URTW_LED_BLINK_NORMAL:
3648 if (sc->sc_gpio_ledinprogress != 0)
3649 break;
3650 sc->sc_gpio_ledinprogress = 1;
3651 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3652 URTW_LED_OFF : URTW_LED_ON;
3653 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3654 break;
3655 case URTW_LED_POWER_ON_BLINK:
3656 urtw_led_on(sc, URTW_LED_GPIO);
3657 urtw_pause_ms(sc, 100);
3658 urtw_led_off(sc, URTW_LED_GPIO);
3659 break;
3660 default:
3661 DPRINTF(sc, URTW_DEBUG_STATE,
3662 "unknown LED status 0x%x", sc->sc_gpio_ledstate);
3663 return (USB_ERR_INVAL);
3664 }
3665 return (0);
3666 }
3667
3668 static usb_error_t
urtw_led_mode1(struct urtw_softc * sc,int mode)3669 urtw_led_mode1(struct urtw_softc *sc, int mode)
3670 {
3671 return (USB_ERR_INVAL);
3672 }
3673
3674 static usb_error_t
urtw_led_mode2(struct urtw_softc * sc,int mode)3675 urtw_led_mode2(struct urtw_softc *sc, int mode)
3676 {
3677 return (USB_ERR_INVAL);
3678 }
3679
3680 static usb_error_t
urtw_led_mode3(struct urtw_softc * sc,int mode)3681 urtw_led_mode3(struct urtw_softc *sc, int mode)
3682 {
3683 return (USB_ERR_INVAL);
3684 }
3685
3686 static usb_error_t
urtw_led_on(struct urtw_softc * sc,int type)3687 urtw_led_on(struct urtw_softc *sc, int type)
3688 {
3689 usb_error_t error;
3690
3691 if (type == URTW_LED_GPIO) {
3692 switch (sc->sc_gpio_ledpin) {
3693 case URTW_LED_PIN_GPIO0:
3694 urtw_write8_m(sc, URTW_GPIO, 0x01);
3695 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3696 break;
3697 default:
3698 DPRINTF(sc, URTW_DEBUG_STATE,
3699 "unsupported LED PIN type 0x%x",
3700 sc->sc_gpio_ledpin);
3701 error = USB_ERR_INVAL;
3702 goto fail;
3703 }
3704 } else {
3705 DPRINTF(sc, URTW_DEBUG_STATE,
3706 "unsupported LED type 0x%x", type);
3707 error = USB_ERR_INVAL;
3708 goto fail;
3709 }
3710
3711 sc->sc_gpio_ledon = 1;
3712 fail:
3713 return (error);
3714 }
3715
3716 static usb_error_t
urtw_led_off(struct urtw_softc * sc,int type)3717 urtw_led_off(struct urtw_softc *sc, int type)
3718 {
3719 usb_error_t error;
3720
3721 if (type == URTW_LED_GPIO) {
3722 switch (sc->sc_gpio_ledpin) {
3723 case URTW_LED_PIN_GPIO0:
3724 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3725 urtw_write8_m(sc,
3726 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3727 break;
3728 default:
3729 DPRINTF(sc, URTW_DEBUG_STATE,
3730 "unsupported LED PIN type 0x%x",
3731 sc->sc_gpio_ledpin);
3732 error = USB_ERR_INVAL;
3733 goto fail;
3734 }
3735 } else {
3736 DPRINTF(sc, URTW_DEBUG_STATE,
3737 "unsupported LED type 0x%x", type);
3738 error = USB_ERR_INVAL;
3739 goto fail;
3740 }
3741
3742 sc->sc_gpio_ledon = 0;
3743
3744 fail:
3745 return (error);
3746 }
3747
3748 static void
urtw_led_ch(void * arg)3749 urtw_led_ch(void *arg)
3750 {
3751 struct urtw_softc *sc = arg;
3752 struct ieee80211com *ic = &sc->sc_ic;
3753
3754 ieee80211_runtask(ic, &sc->sc_led_task);
3755 }
3756
3757 static void
urtw_ledtask(void * arg,int pending)3758 urtw_ledtask(void *arg, int pending)
3759 {
3760 struct urtw_softc *sc = arg;
3761
3762 if (sc->sc_strategy != URTW_SW_LED_MODE0) {
3763 DPRINTF(sc, URTW_DEBUG_STATE,
3764 "could not process a LED strategy 0x%x",
3765 sc->sc_strategy);
3766 return;
3767 }
3768
3769 URTW_LOCK(sc);
3770 urtw_led_blink(sc);
3771 URTW_UNLOCK(sc);
3772 }
3773
3774 static usb_error_t
urtw_led_blink(struct urtw_softc * sc)3775 urtw_led_blink(struct urtw_softc *sc)
3776 {
3777 uint8_t ing = 0;
3778
3779 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3780 urtw_led_on(sc, URTW_LED_GPIO);
3781 else
3782 urtw_led_off(sc, URTW_LED_GPIO);
3783 sc->sc_gpio_blinktime--;
3784 if (sc->sc_gpio_blinktime == 0)
3785 ing = 1;
3786 else {
3787 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3788 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3789 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3790 ing = 1;
3791 }
3792 if (ing == 1) {
3793 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3794 sc->sc_gpio_ledon == 0)
3795 urtw_led_on(sc, URTW_LED_GPIO);
3796 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3797 sc->sc_gpio_ledon == 1)
3798 urtw_led_off(sc, URTW_LED_GPIO);
3799
3800 sc->sc_gpio_blinktime = 0;
3801 sc->sc_gpio_ledinprogress = 0;
3802 return (0);
3803 }
3804
3805 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3806 URTW_LED_ON : URTW_LED_OFF;
3807
3808 switch (sc->sc_gpio_ledstate) {
3809 case URTW_LED_BLINK_NORMAL:
3810 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3811 break;
3812 default:
3813 DPRINTF(sc, URTW_DEBUG_STATE,
3814 "unknown LED status 0x%x",
3815 sc->sc_gpio_ledstate);
3816 return (USB_ERR_INVAL);
3817 }
3818 return (0);
3819 }
3820
3821 static usb_error_t
urtw_rx_enable(struct urtw_softc * sc)3822 urtw_rx_enable(struct urtw_softc *sc)
3823 {
3824 uint8_t data;
3825 usb_error_t error;
3826
3827 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3828 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3829
3830 error = urtw_rx_setconf(sc);
3831 if (error != 0)
3832 goto fail;
3833
3834 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3835 urtw_read8_m(sc, URTW_CMD, &data);
3836 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3837 }
3838 fail:
3839 return (error);
3840 }
3841
3842 static usb_error_t
urtw_tx_enable(struct urtw_softc * sc)3843 urtw_tx_enable(struct urtw_softc *sc)
3844 {
3845 uint8_t data8;
3846 uint32_t data;
3847 usb_error_t error;
3848
3849 if (sc->sc_flags & URTW_RTL8187B) {
3850 urtw_read32_m(sc, URTW_TX_CONF, &data);
3851 data &= ~URTW_TX_LOOPBACK_MASK;
3852 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3853 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3854 data &= ~URTW_TX_SWPLCPLEN;
3855 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3856 (7 << 8) | /* short retry limit */
3857 (7 << 0) | /* long retry limit */
3858 (7 << 21); /* MAX TX DMA */
3859 urtw_write32_m(sc, URTW_TX_CONF, data);
3860
3861 urtw_read8_m(sc, URTW_MSR, &data8);
3862 data8 |= URTW_MSR_LINK_ENEDCA;
3863 urtw_write8_m(sc, URTW_MSR, data8);
3864 return (error);
3865 }
3866
3867 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3868 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3869 urtw_write8_m(sc, URTW_CW_CONF, data8);
3870
3871 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3872 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3873 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3874 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3875 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3876
3877 urtw_read32_m(sc, URTW_TX_CONF, &data);
3878 data &= ~URTW_TX_LOOPBACK_MASK;
3879 data |= URTW_TX_LOOPBACK_NONE;
3880 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3881 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3882 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3883 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3884 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3885 data &= ~URTW_TX_SWPLCPLEN;
3886 data |= URTW_TX_NOICV;
3887 urtw_write32_m(sc, URTW_TX_CONF, data);
3888
3889 urtw_read8_m(sc, URTW_CMD, &data8);
3890 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3891 fail:
3892 return (error);
3893 }
3894
3895 static usb_error_t
urtw_rx_setconf(struct urtw_softc * sc)3896 urtw_rx_setconf(struct urtw_softc *sc)
3897 {
3898 struct ieee80211com *ic = &sc->sc_ic;
3899 uint32_t data;
3900 usb_error_t error;
3901
3902 urtw_read32_m(sc, URTW_RX, &data);
3903 data = data &~ URTW_RX_FILTER_MASK;
3904 if (sc->sc_flags & URTW_RTL8187B) {
3905 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3906 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3907 URTW_RX_FIFO_THRESHOLD_NONE |
3908 URTW_MAX_RX_DMA_2048 |
3909 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3910 } else {
3911 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3912 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3913
3914 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3915 data = data | URTW_RX_FILTER_ICVERR;
3916 data = data | URTW_RX_FILTER_PWR;
3917 }
3918 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3919 data = data | URTW_RX_FILTER_CRCERR;
3920
3921 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3922 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3923 URTW_RX_AUTORESETPHY;
3924 data = data &~ URTW_MAX_RX_DMA_MASK;
3925 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3926 }
3927
3928 /* XXX allmulti should not be checked here... */
3929 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3930 ic->ic_promisc > 0 || ic->ic_allmulti > 0) {
3931 data = data | URTW_RX_FILTER_CTL;
3932 data = data | URTW_RX_FILTER_ALLMAC;
3933 } else {
3934 data = data | URTW_RX_FILTER_NICMAC;
3935 data = data | URTW_RX_CHECK_BSSID;
3936 }
3937
3938 urtw_write32_m(sc, URTW_RX, data);
3939 fail:
3940 return (error);
3941 }
3942
3943 static struct mbuf *
urtw_rxeof(struct usb_xfer * xfer,struct urtw_data * data,int * rssi_p,int8_t * nf_p)3944 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3945 int8_t *nf_p)
3946 {
3947 int actlen, flen, rssi;
3948 struct ieee80211_frame *wh;
3949 struct mbuf *m, *mnew;
3950 struct urtw_softc *sc = data->sc;
3951 struct ieee80211com *ic = &sc->sc_ic;
3952 uint8_t noise = 0, rate;
3953 uint64_t mactime;
3954
3955 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3956
3957 if (sc->sc_flags & URTW_RTL8187B) {
3958 struct urtw_8187b_rxhdr *rx;
3959
3960 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN)
3961 goto fail;
3962
3963 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3964 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3965 flen = le32toh(rx->flag) & 0xfff;
3966 if (flen > actlen - sizeof(*rx))
3967 goto fail;
3968
3969 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3970 /* XXX correct? */
3971 rssi = rx->rssi & URTW_RX_RSSI_MASK;
3972 noise = rx->noise;
3973
3974 if (ieee80211_radiotap_active(ic))
3975 mactime = rx->mactime;
3976 } else {
3977 struct urtw_8187l_rxhdr *rx;
3978
3979 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN)
3980 goto fail;
3981
3982 rx = (struct urtw_8187l_rxhdr *)(data->buf +
3983 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
3984 flen = le32toh(rx->flag) & 0xfff;
3985 if (flen > actlen - sizeof(*rx))
3986 goto fail;
3987
3988 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3989 /* XXX correct? */
3990 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
3991 noise = rx->noise;
3992
3993 if (ieee80211_radiotap_active(ic))
3994 mactime = rx->mactime;
3995 }
3996
3997 if (flen < IEEE80211_ACK_LEN)
3998 goto fail;
3999
4000 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
4001 if (mnew == NULL)
4002 goto fail;
4003
4004 m = data->m;
4005 data->m = mnew;
4006 data->buf = mtod(mnew, uint8_t *);
4007
4008 /* finalize mbuf */
4009 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4010
4011 if (ieee80211_radiotap_active(ic)) {
4012 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4013
4014 tap->wr_tsf = mactime;
4015 tap->wr_flags = 0;
4016 tap->wr_dbm_antsignal = (int8_t)rssi;
4017 }
4018
4019 wh = mtod(m, struct ieee80211_frame *);
4020 if (IEEE80211_IS_DATA(wh))
4021 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4022
4023 *rssi_p = rssi;
4024 *nf_p = noise; /* XXX correct? */
4025
4026 return (m);
4027
4028 fail:
4029 counter_u64_add(ic->ic_ierrors, 1);
4030 return (NULL);
4031 }
4032
4033 static void
urtw_bulk_rx_callback(struct usb_xfer * xfer,usb_error_t error)4034 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4035 {
4036 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4037 struct ieee80211com *ic = &sc->sc_ic;
4038 struct ieee80211_node *ni;
4039 struct mbuf *m = NULL;
4040 struct urtw_data *data;
4041 int8_t nf = -95;
4042 int rssi = 1;
4043
4044 URTW_ASSERT_LOCKED(sc);
4045
4046 switch (USB_GET_STATE(xfer)) {
4047 case USB_ST_TRANSFERRED:
4048 data = STAILQ_FIRST(&sc->sc_rx_active);
4049 if (data == NULL)
4050 goto setup;
4051 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4052 m = urtw_rxeof(xfer, data, &rssi, &nf);
4053 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4054 /* FALLTHROUGH */
4055 case USB_ST_SETUP:
4056 setup:
4057 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4058 if (data == NULL) {
4059 KASSERT(m == NULL, ("mbuf isn't NULL"));
4060 return;
4061 }
4062 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4063 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4064 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4065 usbd_xfer_max_len(xfer));
4066 usbd_transfer_submit(xfer);
4067
4068 /*
4069 * To avoid LOR we should unlock our private mutex here to call
4070 * ieee80211_input() because here is at the end of a USB
4071 * callback and safe to unlock.
4072 */
4073 URTW_UNLOCK(sc);
4074 if (m != NULL) {
4075 if (m->m_pkthdr.len >=
4076 sizeof(struct ieee80211_frame_min)) {
4077 ni = ieee80211_find_rxnode(ic,
4078 mtod(m, struct ieee80211_frame_min *));
4079 } else
4080 ni = NULL;
4081
4082 if (ni != NULL) {
4083 (void) ieee80211_input(ni, m, rssi, nf);
4084 /* node is no longer needed */
4085 ieee80211_free_node(ni);
4086 } else
4087 (void) ieee80211_input_all(ic, m, rssi, nf);
4088 m = NULL;
4089 }
4090 URTW_LOCK(sc);
4091 break;
4092 default:
4093 /* needs it to the inactive queue due to a error. */
4094 data = STAILQ_FIRST(&sc->sc_rx_active);
4095 if (data != NULL) {
4096 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4097 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4098 }
4099 if (error != USB_ERR_CANCELLED) {
4100 usbd_xfer_set_stall(xfer);
4101 counter_u64_add(ic->ic_ierrors, 1);
4102 goto setup;
4103 }
4104 break;
4105 }
4106 }
4107
4108 #define URTW_STATUS_TYPE_TXCLOSE 1
4109 #define URTW_STATUS_TYPE_BEACON_INTR 0
4110
4111 static void
urtw_txstatus_eof(struct usb_xfer * xfer)4112 urtw_txstatus_eof(struct usb_xfer *xfer)
4113 {
4114 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4115 struct ieee80211com *ic = &sc->sc_ic;
4116 int actlen, type, pktretry;
4117 uint64_t val;
4118
4119 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4120
4121 if (actlen != sizeof(uint64_t))
4122 return;
4123
4124 val = le64toh(sc->sc_txstatus);
4125 type = (val >> 30) & 0x3;
4126 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4127 pktretry = val & 0xff;
4128 if (pktretry == URTW_TX_MAXRETRY)
4129 counter_u64_add(ic->ic_oerrors, 1);
4130 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4131 pktretry, (val >> 16) & 0xff);
4132 }
4133 }
4134
4135 static void
urtw_bulk_tx_status_callback(struct usb_xfer * xfer,usb_error_t error)4136 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4137 {
4138 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4139 struct ieee80211com *ic = &sc->sc_ic;
4140 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0);
4141
4142 URTW_ASSERT_LOCKED(sc);
4143
4144 switch (USB_GET_STATE(xfer)) {
4145 case USB_ST_TRANSFERRED:
4146 urtw_txstatus_eof(xfer);
4147 /* FALLTHROUGH */
4148 case USB_ST_SETUP:
4149 setup:
4150 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t));
4151 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t));
4152 usbd_transfer_submit(xfer);
4153 break;
4154 default:
4155 if (error != USB_ERR_CANCELLED) {
4156 usbd_xfer_set_stall(xfer);
4157 counter_u64_add(ic->ic_ierrors, 1);
4158 goto setup;
4159 }
4160 break;
4161 }
4162 }
4163
4164 static void
urtw_txeof(struct usb_xfer * xfer,struct urtw_data * data)4165 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4166 {
4167 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4168
4169 URTW_ASSERT_LOCKED(sc);
4170
4171 if (data->m) {
4172 /* XXX status? */
4173 ieee80211_tx_complete(data->ni, data->m, 0);
4174 data->m = NULL;
4175 data->ni = NULL;
4176 }
4177 sc->sc_txtimer = 0;
4178 }
4179
4180 static void
urtw_bulk_tx_callback(struct usb_xfer * xfer,usb_error_t error)4181 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4182 {
4183 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4184 struct urtw_data *data;
4185
4186 URTW_ASSERT_LOCKED(sc);
4187
4188 switch (USB_GET_STATE(xfer)) {
4189 case USB_ST_TRANSFERRED:
4190 data = STAILQ_FIRST(&sc->sc_tx_active);
4191 if (data == NULL)
4192 goto setup;
4193 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4194 urtw_txeof(xfer, data);
4195 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4196 /* FALLTHROUGH */
4197 case USB_ST_SETUP:
4198 setup:
4199 data = STAILQ_FIRST(&sc->sc_tx_pending);
4200 if (data == NULL) {
4201 DPRINTF(sc, URTW_DEBUG_XMIT,
4202 "%s: empty pending queue\n", __func__);
4203 return;
4204 }
4205 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4206 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4207
4208 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4209 usbd_transfer_submit(xfer);
4210
4211 urtw_start(sc);
4212 break;
4213 default:
4214 data = STAILQ_FIRST(&sc->sc_tx_active);
4215 if (data == NULL)
4216 goto setup;
4217 if (data->ni != NULL) {
4218 if_inc_counter(data->ni->ni_vap->iv_ifp,
4219 IFCOUNTER_OERRORS, 1);
4220 ieee80211_free_node(data->ni);
4221 data->ni = NULL;
4222 }
4223 if (error != USB_ERR_CANCELLED) {
4224 usbd_xfer_set_stall(xfer);
4225 goto setup;
4226 }
4227 break;
4228 }
4229 }
4230
4231 static struct urtw_data *
_urtw_getbuf(struct urtw_softc * sc)4232 _urtw_getbuf(struct urtw_softc *sc)
4233 {
4234 struct urtw_data *bf;
4235
4236 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4237 if (bf != NULL)
4238 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4239 else
4240 bf = NULL;
4241 if (bf == NULL)
4242 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4243 "out of xmit buffers");
4244 return (bf);
4245 }
4246
4247 static struct urtw_data *
urtw_getbuf(struct urtw_softc * sc)4248 urtw_getbuf(struct urtw_softc *sc)
4249 {
4250 struct urtw_data *bf;
4251
4252 URTW_ASSERT_LOCKED(sc);
4253
4254 bf = _urtw_getbuf(sc);
4255 if (bf == NULL)
4256 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4257 return (bf);
4258 }
4259
4260 static int
urtw_isbmode(uint16_t rate)4261 urtw_isbmode(uint16_t rate)
4262 {
4263
4264 return ((rate <= 22 && rate != 12 && rate != 18) ||
4265 rate == 44) ? (1) : (0);
4266 }
4267
4268 static uint16_t
urtw_rate2dbps(uint16_t rate)4269 urtw_rate2dbps(uint16_t rate)
4270 {
4271
4272 switch(rate) {
4273 case 12:
4274 case 18:
4275 case 24:
4276 case 36:
4277 case 48:
4278 case 72:
4279 case 96:
4280 case 108:
4281 return (rate * 2);
4282 default:
4283 break;
4284 }
4285 return (24);
4286 }
4287
4288 static int
urtw_compute_txtime(uint16_t framelen,uint16_t rate,uint8_t ismgt,uint8_t isshort)4289 urtw_compute_txtime(uint16_t framelen, uint16_t rate,
4290 uint8_t ismgt, uint8_t isshort)
4291 {
4292 uint16_t ceiling, frametime, n_dbps;
4293
4294 if (urtw_isbmode(rate)) {
4295 if (ismgt || !isshort || rate == 2)
4296 frametime = (uint16_t)(144 + 48 +
4297 (framelen * 8 / (rate / 2)));
4298 else
4299 frametime = (uint16_t)(72 + 24 +
4300 (framelen * 8 / (rate / 2)));
4301 if ((framelen * 8 % (rate / 2)) != 0)
4302 frametime++;
4303 } else {
4304 n_dbps = urtw_rate2dbps(rate);
4305 ceiling = (16 + 8 * framelen + 6) / n_dbps
4306 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0);
4307 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6);
4308 }
4309 return (frametime);
4310 }
4311
4312 /*
4313 * Callback from the 802.11 layer to update the
4314 * slot time based on the current setting.
4315 */
4316 static void
urtw_updateslot(struct ieee80211com * ic)4317 urtw_updateslot(struct ieee80211com *ic)
4318 {
4319 struct urtw_softc *sc = ic->ic_softc;
4320
4321 ieee80211_runtask(ic, &sc->sc_updateslot_task);
4322 }
4323
4324 static void
urtw_updateslottask(void * arg,int pending)4325 urtw_updateslottask(void *arg, int pending)
4326 {
4327 struct urtw_softc *sc = arg;
4328 struct ieee80211com *ic = &sc->sc_ic;
4329 int error;
4330
4331 URTW_LOCK(sc);
4332 if ((sc->sc_flags & URTW_RUNNING) == 0) {
4333 URTW_UNLOCK(sc);
4334 return;
4335 }
4336 if (sc->sc_flags & URTW_RTL8187B) {
4337 urtw_write8_m(sc, URTW_SIFS, 0x22);
4338 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
4339 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT);
4340 else
4341 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT);
4342 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b);
4343 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b);
4344 } else {
4345 urtw_write8_m(sc, URTW_SIFS, 0x22);
4346 if (sc->sc_state == IEEE80211_S_ASSOC &&
4347 ic->ic_flags & IEEE80211_F_SHSLOT)
4348 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT);
4349 else
4350 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT);
4351 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
4352 urtw_write8_m(sc, URTW_DIFS, 0x14);
4353 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
4354 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
4355 } else {
4356 urtw_write8_m(sc, URTW_DIFS, 0x24);
4357 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
4358 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
4359 }
4360 }
4361 fail:
4362 URTW_UNLOCK(sc);
4363 }
4364
4365 static void
urtw_sysctl_node(struct urtw_softc * sc)4366 urtw_sysctl_node(struct urtw_softc *sc)
4367 {
4368 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \
4369 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
4370 struct sysctl_ctx_list *ctx;
4371 struct sysctl_oid_list *child, *parent;
4372 struct sysctl_oid *tree;
4373 struct urtw_stats *stats = &sc->sc_stats;
4374
4375 ctx = device_get_sysctl_ctx(sc->sc_dev);
4376 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
4377
4378 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
4379 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "URTW statistics");
4380 parent = SYSCTL_CHILDREN(tree);
4381
4382 /* Tx statistics. */
4383 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
4384 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
4385 child = SYSCTL_CHILDREN(tree);
4386 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0],
4387 "1 Mbit/s");
4388 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1],
4389 "2 Mbit/s");
4390 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2],
4391 "5.5 Mbit/s");
4392 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4],
4393 "6 Mbit/s");
4394 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5],
4395 "9 Mbit/s");
4396 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3],
4397 "11 Mbit/s");
4398 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6],
4399 "12 Mbit/s");
4400 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7],
4401 "18 Mbit/s");
4402 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8],
4403 "24 Mbit/s");
4404 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9],
4405 "36 Mbit/s");
4406 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10],
4407 "48 Mbit/s");
4408 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11],
4409 "54 Mbit/s");
4410 #undef URTW_SYSCTL_STAT_ADD32
4411 }
4412
4413 static device_method_t urtw_methods[] = {
4414 DEVMETHOD(device_probe, urtw_match),
4415 DEVMETHOD(device_attach, urtw_attach),
4416 DEVMETHOD(device_detach, urtw_detach),
4417 DEVMETHOD_END
4418 };
4419
4420 static driver_t urtw_driver = {
4421 .name = "urtw",
4422 .methods = urtw_methods,
4423 .size = sizeof(struct urtw_softc)
4424 };
4425
4426 DRIVER_MODULE(urtw, uhub, urtw_driver, NULL, NULL);
4427 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4428 MODULE_DEPEND(urtw, usb, 1, 1, 1);
4429 MODULE_VERSION(urtw, 1);
4430 USB_PNP_HOST_INFO(urtw_devs);
4431