1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file and its contents are supplied under the terms of the 31 * Common Development and Distribution License ("CDDL"), version 1.0. 32 * You may only use this file in accordance with the terms of version 33 * 1.0 of the CDDL. 34 * 35 * A full copy of the text of the CDDL should have accompanied this 36 * source. A copy of the CDDL is also available via the Internet at 37 * http://www.illumos.org/license/CDDL. 38 * 39 * Copyright 2022 Oxide Computer Company 40 */ 41 42 #ifndef _VMCB_H_ 43 #define _VMCB_H_ 44 45 struct svm_softc; 46 47 #define BIT(n) (1ULL << n) 48 49 /* 50 * Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15 51 * Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B 52 */ 53 54 /* vmcb_ctrl->intercept[] array indices */ 55 #define VMCB_CR_INTCPT 0 56 #define VMCB_DR_INTCPT 1 57 #define VMCB_EXC_INTCPT 2 58 #define VMCB_CTRL1_INTCPT 3 59 #define VMCB_CTRL2_INTCPT 4 60 61 /* intercept[VMCB_CTRL1_INTCPT] fields */ 62 #define VMCB_INTCPT_INTR BIT(0) 63 #define VMCB_INTCPT_NMI BIT(1) 64 #define VMCB_INTCPT_SMI BIT(2) 65 #define VMCB_INTCPT_INIT BIT(3) 66 #define VMCB_INTCPT_VINTR BIT(4) 67 #define VMCB_INTCPT_CR0_WRITE BIT(5) 68 #define VMCB_INTCPT_IDTR_READ BIT(6) 69 #define VMCB_INTCPT_GDTR_READ BIT(7) 70 #define VMCB_INTCPT_LDTR_READ BIT(8) 71 #define VMCB_INTCPT_TR_READ BIT(9) 72 #define VMCB_INTCPT_IDTR_WRITE BIT(10) 73 #define VMCB_INTCPT_GDTR_WRITE BIT(11) 74 #define VMCB_INTCPT_LDTR_WRITE BIT(12) 75 #define VMCB_INTCPT_TR_WRITE BIT(13) 76 #define VMCB_INTCPT_RDTSC BIT(14) 77 #define VMCB_INTCPT_RDPMC BIT(15) 78 #define VMCB_INTCPT_PUSHF BIT(16) 79 #define VMCB_INTCPT_POPF BIT(17) 80 #define VMCB_INTCPT_CPUID BIT(18) 81 #define VMCB_INTCPT_RSM BIT(19) 82 #define VMCB_INTCPT_IRET BIT(20) 83 #define VMCB_INTCPT_INTn BIT(21) 84 #define VMCB_INTCPT_INVD BIT(22) 85 #define VMCB_INTCPT_PAUSE BIT(23) 86 #define VMCB_INTCPT_HLT BIT(24) 87 #define VMCB_INTCPT_INVLPG BIT(25) 88 #define VMCB_INTCPT_INVLPGA BIT(26) 89 #define VMCB_INTCPT_IO BIT(27) 90 #define VMCB_INTCPT_MSR BIT(28) 91 #define VMCB_INTCPT_TASK_SWITCH BIT(29) 92 #define VMCB_INTCPT_FERR_FREEZE BIT(30) 93 #define VMCB_INTCPT_SHUTDOWN BIT(31) 94 95 /* intercept[VMCB_CTRL2_INTCPT] fields */ 96 #define VMCB_INTCPT_VMRUN BIT(0) 97 #define VMCB_INTCPT_VMMCALL BIT(1) 98 #define VMCB_INTCPT_VMLOAD BIT(2) 99 #define VMCB_INTCPT_VMSAVE BIT(3) 100 #define VMCB_INTCPT_STGI BIT(4) 101 #define VMCB_INTCPT_CLGI BIT(5) 102 #define VMCB_INTCPT_SKINIT BIT(6) 103 #define VMCB_INTCPT_RDTSCP BIT(7) 104 #define VMCB_INTCPT_ICEBP BIT(8) 105 #define VMCB_INTCPT_WBINVD BIT(9) 106 #define VMCB_INTCPT_MONITOR BIT(10) 107 #define VMCB_INTCPT_MWAIT BIT(11) 108 #define VMCB_INTCPT_MWAIT_ARMED BIT(12) 109 #define VMCB_INTCPT_XSETBV BIT(13) 110 111 /* VMCB TLB control */ 112 #define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */ 113 #define VMCB_TLB_FLUSH_ALL 1 /* Flush entire TLB */ 114 #define VMCB_TLB_FLUSH_GUEST 3 /* Flush all guest entries */ 115 #define VMCB_TLB_FLUSH_GUEST_NONGLOBAL 7 /* Flush guest non-PG entries */ 116 117 /* VMCB state caching */ 118 #define VMCB_CACHE_NONE 0 /* No caching */ 119 #define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */ 120 #define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */ 121 #define VMCB_CACHE_ASID BIT(2) /* ASID */ 122 #define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */ 123 #define VMCB_CACHE_NP BIT(4) /* Nested Paging */ 124 #define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */ 125 #define VMCB_CACHE_DR BIT(6) /* Debug registers */ 126 #define VMCB_CACHE_DT BIT(7) /* GDT/IDT */ 127 #define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */ 128 #define VMCB_CACHE_CR2 BIT(9) /* page fault address */ 129 #define VMCB_CACHE_LBR BIT(10) /* Last branch */ 130 131 /* VMCB control event injection */ 132 #define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */ 133 #define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */ 134 135 /* Event types that can be injected */ 136 #define VMCB_EVENTINJ_TYPE_INTR 0 137 #define VMCB_EVENTINJ_TYPE_NMI (2 << 8) 138 #define VMCB_EVENTINJ_TYPE_EXCEPTION (3 << 8) 139 #define VMCB_EVENTINJ_TYPE_INTn (4 << 8) 140 141 /* VMCB exit code, APM vol2 Appendix C */ 142 #define VMCB_EXIT_CR0_READ 0x00 143 #define VMCB_EXIT_CR15_READ 0x0f 144 #define VMCB_EXIT_CR0_WRITE 0x10 145 #define VMCB_EXIT_CR15_WRITE 0x1f 146 #define VMCB_EXIT_EXCP0 0x40 147 #define VMCB_EXIT_EXCP31 0x5f 148 #define VMCB_EXIT_INTR 0x60 149 #define VMCB_EXIT_NMI 0x61 150 #define VMCB_EXIT_SMI 0x62 151 #define VMCB_EXIT_INIT 0x63 152 #define VMCB_EXIT_VINTR 0x64 153 #define VMCB_EXIT_CR0_SEL_WRITE 0x65 154 #define VMCB_EXIT_RDPMC 0x6f 155 #define VMCB_EXIT_PUSHF 0x70 156 #define VMCB_EXIT_POPF 0x71 157 #define VMCB_EXIT_CPUID 0x72 158 #define VMCB_EXIT_IRET 0x74 159 #define VMCB_EXIT_INVD 0x76 160 #define VMCB_EXIT_PAUSE 0x77 161 #define VMCB_EXIT_HLT 0x78 162 #define VMCB_EXIT_INVLPG 0x79 163 #define VMCB_EXIT_INVLPGA 0x7A 164 #define VMCB_EXIT_IO 0x7B 165 #define VMCB_EXIT_MSR 0x7C 166 #define VMCB_EXIT_SHUTDOWN 0x7F 167 #define VMCB_EXIT_VMRUN 0x80 168 #define VMCB_EXIT_VMMCALL 0x81 169 #define VMCB_EXIT_VMLOAD 0x82 170 #define VMCB_EXIT_VMSAVE 0x83 171 #define VMCB_EXIT_STGI 0x84 172 #define VMCB_EXIT_CLGI 0x85 173 #define VMCB_EXIT_SKINIT 0x86 174 #define VMCB_EXIT_WBINVD 0x89 175 #define VMCB_EXIT_MONITOR 0x8A 176 #define VMCB_EXIT_MWAIT 0x8B 177 #define VMCB_EXIT_NPF 0x400 178 #define VMCB_EXIT_INVALID -1 179 180 /* 181 * Move to/from CRx 182 * Bit definitions to decode EXITINFO1 183 */ 184 #define VMCB_CRx_INFO1_GPR(x) ((x) & 0xf) 185 #define VMCB_CRx_INFO1_VALID(x) ((x) & (1UL << 63)) 186 187 /* 188 * Nested page fault. 189 * Bit definitions to decode EXITINFO1. 190 */ 191 #define VMCB_NPF_INFO1_P BIT(0) /* Nested page present. */ 192 #define VMCB_NPF_INFO1_W BIT(1) /* Access was write. */ 193 #define VMCB_NPF_INFO1_U BIT(2) /* Access was user access. */ 194 #define VMCB_NPF_INFO1_RSV BIT(3) /* Reserved bits present. */ 195 #define VMCB_NPF_INFO1_ID BIT(4) /* Code read. */ 196 197 #define VMCB_NPF_INFO1_GPA BIT(32) /* Guest physical address. */ 198 #define VMCB_NPF_INFO1_GPT BIT(33) /* Guest page table. */ 199 200 /* 201 * EXITINTINFO, Interrupt exit info for all intrecepts. 202 * Section 15.7.2, Intercepts during IDT Interrupt Delivery. 203 */ 204 #define VMCB_EXITINTINFO_VECTOR(x) ((x) & 0xFF) 205 #define VMCB_EXITINTINFO_TYPE(x) ((x) & (0x7 << 8)) 206 #define VMCB_EXITINTINFO_EC_VALID(x) (((x) & BIT(11)) != 0) 207 #define VMCB_EXITINTINFO_VALID(x) (((x) & BIT(31)) != 0) 208 #define VMCB_EXITINTINFO_EC(x) (((x) >> 32) & 0xFFFFFFFF) 209 210 /* Offset of various VMCB fields. */ 211 #define VMCB_OFF_CTRL(x) (x) 212 #define VMCB_OFF_STATE(x) ((x) + 0x400) 213 214 #define VMCB_OFF_CR_INTERCEPT VMCB_OFF_CTRL(0x0) 215 #define VMCB_OFF_DR_INTERCEPT VMCB_OFF_CTRL(0x4) 216 #define VMCB_OFF_EXC_INTERCEPT VMCB_OFF_CTRL(0x8) 217 #define VMCB_OFF_INST1_INTERCEPT VMCB_OFF_CTRL(0xC) 218 #define VMCB_OFF_INST2_INTERCEPT VMCB_OFF_CTRL(0x10) 219 #define VMCB_OFF_IO_PERM VMCB_OFF_CTRL(0x40) 220 #define VMCB_OFF_MSR_PERM VMCB_OFF_CTRL(0x48) 221 #define VMCB_OFF_TSC_OFFSET VMCB_OFF_CTRL(0x50) 222 #define VMCB_OFF_ASID VMCB_OFF_CTRL(0x58) 223 #define VMCB_OFF_TLB_CTRL VMCB_OFF_CTRL(0x5C) 224 #define VMCB_OFF_VIRQ VMCB_OFF_CTRL(0x60) 225 #define VMCB_OFF_EXIT_REASON VMCB_OFF_CTRL(0x70) 226 #define VMCB_OFF_EXITINFO1 VMCB_OFF_CTRL(0x78) 227 #define VMCB_OFF_EXITINFO2 VMCB_OFF_CTRL(0x80) 228 #define VMCB_OFF_EXITINTINFO VMCB_OFF_CTRL(0x88) 229 #define VMCB_OFF_AVIC_BAR VMCB_OFF_CTRL(0x98) 230 #define VMCB_OFF_NPT_BASE VMCB_OFF_CTRL(0xB0) 231 #define VMCB_OFF_AVIC_PAGE VMCB_OFF_CTRL(0xE0) 232 #define VMCB_OFF_AVIC_LT VMCB_OFF_CTRL(0xF0) 233 #define VMCB_OFF_AVIC_PT VMCB_OFF_CTRL(0xF8) 234 #define VMCB_OFF_SYSENTER_CS VMCB_OFF_STATE(0x228) 235 #define VMCB_OFF_SYSENTER_ESP VMCB_OFF_STATE(0x230) 236 #define VMCB_OFF_SYSENTER_EIP VMCB_OFF_STATE(0x238) 237 #define VMCB_OFF_GUEST_PAT VMCB_OFF_STATE(0x268) 238 239 #ifdef _KERNEL 240 /* VMCB save state area segment format */ 241 struct vmcb_segment { 242 uint16_t selector; 243 uint16_t attrib; 244 uint32_t limit; 245 uint64_t base; 246 }; 247 CTASSERT(sizeof (struct vmcb_segment) == 16); 248 249 /* Convert to/from vmcb segment access to generic (VMX) access */ 250 #define VMCB_ATTR2ACCESS(attr) ((((attr) & 0xf00) << 4) | ((attr) & 0xff)) 251 #define VMCB_ACCESS2ATTR(acc) ((((acc) & 0xf000) >> 4) | ((acc) & 0xff)) 252 253 /* Code segment descriptor attribute in 12 bit format as saved by VMCB. */ 254 #define VMCB_CS_ATTRIB_L BIT(9) /* Long mode. */ 255 #define VMCB_CS_ATTRIB_D BIT(10) /* OPerand size bit. */ 256 257 /* Fields for Virtual Interrupt Control (v_irq) */ 258 #define V_IRQ BIT(0) /* Offset 0x60 bit 8 (0x61 bit 0) */ 259 #define V_VGIF_VALUE BIT(1) /* Offset 0x60 bit 9 (0x61 bit 1) */ 260 261 /* Fields for Virtual Interrupt Control (v_intr_prio) */ 262 #define V_INTR_PRIO 0xf /* Offset 0x60 bits 16-19 (0x62 bits 0-3) */ 263 #define V_IGN_TPR BIT(4) /* Offset 0x60 bit 20 (0x62 bit 4) */ 264 265 /* Fields for Virtual Interrupt Control (v_intr_ctrl) */ 266 #define V_INTR_MASKING BIT(0) /* Offset 0x60 bit 24 (0x63 bit 0) */ 267 #define V_VGIF_ENABLE BIT(1) /* Offset 0x60 bit 25 (0x63 bit 1) */ 268 #define V_AVIC_ENABLE BIT(7) /* Offset 0x60 bit 31 (0x63 bit 7) */ 269 270 /* Fields in Interrupt Shadow, offset 0x68 */ 271 #define VIRTUAL_INTR_SHADOW BIT(0) 272 #define GUEST_INTERRUPT_MASK BIT(1) 273 274 /* Fields in Nested Paging, offset 0x90 */ 275 #define NP_ENABLE BIT(0) /* Enable nested paging */ 276 #define SEV_ENABLE BIT(1) /* Enable SEV */ 277 #define SEV_ES_ENABLE BIT(2) /* Enable SEV-ES */ 278 #define GUEST_MODE_EXEC_TRAP BIT(3) /* Guest mode execute trap */ 279 #define VIRT_TRANSPAR_ENCRYPT BIT(5) /* Virtual transparent encryption */ 280 281 /* Fields in Misc virt controls, offset 0xB8 */ 282 #define LBR_VIRT_ENABLE BIT(0) /* Enable LBR virtualization accel */ 283 #define VIRT_VMSAVE_VMLOAD BIT(1) /* Virtualized VMSAVE/VMLOAD */ 284 285 /* 286 * The VMCB is divided into two areas - the first one contains various 287 * control bits including the intercept vector and the second one contains 288 * the guest state. 289 */ 290 291 /* VMCB control area - padded up to 1024 bytes */ 292 struct vmcb_ctrl { 293 uint32_t intercept[5]; /* 0x00-0x13: all intercepts */ 294 uint32_t _pad1[10]; /* 0x14-0x3B: Reserved. */ 295 uint32_t pause_ctrl; /* 0x3C, PAUSE filter thresh/count */ 296 uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */ 297 uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */ 298 uint64_t tsc_offset; /* 0x50: TSC_OFFSET */ 299 uint32_t asid; /* 0x58: Guest ASID */ 300 uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */ 301 uint8_t _pad2[3]; /* 0x5D-0x5F: Reserved. */ 302 uint8_t v_tpr; /* 0x60: Virtual TPR */ 303 uint8_t v_irq; /* 0x61: V_IRQ, V_GIF_VALUE + Reserved */ 304 uint8_t v_intr_prio; /* 0x62: V_INTR_PRIO, V_IGN_TPR */ 305 uint8_t v_intr_ctrl; /* 0x63: V_INTR_MASKING, vGIF and AVIC enable */ 306 uint8_t v_intr_vector; /* 0x64: Virtual interrupt vector */ 307 uint8_t _pad3[3]; /* 0x65-0x67: Reserved */ 308 uint64_t intr_shadow; /* 0x68: Interrupt shadow (and more) */ 309 uint64_t exitcode; /* 0x70, Exitcode */ 310 uint64_t exitinfo1; /* 0x78, EXITINFO1 */ 311 uint64_t exitinfo2; /* 0x80, EXITINFO2 */ 312 uint64_t exitintinfo; /* 0x88, Interrupt exit value. */ 313 uint64_t np_ctrl; /* 0x90, Nested paging control. */ 314 uint64_t _pad4[2]; /* 0x98-0xA7 reserved. */ 315 uint64_t eventinj; /* 0xA8, Event injection. */ 316 uint64_t n_cr3; /* 0xB0, Nested page table. */ 317 uint64_t misc_ctrl; /* 0xB8, Misc virt controls */ 318 uint32_t vmcb_clean; /* 0xC0: VMCB clean bits for caching */ 319 uint32_t _pad5; /* 0xC4: Reserved */ 320 uint64_t nrip; /* 0xC8: Guest next nRIP. */ 321 uint8_t inst_len; /* 0xD0: #NPF decode assist */ 322 uint8_t inst_bytes[15]; /* 0xD1-0xDF: guest instr bytes */ 323 uint64_t avic_page_pa; /* 0xEO: AVIC backing page */ 324 uint64_t _pad6; /* 0xE8-0xEF: Reserved */ 325 uint64_t avic_log_tbl; /* 0xFO: AVIC logical table */ 326 uint64_t avic_phys_tbl; /* 0xF8: AVIC physical page */ 327 uint64_t _pad7; /* 0x100-0x107: Reserved */ 328 uint64_t vmsa_pa; /* 0x108: VMSA pointer */ 329 uint64_t _pad8[94]; /* 0x110-0x3FF: Reserved */ 330 }; 331 CTASSERT(sizeof (struct vmcb_ctrl) == 1024); 332 CTASSERT(offsetof(struct vmcb_ctrl, vmsa_pa) == 0x108); 333 334 struct vmcb_state { 335 struct vmcb_segment es; /* 0x00: 32bit base */ 336 struct vmcb_segment cs; /* 0x10: 32bit base */ 337 struct vmcb_segment ss; /* 0x20: 32bit base */ 338 struct vmcb_segment ds; /* 0x30: 32bit base */ 339 struct vmcb_segment fs; /* 0x40 */ 340 struct vmcb_segment gs; /* 0x50 */ 341 struct vmcb_segment gdt; /* 0x60: base + 16bit limit */ 342 struct vmcb_segment ldt; /* 0x70 */ 343 struct vmcb_segment idt; /* 0x80: base + 16bit limit */ 344 struct vmcb_segment tr; /* 0x90 */ 345 uint8_t _pad1[43]; /* 0xA0-0xCA: Reserved */ 346 uint8_t cpl; /* 0xCB: CPL (real mode: 0, virt: 3) */ 347 uint32_t _pad2; /* 0xCC-0xCF: Reserved */ 348 uint64_t efer; /* 0xD0 */ 349 uint64_t _pad3[14]; /* 0xD8-0x147: Reserved */ 350 uint64_t cr4; /* 0x148 */ 351 uint64_t cr3; /* 0x150 */ 352 uint64_t cr0; /* 0x158 */ 353 uint64_t dr7; /* 0x160 */ 354 uint64_t dr6; /* 0x168 */ 355 uint64_t rflags; /* 0x170 */ 356 uint64_t rip; /* 0x178 */ 357 uint64_t _pad4[11]; /* 0x180-0x1D7: Reserved */ 358 uint64_t rsp; /* 0x1D8 */ 359 uint64_t _pad5[3]; /* 0x1E0-0x1F7: Reserved */ 360 uint64_t rax; /* 0x1F8 */ 361 uint64_t star; /* 0x200 */ 362 uint64_t lstar; /* 0x208 */ 363 uint64_t cstar; /* 0x210 */ 364 uint64_t sfmask; /* 0x218 */ 365 uint64_t kernelgsbase; /* 0x220 */ 366 uint64_t sysenter_cs; /* 0x228 */ 367 uint64_t sysenter_esp; /* 0x230 */ 368 uint64_t sysenter_eip; /* 0x238 */ 369 uint64_t cr2; /* 0x240 */ 370 uint64_t _pad6[4]; /* 0x248-0x267: Reserved */ 371 uint64_t g_pat; /* 0x268 */ 372 uint64_t dbgctl; /* 0x270 */ 373 uint64_t br_from; /* 0x278 */ 374 uint64_t br_to; /* 0x280 */ 375 uint64_t int_from; /* 0x288 */ 376 uint64_t int_to; /* 0x290 */ 377 uint64_t _pad7[301]; /* Reserved up to end of VMCB */ 378 }; 379 CTASSERT(sizeof (struct vmcb_state) == 0xC00); 380 CTASSERT(offsetof(struct vmcb_state, int_to) == 0x290); 381 382 /* 383 * The VMCB aka Virtual Machine Control Block is a 4KB aligned page 384 * in memory that describes the virtual machine. 385 * 386 * The VMCB contains: 387 * - instructions or events in the guest to intercept 388 * - control bits that modify execution environment of the guest 389 * - guest processor state (e.g. general purpose registers) 390 */ 391 struct vmcb { 392 struct vmcb_ctrl ctrl; 393 struct vmcb_state state; 394 }; 395 CTASSERT(sizeof (struct vmcb) == PAGE_SIZE); 396 CTASSERT(offsetof(struct vmcb, state) == 0x400); 397 398 struct vmcb_segment *vmcb_segptr(struct vmcb *vmcb, int type); 399 uint64_t *vmcb_regptr(struct vmcb *vmcb, int ident, uint32_t *dirtyp); 400 uint64_t *vmcb_msr_ptr(struct vmcb *vmcb, uint32_t ident, uint32_t *dirtyp); 401 402 #endif /* _KERNEL */ 403 #endif /* _VMCB_H_ */ 404