1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /* 82571EB Gigabit Ethernet Controller
36 * 82571EB Gigabit Ethernet Controller (Copper)
37 * 82571EB Gigabit Ethernet Controller (Fiber)
38 * 82571EB Dual Port Gigabit Mezzanine Adapter
39 * 82571EB Quad Port Gigabit Mezzanine Adapter
40 * 82571PT Gigabit PT Quad Port Server ExpressModule
41 * 82572EI Gigabit Ethernet Controller (Copper)
42 * 82572EI Gigabit Ethernet Controller (Fiber)
43 * 82572EI Gigabit Ethernet Controller
44 * 82573V Gigabit Ethernet Controller (Copper)
45 * 82573E Gigabit Ethernet Controller (Copper)
46 * 82573L Gigabit Ethernet Controller
47 * 82574L Gigabit Network Connection
48 * 82583V Gigabit Network Connection
49 */
50
51 #include "e1000_api.h"
52
53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
54 static void e1000_release_nvm_82571(struct e1000_hw *hw);
55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
61 bool active);
62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
63 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
64 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
66 static s32 e1000_led_on_82574(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
74 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
75 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
76 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
77 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
78 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
79 bool active);
80 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
81 bool active);
82 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
83 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
84 u16 words, u16 *data);
85 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
86 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
87
88 /**
89 * e1000_init_phy_params_82571 - Init PHY func ptrs.
90 * @hw: pointer to the HW structure
91 **/
e1000_init_phy_params_82571(struct e1000_hw * hw)92 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
93 {
94 struct e1000_phy_info *phy = &hw->phy;
95 s32 ret_val;
96
97 DEBUGFUNC("e1000_init_phy_params_82571");
98
99 if (hw->phy.media_type != e1000_media_type_copper) {
100 phy->type = e1000_phy_none;
101 return E1000_SUCCESS;
102 }
103
104 phy->addr = 1;
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
106 phy->reset_delay_us = 100;
107
108 phy->ops.check_reset_block = e1000_check_reset_block_generic;
109 phy->ops.reset = e1000_phy_hw_reset_generic;
110 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
111 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
112 phy->ops.power_up = e1000_power_up_phy_copper;
113 phy->ops.power_down = e1000_power_down_phy_copper_82571;
114
115 switch (hw->mac.type) {
116 case e1000_82571:
117 case e1000_82572:
118 phy->type = e1000_phy_igp_2;
119 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
120 phy->ops.get_info = e1000_get_phy_info_igp;
121 phy->ops.check_polarity = e1000_check_polarity_igp;
122 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
123 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
124 phy->ops.read_reg = e1000_read_phy_reg_igp;
125 phy->ops.write_reg = e1000_write_phy_reg_igp;
126 phy->ops.acquire = e1000_get_hw_semaphore_82571;
127 phy->ops.release = e1000_put_hw_semaphore;
128 break;
129 case e1000_82573:
130 phy->type = e1000_phy_m88;
131 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
132 phy->ops.get_info = e1000_get_phy_info_m88;
133 phy->ops.check_polarity = e1000_check_polarity_m88;
134 phy->ops.commit = e1000_phy_sw_reset_generic;
135 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
136 phy->ops.get_cable_length = e1000_get_cable_length_m88;
137 phy->ops.read_reg = e1000_read_phy_reg_m88;
138 phy->ops.write_reg = e1000_write_phy_reg_m88;
139 phy->ops.acquire = e1000_get_hw_semaphore_82571;
140 phy->ops.release = e1000_put_hw_semaphore;
141 break;
142 case e1000_82574:
143 case e1000_82583:
144
145 phy->type = e1000_phy_bm;
146 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
147 phy->ops.get_info = e1000_get_phy_info_m88;
148 phy->ops.check_polarity = e1000_check_polarity_m88;
149 phy->ops.commit = e1000_phy_sw_reset_generic;
150 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
151 phy->ops.get_cable_length = e1000_get_cable_length_m88;
152 phy->ops.read_reg = e1000_read_phy_reg_bm2;
153 phy->ops.write_reg = e1000_write_phy_reg_bm2;
154 phy->ops.acquire = e1000_get_hw_semaphore_82574;
155 phy->ops.release = e1000_put_hw_semaphore_82574;
156 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
157 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
158 break;
159 default:
160 return -E1000_ERR_PHY;
161 break;
162 }
163
164 /* This can only be done after all function pointers are setup. */
165 ret_val = e1000_get_phy_id_82571(hw);
166 if (ret_val) {
167 DEBUGOUT("Error getting PHY ID\n");
168 return ret_val;
169 }
170
171 /* Verify phy id */
172 switch (hw->mac.type) {
173 case e1000_82571:
174 case e1000_82572:
175 if (phy->id != IGP01E1000_I_PHY_ID)
176 ret_val = -E1000_ERR_PHY;
177 break;
178 case e1000_82573:
179 if (phy->id != M88E1111_I_PHY_ID)
180 ret_val = -E1000_ERR_PHY;
181 break;
182 case e1000_82574:
183 case e1000_82583:
184 if (phy->id != BME1000_E_PHY_ID_R2)
185 ret_val = -E1000_ERR_PHY;
186 break;
187 default:
188 ret_val = -E1000_ERR_PHY;
189 break;
190 }
191
192 if (ret_val)
193 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
194
195 return ret_val;
196 }
197
198 /**
199 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
200 * @hw: pointer to the HW structure
201 **/
e1000_init_nvm_params_82571(struct e1000_hw * hw)202 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
203 {
204 struct e1000_nvm_info *nvm = &hw->nvm;
205 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
206 u16 size;
207
208 DEBUGFUNC("e1000_init_nvm_params_82571");
209
210 nvm->opcode_bits = 8;
211 nvm->delay_usec = 1;
212 switch (nvm->override) {
213 case e1000_nvm_override_spi_large:
214 nvm->page_size = 32;
215 nvm->address_bits = 16;
216 break;
217 case e1000_nvm_override_spi_small:
218 nvm->page_size = 8;
219 nvm->address_bits = 8;
220 break;
221 default:
222 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
223 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
224 break;
225 }
226
227 switch (hw->mac.type) {
228 case e1000_82573:
229 case e1000_82574:
230 case e1000_82583:
231 if (((eecd >> 15) & 0x3) == 0x3) {
232 nvm->type = e1000_nvm_flash_hw;
233 nvm->word_size = 2048;
234 /* Autonomous Flash update bit must be cleared due
235 * to Flash update issue.
236 */
237 eecd &= ~E1000_EECD_AUPDEN;
238 E1000_WRITE_REG(hw, E1000_EECD, eecd);
239 break;
240 }
241 /* FALLTHROUGH */
242 default:
243 nvm->type = e1000_nvm_eeprom_spi;
244 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
245 E1000_EECD_SIZE_EX_SHIFT);
246 /* Added to a constant, "size" becomes the left-shift value
247 * for setting word_size.
248 */
249 size += NVM_WORD_SIZE_BASE_SHIFT;
250
251 /* EEPROM access above 16k is unsupported */
252 if (size > 14)
253 size = 14;
254 nvm->word_size = 1 << size;
255 break;
256 }
257
258 /* Function Pointers */
259 switch (hw->mac.type) {
260 case e1000_82574:
261 case e1000_82583:
262 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
263 nvm->ops.release = e1000_put_hw_semaphore_82574;
264 break;
265 default:
266 nvm->ops.acquire = e1000_acquire_nvm_82571;
267 nvm->ops.release = e1000_release_nvm_82571;
268 break;
269 }
270 nvm->ops.read = e1000_read_nvm_eerd;
271 nvm->ops.update = e1000_update_nvm_checksum_82571;
272 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
273 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
274 nvm->ops.write = e1000_write_nvm_82571;
275
276 return E1000_SUCCESS;
277 }
278
279 /**
280 * e1000_init_mac_params_82571 - Init MAC func ptrs.
281 * @hw: pointer to the HW structure
282 **/
e1000_init_mac_params_82571(struct e1000_hw * hw)283 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
284 {
285 struct e1000_mac_info *mac = &hw->mac;
286 u32 swsm = 0;
287 u32 swsm2 = 0;
288 bool force_clear_smbi = false;
289
290 DEBUGFUNC("e1000_init_mac_params_82571");
291
292 /* Set media type and media-dependent function pointers */
293 switch (hw->device_id) {
294 case E1000_DEV_ID_82571EB_FIBER:
295 case E1000_DEV_ID_82572EI_FIBER:
296 case E1000_DEV_ID_82571EB_QUAD_FIBER:
297 hw->phy.media_type = e1000_media_type_fiber;
298 mac->ops.setup_physical_interface =
299 e1000_setup_fiber_serdes_link_82571;
300 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
301 mac->ops.get_link_up_info =
302 e1000_get_speed_and_duplex_fiber_serdes_generic;
303 break;
304 case E1000_DEV_ID_82571EB_SERDES:
305 case E1000_DEV_ID_82571EB_SERDES_DUAL:
306 case E1000_DEV_ID_82571EB_SERDES_QUAD:
307 case E1000_DEV_ID_82572EI_SERDES:
308 hw->phy.media_type = e1000_media_type_internal_serdes;
309 mac->ops.setup_physical_interface =
310 e1000_setup_fiber_serdes_link_82571;
311 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
312 mac->ops.get_link_up_info =
313 e1000_get_speed_and_duplex_fiber_serdes_generic;
314 break;
315 default:
316 hw->phy.media_type = e1000_media_type_copper;
317 mac->ops.setup_physical_interface =
318 e1000_setup_copper_link_82571;
319 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
320 mac->ops.get_link_up_info =
321 e1000_get_speed_and_duplex_copper_generic;
322 break;
323 }
324
325 /* Set mta register count */
326 mac->mta_reg_count = 128;
327 /* Set rar entry count */
328 mac->rar_entry_count = E1000_RAR_ENTRIES;
329 /* Set if part includes ASF firmware */
330 mac->asf_firmware_present = true;
331 /* Adaptive IFS supported */
332 mac->adaptive_ifs = true;
333
334 /* Function pointers */
335
336 /* bus type/speed/width */
337 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
338 /* reset */
339 mac->ops.reset_hw = e1000_reset_hw_82571;
340 /* hw initialization */
341 mac->ops.init_hw = e1000_init_hw_82571;
342 /* link setup */
343 mac->ops.setup_link = e1000_setup_link_82571;
344 /* multicast address update */
345 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
346 /* writing VFTA */
347 mac->ops.write_vfta = e1000_write_vfta_generic;
348 /* clearing VFTA */
349 mac->ops.clear_vfta = e1000_clear_vfta_82571;
350 /* read mac address */
351 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
352 /* ID LED init */
353 mac->ops.id_led_init = e1000_id_led_init_generic;
354 /* setup LED */
355 mac->ops.setup_led = e1000_setup_led_generic;
356 /* cleanup LED */
357 mac->ops.cleanup_led = e1000_cleanup_led_generic;
358 /* turn off LED */
359 mac->ops.led_off = e1000_led_off_generic;
360 /* clear hardware counters */
361 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
362
363 /* MAC-specific function pointers */
364 switch (hw->mac.type) {
365 case e1000_82573:
366 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
367 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
368 mac->ops.led_on = e1000_led_on_generic;
369 mac->ops.blink_led = e1000_blink_led_generic;
370
371 /* FWSM register */
372 mac->has_fwsm = true;
373 /* ARC supported; valid only if manageability features are
374 * enabled.
375 */
376 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
377 E1000_FWSM_MODE_MASK);
378 break;
379 case e1000_82574:
380 case e1000_82583:
381 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
382 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
383 mac->ops.led_on = e1000_led_on_82574;
384 break;
385 default:
386 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
387 mac->ops.led_on = e1000_led_on_generic;
388 mac->ops.blink_led = e1000_blink_led_generic;
389
390 /* FWSM register */
391 mac->has_fwsm = true;
392 break;
393 }
394
395 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
396 * first NVM or PHY access. This should be done for single-port
397 * devices, and for one port only on dual-port devices so that
398 * for those devices we can still use the SMBI lock to synchronize
399 * inter-port accesses to the PHY & NVM.
400 */
401 switch (hw->mac.type) {
402 case e1000_82571:
403 case e1000_82572:
404 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
405
406 if (!(swsm2 & E1000_SWSM2_LOCK)) {
407 /* Only do this for the first interface on this card */
408 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
409 E1000_SWSM2_LOCK);
410 force_clear_smbi = true;
411 } else {
412 force_clear_smbi = false;
413 }
414 break;
415 default:
416 force_clear_smbi = true;
417 break;
418 }
419
420 if (force_clear_smbi) {
421 /* Make sure SWSM.SMBI is clear */
422 swsm = E1000_READ_REG(hw, E1000_SWSM);
423 if (swsm & E1000_SWSM_SMBI) {
424 /* This bit should not be set on a first interface, and
425 * indicates that the bootagent or EFI code has
426 * improperly left this bit enabled
427 */
428 DEBUGOUT("Please update your 82571 Bootagent\n");
429 }
430 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
431 }
432
433 /* Initialze device specific counter of SMBI acquisition timeouts. */
434 hw->dev_spec._82571.smb_counter = 0;
435
436 return E1000_SUCCESS;
437 }
438
439 /**
440 * e1000_init_function_pointers_82571 - Init func ptrs.
441 * @hw: pointer to the HW structure
442 *
443 * Called to initialize all function pointers and parameters.
444 **/
e1000_init_function_pointers_82571(struct e1000_hw * hw)445 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
446 {
447 DEBUGFUNC("e1000_init_function_pointers_82571");
448
449 hw->mac.ops.init_params = e1000_init_mac_params_82571;
450 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
451 hw->phy.ops.init_params = e1000_init_phy_params_82571;
452 }
453
454 /**
455 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
456 * @hw: pointer to the HW structure
457 *
458 * Reads the PHY registers and stores the PHY ID and possibly the PHY
459 * revision in the hardware structure.
460 **/
e1000_get_phy_id_82571(struct e1000_hw * hw)461 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
462 {
463 struct e1000_phy_info *phy = &hw->phy;
464 s32 ret_val;
465 u16 phy_id = 0;
466
467 DEBUGFUNC("e1000_get_phy_id_82571");
468
469 switch (hw->mac.type) {
470 case e1000_82571:
471 case e1000_82572:
472 /* The 82571 firmware may still be configuring the PHY.
473 * In this case, we cannot access the PHY until the
474 * configuration is done. So we explicitly set the
475 * PHY ID.
476 */
477 phy->id = IGP01E1000_I_PHY_ID;
478 break;
479 case e1000_82573:
480 return e1000_get_phy_id(hw);
481 break;
482 case e1000_82574:
483 case e1000_82583:
484 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
485 if (ret_val)
486 return ret_val;
487
488 phy->id = (u32)phy_id << 16;
489 usec_delay(20);
490 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
491 if (ret_val)
492 return ret_val;
493
494 phy->id |= (u32)(phy_id);
495 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
496 break;
497 default:
498 return -E1000_ERR_PHY;
499 break;
500 }
501
502 return E1000_SUCCESS;
503 }
504
505 /**
506 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
507 * @hw: pointer to the HW structure
508 *
509 * Acquire the HW semaphore during reset.
510 *
511 **/
512 static s32
e1000_get_hw_semaphore_82574(struct e1000_hw * hw)513 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
514 {
515 u32 extcnf_ctrl;
516 s32 i = 0;
517 /* XXX assert that mutex is held */
518 DEBUGFUNC("e1000_get_hw_semaphore_82574");
519
520 ASSERT_CTX_LOCK_HELD(hw);
521 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
522 do {
523 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
524 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
525 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
526
527 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
528 break;
529
530 msec_delay(2);
531 i++;
532 } while (i < MDIO_OWNERSHIP_TIMEOUT);
533
534 if (i == MDIO_OWNERSHIP_TIMEOUT) {
535 /* Release semaphores */
536 e1000_put_hw_semaphore_82574(hw);
537 DEBUGOUT("Driver can't access the PHY\n");
538 return -E1000_ERR_PHY;
539 }
540
541 return E1000_SUCCESS;
542 }
543
544 /**
545 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
546 * @hw: pointer to the HW structure
547 *
548 * Release hardware semaphore used during reset.
549 *
550 **/
551 static void
e1000_put_hw_semaphore_82574(struct e1000_hw * hw)552 e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
553 {
554 u32 extcnf_ctrl;
555
556 DEBUGFUNC("e1000_put_hw_semaphore_82574");
557
558 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
559 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
560 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
561 }
562
563 /**
564 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
565 * @hw: pointer to the HW structure
566 * @active: true to enable LPLU, false to disable
567 *
568 * Sets the LPLU D0 state according to the active flag.
569 * LPLU will not be activated unless the
570 * device autonegotiation advertisement meets standards of
571 * either 10 or 10/100 or 10/100/1000 at all duplexes.
572 * This is a function pointer entry point only called by
573 * PHY setup routines.
574 **/
e1000_set_d0_lplu_state_82574(struct e1000_hw * hw,bool active)575 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
576 {
577 u32 data = E1000_READ_REG(hw, E1000_POEMB);
578
579 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
580
581 if (active)
582 data |= E1000_PHY_CTRL_D0A_LPLU;
583 else
584 data &= ~E1000_PHY_CTRL_D0A_LPLU;
585
586 E1000_WRITE_REG(hw, E1000_POEMB, data);
587 return E1000_SUCCESS;
588 }
589
590 /**
591 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
592 * @hw: pointer to the HW structure
593 * @active: boolean used to enable/disable lplu
594 *
595 * The low power link up (lplu) state is set to the power management level D3
596 * when active is true, else clear lplu for D3. LPLU
597 * is used during Dx states where the power conservation is most important.
598 * During driver activity, SmartSpeed should be enabled so performance is
599 * maintained.
600 **/
e1000_set_d3_lplu_state_82574(struct e1000_hw * hw,bool active)601 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
602 {
603 u32 data = E1000_READ_REG(hw, E1000_POEMB);
604
605 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
606
607 if (!active) {
608 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
609 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
610 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
611 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
612 data |= E1000_PHY_CTRL_NOND0A_LPLU;
613 }
614
615 E1000_WRITE_REG(hw, E1000_POEMB, data);
616 return E1000_SUCCESS;
617 }
618
619 /**
620 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
621 * @hw: pointer to the HW structure
622 *
623 * Acquire the hardware semaphore while preserving the 82571 inter-port
624 * compatibility policy.
625 **/
626 static s32
e1000_get_hw_semaphore_82571(struct e1000_hw * hw)627 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
628 {
629 u32 swsm;
630 s32 sw_timeout = hw->nvm.word_size + 1;
631 s32 fw_timeout = hw->nvm.word_size + 1;
632 s32 i = 0;
633
634 DEBUGFUNC("e1000_get_hw_semaphore_82571");
635
636 /*
637 * After three SMBI timeouts, minimize interference with an older
638 * peer driver which may not release the inter-port semaphore.
639 */
640 if (hw->dev_spec._82571.smb_counter > 2)
641 sw_timeout = 1;
642
643 while (i < sw_timeout) {
644 swsm = E1000_READ_REG(hw, E1000_SWSM);
645 if (!(swsm & E1000_SWSM_SMBI))
646 break;
647 usec_delay(50);
648 i++;
649 }
650
651 if (i == sw_timeout) {
652 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
653 hw->dev_spec._82571.smb_counter++;
654 }
655
656 for (i = 0; i < fw_timeout; i++) {
657 swsm = E1000_READ_REG(hw, E1000_SWSM);
658 E1000_WRITE_REG(hw, E1000_SWSM,
659 swsm | E1000_SWSM_SWESMBI);
660 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
661 break;
662 usec_delay(50);
663 }
664
665 if (i == fw_timeout) {
666 e1000_put_hw_semaphore(hw);
667 DEBUGOUT("Driver can't access the NVM\n");
668 return -E1000_ERR_NVM;
669 }
670
671 return E1000_SUCCESS;
672 }
673
674 /**
675 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
676 * @hw: pointer to the HW structure
677 *
678 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
679 * Then for non-82573 hardware, set the EEPROM access request bit and wait
680 * for EEPROM access grant bit. If the access grant bit is not set, release
681 * hardware semaphore.
682 **/
e1000_acquire_nvm_82571(struct e1000_hw * hw)683 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
684 {
685 s32 ret_val;
686
687 DEBUGFUNC("e1000_acquire_nvm_82571");
688
689 ret_val = e1000_get_hw_semaphore_82571(hw);
690 if (ret_val)
691 return ret_val;
692
693 switch (hw->mac.type) {
694 case e1000_82573:
695 break;
696 default:
697 ret_val = e1000_acquire_nvm_generic(hw);
698 break;
699 }
700
701 if (ret_val)
702 e1000_put_hw_semaphore(hw);
703
704 return ret_val;
705 }
706
707 /**
708 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
709 * @hw: pointer to the HW structure
710 *
711 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
712 **/
e1000_release_nvm_82571(struct e1000_hw * hw)713 static void e1000_release_nvm_82571(struct e1000_hw *hw)
714 {
715 DEBUGFUNC("e1000_release_nvm_82571");
716
717 e1000_release_nvm_generic(hw);
718 e1000_put_hw_semaphore(hw);
719 }
720
721 /**
722 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
723 * @hw: pointer to the HW structure
724 * @offset: offset within the EEPROM to be written to
725 * @words: number of words to write
726 * @data: 16 bit word(s) to be written to the EEPROM
727 *
728 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
729 *
730 * If e1000_update_nvm_checksum is not called after this function, the
731 * EEPROM will most likely contain an invalid checksum.
732 **/
e1000_write_nvm_82571(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)733 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
734 u16 *data)
735 {
736 s32 ret_val;
737
738 DEBUGFUNC("e1000_write_nvm_82571");
739
740 switch (hw->mac.type) {
741 case e1000_82573:
742 case e1000_82574:
743 case e1000_82583:
744 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
745 break;
746 case e1000_82571:
747 case e1000_82572:
748 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
749 break;
750 default:
751 ret_val = -E1000_ERR_NVM;
752 break;
753 }
754
755 return ret_val;
756 }
757
758 /**
759 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
760 * @hw: pointer to the HW structure
761 *
762 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
763 * up to the checksum. Then calculates the EEPROM checksum and writes the
764 * value to the EEPROM.
765 **/
e1000_update_nvm_checksum_82571(struct e1000_hw * hw)766 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
767 {
768 u32 eecd;
769 s32 ret_val;
770 u16 i;
771
772 DEBUGFUNC("e1000_update_nvm_checksum_82571");
773
774 ret_val = e1000_update_nvm_checksum_generic(hw);
775 if (ret_val)
776 return ret_val;
777
778 /* If our nvm is an EEPROM, then we're done
779 * otherwise, commit the checksum to the flash NVM.
780 */
781 if (hw->nvm.type != e1000_nvm_flash_hw)
782 return E1000_SUCCESS;
783
784 /* Check for pending operations. */
785 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
786 msec_delay(1);
787 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
788 break;
789 }
790
791 if (i == E1000_FLASH_UPDATES)
792 return -E1000_ERR_NVM;
793
794 /* Reset the firmware if using STM opcode. */
795 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
796 /* The enabling of and the actual reset must be done
797 * in two write cycles.
798 */
799 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
800 E1000_WRITE_FLUSH(hw);
801 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
802 }
803
804 /* Commit the write to flash */
805 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
806 E1000_WRITE_REG(hw, E1000_EECD, eecd);
807
808 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
809 msec_delay(1);
810 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
811 break;
812 }
813
814 if (i == E1000_FLASH_UPDATES)
815 return -E1000_ERR_NVM;
816
817 return E1000_SUCCESS;
818 }
819
820 /**
821 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
822 * @hw: pointer to the HW structure
823 *
824 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
825 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
826 **/
e1000_validate_nvm_checksum_82571(struct e1000_hw * hw)827 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
828 {
829 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
830
831 if (hw->nvm.type == e1000_nvm_flash_hw)
832 e1000_fix_nvm_checksum_82571(hw);
833
834 return e1000_validate_nvm_checksum_generic(hw);
835 }
836
837 /**
838 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
839 * @hw: pointer to the HW structure
840 * @offset: offset within the EEPROM to be written to
841 * @words: number of words to write
842 * @data: 16 bit word(s) to be written to the EEPROM
843 *
844 * After checking for invalid values, poll the EEPROM to ensure the previous
845 * command has completed before trying to write the next word. After write
846 * poll for completion.
847 *
848 * If e1000_update_nvm_checksum is not called after this function, the
849 * EEPROM will most likely contain an invalid checksum.
850 **/
e1000_write_nvm_eewr_82571(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)851 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
852 u16 words, u16 *data)
853 {
854 struct e1000_nvm_info *nvm = &hw->nvm;
855 u32 i, eewr = 0;
856 s32 ret_val = E1000_SUCCESS;
857
858 DEBUGFUNC("e1000_write_nvm_eewr_82571");
859
860 /* A check for invalid values: offset too large, too many words,
861 * and not enough words.
862 */
863 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
864 (words == 0)) {
865 DEBUGOUT("nvm parameter(s) out of bounds\n");
866 return -E1000_ERR_NVM;
867 }
868
869 for (i = 0; i < words; i++) {
870 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
871 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
872 E1000_NVM_RW_REG_START);
873
874 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
875 if (ret_val)
876 break;
877
878 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
879
880 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
881 if (ret_val)
882 break;
883 }
884
885 return ret_val;
886 }
887
888 /**
889 * e1000_get_cfg_done_82571 - Poll for configuration done
890 * @hw: pointer to the HW structure
891 *
892 * Reads the management control register for the config done bit to be set.
893 **/
e1000_get_cfg_done_82571(struct e1000_hw * hw)894 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
895 {
896 s32 timeout = PHY_CFG_TIMEOUT;
897
898 DEBUGFUNC("e1000_get_cfg_done_82571");
899
900 while (timeout) {
901 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
902 E1000_NVM_CFG_DONE_PORT_0)
903 break;
904 msec_delay(1);
905 timeout--;
906 }
907 if (!timeout) {
908 DEBUGOUT("MNG configuration cycle has not completed.\n");
909 return -E1000_ERR_RESET;
910 }
911
912 return E1000_SUCCESS;
913 }
914
915 /**
916 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
917 * @hw: pointer to the HW structure
918 * @active: true to enable LPLU, false to disable
919 *
920 * Sets the LPLU D0 state according to the active flag. When activating LPLU
921 * this function also disables smart speed and vice versa. LPLU will not be
922 * activated unless the device autonegotiation advertisement meets standards
923 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
924 * pointer entry point only called by PHY setup routines.
925 **/
e1000_set_d0_lplu_state_82571(struct e1000_hw * hw,bool active)926 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
927 {
928 struct e1000_phy_info *phy = &hw->phy;
929 s32 ret_val;
930 u16 data;
931
932 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
933
934 if (!(phy->ops.read_reg))
935 return E1000_SUCCESS;
936
937 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
938 if (ret_val)
939 return ret_val;
940
941 if (active) {
942 data |= IGP02E1000_PM_D0_LPLU;
943 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
944 data);
945 if (ret_val)
946 return ret_val;
947
948 /* When LPLU is enabled, we should disable SmartSpeed */
949 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
950 &data);
951 if (ret_val)
952 return ret_val;
953 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
954 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
955 data);
956 if (ret_val)
957 return ret_val;
958 } else {
959 data &= ~IGP02E1000_PM_D0_LPLU;
960 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
961 data);
962 if (ret_val)
963 return ret_val;
964 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
965 * during Dx states where the power conservation is most
966 * important. During driver activity we should enable
967 * SmartSpeed, so performance is maintained.
968 */
969 if (phy->smart_speed == e1000_smart_speed_on) {
970 ret_val = phy->ops.read_reg(hw,
971 IGP01E1000_PHY_PORT_CONFIG,
972 &data);
973 if (ret_val)
974 return ret_val;
975
976 data |= IGP01E1000_PSCFR_SMART_SPEED;
977 ret_val = phy->ops.write_reg(hw,
978 IGP01E1000_PHY_PORT_CONFIG,
979 data);
980 if (ret_val)
981 return ret_val;
982 } else if (phy->smart_speed == e1000_smart_speed_off) {
983 ret_val = phy->ops.read_reg(hw,
984 IGP01E1000_PHY_PORT_CONFIG,
985 &data);
986 if (ret_val)
987 return ret_val;
988
989 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
990 ret_val = phy->ops.write_reg(hw,
991 IGP01E1000_PHY_PORT_CONFIG,
992 data);
993 if (ret_val)
994 return ret_val;
995 }
996 }
997
998 return E1000_SUCCESS;
999 }
1000
1001 /**
1002 * e1000_reset_hw_82571 - Reset hardware
1003 * @hw: pointer to the HW structure
1004 *
1005 * This resets the hardware into a known state.
1006 **/
e1000_reset_hw_82571(struct e1000_hw * hw)1007 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1008 {
1009 u32 ctrl, ctrl_ext, eecd, tctl;
1010 s32 ret_val;
1011
1012 DEBUGFUNC("e1000_reset_hw_82571");
1013
1014 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1015 * on the last TLP read/write transaction when MAC is reset.
1016 */
1017 ret_val = e1000_disable_pcie_master_generic(hw);
1018 if (ret_val)
1019 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1020
1021 DEBUGOUT("Masking off all interrupts\n");
1022 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1023
1024 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1025 tctl = E1000_READ_REG(hw, E1000_TCTL);
1026 tctl &= ~E1000_TCTL_EN;
1027 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1028 E1000_WRITE_FLUSH(hw);
1029
1030 msec_delay(10);
1031
1032 /* Must acquire the MDIO ownership before MAC reset.
1033 * Ownership defaults to firmware after a reset.
1034 */
1035 switch (hw->mac.type) {
1036 case e1000_82573:
1037 case e1000_82574:
1038 case e1000_82583:
1039 ret_val = e1000_get_hw_semaphore_82574(hw);
1040 break;
1041 default:
1042 break;
1043 }
1044
1045 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1046
1047 DEBUGOUT("Issuing a global reset to MAC\n");
1048 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1049
1050 /* Must release MDIO ownership and mutex after MAC reset. */
1051 switch (hw->mac.type) {
1052 case e1000_82573:
1053 case e1000_82574:
1054 case e1000_82583:
1055 /* Release mutex only if the hw semaphore is acquired */
1056 if (!ret_val)
1057 e1000_put_hw_semaphore_82574(hw);
1058 break;
1059 default:
1060 /* we didn't get the semaphore no need to put it */
1061 break;
1062 }
1063
1064 if (hw->nvm.type == e1000_nvm_flash_hw) {
1065 usec_delay(10);
1066 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1067 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1068 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1069 E1000_WRITE_FLUSH(hw);
1070 }
1071
1072 ret_val = e1000_get_auto_rd_done_generic(hw);
1073 if (ret_val)
1074 /* We don't want to continue accessing MAC registers. */
1075 return ret_val;
1076
1077 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1078 * Need to wait for Phy configuration completion before accessing
1079 * NVM and Phy.
1080 */
1081
1082 switch (hw->mac.type) {
1083 case e1000_82571:
1084 case e1000_82572:
1085 /* REQ and GNT bits need to be cleared when using AUTO_RD
1086 * to access the EEPROM.
1087 */
1088 eecd = E1000_READ_REG(hw, E1000_EECD);
1089 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1090 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1091 break;
1092 case e1000_82573:
1093 case e1000_82574:
1094 case e1000_82583:
1095 msec_delay(25);
1096 break;
1097 default:
1098 break;
1099 }
1100
1101 /* Clear any pending interrupt events. */
1102 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1103 E1000_READ_REG(hw, E1000_ICR);
1104
1105 if (hw->mac.type == e1000_82571) {
1106 /* Install any alternate MAC address into RAR0 */
1107 ret_val = e1000_check_alt_mac_addr_generic(hw);
1108 if (ret_val)
1109 return ret_val;
1110
1111 e1000_set_laa_state_82571(hw, true);
1112 }
1113
1114 /* Reinitialize the 82571 serdes link state machine */
1115 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1116 hw->mac.serdes_link_state = e1000_serdes_link_down;
1117
1118 return E1000_SUCCESS;
1119 }
1120
1121 /**
1122 * e1000_init_hw_82571 - Initialize hardware
1123 * @hw: pointer to the HW structure
1124 *
1125 * This inits the hardware readying it for operation.
1126 **/
e1000_init_hw_82571(struct e1000_hw * hw)1127 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1128 {
1129 struct e1000_mac_info *mac = &hw->mac;
1130 u32 reg_data;
1131 s32 ret_val;
1132 u16 i, rar_count = mac->rar_entry_count;
1133
1134 DEBUGFUNC("e1000_init_hw_82571");
1135
1136 e1000_initialize_hw_bits_82571(hw);
1137
1138 /* Initialize identification LED */
1139 ret_val = mac->ops.id_led_init(hw);
1140 /* An error is not fatal and we should not stop init due to this */
1141 if (ret_val)
1142 DEBUGOUT("Error initializing identification LED\n");
1143
1144 /* Disabling VLAN filtering */
1145 DEBUGOUT("Initializing the IEEE VLAN\n");
1146 mac->ops.clear_vfta(hw);
1147
1148 /* Setup the receive address.
1149 * If, however, a locally administered address was assigned to the
1150 * 82571, we must reserve a RAR for it to work around an issue where
1151 * resetting one port will reload the MAC on the other port.
1152 */
1153 if (e1000_get_laa_state_82571(hw))
1154 rar_count--;
1155 e1000_init_rx_addrs_generic(hw, rar_count);
1156
1157 /* Zero out the Multicast HASH table */
1158 DEBUGOUT("Zeroing the MTA\n");
1159 for (i = 0; i < mac->mta_reg_count; i++)
1160 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1161
1162 /* Setup link and flow control */
1163 ret_val = mac->ops.setup_link(hw);
1164
1165 /* Set the transmit descriptor write-back policy */
1166 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1167 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1168 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1169 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1170
1171 /* ...for both queues. */
1172 switch (mac->type) {
1173 case e1000_82573:
1174 e1000_enable_tx_pkt_filtering_generic(hw);
1175 /* FALLTHROUGH */
1176 case e1000_82574:
1177 case e1000_82583:
1178 reg_data = E1000_READ_REG(hw, E1000_GCR);
1179 /* 82574 Errata 25, 82583 Errata 12 */
1180 reg_data &= ~E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1181 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1182 break;
1183 default:
1184 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1185 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1186 E1000_TXDCTL_FULL_TX_DESC_WB |
1187 E1000_TXDCTL_COUNT_DESC);
1188 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1189 break;
1190 }
1191
1192 /* Clear all of the statistics registers (clear on read). It is
1193 * important that we do this after we have tried to establish link
1194 * because the symbol error count will increment wildly if there
1195 * is no link.
1196 */
1197 e1000_clear_hw_cntrs_82571(hw);
1198
1199 return ret_val;
1200 }
1201
1202 /**
1203 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1204 * @hw: pointer to the HW structure
1205 *
1206 * Initializes required hardware-dependent bits needed for normal operation.
1207 **/
e1000_initialize_hw_bits_82571(struct e1000_hw * hw)1208 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1209 {
1210 u32 reg;
1211
1212 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1213
1214 /* Transmit Descriptor Control 0 */
1215 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1216 reg |= (1 << 22);
1217 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1218
1219 /* Transmit Descriptor Control 1 */
1220 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1221 reg |= (1 << 22);
1222 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1223
1224 /* Transmit Arbitration Control 0 */
1225 reg = E1000_READ_REG(hw, E1000_TARC(0));
1226 reg &= ~(0xF << 27); /* 30:27 */
1227 switch (hw->mac.type) {
1228 case e1000_82571:
1229 case e1000_82572:
1230 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1231 break;
1232 case e1000_82574:
1233 case e1000_82583:
1234 reg |= (1 << 26);
1235 break;
1236 default:
1237 break;
1238 }
1239 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1240
1241 /* Transmit Arbitration Control 1 */
1242 reg = E1000_READ_REG(hw, E1000_TARC(1));
1243 switch (hw->mac.type) {
1244 case e1000_82571:
1245 case e1000_82572:
1246 reg &= ~((1 << 29) | (1 << 30));
1247 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1248 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1249 reg &= ~(1 << 28);
1250 else
1251 reg |= (1 << 28);
1252 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1253 break;
1254 default:
1255 break;
1256 }
1257
1258 /* Device Control */
1259 switch (hw->mac.type) {
1260 case e1000_82573:
1261 case e1000_82574:
1262 case e1000_82583:
1263 reg = E1000_READ_REG(hw, E1000_CTRL);
1264 reg &= ~(1 << 29);
1265 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1266 break;
1267 default:
1268 break;
1269 }
1270
1271 /* Extended Device Control */
1272 switch (hw->mac.type) {
1273 case e1000_82573:
1274 case e1000_82574:
1275 case e1000_82583:
1276 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1277 reg &= ~(1 << 23);
1278 reg |= (1 << 22);
1279 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1280 break;
1281 default:
1282 break;
1283 }
1284
1285 if (hw->mac.type == e1000_82571) {
1286 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1287 reg |= E1000_PBA_ECC_CORR_EN;
1288 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1289 }
1290
1291 /* Workaround for hardware errata.
1292 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1293 */
1294 if ((hw->mac.type == e1000_82571) ||
1295 (hw->mac.type == e1000_82572)) {
1296 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1297 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1298 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1299 }
1300
1301 /* Disable IPv6 extension header parsing because some malformed
1302 * IPv6 headers can hang the Rx.
1303 */
1304 if (hw->mac.type <= e1000_82573) {
1305 reg = E1000_READ_REG(hw, E1000_RFCTL);
1306 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1307 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1308 }
1309
1310 /* PCI-Ex Control Registers */
1311 switch (hw->mac.type) {
1312 case e1000_82574:
1313 case e1000_82583:
1314 reg = E1000_READ_REG(hw, E1000_GCR);
1315 reg |= (1 << 22);
1316 E1000_WRITE_REG(hw, E1000_GCR, reg);
1317
1318 /* Workaround for hardware errata.
1319 * apply workaround for hardware errata documented in errata
1320 * docs Fixes issue where some error prone or unreliable PCIe
1321 * completions are occurring, particularly with ASPM enabled.
1322 * Without fix, issue can cause Tx timeouts.
1323 */
1324 reg = E1000_READ_REG(hw, E1000_GCR2);
1325 reg |= 1;
1326 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1327 break;
1328 default:
1329 break;
1330 }
1331
1332 return;
1333 }
1334
1335 /**
1336 * e1000_clear_vfta_82571 - Clear VLAN filter table
1337 * @hw: pointer to the HW structure
1338 *
1339 * Clears the register array which contains the VLAN filter table by
1340 * setting all the values to 0.
1341 **/
e1000_clear_vfta_82571(struct e1000_hw * hw)1342 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1343 {
1344 u32 offset;
1345 u32 vfta_value = 0;
1346 u32 vfta_offset = 0;
1347 u32 vfta_bit_in_reg = 0;
1348
1349 DEBUGFUNC("e1000_clear_vfta_82571");
1350
1351 switch (hw->mac.type) {
1352 case e1000_82573:
1353 case e1000_82574:
1354 case e1000_82583:
1355 if (hw->mng_cookie.vlan_id != 0) {
1356 /* The VFTA is a 4096b bit-field, each identifying
1357 * a single VLAN ID. The following operations
1358 * determine which 32b entry (i.e. offset) into the
1359 * array we want to set the VLAN ID (i.e. bit) of
1360 * the manageability unit.
1361 */
1362 vfta_offset = (hw->mng_cookie.vlan_id >>
1363 E1000_VFTA_ENTRY_SHIFT) &
1364 E1000_VFTA_ENTRY_MASK;
1365 vfta_bit_in_reg =
1366 1U << (hw->mng_cookie.vlan_id &
1367 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1368 }
1369 break;
1370 default:
1371 break;
1372 }
1373 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1374 /* If the offset we want to clear is the same offset of the
1375 * manageability VLAN ID, then clear all bits except that of
1376 * the manageability unit.
1377 */
1378 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1379 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1380 E1000_WRITE_FLUSH(hw);
1381 }
1382 }
1383
1384 /**
1385 * e1000_check_mng_mode_82574 - Check manageability is enabled
1386 * @hw: pointer to the HW structure
1387 *
1388 * Reads the NVM Initialization Control Word 2 and returns true
1389 * (>0) if any manageability is enabled, else false (0).
1390 **/
e1000_check_mng_mode_82574(struct e1000_hw * hw)1391 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1392 {
1393 u16 data;
1394 s32 ret_val;
1395
1396 DEBUGFUNC("e1000_check_mng_mode_82574");
1397
1398 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1399 if (ret_val)
1400 return false;
1401
1402 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1403 }
1404
1405 /**
1406 * e1000_led_on_82574 - Turn LED on
1407 * @hw: pointer to the HW structure
1408 *
1409 * Turn LED on.
1410 **/
e1000_led_on_82574(struct e1000_hw * hw)1411 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1412 {
1413 u32 ctrl;
1414 u32 i;
1415
1416 DEBUGFUNC("e1000_led_on_82574");
1417
1418 ctrl = hw->mac.ledctl_mode2;
1419 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1420 /* If no link, then turn LED on by setting the invert bit
1421 * for each LED that's "on" (0x0E) in ledctl_mode2.
1422 */
1423 for (i = 0; i < 4; i++)
1424 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1425 E1000_LEDCTL_MODE_LED_ON)
1426 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1427 }
1428 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1429
1430 return E1000_SUCCESS;
1431 }
1432
1433 /**
1434 * e1000_check_phy_82574 - check 82574 phy hung state
1435 * @hw: pointer to the HW structure
1436 *
1437 * Returns whether phy is hung or not
1438 **/
e1000_check_phy_82574(struct e1000_hw * hw)1439 bool e1000_check_phy_82574(struct e1000_hw *hw)
1440 {
1441 u16 status_1kbt = 0;
1442 u16 receive_errors = 0;
1443 s32 ret_val;
1444
1445 DEBUGFUNC("e1000_check_phy_82574");
1446
1447 /* Read PHY Receive Error counter first, if its is max - all F's then
1448 * read the Base1000T status register If both are max then PHY is hung.
1449 */
1450 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1451 &receive_errors);
1452 if (ret_val)
1453 return false;
1454 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1455 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1456 &status_1kbt);
1457 if (ret_val)
1458 return false;
1459 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1460 E1000_IDLE_ERROR_COUNT_MASK)
1461 return true;
1462 }
1463
1464 return false;
1465 }
1466
1467
1468 /**
1469 * e1000_setup_link_82571 - Setup flow control and link settings
1470 * @hw: pointer to the HW structure
1471 *
1472 * Determines which flow control settings to use, then configures flow
1473 * control. Calls the appropriate media-specific link configuration
1474 * function. Assuming the adapter has a valid link partner, a valid link
1475 * should be established. Assumes the hardware has previously been reset
1476 * and the transmitter and receiver are not enabled.
1477 **/
e1000_setup_link_82571(struct e1000_hw * hw)1478 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1479 {
1480 DEBUGFUNC("e1000_setup_link_82571");
1481
1482 /* 82573 does not have a word in the NVM to determine
1483 * the default flow control setting, so we explicitly
1484 * set it to full.
1485 */
1486 switch (hw->mac.type) {
1487 case e1000_82573:
1488 case e1000_82574:
1489 case e1000_82583:
1490 if (hw->fc.requested_mode == e1000_fc_default)
1491 hw->fc.requested_mode = e1000_fc_full;
1492 break;
1493 default:
1494 break;
1495 }
1496
1497 return e1000_setup_link_generic(hw);
1498 }
1499
1500 /**
1501 * e1000_setup_copper_link_82571 - Configure copper link settings
1502 * @hw: pointer to the HW structure
1503 *
1504 * Configures the link for auto-neg or forced speed and duplex. Then we check
1505 * for link, once link is established calls to configure collision distance
1506 * and flow control are called.
1507 **/
e1000_setup_copper_link_82571(struct e1000_hw * hw)1508 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1509 {
1510 u32 ctrl;
1511 s32 ret_val;
1512
1513 DEBUGFUNC("e1000_setup_copper_link_82571");
1514
1515 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1516 ctrl |= E1000_CTRL_SLU;
1517 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1518 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1519
1520 switch (hw->phy.type) {
1521 case e1000_phy_m88:
1522 case e1000_phy_bm:
1523 ret_val = e1000_copper_link_setup_m88(hw);
1524 break;
1525 case e1000_phy_igp_2:
1526 ret_val = e1000_copper_link_setup_igp(hw);
1527 break;
1528 default:
1529 return -E1000_ERR_PHY;
1530 break;
1531 }
1532
1533 if (ret_val)
1534 return ret_val;
1535
1536 return e1000_setup_copper_link_generic(hw);
1537 }
1538
1539 /**
1540 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1541 * @hw: pointer to the HW structure
1542 *
1543 * Configures collision distance and flow control for fiber and serdes links.
1544 * Upon successful setup, poll for link.
1545 **/
e1000_setup_fiber_serdes_link_82571(struct e1000_hw * hw)1546 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1547 {
1548 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1549
1550 switch (hw->mac.type) {
1551 case e1000_82571:
1552 case e1000_82572:
1553 /* If SerDes loopback mode is entered, there is no form
1554 * of reset to take the adapter out of that mode. So we
1555 * have to explicitly take the adapter out of loopback
1556 * mode. This prevents drivers from twiddling their thumbs
1557 * if another tool failed to take it out of loopback mode.
1558 */
1559 E1000_WRITE_REG(hw, E1000_SCTL,
1560 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1561 break;
1562 default:
1563 break;
1564 }
1565
1566 return e1000_setup_fiber_serdes_link_generic(hw);
1567 }
1568
1569 /**
1570 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1571 * @hw: pointer to the HW structure
1572 *
1573 * Reports the link state as up or down.
1574 *
1575 * If autonegotiation is supported by the link partner, the link state is
1576 * determined by the result of autonegotiation. This is the most likely case.
1577 * If autonegotiation is not supported by the link partner, and the link
1578 * has a valid signal, force the link up.
1579 *
1580 * The link state is represented internally here by 4 states:
1581 *
1582 * 1) down
1583 * 2) autoneg_progress
1584 * 3) autoneg_complete (the link successfully autonegotiated)
1585 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1586 *
1587 **/
e1000_check_for_serdes_link_82571(struct e1000_hw * hw)1588 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1589 {
1590 struct e1000_mac_info *mac = &hw->mac;
1591 u32 rxcw;
1592 u32 ctrl;
1593 u32 status;
1594 u32 txcw;
1595 u32 i;
1596 s32 ret_val = E1000_SUCCESS;
1597
1598 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1599
1600 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1601 status = E1000_READ_REG(hw, E1000_STATUS);
1602 E1000_READ_REG(hw, E1000_RXCW);
1603 /* SYNCH bit and IV bit are sticky */
1604 usec_delay(10);
1605 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1606
1607 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1608 /* Receiver is synchronized with no invalid bits. */
1609 switch (mac->serdes_link_state) {
1610 case e1000_serdes_link_autoneg_complete:
1611 if (!(status & E1000_STATUS_LU)) {
1612 /* We have lost link, retry autoneg before
1613 * reporting link failure
1614 */
1615 mac->serdes_link_state =
1616 e1000_serdes_link_autoneg_progress;
1617 mac->serdes_has_link = false;
1618 DEBUGOUT("AN_UP -> AN_PROG\n");
1619 } else {
1620 mac->serdes_has_link = true;
1621 }
1622 break;
1623
1624 case e1000_serdes_link_forced_up:
1625 /* If we are receiving /C/ ordered sets, re-enable
1626 * auto-negotiation in the TXCW register and disable
1627 * forced link in the Device Control register in an
1628 * attempt to auto-negotiate with our link partner.
1629 */
1630 if (rxcw & E1000_RXCW_C) {
1631 /* Enable autoneg, and unforce link up */
1632 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1633 E1000_WRITE_REG(hw, E1000_CTRL,
1634 (ctrl & ~E1000_CTRL_SLU));
1635 mac->serdes_link_state =
1636 e1000_serdes_link_autoneg_progress;
1637 mac->serdes_has_link = false;
1638 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1639 } else {
1640 mac->serdes_has_link = true;
1641 }
1642 break;
1643
1644 case e1000_serdes_link_autoneg_progress:
1645 if (rxcw & E1000_RXCW_C) {
1646 /* We received /C/ ordered sets, meaning the
1647 * link partner has autonegotiated, and we can
1648 * trust the Link Up (LU) status bit.
1649 */
1650 if (status & E1000_STATUS_LU) {
1651 mac->serdes_link_state =
1652 e1000_serdes_link_autoneg_complete;
1653 DEBUGOUT("AN_PROG -> AN_UP\n");
1654 mac->serdes_has_link = true;
1655 } else {
1656 /* Autoneg completed, but failed. */
1657 mac->serdes_link_state =
1658 e1000_serdes_link_down;
1659 DEBUGOUT("AN_PROG -> DOWN\n");
1660 }
1661 } else {
1662 /* The link partner did not autoneg.
1663 * Force link up and full duplex, and change
1664 * state to forced.
1665 */
1666 E1000_WRITE_REG(hw, E1000_TXCW,
1667 (mac->txcw & ~E1000_TXCW_ANE));
1668 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1669 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1670
1671 /* Configure Flow Control after link up. */
1672 ret_val =
1673 e1000_config_fc_after_link_up_generic(hw);
1674 if (ret_val) {
1675 DEBUGOUT("Error config flow control\n");
1676 break;
1677 }
1678 mac->serdes_link_state =
1679 e1000_serdes_link_forced_up;
1680 mac->serdes_has_link = true;
1681 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1682 }
1683 break;
1684
1685 case e1000_serdes_link_down:
1686 default:
1687 /* The link was down but the receiver has now gained
1688 * valid sync, so lets see if we can bring the link
1689 * up.
1690 */
1691 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1692 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1693 ~E1000_CTRL_SLU));
1694 mac->serdes_link_state =
1695 e1000_serdes_link_autoneg_progress;
1696 mac->serdes_has_link = false;
1697 DEBUGOUT("DOWN -> AN_PROG\n");
1698 break;
1699 }
1700 } else {
1701 if (!(rxcw & E1000_RXCW_SYNCH)) {
1702 mac->serdes_has_link = false;
1703 mac->serdes_link_state = e1000_serdes_link_down;
1704 DEBUGOUT("ANYSTATE -> DOWN\n");
1705 } else {
1706 /* Check several times, if SYNCH bit and CONFIG
1707 * bit both are consistently 1 then simply ignore
1708 * the IV bit and restart Autoneg
1709 */
1710 for (i = 0; i < AN_RETRY_COUNT; i++) {
1711 usec_delay(10);
1712 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1713 if ((rxcw & E1000_RXCW_SYNCH) &&
1714 (rxcw & E1000_RXCW_C))
1715 continue;
1716
1717 if (rxcw & E1000_RXCW_IV) {
1718 mac->serdes_has_link = false;
1719 mac->serdes_link_state =
1720 e1000_serdes_link_down;
1721 DEBUGOUT("ANYSTATE -> DOWN\n");
1722 break;
1723 }
1724 }
1725
1726 if (i == AN_RETRY_COUNT) {
1727 txcw = E1000_READ_REG(hw, E1000_TXCW);
1728 txcw |= E1000_TXCW_ANE;
1729 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1730 mac->serdes_link_state =
1731 e1000_serdes_link_autoneg_progress;
1732 mac->serdes_has_link = false;
1733 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1734 }
1735 }
1736 }
1737
1738 return ret_val;
1739 }
1740
1741 /**
1742 * e1000_valid_led_default_82571 - Verify a valid default LED config
1743 * @hw: pointer to the HW structure
1744 * @data: pointer to the NVM (EEPROM)
1745 *
1746 * Read the EEPROM for the current default LED configuration. If the
1747 * LED configuration is not valid, set to a valid LED configuration.
1748 **/
e1000_valid_led_default_82571(struct e1000_hw * hw,u16 * data)1749 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1750 {
1751 s32 ret_val;
1752
1753 DEBUGFUNC("e1000_valid_led_default_82571");
1754
1755 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1756 if (ret_val) {
1757 DEBUGOUT("NVM Read Error\n");
1758 return ret_val;
1759 }
1760
1761 switch (hw->mac.type) {
1762 case e1000_82573:
1763 case e1000_82574:
1764 case e1000_82583:
1765 if (*data == ID_LED_RESERVED_F746)
1766 *data = ID_LED_DEFAULT_82573;
1767 break;
1768 default:
1769 if (*data == ID_LED_RESERVED_0000 ||
1770 *data == ID_LED_RESERVED_FFFF)
1771 *data = ID_LED_DEFAULT;
1772 break;
1773 }
1774
1775 return E1000_SUCCESS;
1776 }
1777
1778 /**
1779 * e1000_get_laa_state_82571 - Get locally administered address state
1780 * @hw: pointer to the HW structure
1781 *
1782 * Retrieve and return the current locally administered address state.
1783 **/
e1000_get_laa_state_82571(struct e1000_hw * hw)1784 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1785 {
1786 DEBUGFUNC("e1000_get_laa_state_82571");
1787
1788 if (hw->mac.type != e1000_82571)
1789 return false;
1790
1791 return hw->dev_spec._82571.laa_is_present;
1792 }
1793
1794 /**
1795 * e1000_set_laa_state_82571 - Set locally administered address state
1796 * @hw: pointer to the HW structure
1797 * @state: enable/disable locally administered address
1798 *
1799 * Enable/Disable the current locally administered address state.
1800 **/
e1000_set_laa_state_82571(struct e1000_hw * hw,bool state)1801 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1802 {
1803 DEBUGFUNC("e1000_set_laa_state_82571");
1804
1805 if (hw->mac.type != e1000_82571)
1806 return;
1807
1808 hw->dev_spec._82571.laa_is_present = state;
1809
1810 /* If workaround is activated... */
1811 if (state)
1812 /* Hold a copy of the LAA in RAR[14] This is done so that
1813 * between the time RAR[0] gets clobbered and the time it
1814 * gets fixed, the actual LAA is in one of the RARs and no
1815 * incoming packets directed to this port are dropped.
1816 * Eventually the LAA will be in RAR[0] and RAR[14].
1817 */
1818 hw->mac.ops.rar_set(hw, hw->mac.addr,
1819 hw->mac.rar_entry_count - 1);
1820 return;
1821 }
1822
1823 /**
1824 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1825 * @hw: pointer to the HW structure
1826 *
1827 * Verifies that the EEPROM has completed the update. After updating the
1828 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1829 * the checksum fix is not implemented, we need to set the bit and update
1830 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1831 * we need to return bad checksum.
1832 **/
e1000_fix_nvm_checksum_82571(struct e1000_hw * hw)1833 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1834 {
1835 struct e1000_nvm_info *nvm = &hw->nvm;
1836 s32 ret_val;
1837 u16 data;
1838
1839 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1840
1841 if (nvm->type != e1000_nvm_flash_hw)
1842 return E1000_SUCCESS;
1843
1844 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1845 * 10h-12h. Checksum may need to be fixed.
1846 */
1847 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1848 if (ret_val)
1849 return ret_val;
1850
1851 if (!(data & 0x10)) {
1852 /* Read 0x23 and check bit 15. This bit is a 1
1853 * when the checksum has already been fixed. If
1854 * the checksum is still wrong and this bit is a
1855 * 1, we need to return bad checksum. Otherwise,
1856 * we need to set this bit to a 1 and update the
1857 * checksum.
1858 */
1859 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1860 if (ret_val)
1861 return ret_val;
1862
1863 if (!(data & 0x8000)) {
1864 data |= 0x8000;
1865 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1866 if (ret_val)
1867 return ret_val;
1868 ret_val = nvm->ops.update(hw);
1869 if (ret_val)
1870 return ret_val;
1871 }
1872 }
1873
1874 return E1000_SUCCESS;
1875 }
1876
1877
1878 /**
1879 * e1000_read_mac_addr_82571 - Read device MAC address
1880 * @hw: pointer to the HW structure
1881 **/
e1000_read_mac_addr_82571(struct e1000_hw * hw)1882 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1883 {
1884 DEBUGFUNC("e1000_read_mac_addr_82571");
1885
1886 if (hw->mac.type == e1000_82571) {
1887 s32 ret_val;
1888
1889 /* If there's an alternate MAC address place it in RAR0
1890 * so that it will override the Si installed default perm
1891 * address.
1892 */
1893 ret_val = e1000_check_alt_mac_addr_generic(hw);
1894 if (ret_val)
1895 return ret_val;
1896 }
1897
1898 return e1000_read_mac_addr_generic(hw);
1899 }
1900
1901 /**
1902 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1903 * @hw: pointer to the HW structure
1904 *
1905 * In the case of a PHY power down to save power, or to turn off link during a
1906 * driver unload, or wake on lan is not enabled, remove the link.
1907 **/
e1000_power_down_phy_copper_82571(struct e1000_hw * hw)1908 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1909 {
1910 struct e1000_phy_info *phy = &hw->phy;
1911 struct e1000_mac_info *mac = &hw->mac;
1912
1913 if (!phy->ops.check_reset_block)
1914 return;
1915
1916 /* If the management interface is not enabled, then power down */
1917 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1918 e1000_power_down_phy_copper(hw);
1919
1920 return;
1921 }
1922
1923 /**
1924 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1925 * @hw: pointer to the HW structure
1926 *
1927 * Clears the hardware counters by reading the counter registers.
1928 **/
e1000_clear_hw_cntrs_82571(struct e1000_hw * hw)1929 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1930 {
1931 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1932
1933 e1000_clear_hw_cntrs_base_generic(hw);
1934
1935 E1000_READ_REG(hw, E1000_PRC64);
1936 E1000_READ_REG(hw, E1000_PRC127);
1937 E1000_READ_REG(hw, E1000_PRC255);
1938 E1000_READ_REG(hw, E1000_PRC511);
1939 E1000_READ_REG(hw, E1000_PRC1023);
1940 E1000_READ_REG(hw, E1000_PRC1522);
1941 E1000_READ_REG(hw, E1000_PTC64);
1942 E1000_READ_REG(hw, E1000_PTC127);
1943 E1000_READ_REG(hw, E1000_PTC255);
1944 E1000_READ_REG(hw, E1000_PTC511);
1945 E1000_READ_REG(hw, E1000_PTC1023);
1946 E1000_READ_REG(hw, E1000_PTC1522);
1947
1948 E1000_READ_REG(hw, E1000_ALGNERRC);
1949 E1000_READ_REG(hw, E1000_RXERRC);
1950 E1000_READ_REG(hw, E1000_TNCRS);
1951 E1000_READ_REG(hw, E1000_CEXTERR);
1952 E1000_READ_REG(hw, E1000_TSCTC);
1953 E1000_READ_REG(hw, E1000_TSCTFC);
1954
1955 E1000_READ_REG(hw, E1000_MGTPRC);
1956 E1000_READ_REG(hw, E1000_MGTPDC);
1957 E1000_READ_REG(hw, E1000_MGTPTC);
1958
1959 E1000_READ_REG(hw, E1000_IAC);
1960 E1000_READ_REG(hw, E1000_ICRXOC);
1961
1962 E1000_READ_REG(hw, E1000_ICRXPTC);
1963 E1000_READ_REG(hw, E1000_ICRXATC);
1964 E1000_READ_REG(hw, E1000_ICTXPTC);
1965 E1000_READ_REG(hw, E1000_ICTXATC);
1966 E1000_READ_REG(hw, E1000_ICTXQEC);
1967 E1000_READ_REG(hw, E1000_ICTXQMTC);
1968 E1000_READ_REG(hw, E1000_ICRXDMTC);
1969 }
1970