1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/firmware/qcom/qcom_pas.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/remoteproc.h>
13 #include <linux/soc/qcom/mdt_loader.h>
14 #include <linux/soc/qcom/smem_state.h>
15 #include <linux/of_reserved_mem.h>
16 #include "ahb.h"
17 #include "debug.h"
18 #include "hif.h"
19
20 #define ATH12K_IRQ_CE0_OFFSET 4
21 #define ATH12K_UPD_IRQ_WRD_LEN 18
22
23 static struct ath12k_ahb_driver *ath12k_ahb_family_drivers[ATH12K_DEVICE_FAMILY_MAX];
24 static const char ath12k_userpd_irq[][9] = {"spawn",
25 "ready",
26 "stop-ack"};
27
28 /*
29 * Multi-UserPD Architecture:
30 *
31 * One Q6 RootPD (managed by separate rproc driver) supports multiple
32 * ath12k UserPDs. Each UserPD represents a WiFi radio instance.
33 *
34 * Lifecycle:
35 * - RootPD boots when first UserPD probes
36 * - All UserPDs share RootPD's SSR notifier
37 *
38 * Locking:
39 * - ath12k_rproc_info_lock: Protects g_rproc_info allocation/free
40 */
41 static struct ath12k_ahb_rproc_info *g_rproc_info;
42 static DEFINE_MUTEX(ath12k_rproc_info_lock);
43
44 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {
45 "misc-pulse1",
46 "misc-latch",
47 "sw-exception",
48 "watchdog",
49 "ce0",
50 "ce1",
51 "ce2",
52 "ce3",
53 "ce4",
54 "ce5",
55 "ce6",
56 "ce7",
57 "ce8",
58 "ce9",
59 "ce10",
60 "ce11",
61 "host2wbm-desc-feed",
62 "host2reo-re-injection",
63 "host2reo-command",
64 "host2rxdma-monitor-ring3",
65 "host2rxdma-monitor-ring2",
66 "host2rxdma-monitor-ring1",
67 "reo2ost-exception",
68 "wbm2host-rx-release",
69 "reo2host-status",
70 "reo2host-destination-ring4",
71 "reo2host-destination-ring3",
72 "reo2host-destination-ring2",
73 "reo2host-destination-ring1",
74 "rxdma2host-monitor-destination-mac3",
75 "rxdma2host-monitor-destination-mac2",
76 "rxdma2host-monitor-destination-mac1",
77 "ppdu-end-interrupts-mac3",
78 "ppdu-end-interrupts-mac2",
79 "ppdu-end-interrupts-mac1",
80 "rxdma2host-monitor-status-ring-mac3",
81 "rxdma2host-monitor-status-ring-mac2",
82 "rxdma2host-monitor-status-ring-mac1",
83 "host2rxdma-host-buf-ring-mac3",
84 "host2rxdma-host-buf-ring-mac2",
85 "host2rxdma-host-buf-ring-mac1",
86 "rxdma2host-destination-ring-mac3",
87 "rxdma2host-destination-ring-mac2",
88 "rxdma2host-destination-ring-mac1",
89 "host2tcl-input-ring4",
90 "host2tcl-input-ring3",
91 "host2tcl-input-ring2",
92 "host2tcl-input-ring1",
93 "wbm2host-tx-completions-ring4",
94 "wbm2host-tx-completions-ring3",
95 "wbm2host-tx-completions-ring2",
96 "wbm2host-tx-completions-ring1",
97 "tcl2host-status-ring",
98 };
99
100 enum ext_irq_num {
101 host2wbm_desc_feed = 16,
102 host2reo_re_injection,
103 host2reo_command,
104 host2rxdma_monitor_ring3,
105 host2rxdma_monitor_ring2,
106 host2rxdma_monitor_ring1,
107 reo2host_exception,
108 wbm2host_rx_release,
109 reo2host_status,
110 reo2host_destination_ring4,
111 reo2host_destination_ring3,
112 reo2host_destination_ring2,
113 reo2host_destination_ring1,
114 rxdma2host_monitor_destination_mac3,
115 rxdma2host_monitor_destination_mac2,
116 rxdma2host_monitor_destination_mac1,
117 ppdu_end_interrupts_mac3,
118 ppdu_end_interrupts_mac2,
119 ppdu_end_interrupts_mac1,
120 rxdma2host_monitor_status_ring_mac3,
121 rxdma2host_monitor_status_ring_mac2,
122 rxdma2host_monitor_status_ring_mac1,
123 host2rxdma_host_buf_ring_mac3,
124 host2rxdma_host_buf_ring_mac2,
125 host2rxdma_host_buf_ring_mac1,
126 rxdma2host_destination_ring_mac3,
127 rxdma2host_destination_ring_mac2,
128 rxdma2host_destination_ring_mac1,
129 host2tcl_input_ring4,
130 host2tcl_input_ring3,
131 host2tcl_input_ring2,
132 host2tcl_input_ring1,
133 wbm2host_tx_completions_ring4,
134 wbm2host_tx_completions_ring3,
135 wbm2host_tx_completions_ring2,
136 wbm2host_tx_completions_ring1,
137 tcl2host_status_ring,
138 };
139
ath12k_ahb_read32(struct ath12k_base * ab,u32 offset)140 static u32 ath12k_ahb_read32(struct ath12k_base *ab, u32 offset)
141 {
142 if (ab->ce_remap && offset < ab->cmem_offset)
143 return ioread32(ab->mem_ce + offset);
144 return ioread32(ab->mem + offset);
145 }
146
ath12k_ahb_write32(struct ath12k_base * ab,u32 offset,u32 value)147 static void ath12k_ahb_write32(struct ath12k_base *ab, u32 offset,
148 u32 value)
149 {
150 if (ab->ce_remap && offset < ab->cmem_offset)
151 iowrite32(value, ab->mem_ce + offset);
152 else
153 iowrite32(value, ab->mem + offset);
154 }
155
ath12k_ahb_cancel_workqueue(struct ath12k_base * ab)156 static void ath12k_ahb_cancel_workqueue(struct ath12k_base *ab)
157 {
158 int i;
159
160 for (i = 0; i < ab->hw_params->ce_count; i++) {
161 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
162
163 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
164 continue;
165
166 cancel_work_sync(&ce_pipe->intr_wq);
167 }
168 }
169
ath12k_ahb_ext_grp_disable(struct ath12k_ext_irq_grp * irq_grp)170 static void ath12k_ahb_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
171 {
172 int i;
173
174 for (i = 0; i < irq_grp->num_irq; i++)
175 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
176 }
177
__ath12k_ahb_ext_irq_disable(struct ath12k_base * ab)178 static void __ath12k_ahb_ext_irq_disable(struct ath12k_base *ab)
179 {
180 int i;
181
182 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
183 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
184
185 ath12k_ahb_ext_grp_disable(irq_grp);
186 if (irq_grp->napi_enabled) {
187 napi_synchronize(&irq_grp->napi);
188 napi_disable(&irq_grp->napi);
189 irq_grp->napi_enabled = false;
190 }
191 }
192 }
193
ath12k_ahb_ext_grp_enable(struct ath12k_ext_irq_grp * irq_grp)194 static void ath12k_ahb_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)
195 {
196 int i;
197
198 for (i = 0; i < irq_grp->num_irq; i++)
199 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
200 }
201
ath12k_ahb_setbit32(struct ath12k_base * ab,u8 bit,u32 offset)202 static void ath12k_ahb_setbit32(struct ath12k_base *ab, u8 bit, u32 offset)
203 {
204 u32 val;
205
206 val = ath12k_ahb_read32(ab, offset);
207 ath12k_ahb_write32(ab, offset, val | BIT(bit));
208 }
209
ath12k_ahb_clearbit32(struct ath12k_base * ab,u8 bit,u32 offset)210 static void ath12k_ahb_clearbit32(struct ath12k_base *ab, u8 bit, u32 offset)
211 {
212 u32 val;
213
214 val = ath12k_ahb_read32(ab, offset);
215 ath12k_ahb_write32(ab, offset, val & ~BIT(bit));
216 }
217
ath12k_ahb_ce_irq_enable(struct ath12k_base * ab,u16 ce_id)218 static void ath12k_ahb_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)
219 {
220 const struct ce_attr *ce_attr;
221 const struct ce_ie_addr *ce_ie_addr = ab->hw_params->ce_ie_addr;
222 u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr;
223
224 ie1_reg_addr = ce_ie_addr->ie1_reg_addr;
225 ie2_reg_addr = ce_ie_addr->ie2_reg_addr;
226 ie3_reg_addr = ce_ie_addr->ie3_reg_addr;
227
228 ce_attr = &ab->hw_params->host_ce_config[ce_id];
229 if (ce_attr->src_nentries)
230 ath12k_ahb_setbit32(ab, ce_id, ie1_reg_addr);
231
232 if (ce_attr->dest_nentries) {
233 ath12k_ahb_setbit32(ab, ce_id, ie2_reg_addr);
234 ath12k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
235 ie3_reg_addr);
236 }
237 }
238
ath12k_ahb_ce_irq_disable(struct ath12k_base * ab,u16 ce_id)239 static void ath12k_ahb_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)
240 {
241 const struct ce_attr *ce_attr;
242 const struct ce_ie_addr *ce_ie_addr = ab->hw_params->ce_ie_addr;
243 u32 ie1_reg_addr, ie2_reg_addr, ie3_reg_addr;
244
245 ie1_reg_addr = ce_ie_addr->ie1_reg_addr;
246 ie2_reg_addr = ce_ie_addr->ie2_reg_addr;
247 ie3_reg_addr = ce_ie_addr->ie3_reg_addr;
248
249 ce_attr = &ab->hw_params->host_ce_config[ce_id];
250 if (ce_attr->src_nentries)
251 ath12k_ahb_clearbit32(ab, ce_id, ie1_reg_addr);
252
253 if (ce_attr->dest_nentries) {
254 ath12k_ahb_clearbit32(ab, ce_id, ie2_reg_addr);
255 ath12k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
256 ie3_reg_addr);
257 }
258 }
259
ath12k_ahb_sync_ce_irqs(struct ath12k_base * ab)260 static void ath12k_ahb_sync_ce_irqs(struct ath12k_base *ab)
261 {
262 int i;
263 int irq_idx;
264
265 for (i = 0; i < ab->hw_params->ce_count; i++) {
266 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
267 continue;
268
269 irq_idx = ATH12K_IRQ_CE0_OFFSET + i;
270 synchronize_irq(ab->irq_num[irq_idx]);
271 }
272 }
273
ath12k_ahb_sync_ext_irqs(struct ath12k_base * ab)274 static void ath12k_ahb_sync_ext_irqs(struct ath12k_base *ab)
275 {
276 int i, j;
277 int irq_idx;
278
279 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
280 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
281
282 for (j = 0; j < irq_grp->num_irq; j++) {
283 irq_idx = irq_grp->irqs[j];
284 synchronize_irq(ab->irq_num[irq_idx]);
285 }
286 }
287 }
288
ath12k_ahb_ce_irqs_enable(struct ath12k_base * ab)289 static void ath12k_ahb_ce_irqs_enable(struct ath12k_base *ab)
290 {
291 int i;
292
293 for (i = 0; i < ab->hw_params->ce_count; i++) {
294 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
295 continue;
296 ath12k_ahb_ce_irq_enable(ab, i);
297 }
298 }
299
ath12k_ahb_ce_irqs_disable(struct ath12k_base * ab)300 static void ath12k_ahb_ce_irqs_disable(struct ath12k_base *ab)
301 {
302 int i;
303
304 for (i = 0; i < ab->hw_params->ce_count; i++) {
305 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
306 continue;
307 ath12k_ahb_ce_irq_disable(ab, i);
308 }
309 }
310
ath12k_ahb_start(struct ath12k_base * ab)311 static int ath12k_ahb_start(struct ath12k_base *ab)
312 {
313 ath12k_ahb_ce_irqs_enable(ab);
314 ath12k_ce_rx_post_buf(ab);
315
316 return 0;
317 }
318
ath12k_ahb_ext_irq_enable(struct ath12k_base * ab)319 static void ath12k_ahb_ext_irq_enable(struct ath12k_base *ab)
320 {
321 struct ath12k_ext_irq_grp *irq_grp;
322 int i;
323
324 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
325 irq_grp = &ab->ext_irq_grp[i];
326 if (!irq_grp->napi_enabled) {
327 napi_enable(&irq_grp->napi);
328 irq_grp->napi_enabled = true;
329 }
330 ath12k_ahb_ext_grp_enable(irq_grp);
331 }
332 }
333
ath12k_ahb_ext_irq_disable(struct ath12k_base * ab)334 static void ath12k_ahb_ext_irq_disable(struct ath12k_base *ab)
335 {
336 __ath12k_ahb_ext_irq_disable(ab);
337 ath12k_ahb_sync_ext_irqs(ab);
338 }
339
ath12k_ahb_stop(struct ath12k_base * ab)340 static void ath12k_ahb_stop(struct ath12k_base *ab)
341 {
342 if (!test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags))
343 ath12k_ahb_ce_irqs_disable(ab);
344 ath12k_ahb_sync_ce_irqs(ab);
345 ath12k_ahb_cancel_workqueue(ab);
346 timer_delete_sync(&ab->rx_replenish_retry);
347 ath12k_ce_cleanup_pipes(ab);
348 }
349
ath12k_ahb_power_up(struct ath12k_base * ab)350 static int ath12k_ahb_power_up(struct ath12k_base *ab)
351 {
352 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
353 char fw_name[ATH12K_USERPD_FW_NAME_LEN];
354 char fw2_name[ATH12K_USERPD_FW_NAME_LEN];
355 struct device *dev = ab->dev;
356 const struct firmware *fw, *fw2;
357 unsigned long time_left;
358 phys_addr_t mem_phys;
359 struct resource res;
360 void *mem_region;
361 size_t mem_size;
362 u32 pasid;
363 int ret;
364
365 ret = of_reserved_mem_region_to_resource_byname(dev->of_node, "q6-region",
366 &res);
367 if (ret)
368 return ret;
369
370 mem_phys = res.start;
371 mem_size = resource_size(&res);
372 mem_region = devm_memremap(dev, mem_phys, mem_size, MEMREMAP_WC);
373 if (IS_ERR(mem_region)) {
374 ath12k_err(ab, "unable to map memory region: %pa+%zx\n",
375 &res.start, mem_size);
376 return PTR_ERR(mem_region);
377 }
378
379 snprintf(fw_name, sizeof(fw_name), "%s/%s/%s%d%s", ATH12K_FW_DIR,
380 ab->hw_params->fw.dir, ATH12K_AHB_FW_PREFIX, ab_ahb->userpd_id,
381 ATH12K_AHB_FW_SUFFIX);
382
383 ret = request_firmware(&fw, fw_name, dev);
384 if (ret < 0) {
385 ath12k_err(ab, "request_firmware failed\n");
386 return ret;
387 }
388
389 ath12k_dbg(ab, ATH12K_DBG_AHB, "Booting fw image %s, size %zd\n", fw_name,
390 fw->size);
391
392 if (!fw->size) {
393 ath12k_err(ab, "Invalid firmware size\n");
394 ret = -EINVAL;
395 goto err_fw;
396 }
397
398 pasid = (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) |
399 ATH12K_AHB_UPD_SWID;
400
401 /* Load FW image to a reserved memory location */
402 if (ab_ahb->scm_auth_enabled)
403 ret = qcom_mdt_load(dev, fw, fw_name, pasid, mem_region,
404 mem_phys, mem_size, &mem_phys);
405 else
406 ret = qcom_mdt_load_no_init(dev, fw, fw_name, mem_region,
407 mem_phys, mem_size, &mem_phys);
408 if (ret) {
409 ath12k_err(ab, "Failed to load MDT segments: %d\n", ret);
410 goto err_fw;
411 }
412
413 snprintf(fw2_name, sizeof(fw2_name), "%s/%s/%s", ATH12K_FW_DIR,
414 ab->hw_params->fw.dir, ATH12K_AHB_FW2);
415
416 ret = request_firmware(&fw2, fw2_name, dev);
417 if (ret < 0) {
418 ath12k_err(ab, "request_firmware failed\n");
419 goto err_fw;
420 }
421
422 ath12k_dbg(ab, ATH12K_DBG_AHB, "Booting fw image %s, size %zd\n", fw2_name,
423 fw2->size);
424
425 if (!fw2->size) {
426 ath12k_err(ab, "Invalid firmware size\n");
427 ret = -EINVAL;
428 goto err_fw2;
429 }
430
431 ret = qcom_mdt_load_no_init(dev, fw2, fw2_name, mem_region, mem_phys,
432 mem_size, &mem_phys);
433 if (ret) {
434 ath12k_err(ab, "Failed to load MDT segments: %d\n", ret);
435 goto err_fw2;
436 }
437
438 if (ab_ahb->scm_auth_enabled) {
439 /* Authenticate FW image using peripheral ID */
440 ret = qcom_pas_auth_and_reset(pasid);
441 if (ret) {
442 ath12k_err(ab, "failed to boot the remote processor %d\n", ret);
443 goto err_fw2;
444 }
445 }
446
447 /* Instruct Q6 to spawn userPD thread */
448 ret = qcom_smem_state_update_bits(ab_ahb->spawn_state, BIT(ab_ahb->spawn_bit),
449 BIT(ab_ahb->spawn_bit));
450 if (ret) {
451 ath12k_err(ab, "Failed to update spawn state %d\n", ret);
452 goto err_fw2;
453 }
454
455 time_left = wait_for_completion_timeout(&ab_ahb->userpd_spawned,
456 ATH12K_USERPD_SPAWN_TIMEOUT);
457 if (!time_left) {
458 ath12k_err(ab, "UserPD spawn wait timed out\n");
459 ret = -ETIMEDOUT;
460 goto err_fw2;
461 }
462
463 time_left = wait_for_completion_timeout(&ab_ahb->userpd_ready,
464 ATH12K_USERPD_READY_TIMEOUT);
465 if (!time_left) {
466 ath12k_err(ab, "UserPD ready wait timed out\n");
467 ret = -ETIMEDOUT;
468 goto err_fw2;
469 }
470
471 qcom_smem_state_update_bits(ab_ahb->spawn_state, BIT(ab_ahb->spawn_bit), 0);
472
473 ath12k_dbg(ab, ATH12K_DBG_AHB, "UserPD%d is now UP\n", ab_ahb->userpd_id);
474
475 err_fw2:
476 release_firmware(fw2);
477 err_fw:
478 release_firmware(fw);
479 return ret;
480 }
481
ath12k_ahb_power_down(struct ath12k_base * ab,bool is_suspend)482 static void ath12k_ahb_power_down(struct ath12k_base *ab, bool is_suspend)
483 {
484 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
485 unsigned long time_left;
486 u32 pasid;
487 int ret;
488
489 qcom_smem_state_update_bits(ab_ahb->stop_state, BIT(ab_ahb->stop_bit),
490 BIT(ab_ahb->stop_bit));
491
492 time_left = wait_for_completion_timeout(&ab_ahb->userpd_stopped,
493 ATH12K_USERPD_STOP_TIMEOUT);
494 if (!time_left) {
495 ath12k_err(ab, "UserPD stop wait timed out\n");
496 return;
497 }
498
499 qcom_smem_state_update_bits(ab_ahb->stop_state, BIT(ab_ahb->stop_bit), 0);
500
501 if (ab_ahb->scm_auth_enabled) {
502 pasid = (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) |
503 ATH12K_AHB_UPD_SWID;
504 /* Release the firmware */
505 ret = qcom_pas_shutdown(pasid);
506 if (ret)
507 ath12k_err(ab, "PAS shutdown failed for userPD%d: %d\n",
508 ab_ahb->userpd_id, ret);
509 }
510 }
511
ath12k_ahb_init_qmi_ce_config(struct ath12k_base * ab)512 static void ath12k_ahb_init_qmi_ce_config(struct ath12k_base *ab)
513 {
514 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
515
516 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
517 cfg->tgt_ce = ab->hw_params->target_ce_config;
518 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
519 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
520 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
521 }
522
ath12k_ahb_ce_workqueue(struct work_struct * work)523 static void ath12k_ahb_ce_workqueue(struct work_struct *work)
524 {
525 struct ath12k_ce_pipe *ce_pipe = from_work(ce_pipe, work, intr_wq);
526
527 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
528
529 ath12k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
530 }
531
ath12k_ahb_ce_interrupt_handler(int irq,void * arg)532 static irqreturn_t ath12k_ahb_ce_interrupt_handler(int irq, void *arg)
533 {
534 struct ath12k_ce_pipe *ce_pipe = arg;
535
536 /* last interrupt received for this CE */
537 ce_pipe->timestamp = jiffies;
538
539 ath12k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
540
541 queue_work(system_bh_wq, &ce_pipe->intr_wq);
542
543 return IRQ_HANDLED;
544 }
545
ath12k_ahb_ext_grp_napi_poll(struct napi_struct * napi,int budget)546 static int ath12k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget)
547 {
548 struct ath12k_ext_irq_grp *irq_grp = container_of(napi,
549 struct ath12k_ext_irq_grp,
550 napi);
551 struct ath12k_base *ab = irq_grp->ab;
552 struct ath12k_dp *dp = ath12k_ab_to_dp(ab);
553 int work_done;
554
555 work_done = ath12k_dp_service_srng(dp, irq_grp, budget);
556 if (work_done < budget) {
557 napi_complete_done(napi, work_done);
558 ath12k_ahb_ext_grp_enable(irq_grp);
559 }
560
561 if (work_done > budget)
562 work_done = budget;
563
564 return work_done;
565 }
566
ath12k_ahb_ext_interrupt_handler(int irq,void * arg)567 static irqreturn_t ath12k_ahb_ext_interrupt_handler(int irq, void *arg)
568 {
569 struct ath12k_ext_irq_grp *irq_grp = arg;
570
571 /* last interrupt received for this group */
572 irq_grp->timestamp = jiffies;
573
574 ath12k_ahb_ext_grp_disable(irq_grp);
575
576 napi_schedule(&irq_grp->napi);
577
578 return IRQ_HANDLED;
579 }
580
ath12k_ahb_config_ext_irq(struct ath12k_base * ab)581 static int ath12k_ahb_config_ext_irq(struct ath12k_base *ab)
582 {
583 const struct ath12k_hw_ring_mask *ring_mask;
584 struct ath12k_ext_irq_grp *irq_grp;
585 int i, j, irq, irq_idx, ret;
586 u32 num_irq;
587
588 ring_mask = ab->hw_params->ring_mask;
589 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
590 irq_grp = &ab->ext_irq_grp[i];
591 num_irq = 0;
592
593 irq_grp->ab = ab;
594 irq_grp->grp_id = i;
595
596 irq_grp->napi_ndev = alloc_netdev_dummy(0);
597 if (!irq_grp->napi_ndev)
598 return -ENOMEM;
599
600 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi,
601 ath12k_ahb_ext_grp_napi_poll);
602
603 for (j = 0; j < DP_TCL_NUM_RING_MAX; j++) {
604 if (ring_mask->tx[i] &
605 BIT(ab->hal.tcl_to_wbm_rbm_map[j].wbm_ring_num) &&
606 num_irq < ATH12K_EXT_IRQ_NUM_MAX) {
607 irq_grp->irqs[num_irq++] =
608 wbm2host_tx_completions_ring1 - j;
609 }
610 }
611
612 for (j = 0; j < ATH12K_EXT_IRQ_NUM_MAX; j++) {
613 if (ring_mask->rx[i] & BIT(j) &&
614 num_irq < ATH12K_EXT_IRQ_NUM_MAX) {
615 irq_grp->irqs[num_irq++] =
616 reo2host_destination_ring1 - j;
617 }
618
619 if (ring_mask->rx_err[i] & BIT(j) &&
620 num_irq < ATH12K_EXT_IRQ_NUM_MAX)
621 irq_grp->irqs[num_irq++] = reo2host_exception;
622
623 if (ring_mask->rx_wbm_rel[i] & BIT(j) &&
624 num_irq < ATH12K_EXT_IRQ_NUM_MAX)
625 irq_grp->irqs[num_irq++] = wbm2host_rx_release;
626
627 if (ring_mask->reo_status[i] & BIT(j) &&
628 num_irq < ATH12K_EXT_IRQ_NUM_MAX)
629 irq_grp->irqs[num_irq++] = reo2host_status;
630
631 if (ring_mask->rx_mon_dest[i] & BIT(j) &&
632 num_irq < ATH12K_EXT_IRQ_NUM_MAX)
633 irq_grp->irqs[num_irq++] =
634 rxdma2host_monitor_destination_mac1;
635 }
636
637 irq_grp->num_irq = num_irq;
638
639 for (j = 0; j < irq_grp->num_irq; j++) {
640 irq_idx = irq_grp->irqs[j];
641
642 irq = platform_get_irq_byname(ab->pdev,
643 irq_name[irq_idx]);
644 ab->irq_num[irq_idx] = irq;
645 irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_DISABLE_UNLAZY);
646 ret = devm_request_irq(ab->dev, irq,
647 ath12k_ahb_ext_interrupt_handler,
648 IRQF_TRIGGER_RISING,
649 irq_name[irq_idx], irq_grp);
650 if (ret)
651 ath12k_warn(ab, "failed request_irq for %d\n", irq);
652 }
653 }
654
655 return 0;
656 }
657
ath12k_ahb_config_irq(struct ath12k_base * ab)658 static int ath12k_ahb_config_irq(struct ath12k_base *ab)
659 {
660 int irq, irq_idx, i;
661 int ret;
662
663 /* Configure CE irqs */
664 for (i = 0; i < ab->hw_params->ce_count; i++) {
665 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
666
667 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
668 continue;
669
670 irq_idx = ATH12K_IRQ_CE0_OFFSET + i;
671
672 INIT_WORK(&ce_pipe->intr_wq, ath12k_ahb_ce_workqueue);
673 irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]);
674 ret = devm_request_irq(ab->dev, irq, ath12k_ahb_ce_interrupt_handler,
675 IRQF_TRIGGER_RISING, irq_name[irq_idx],
676 ce_pipe);
677 if (ret)
678 return ret;
679
680 ab->irq_num[irq_idx] = irq;
681 }
682
683 /* Configure external interrupts */
684 ret = ath12k_ahb_config_ext_irq(ab);
685
686 return ret;
687 }
688
ath12k_ahb_map_service_to_pipe(struct ath12k_base * ab,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)689 static int ath12k_ahb_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
690 u8 *ul_pipe, u8 *dl_pipe)
691 {
692 const struct service_to_pipe *entry;
693 bool ul_set = false, dl_set = false;
694 u32 pipedir;
695 int i;
696
697 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) {
698 entry = &ab->hw_params->svc_to_ce_map[i];
699
700 if (__le32_to_cpu(entry->service_id) != service_id)
701 continue;
702
703 pipedir = __le32_to_cpu(entry->pipedir);
704 if (pipedir == PIPEDIR_IN || pipedir == PIPEDIR_INOUT) {
705 WARN_ON(dl_set);
706 *dl_pipe = __le32_to_cpu(entry->pipenum);
707 dl_set = true;
708 }
709
710 if (pipedir == PIPEDIR_OUT || pipedir == PIPEDIR_INOUT) {
711 WARN_ON(ul_set);
712 *ul_pipe = __le32_to_cpu(entry->pipenum);
713 ul_set = true;
714 }
715 }
716
717 if (WARN_ON(!ul_set || !dl_set))
718 return -ENOENT;
719
720 return 0;
721 }
722
723 const struct ath12k_hif_ops ath12k_ahb_hif_ops = {
724 .start = ath12k_ahb_start,
725 .stop = ath12k_ahb_stop,
726 .read32 = ath12k_ahb_read32,
727 .write32 = ath12k_ahb_write32,
728 .irq_enable = ath12k_ahb_ext_irq_enable,
729 .irq_disable = ath12k_ahb_ext_irq_disable,
730 .map_service_to_pipe = ath12k_ahb_map_service_to_pipe,
731 .power_up = ath12k_ahb_power_up,
732 .power_down = ath12k_ahb_power_down,
733 };
734 EXPORT_SYMBOL(ath12k_ahb_hif_ops);
735
ath12k_userpd_irq_handler(int irq,void * data)736 static irqreturn_t ath12k_userpd_irq_handler(int irq, void *data)
737 {
738 struct ath12k_base *ab = data;
739 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
740
741 if (irq == ab_ahb->userpd_irq_num[ATH12K_USERPD_SPAWN_IRQ]) {
742 complete(&ab_ahb->userpd_spawned);
743 } else if (irq == ab_ahb->userpd_irq_num[ATH12K_USERPD_READY_IRQ]) {
744 complete(&ab_ahb->userpd_ready);
745 } else if (irq == ab_ahb->userpd_irq_num[ATH12K_USERPD_STOP_ACK_IRQ]) {
746 complete(&ab_ahb->userpd_stopped);
747 } else {
748 ath12k_err(ab, "Invalid userpd interrupt\n");
749 return IRQ_NONE;
750 }
751
752 return IRQ_HANDLED;
753 }
754
ath12k_ahb_config_rproc_irq(struct ath12k_base * ab)755 static int ath12k_ahb_config_rproc_irq(struct ath12k_base *ab)
756 {
757 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
758 int i, ret;
759 char *upd_irq_name;
760
761 for (i = 0; i < ATH12K_USERPD_MAX_IRQ; i++) {
762 ab_ahb->userpd_irq_num[i] = platform_get_irq_byname(ab->pdev,
763 ath12k_userpd_irq[i]);
764 if (ab_ahb->userpd_irq_num[i] < 0)
765 return ab_ahb->userpd_irq_num[i];
766
767 upd_irq_name = devm_kzalloc(&ab->pdev->dev, ATH12K_UPD_IRQ_WRD_LEN,
768 GFP_KERNEL);
769 if (!upd_irq_name)
770 return -ENOMEM;
771
772 scnprintf(upd_irq_name, ATH12K_UPD_IRQ_WRD_LEN, "UserPD%u-%s",
773 ab_ahb->userpd_id, ath12k_userpd_irq[i]);
774 ret = devm_request_threaded_irq(&ab->pdev->dev, ab_ahb->userpd_irq_num[i],
775 NULL, ath12k_userpd_irq_handler,
776 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
777 upd_irq_name, ab);
778 if (ret)
779 return dev_err_probe(&ab->pdev->dev, ret,
780 "Request %s irq failed: %d\n",
781 ath12k_userpd_irq[i], ret);
782 }
783
784 ab_ahb->spawn_state = devm_qcom_smem_state_get(&ab->pdev->dev, "spawn",
785 &ab_ahb->spawn_bit);
786 if (IS_ERR(ab_ahb->spawn_state))
787 return dev_err_probe(&ab->pdev->dev, PTR_ERR(ab_ahb->spawn_state),
788 "Failed to acquire spawn state\n");
789
790 ab_ahb->stop_state = devm_qcom_smem_state_get(&ab->pdev->dev, "stop",
791 &ab_ahb->stop_bit);
792 if (IS_ERR(ab_ahb->stop_state))
793 return dev_err_probe(&ab->pdev->dev, PTR_ERR(ab_ahb->stop_state),
794 "Failed to acquire stop state\n");
795
796 init_completion(&ab_ahb->userpd_spawned);
797 init_completion(&ab_ahb->userpd_ready);
798 init_completion(&ab_ahb->userpd_stopped);
799 return 0;
800 }
801
ath12k_ahb_root_pd_state_notifier(struct notifier_block * nb,const unsigned long event,void * data)802 static int ath12k_ahb_root_pd_state_notifier(struct notifier_block *nb,
803 const unsigned long event, void *data)
804 {
805 struct ath12k_ahb_rproc_info *rproc_info =
806 container_of(nb, struct ath12k_ahb_rproc_info, root_pd_nb);
807
808 if (event == ATH12K_RPROC_AFTER_POWERUP) {
809 ath12k_generic_dbg(ATH12K_DBG_AHB, "Root PD is UP\n");
810 complete(&rproc_info->rootpd_ready);
811 }
812
813 return 0;
814 }
815
ath12k_ahb_register_rproc_notifier(void)816 static int ath12k_ahb_register_rproc_notifier(void)
817 {
818 int ret;
819
820 lockdep_assert_held(&ath12k_rproc_info_lock);
821
822 if (g_rproc_info->root_pd_notifier)
823 return 0;
824
825 g_rproc_info->root_pd_nb.notifier_call = ath12k_ahb_root_pd_state_notifier;
826
827 g_rproc_info->root_pd_notifier =
828 qcom_register_ssr_notifier(g_rproc_info->tgt_rproc->name,
829 &g_rproc_info->root_pd_nb);
830 if (IS_ERR(g_rproc_info->root_pd_notifier)) {
831 ret = PTR_ERR(g_rproc_info->root_pd_notifier);
832 g_rproc_info->root_pd_notifier = NULL;
833 return ret;
834 }
835
836 return 0;
837 }
838
ath12k_ahb_unregister_rproc_notifier(void)839 static void ath12k_ahb_unregister_rproc_notifier(void)
840 {
841 lockdep_assert_held(&ath12k_rproc_info_lock);
842
843 if (!g_rproc_info->root_pd_notifier)
844 return;
845
846 qcom_unregister_ssr_notifier(g_rproc_info->root_pd_notifier,
847 &g_rproc_info->root_pd_nb);
848 g_rproc_info->root_pd_notifier = NULL;
849 }
850
ath12k_ahb_cleanup_userpd(struct ath12k_base * ab)851 static void ath12k_ahb_cleanup_userpd(struct ath12k_base *ab)
852 {
853 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
854 struct ath12k_ahb_rproc_info *rproc_info = ab_ahb->rproc_info;
855
856 lockdep_assert_held(&ath12k_rproc_info_lock);
857
858 if (!rproc_info)
859 return;
860
861 rproc_info->userpd[ab_ahb->userpd_id - 1] = NULL;
862 rproc_info->num_userpd--;
863 ab_ahb->rproc_info = NULL;
864 }
865
ath12k_ahb_rproc_info_alloc(struct ath12k_base * ab)866 static struct ath12k_ahb_rproc_info *ath12k_ahb_rproc_info_alloc(struct ath12k_base *ab)
867 {
868 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
869 struct ath12k_ahb_rproc_info *rproc_info;
870
871 lockdep_assert_held(&ath12k_rproc_info_lock);
872
873 rproc_info = kzalloc_obj(*rproc_info);
874 if (!rproc_info)
875 return NULL;
876
877 rproc_info->rootpd_booted_by_driver = false;
878 rproc_info->userpd[ab_ahb->userpd_id - 1] = ab_ahb;
879 rproc_info->num_userpd = 1;
880 init_completion(&rproc_info->rootpd_ready);
881 ab_ahb->rproc_info = rproc_info;
882
883 return rproc_info;
884 }
885
ath12k_ahb_get_rproc(struct ath12k_base * ab)886 static int ath12k_ahb_get_rproc(struct ath12k_base *ab)
887 {
888 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
889 struct device *dev = ab->dev;
890 struct device_node *np;
891 struct rproc *prproc;
892 int ret;
893
894 lockdep_assert_held(&ath12k_rproc_info_lock);
895
896 if (ab_ahb->userpd_id > ATH12K_MAX_DEVICES)
897 return -ENOSPC;
898
899 if (g_rproc_info) {
900 if (g_rproc_info->num_userpd >= ATH12K_MAX_DEVICES) {
901 ath12k_err(ab, "Max UserPD limit reached\n");
902 return -ENOSPC;
903 }
904
905 g_rproc_info->userpd[ab_ahb->userpd_id - 1] = ab_ahb;
906 g_rproc_info->num_userpd++;
907 ab_ahb->rproc_info = g_rproc_info;
908 return 0;
909 }
910
911 g_rproc_info = ath12k_ahb_rproc_info_alloc(ab);
912 if (!g_rproc_info)
913 return -ENOMEM;
914
915 np = of_parse_phandle(dev->of_node, "qcom,rproc", 0);
916 if (!np) {
917 ath12k_err(ab, "failed to get q6_rproc handle\n");
918 ret = -ENOENT;
919 goto err_free_rproc_info;
920 }
921
922 prproc = rproc_get_by_phandle(np->phandle);
923 of_node_put(np);
924 if (!prproc) {
925 ret = dev_err_probe(&ab->pdev->dev, -EPROBE_DEFER,
926 "failed to get rproc\n");
927 goto err_free_rproc_info;
928 }
929
930 g_rproc_info->tgt_rproc = prproc;
931 return 0;
932
933 err_free_rproc_info:
934 ab_ahb->rproc_info = NULL;
935 kfree(g_rproc_info);
936 g_rproc_info = NULL;
937 return ret;
938 }
939
ath12k_ahb_boot_root_pd(struct ath12k_base * ab)940 static int ath12k_ahb_boot_root_pd(struct ath12k_base *ab)
941 {
942 unsigned long time_left;
943 int ret;
944
945 lockdep_assert_held(&ath12k_rproc_info_lock);
946 reinit_completion(&g_rproc_info->rootpd_ready);
947
948 ret = rproc_boot(g_rproc_info->tgt_rproc);
949 if (ret < 0) {
950 ath12k_err(ab, "RootPD boot failed\n");
951 return ret;
952 }
953
954 time_left = wait_for_completion_timeout(&g_rproc_info->rootpd_ready,
955 ATH12K_ROOTPD_READY_TIMEOUT);
956 if (!time_left) {
957 ath12k_err(ab, "RootPD ready wait timed out\n");
958 return -ETIMEDOUT;
959 }
960
961 return 0;
962 }
963
ath12k_ahb_configure_rproc(struct ath12k_base * ab)964 static int ath12k_ahb_configure_rproc(struct ath12k_base *ab)
965 {
966 int ret;
967
968 mutex_lock(&ath12k_rproc_info_lock);
969
970 ret = ath12k_ahb_get_rproc(ab);
971 if (ret < 0) {
972 mutex_unlock(&ath12k_rproc_info_lock);
973 return ret;
974 }
975
976 ret = ath12k_ahb_register_rproc_notifier();
977 if (ret < 0) {
978 ret = dev_err_probe(&ab->pdev->dev, ret,
979 "failed to register rproc notifier\n");
980 goto err_cleanup_userpd;
981 }
982
983 if (g_rproc_info->tgt_rproc->state != RPROC_RUNNING) {
984 ret = ath12k_ahb_boot_root_pd(ab);
985 if (ret < 0) {
986 ath12k_err(ab, "failed to boot the remote processor Q6\n");
987 goto err_unreg_notifier;
988 }
989 g_rproc_info->rootpd_booted_by_driver = true;
990 }
991
992 mutex_unlock(&ath12k_rproc_info_lock);
993 return 0;
994
995 err_unreg_notifier:
996 ath12k_ahb_unregister_rproc_notifier();
997
998 err_cleanup_userpd:
999 ath12k_ahb_cleanup_userpd(ab);
1000
1001 if (g_rproc_info && !g_rproc_info->num_userpd) {
1002 rproc_put(g_rproc_info->tgt_rproc);
1003 kfree(g_rproc_info);
1004 g_rproc_info = NULL;
1005 }
1006
1007 mutex_unlock(&ath12k_rproc_info_lock);
1008 return ret;
1009 }
1010
ath12k_ahb_deconfigure_rproc(struct ath12k_base * ab)1011 static void ath12k_ahb_deconfigure_rproc(struct ath12k_base *ab)
1012 {
1013 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
1014 struct ath12k_ahb_rproc_info *rproc_info = ab_ahb->rproc_info;
1015
1016 lockdep_assert_held(&ath12k_rproc_info_lock);
1017
1018 if (!rproc_info || !g_rproc_info)
1019 return;
1020
1021 ath12k_ahb_cleanup_userpd(ab);
1022
1023 if (!g_rproc_info->num_userpd) {
1024 ath12k_ahb_unregister_rproc_notifier();
1025
1026 if (g_rproc_info->rootpd_booted_by_driver &&
1027 g_rproc_info->tgt_rproc->state == RPROC_RUNNING)
1028 rproc_shutdown(g_rproc_info->tgt_rproc);
1029
1030 rproc_put(g_rproc_info->tgt_rproc);
1031 kfree(g_rproc_info);
1032 g_rproc_info = NULL;
1033 }
1034 }
1035
ath12k_ahb_resource_init(struct ath12k_base * ab)1036 static int ath12k_ahb_resource_init(struct ath12k_base *ab)
1037 {
1038 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
1039 struct platform_device *pdev = ab->pdev;
1040 struct resource *mem_res;
1041 int ret;
1042
1043 ab->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
1044 if (IS_ERR(ab->mem)) {
1045 ret = dev_err_probe(&pdev->dev, PTR_ERR(ab->mem), "ioremap error\n");
1046 goto out;
1047 }
1048
1049 ab->mem_len = resource_size(mem_res);
1050
1051 if (ab->hw_params->ce_remap) {
1052 const struct ce_remap *ce_remap = ab->hw_params->ce_remap;
1053 /* CE register space is moved out of WCSS and the space is not
1054 * contiguous, hence remapping the CE registers to a new space
1055 * for accessing them.
1056 */
1057 ab->mem_ce = ioremap(ce_remap->base, ce_remap->size);
1058 if (!ab->mem_ce) {
1059 dev_err(&pdev->dev, "ce ioremap error\n");
1060 ret = -ENOMEM;
1061 goto err_mem_unmap;
1062 }
1063 ab->ce_remap = true;
1064 ab->cmem_offset = ce_remap->cmem_offset;
1065 ab->ce_remap_base_addr = ce_remap->base;
1066 }
1067
1068 ab_ahb->xo_clk = devm_clk_get(ab->dev, "xo");
1069 if (IS_ERR(ab_ahb->xo_clk)) {
1070 ret = dev_err_probe(&pdev->dev, PTR_ERR(ab_ahb->xo_clk),
1071 "failed to get xo clock\n");
1072 goto err_mem_ce_unmap;
1073 }
1074
1075 ret = clk_prepare_enable(ab_ahb->xo_clk);
1076 if (ret) {
1077 dev_err(&pdev->dev, "failed to enable gcc_xo_clk: %d\n", ret);
1078 goto err_clock_deinit;
1079 }
1080
1081 return 0;
1082
1083 err_clock_deinit:
1084 devm_clk_put(ab->dev, ab_ahb->xo_clk);
1085
1086 err_mem_ce_unmap:
1087 ab_ahb->xo_clk = NULL;
1088 if (ab->hw_params->ce_remap)
1089 iounmap(ab->mem_ce);
1090
1091 err_mem_unmap:
1092 ab->mem_ce = NULL;
1093 devm_iounmap(ab->dev, ab->mem);
1094
1095 out:
1096 ab->mem = NULL;
1097 return ret;
1098 }
1099
ath12k_ahb_resource_deinit(struct ath12k_base * ab)1100 static void ath12k_ahb_resource_deinit(struct ath12k_base *ab)
1101 {
1102 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
1103
1104 if (ab->mem)
1105 devm_iounmap(ab->dev, ab->mem);
1106
1107 if (ab->mem_ce)
1108 iounmap(ab->mem_ce);
1109
1110 ab->mem = NULL;
1111 ab->mem_ce = NULL;
1112
1113 clk_disable_unprepare(ab_ahb->xo_clk);
1114 devm_clk_put(ab->dev, ab_ahb->xo_clk);
1115 ab_ahb->xo_clk = NULL;
1116 }
1117
1118 static enum ath12k_device_family
ath12k_ahb_get_device_family(const struct platform_device * pdev)1119 ath12k_ahb_get_device_family(const struct platform_device *pdev)
1120 {
1121 enum ath12k_device_family device_family_id;
1122 struct ath12k_ahb_driver *driver;
1123 const struct of_device_id *of_id;
1124
1125 for (device_family_id = ATH12K_DEVICE_FAMILY_START;
1126 device_family_id < ATH12K_DEVICE_FAMILY_MAX; device_family_id++) {
1127 driver = ath12k_ahb_family_drivers[device_family_id];
1128 if (driver) {
1129 of_id = of_match_device(driver->id_table, &pdev->dev);
1130 if (of_id) {
1131 /* Found the driver */
1132 return device_family_id;
1133 }
1134 }
1135 }
1136
1137 return ATH12K_DEVICE_FAMILY_MAX;
1138 }
1139
ath12k_ahb_probe(struct platform_device * pdev)1140 static int ath12k_ahb_probe(struct platform_device *pdev)
1141 {
1142 enum ath12k_device_family device_id;
1143 struct ath12k_ahb *ab_ahb;
1144 struct ath12k_base *ab;
1145 u32 addr;
1146 int ret;
1147
1148 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1149 if (ret) {
1150 dev_err(&pdev->dev, "Failed to set 32-bit coherent dma\n");
1151 return ret;
1152 }
1153
1154 ab = ath12k_core_alloc(&pdev->dev, sizeof(struct ath12k_ahb),
1155 ATH12K_BUS_AHB);
1156 if (!ab)
1157 return -ENOMEM;
1158
1159 ab_ahb = ath12k_ab_to_ahb(ab);
1160 ab_ahb->ab = ab;
1161 ab->pdev = pdev;
1162 platform_set_drvdata(pdev, ab);
1163
1164 device_id = ath12k_ahb_get_device_family(pdev);
1165 if (device_id >= ATH12K_DEVICE_FAMILY_MAX) {
1166 ath12k_err(ab, "failed to get device family: %d\n", device_id);
1167 ret = -EINVAL;
1168 goto err_core_free;
1169 }
1170
1171 ath12k_dbg(ab, ATH12K_DBG_AHB, "AHB device family id: %d\n", device_id);
1172
1173 ab_ahb->device_family_ops = &ath12k_ahb_family_drivers[device_id]->ops;
1174
1175 /* Call device specific probe. This is the callback that can
1176 * be used to override any ops in future
1177 * probe is validated for NULL during registration.
1178 */
1179 ret = ab_ahb->device_family_ops->probe(pdev);
1180 if (ret) {
1181 ath12k_err(ab, "failed to probe device: %d\n", ret);
1182 goto err_core_free;
1183 }
1184
1185 /* Set fixed_mem_region to true for platforms that support fixed memory
1186 * reservation from DT. If memory is reserved from DT for FW, ath12k driver
1187 * need not to allocate memory.
1188 */
1189 if (!of_property_read_u32(ab->dev->of_node, "memory-region", &addr))
1190 set_bit(ATH12K_FLAG_FIXED_MEM_REGION, &ab->dev_flags);
1191
1192 ret = ath12k_core_pre_init(ab);
1193 if (ret)
1194 goto err_core_free;
1195
1196 ret = ath12k_ahb_resource_init(ab);
1197 if (ret)
1198 goto err_core_free;
1199
1200 ret = ath12k_hal_srng_init(ab);
1201 if (ret)
1202 goto err_resource_deinit;
1203
1204 ret = ath12k_ce_alloc_pipes(ab);
1205 if (ret) {
1206 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1207 goto err_hal_srng_deinit;
1208 }
1209
1210 ath12k_ahb_init_qmi_ce_config(ab);
1211
1212 ret = ath12k_ahb_configure_rproc(ab);
1213 if (ret)
1214 goto err_ce_free;
1215
1216 ret = ath12k_ahb_config_rproc_irq(ab);
1217 if (ret)
1218 goto err_rproc_deconfigure;
1219
1220 ret = ath12k_ahb_config_irq(ab);
1221 if (ret) {
1222 ath12k_err(ab, "failed to configure irq: %d\n", ret);
1223 goto err_rproc_deconfigure;
1224 }
1225
1226 /* Invoke arch_init here so that arch-specific init operations
1227 * can utilize already initialized ab fields, such as HAL SRNGs.
1228 */
1229 ret = ab_ahb->device_family_ops->arch_init(ab);
1230 if (ret) {
1231 ath12k_err(ab, "AHB arch_init failed %d\n", ret);
1232 goto err_rproc_deconfigure;
1233 }
1234
1235 ret = ath12k_core_init(ab);
1236 if (ret) {
1237 ath12k_err(ab, "failed to init core: %d\n", ret);
1238 goto err_deinit_arch;
1239 }
1240
1241 return 0;
1242
1243 err_deinit_arch:
1244 ab_ahb->device_family_ops->arch_deinit(ab);
1245
1246 err_rproc_deconfigure:
1247 mutex_lock(&ath12k_rproc_info_lock);
1248 ath12k_ahb_deconfigure_rproc(ab);
1249 mutex_unlock(&ath12k_rproc_info_lock);
1250
1251 err_ce_free:
1252 ath12k_ce_free_pipes(ab);
1253
1254 err_hal_srng_deinit:
1255 ath12k_hal_srng_deinit(ab);
1256
1257 err_resource_deinit:
1258 ath12k_ahb_resource_deinit(ab);
1259
1260 err_core_free:
1261 ath12k_core_free(ab);
1262 platform_set_drvdata(pdev, NULL);
1263
1264 return ret;
1265 }
1266
ath12k_ahb_remove_prepare(struct ath12k_base * ab)1267 static void ath12k_ahb_remove_prepare(struct ath12k_base *ab)
1268 {
1269 unsigned long left;
1270
1271 if (test_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags)) {
1272 left = wait_for_completion_timeout(&ab->driver_recovery,
1273 ATH12K_AHB_RECOVERY_TIMEOUT);
1274 if (!left)
1275 ath12k_warn(ab, "failed to receive recovery response completion\n");
1276 }
1277
1278 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags);
1279 cancel_work_sync(&ab->restart_work);
1280 cancel_work_sync(&ab->qmi.event_work);
1281 }
1282
ath12k_ahb_free_resources(struct ath12k_base * ab)1283 static void ath12k_ahb_free_resources(struct ath12k_base *ab)
1284 {
1285 struct platform_device *pdev = ab->pdev;
1286 struct ath12k_ahb *ab_ahb = ath12k_ab_to_ahb(ab);
1287
1288 ath12k_hal_srng_deinit(ab);
1289 ath12k_ce_free_pipes(ab);
1290 ath12k_ahb_resource_deinit(ab);
1291 mutex_lock(&ath12k_rproc_info_lock);
1292 ath12k_ahb_deconfigure_rproc(ab);
1293 mutex_unlock(&ath12k_rproc_info_lock);
1294 ab_ahb->device_family_ops->arch_deinit(ab);
1295 ath12k_core_free(ab);
1296 platform_set_drvdata(pdev, NULL);
1297 }
1298
ath12k_ahb_remove(struct platform_device * pdev)1299 static void ath12k_ahb_remove(struct platform_device *pdev)
1300 {
1301 struct ath12k_base *ab = platform_get_drvdata(pdev);
1302
1303 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1304 ath12k_ahb_power_down(ab, false);
1305 goto qmi_fail;
1306 }
1307
1308 ath12k_ahb_remove_prepare(ab);
1309 ath12k_core_hw_group_cleanup(ab->ag);
1310 qmi_fail:
1311 ath12k_core_deinit(ab);
1312 ath12k_ahb_free_resources(ab);
1313 }
1314
ath12k_ahb_register_driver(const enum ath12k_device_family device_id,struct ath12k_ahb_driver * driver)1315 int ath12k_ahb_register_driver(const enum ath12k_device_family device_id,
1316 struct ath12k_ahb_driver *driver)
1317 {
1318 struct platform_driver *ahb_driver;
1319
1320 if (device_id >= ATH12K_DEVICE_FAMILY_MAX)
1321 return -EINVAL;
1322
1323 if (!driver || !driver->ops.probe ||
1324 !driver->ops.arch_init || !driver->ops.arch_deinit)
1325 return -EINVAL;
1326
1327 if (ath12k_ahb_family_drivers[device_id]) {
1328 pr_err("Driver already registered for id %d\n", device_id);
1329 return -EALREADY;
1330 }
1331
1332 ath12k_ahb_family_drivers[device_id] = driver;
1333
1334 ahb_driver = &ath12k_ahb_family_drivers[device_id]->driver;
1335 ahb_driver->driver.name = driver->name;
1336 ahb_driver->driver.of_match_table = driver->id_table;
1337 ahb_driver->probe = ath12k_ahb_probe;
1338 ahb_driver->remove = ath12k_ahb_remove;
1339
1340 return platform_driver_register(ahb_driver);
1341 }
1342 EXPORT_SYMBOL(ath12k_ahb_register_driver);
1343
ath12k_ahb_unregister_driver(const enum ath12k_device_family device_id)1344 void ath12k_ahb_unregister_driver(const enum ath12k_device_family device_id)
1345 {
1346 struct platform_driver *ahb_driver;
1347
1348 if (device_id >= ATH12K_DEVICE_FAMILY_MAX)
1349 return;
1350
1351 if (!ath12k_ahb_family_drivers[device_id])
1352 return;
1353
1354 ahb_driver = &ath12k_ahb_family_drivers[device_id]->driver;
1355 platform_driver_unregister(ahb_driver);
1356 ath12k_ahb_family_drivers[device_id] = NULL;
1357 }
1358 EXPORT_SYMBOL(ath12k_ahb_unregister_driver);
1359