1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/clock/nxp,imx95-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13#include "imx95-clock.h" 14#include "imx95-pinfunc.h" 15#include "imx95-power.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 idle-states { 27 entry-method = "psci"; 28 29 cpu_pd_wait: cpu-pd-wait { 30 compatible = "arm,idle-state"; 31 arm,psci-suspend-param = <0x0010033>; 32 local-timer-stop; 33 entry-latency-us = <10000>; 34 exit-latency-us = <7000>; 35 min-residency-us = <27000>; 36 wakeup-latency-us = <15000>; 37 }; 38 }; 39 40 A55_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&cpu_pd_wait>; 47 power-domains = <&scmi_perf IMX95_PERF_A55>; 48 power-domain-names = "perf"; 49 i-cache-size = <32768>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <128>; 52 d-cache-size = <32768>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 next-level-cache = <&l2_cache_l0>; 56 }; 57 58 A55_1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x100>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; 64 cpu-idle-states = <&cpu_pd_wait>; 65 power-domains = <&scmi_perf IMX95_PERF_A55>; 66 power-domain-names = "perf"; 67 i-cache-size = <32768>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <128>; 70 d-cache-size = <32768>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2_cache_l1>; 74 }; 75 76 A55_2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x200>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 power-domains = <&scmi_perf IMX95_PERF_A55>; 84 power-domain-names = "perf"; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l2>; 92 }; 93 94 A55_3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x300>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; 100 cpu-idle-states = <&cpu_pd_wait>; 101 power-domains = <&scmi_perf IMX95_PERF_A55>; 102 power-domain-names = "perf"; 103 i-cache-size = <32768>; 104 i-cache-line-size = <64>; 105 i-cache-sets = <128>; 106 d-cache-size = <32768>; 107 d-cache-line-size = <64>; 108 d-cache-sets = <128>; 109 next-level-cache = <&l2_cache_l3>; 110 }; 111 112 A55_4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x400>; 116 power-domains = <&scmi_perf IMX95_PERF_A55>; 117 power-domain-names = "perf"; 118 enable-method = "psci"; 119 #cooling-cells = <2>; 120 cpu-idle-states = <&cpu_pd_wait>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <128>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_cache_l4>; 128 }; 129 130 A55_5: cpu@500 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x500>; 134 power-domains = <&scmi_perf IMX95_PERF_A55>; 135 power-domain-names = "perf"; 136 enable-method = "psci"; 137 #cooling-cells = <2>; 138 cpu-idle-states = <&cpu_pd_wait>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l5>; 146 }; 147 148 l2_cache_l0: l2-cache-l0 { 149 compatible = "cache"; 150 cache-size = <65536>; 151 cache-line-size = <64>; 152 cache-sets = <256>; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&l3_cache>; 156 }; 157 158 l2_cache_l1: l2-cache-l1 { 159 compatible = "cache"; 160 cache-size = <65536>; 161 cache-line-size = <64>; 162 cache-sets = <256>; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&l3_cache>; 166 }; 167 168 l2_cache_l2: l2-cache-l2 { 169 compatible = "cache"; 170 cache-size = <65536>; 171 cache-line-size = <64>; 172 cache-sets = <256>; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_cache>; 176 }; 177 178 l2_cache_l3: l2-cache-l3 { 179 compatible = "cache"; 180 cache-size = <65536>; 181 cache-line-size = <64>; 182 cache-sets = <256>; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_cache>; 186 }; 187 188 l2_cache_l4: l2-cache-l4 { 189 compatible = "cache"; 190 cache-size = <65536>; 191 cache-line-size = <64>; 192 cache-sets = <256>; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_cache>; 196 }; 197 198 l2_cache_l5: l2-cache-l5 { 199 compatible = "cache"; 200 cache-size = <65536>; 201 cache-line-size = <64>; 202 cache-sets = <256>; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_cache>; 206 }; 207 208 l3_cache: l3-cache { 209 compatible = "cache"; 210 cache-size = <524288>; 211 cache-line-size = <64>; 212 cache-sets = <512>; 213 cache-level = <3>; 214 cache-unified; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&A55_0>; 221 }; 222 223 core1 { 224 cpu = <&A55_1>; 225 }; 226 227 core2 { 228 cpu = <&A55_2>; 229 }; 230 231 core3 { 232 cpu = <&A55_3>; 233 }; 234 235 core4 { 236 cpu = <&A55_4>; 237 }; 238 239 core5 { 240 cpu = <&A55_5>; 241 }; 242 }; 243 }; 244 }; 245 246 dummy: clock-dummy { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <0>; 250 clock-output-names = "dummy"; 251 }; 252 253 clk_ext1: clock-ext1 { 254 compatible = "fixed-clock"; 255 #clock-cells = <0>; 256 clock-frequency = <133000000>; 257 clock-output-names = "clk_ext1"; 258 }; 259 260 sai1_mclk: clock-sai-mclk1 { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 clock-frequency = <0>; 264 clock-output-names = "sai1_mclk"; 265 }; 266 267 sai2_mclk: clock-sai-mclk2 { 268 compatible = "fixed-clock"; 269 #clock-cells = <0>; 270 clock-frequency = <0>; 271 clock-output-names = "sai2_mclk"; 272 }; 273 274 sai3_mclk: clock-sai-mclk3 { 275 compatible = "fixed-clock"; 276 #clock-cells = <0>; 277 clock-frequency = <0>; 278 clock-output-names = "sai3_mclk"; 279 }; 280 281 sai4_mclk: clock-sai-mclk4 { 282 compatible = "fixed-clock"; 283 #clock-cells = <0>; 284 clock-frequency = <0>; 285 clock-output-names = "sai4_mclk"; 286 }; 287 288 sai5_mclk: clock-sai-mclk5 { 289 compatible = "fixed-clock"; 290 #clock-cells = <0>; 291 clock-frequency = <0>; 292 clock-output-names = "sai5_mclk"; 293 }; 294 295 clk_sys100m: clock-sys100m { 296 compatible = "fixed-clock"; 297 #clock-cells = <0>; 298 clock-frequency = <100000000>; 299 clock-output-names = "clk_sys100m"; 300 }; 301 302 osc_24m: clock-24m { 303 compatible = "fixed-clock"; 304 #clock-cells = <0>; 305 clock-frequency = <24000000>; 306 clock-output-names = "osc_24m"; 307 }; 308 309 sram1: sram@204c0000 { 310 compatible = "mmio-sram"; 311 reg = <0x0 0x204c0000 0x0 0x18000>; 312 ranges = <0x0 0x0 0x204c0000 0x18000>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 }; 316 317 firmware { 318 scmi { 319 compatible = "arm,scmi"; 320 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 321 shmem = <&scmi_buf0>, <&scmi_buf1>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 arm,max-rx-timeout-ms = <5000>; 325 326 scmi_devpd: protocol@11 { 327 reg = <0x11>; 328 #power-domain-cells = <1>; 329 }; 330 331 scmi_sys_power: protocol@12 { 332 reg = <0x12>; 333 }; 334 335 scmi_perf: protocol@13 { 336 reg = <0x13>; 337 #power-domain-cells = <1>; 338 }; 339 340 scmi_clk: protocol@14 { 341 reg = <0x14>; 342 #clock-cells = <1>; 343 }; 344 345 scmi_sensor: protocol@15 { 346 reg = <0x15>; 347 #thermal-sensor-cells = <1>; 348 }; 349 350 scmi_iomuxc: protocol@19 { 351 reg = <0x19>; 352 }; 353 354 scmi_lmm: protocol@80 { 355 reg = <0x80>; 356 }; 357 358 scmi_bbm: protocol@81 { 359 reg = <0x81>; 360 }; 361 362 scmi_cpu: protocol@82 { 363 reg = <0x82>; 364 }; 365 366 scmi_misc: protocol@84 { 367 reg = <0x84>; 368 }; 369 }; 370 }; 371 372 pmu { 373 compatible = "arm,cortex-a55-pmu"; 374 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 375 }; 376 377 thermal_zones: thermal-zones { 378 a55-thermal { 379 polling-delay-passive = <250>; 380 polling-delay = <2000>; 381 thermal-sensors = <&scmi_sensor 1>; 382 383 trips { 384 cpu_alert0: trip0 { 385 temperature = <105000>; 386 hysteresis = <2000>; 387 type = "passive"; 388 }; 389 390 cpu_crit0: trip1 { 391 temperature = <125000>; 392 hysteresis = <2000>; 393 type = "critical"; 394 }; 395 }; 396 397 cooling-maps { 398 map0 { 399 trip = <&cpu_alert0>; 400 cooling-device = 401 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 402 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 403 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 404 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 405 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 406 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 407 }; 408 }; 409 }; 410 411 ana-thermal { 412 polling-delay-passive = <250>; 413 polling-delay = <2000>; 414 thermal-sensors = <&scmi_sensor 0>; 415 trips { 416 ana_alert: trip0 { 417 temperature = <105000>; 418 hysteresis = <2000>; 419 type = "passive"; 420 }; 421 422 ana_crit0: trip1 { 423 temperature = <125000>; 424 hysteresis = <2000>; 425 type = "critical"; 426 }; 427 }; 428 429 cooling-maps { 430 map0 { 431 trip = <&ana_alert>; 432 cooling-device = 433 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 434 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 435 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 436 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 437 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 438 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 439 }; 440 }; 441 }; 442 }; 443 444 psci { 445 compatible = "arm,psci-1.0"; 446 method = "smc"; 447 }; 448 449 timer { 450 compatible = "arm,armv8-timer"; 451 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 452 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 453 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 454 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 455 clock-frequency = <24000000>; 456 arm,no-tick-in-suspend; 457 interrupt-parent = <&gic>; 458 }; 459 460 gic: interrupt-controller@48000000 { 461 compatible = "arm,gic-v3"; 462 reg = <0 0x48000000 0 0x10000>, 463 <0 0x48060000 0 0xc0000>; 464 #address-cells = <2>; 465 #size-cells = <2>; 466 #interrupt-cells = <3>; 467 interrupt-controller; 468 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-parent = <&gic>; 470 dma-noncoherent; 471 ranges; 472 473 its: msi-controller@48040000 { 474 compatible = "arm,gic-v3-its"; 475 reg = <0 0x48040000 0 0x20000>; 476 msi-controller; 477 #msi-cells = <1>; 478 dma-noncoherent; 479 }; 480 }; 481 482 usbphynop: usbphynop { 483 compatible = "usb-nop-xceiv"; 484 clocks = <&scmi_clk IMX95_CLK_HSIO>; 485 clock-names = "main_clk"; 486 #phy-cells = <0>; 487 }; 488 489 soc { 490 compatible = "simple-bus"; 491 #address-cells = <2>; 492 #size-cells = <2>; 493 ranges; 494 495 etm0: etm@40840000 { 496 compatible = "arm,coresight-etm4x", "arm,primecell"; 497 reg = <0x0 0x40840000 0x0 0x10000>; 498 arm,primecell-periphid = <0xbb95d>; 499 cpu = <&A55_0>; 500 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 501 clock-names = "apb_pclk"; 502 status = "disabled"; 503 504 out-ports { 505 port { 506 etm0_out_port: endpoint { 507 remote-endpoint = <&ca_funnel_in_port0>; 508 }; 509 }; 510 }; 511 }; 512 513 funnel0: funnel { 514 /* 515 * non-configurable funnel don't show up on the AMBA 516 * bus. As such no need to add "arm,primecell". 517 */ 518 compatible = "arm,coresight-static-funnel"; 519 status = "disabled"; 520 521 in-ports { 522 port { 523 ca_funnel_in_port0: endpoint { 524 remote-endpoint = <&etm0_out_port>; 525 }; 526 }; 527 }; 528 529 out-ports { 530 port { 531 ca_funnel_out_port0: endpoint { 532 remote-endpoint = <&hugo_funnel_in_port0>; 533 }; 534 }; 535 }; 536 }; 537 538 funnel1: funnel-sys { 539 compatible = "arm,coresight-static-funnel"; 540 status = "disabled"; 541 542 in-ports { 543 port { 544 hugo_funnel_in_port0: endpoint { 545 remote-endpoint = <&ca_funnel_out_port0>; 546 }; 547 }; 548 }; 549 550 out-ports { 551 port { 552 hugo_funnel_out_port0: endpoint { 553 remote-endpoint = <&etf_in_port>; 554 }; 555 }; 556 }; 557 }; 558 559 etf: etf@41030000 { 560 compatible = "arm,coresight-tmc", "arm,primecell"; 561 reg = <0x0 0x41030000 0x0 0x1000>; 562 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 563 clock-names = "apb_pclk"; 564 status = "disabled"; 565 566 in-ports { 567 port { 568 etf_in_port: endpoint { 569 remote-endpoint = <&hugo_funnel_out_port0>; 570 }; 571 }; 572 }; 573 574 out-ports { 575 port { 576 etf_out_port: endpoint { 577 remote-endpoint = <&etr_in_port>; 578 }; 579 }; 580 }; 581 }; 582 583 etr: etr@41040000 { 584 compatible = "arm,coresight-tmc", "arm,primecell"; 585 reg = <0x0 0x41040000 0x0 0x1000>; 586 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 587 clock-names = "apb_pclk"; 588 status = "disabled"; 589 590 in-ports { 591 port { 592 etr_in_port: endpoint { 593 remote-endpoint = <&etf_out_port>; 594 }; 595 }; 596 }; 597 }; 598 599 aips2: bus@42000000 { 600 compatible = "fsl,aips-bus", "simple-bus"; 601 reg = <0x0 0x42000000 0x0 0x800000>; 602 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 603 <0x28000000 0x0 0x28000000 0x10000000>; 604 #address-cells = <1>; 605 #size-cells = <1>; 606 607 edma2: dma-controller@42000000 { 608 compatible = "fsl,imx95-edma5"; 609 reg = <0x42000000 0x210000>; 610 #dma-cells = <3>; 611 dma-channels = <64>; 612 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 677 clock-names = "dma"; 678 }; 679 680 edma3: dma-controller@42210000 { 681 compatible = "fsl,imx95-edma5"; 682 reg = <0x42210000 0x210000>; 683 #dma-cells = <3>; 684 dma-channels = <64>; 685 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 750 clock-names = "dma"; 751 }; 752 753 mu7: mailbox@42430000 { 754 compatible = "fsl,imx95-mu"; 755 reg = <0x42430000 0x10000>; 756 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 758 #mbox-cells = <2>; 759 status = "disabled"; 760 }; 761 762 wdog3: watchdog@42490000 { 763 compatible = "fsl,imx93-wdt"; 764 reg = <0x42490000 0x10000>; 765 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 767 timeout-sec = <40>; 768 status = "disabled"; 769 }; 770 771 tpm3: pwm@424e0000 { 772 compatible = "fsl,imx7ulp-pwm"; 773 reg = <0x424e0000 0x1000>; 774 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 775 #pwm-cells = <3>; 776 status = "disabled"; 777 }; 778 779 tpm4: pwm@424f0000 { 780 compatible = "fsl,imx7ulp-pwm"; 781 reg = <0x424f0000 0x1000>; 782 clocks = <&scmi_clk IMX95_CLK_TPM4>; 783 #pwm-cells = <3>; 784 status = "disabled"; 785 }; 786 787 tpm5: pwm@42500000 { 788 compatible = "fsl,imx7ulp-pwm"; 789 reg = <0x42500000 0x1000>; 790 clocks = <&scmi_clk IMX95_CLK_TPM5>; 791 #pwm-cells = <3>; 792 status = "disabled"; 793 }; 794 795 tpm6: pwm@42510000 { 796 compatible = "fsl,imx7ulp-pwm"; 797 reg = <0x42510000 0x1000>; 798 clocks = <&scmi_clk IMX95_CLK_TPM6>; 799 #pwm-cells = <3>; 800 status = "disabled"; 801 }; 802 803 i3c2: i3c@42520000 { 804 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 805 reg = <0x42520000 0x10000>; 806 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 807 #address-cells = <3>; 808 #size-cells = <0>; 809 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 810 <&scmi_clk IMX95_CLK_I3C2SLOW>; 811 clock-names = "pclk", "fast_clk"; 812 status = "disabled"; 813 }; 814 815 lpi2c3: i2c@42530000 { 816 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 817 reg = <0x42530000 0x10000>; 818 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 820 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 821 clock-names = "per", "ipg"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 825 dma-names = "tx", "rx"; 826 status = "disabled"; 827 }; 828 829 lpi2c4: i2c@42540000 { 830 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 831 reg = <0x42540000 0x10000>; 832 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 834 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 835 clock-names = "per", "ipg"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 839 dma-names = "tx", "rx"; 840 status = "disabled"; 841 }; 842 843 lpspi3: spi@42550000 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 847 reg = <0x42550000 0x10000>; 848 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 850 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 851 clock-names = "per", "ipg"; 852 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 853 dma-names = "tx", "rx"; 854 status = "disabled"; 855 }; 856 857 lpspi4: spi@42560000 { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 861 reg = <0x42560000 0x10000>; 862 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 864 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 865 clock-names = "per", "ipg"; 866 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 867 dma-names = "tx", "rx"; 868 status = "disabled"; 869 }; 870 871 lpuart3: serial@42570000 { 872 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 873 "fsl,imx7ulp-lpuart"; 874 reg = <0x42570000 0x1000>; 875 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 877 clock-names = "ipg"; 878 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 879 dma-names = "rx", "tx"; 880 status = "disabled"; 881 }; 882 883 lpuart4: serial@42580000 { 884 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 885 "fsl,imx7ulp-lpuart"; 886 reg = <0x42580000 0x1000>; 887 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 889 clock-names = "ipg"; 890 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 891 dma-names = "rx", "tx"; 892 status = "disabled"; 893 }; 894 895 lpuart5: serial@42590000 { 896 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 897 "fsl,imx7ulp-lpuart"; 898 reg = <0x42590000 0x1000>; 899 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 901 clock-names = "ipg"; 902 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 903 dma-names = "rx", "tx"; 904 status = "disabled"; 905 }; 906 907 lpuart6: serial@425a0000 { 908 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 909 "fsl,imx7ulp-lpuart"; 910 reg = <0x425a0000 0x1000>; 911 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 913 clock-names = "ipg"; 914 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 915 dma-names = "rx", "tx"; 916 status = "disabled"; 917 }; 918 919 flexcan2: can@425b0000 { 920 compatible = "fsl,imx95-flexcan"; 921 reg = <0x425b0000 0x10000>; 922 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 924 <&scmi_clk IMX95_CLK_CAN2>; 925 clock-names = "ipg", "per"; 926 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 927 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 928 assigned-clock-rates = <40000000>; 929 fsl,clk-source = /bits/ 8 <0>; 930 status = "disabled"; 931 }; 932 933 flexcan3: can@42600000 { 934 compatible = "fsl,imx95-flexcan"; 935 reg = <0x42600000 0x10000>; 936 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 938 <&scmi_clk IMX95_CLK_CAN3>; 939 clock-names = "ipg", "per"; 940 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 941 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 942 assigned-clock-rates = <40000000>; 943 fsl,clk-source = /bits/ 8 <0>; 944 status = "disabled"; 945 }; 946 947 flexspi1: spi@425e0000 { 948 compatible = "nxp,imx8mm-fspi"; 949 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 950 reg-names = "fspi_base", "fspi_mmap"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 955 <&scmi_clk IMX95_CLK_FLEXSPI1>; 956 clock-names = "fspi_en", "fspi"; 957 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 958 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 959 assigned-clock-rates = <200000000>; 960 status = "disabled"; 961 }; 962 963 sai3: sai@42650000 { 964 compatible = "fsl,imx95-sai"; 965 reg = <0x42650000 0x10000>; 966 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 968 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 969 <&dummy>; 970 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 971 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 972 dma-names = "rx", "tx"; 973 status = "disabled"; 974 }; 975 976 sai4: sai@42660000 { 977 compatible = "fsl,imx95-sai"; 978 reg = <0x42660000 0x10000>; 979 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 981 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 982 <&dummy>; 983 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 984 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 985 dma-names = "rx", "tx"; 986 status = "disabled"; 987 }; 988 989 sai5: sai@42670000 { 990 compatible = "fsl,imx95-sai"; 991 reg = <0x42670000 0x10000>; 992 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 994 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 995 <&dummy>; 996 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 997 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 998 dma-names = "rx", "tx"; 999 status = "disabled"; 1000 }; 1001 1002 xcvr: xcvr@42680000 { 1003 compatible = "fsl,imx95-xcvr"; 1004 reg = <0x42680000 0x800>, <0x42680800 0x400>, 1005 <0x42680c00 0x080>, <0x42680e00 0x080>; 1006 reg-names = "ram", "regs", "rxfifo", "txfifo"; 1007 interrupts = /* XCVR IRQ 0 */ 1008 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1009 /* XCVR IRQ 1 */ 1010 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1012 <&scmi_clk IMX95_CLK_SPDIF>, 1013 <&dummy>, 1014 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 1015 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1016 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 1017 dma-names = "rx", "tx"; 1018 status = "disabled"; 1019 }; 1020 1021 lpuart7: serial@42690000 { 1022 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1023 "fsl,imx7ulp-lpuart"; 1024 reg = <0x42690000 0x1000>; 1025 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 1027 clock-names = "ipg"; 1028 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 1029 dma-names = "rx", "tx"; 1030 status = "disabled"; 1031 }; 1032 1033 lpuart8: serial@426a0000 { 1034 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1035 "fsl,imx7ulp-lpuart"; 1036 reg = <0x426a0000 0x1000>; 1037 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 1039 clock-names = "ipg"; 1040 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 1041 dma-names = "rx", "tx"; 1042 status = "disabled"; 1043 }; 1044 1045 lpi2c5: i2c@426b0000 { 1046 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1047 reg = <0x426b0000 0x10000>; 1048 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 1050 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1051 clock-names = "per", "ipg"; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 1055 dma-names = "tx", "rx"; 1056 status = "disabled"; 1057 }; 1058 1059 lpi2c6: i2c@426c0000 { 1060 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1061 reg = <0x426c0000 0x10000>; 1062 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 1064 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1065 clock-names = "per", "ipg"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 1069 dma-names = "tx", "rx"; 1070 status = "disabled"; 1071 }; 1072 1073 lpi2c7: i2c@426d0000 { 1074 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1075 reg = <0x426d0000 0x10000>; 1076 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 1078 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1079 clock-names = "per", "ipg"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 1083 dma-names = "tx", "rx"; 1084 status = "disabled"; 1085 }; 1086 1087 lpi2c8: i2c@426e0000 { 1088 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1089 reg = <0x426e0000 0x10000>; 1090 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 1092 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1093 clock-names = "per", "ipg"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 1097 dma-names = "tx", "rx"; 1098 status = "disabled"; 1099 }; 1100 1101 lpspi5: spi@426f0000 { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1105 reg = <0x426f0000 0x10000>; 1106 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 1108 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1109 clock-names = "per", "ipg"; 1110 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 1111 dma-names = "tx", "rx"; 1112 status = "disabled"; 1113 }; 1114 1115 lpspi6: spi@42700000 { 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1119 reg = <0x42700000 0x10000>; 1120 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 1122 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1123 clock-names = "per", "ipg"; 1124 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1125 dma-names = "tx", "rx"; 1126 status = "disabled"; 1127 }; 1128 1129 lpspi7: spi@42710000 { 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1133 reg = <0x42710000 0x10000>; 1134 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 1136 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1137 clock-names = "per", "ipg"; 1138 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1139 dma-names = "tx", "rx"; 1140 status = "disabled"; 1141 }; 1142 1143 lpspi8: spi@42720000 { 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1147 reg = <0x42720000 0x10000>; 1148 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1150 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1151 clock-names = "per", "ipg"; 1152 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1153 dma-names = "tx", "rx"; 1154 status = "disabled"; 1155 }; 1156 1157 mu8: mailbox@42730000 { 1158 compatible = "fsl,imx95-mu"; 1159 reg = <0x42730000 0x10000>; 1160 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1162 #mbox-cells = <2>; 1163 status = "disabled"; 1164 }; 1165 1166 flexcan4: can@427c0000 { 1167 compatible = "fsl,imx95-flexcan"; 1168 reg = <0x427c0000 0x10000>; 1169 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1171 <&scmi_clk IMX95_CLK_CAN4>; 1172 clock-names = "ipg", "per"; 1173 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1174 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1175 assigned-clock-rates = <40000000>; 1176 fsl,clk-source = /bits/ 8 <0>; 1177 status = "disabled"; 1178 }; 1179 1180 flexcan5: can@427d0000 { 1181 compatible = "fsl,imx95-flexcan"; 1182 reg = <0x427d0000 0x10000>; 1183 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1185 <&scmi_clk IMX95_CLK_CAN5>; 1186 clock-names = "ipg", "per"; 1187 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1188 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1189 assigned-clock-rates = <40000000>; 1190 fsl,clk-source = /bits/ 8 <0>; 1191 status = "disabled"; 1192 }; 1193 }; 1194 1195 aips3: bus@42800000 { 1196 compatible = "fsl,aips-bus", "simple-bus"; 1197 reg = <0 0x42800000 0 0x800000>; 1198 #address-cells = <1>; 1199 #size-cells = <1>; 1200 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1201 1202 usdhc1: mmc@42850000 { 1203 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1204 reg = <0x42850000 0x10000>; 1205 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1207 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1208 <&scmi_clk IMX95_CLK_USDHC1>; 1209 clock-names = "ipg", "ahb", "per"; 1210 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1211 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1212 assigned-clock-rates = <400000000>; 1213 bus-width = <8>; 1214 fsl,tuning-start-tap = <1>; 1215 fsl,tuning-step = <2>; 1216 status = "disabled"; 1217 }; 1218 1219 usdhc2: mmc@42860000 { 1220 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1221 reg = <0x42860000 0x10000>; 1222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1224 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1225 <&scmi_clk IMX95_CLK_USDHC2>; 1226 clock-names = "ipg", "ahb", "per"; 1227 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1228 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1229 assigned-clock-rates = <400000000>; 1230 bus-width = <4>; 1231 fsl,tuning-start-tap = <1>; 1232 fsl,tuning-step = <2>; 1233 status = "disabled"; 1234 }; 1235 1236 usdhc3: mmc@428b0000 { 1237 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1238 reg = <0x428b0000 0x10000>; 1239 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1241 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1242 <&scmi_clk IMX95_CLK_USDHC3>; 1243 clock-names = "ipg", "ahb", "per"; 1244 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1245 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1246 assigned-clock-rates = <400000000>; 1247 bus-width = <4>; 1248 fsl,tuning-start-tap = <1>; 1249 fsl,tuning-step = <2>; 1250 status = "disabled"; 1251 }; 1252 }; 1253 1254 gpio2: gpio@43810000 { 1255 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1256 reg = <0x0 0x43810000 0x0 0x1000>; 1257 gpio-controller; 1258 #gpio-cells = <2>; 1259 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1261 interrupt-controller; 1262 #interrupt-cells = <2>; 1263 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1264 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1265 clock-names = "gpio", "port"; 1266 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1267 ngpios = <32>; 1268 }; 1269 1270 gpio3: gpio@43820000 { 1271 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1272 reg = <0x0 0x43820000 0x0 0x1000>; 1273 gpio-controller; 1274 #gpio-cells = <2>; 1275 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupt-controller; 1278 #interrupt-cells = <2>; 1279 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1280 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1281 clock-names = "gpio", "port"; 1282 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1283 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1284 ngpios = <32>; 1285 }; 1286 1287 gpio4: gpio@43840000 { 1288 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1289 reg = <0x0 0x43840000 0x0 0x1000>; 1290 gpio-controller; 1291 #gpio-cells = <2>; 1292 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1294 interrupt-controller; 1295 #interrupt-cells = <2>; 1296 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1297 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1298 clock-names = "gpio", "port"; 1299 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1300 ngpios = <30>; 1301 }; 1302 1303 gpio5: gpio@43850000 { 1304 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1305 reg = <0x0 0x43850000 0x0 0x1000>; 1306 gpio-controller; 1307 #gpio-cells = <2>; 1308 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-controller; 1311 #interrupt-cells = <2>; 1312 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1313 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1314 clock-names = "gpio", "port"; 1315 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1316 ngpios = <18>; 1317 }; 1318 1319 aips1: bus@44000000 { 1320 compatible = "fsl,aips-bus", "simple-bus"; 1321 reg = <0x0 0x44000000 0x0 0x800000>; 1322 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1323 #address-cells = <1>; 1324 #size-cells = <1>; 1325 1326 edma1: dma-controller@44000000 { 1327 compatible = "fsl,imx93-edma3"; 1328 reg = <0x44000000 0x200000>; 1329 #dma-cells = <3>; 1330 dma-channels = <31>; 1331 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1363 clock-names = "dma"; 1364 }; 1365 1366 mu1: mailbox@44220000 { 1367 compatible = "fsl,imx95-mu"; 1368 reg = <0x44220000 0x10000>; 1369 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1371 #mbox-cells = <2>; 1372 status = "disabled"; 1373 }; 1374 1375 system_counter: timer@44290000 { 1376 compatible = "nxp,imx95-sysctr-timer"; 1377 reg = <0x44290000 0x30000>; 1378 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&osc_24m>; 1380 clock-names = "per"; 1381 nxp,no-divider; 1382 }; 1383 1384 tpm1: pwm@44310000 { 1385 compatible = "fsl,imx7ulp-pwm"; 1386 reg = <0x44310000 0x1000>; 1387 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1388 #pwm-cells = <3>; 1389 status = "disabled"; 1390 }; 1391 1392 tpm2: pwm@44320000 { 1393 compatible = "fsl,imx7ulp-pwm"; 1394 reg = <0x44320000 0x1000>; 1395 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1396 #pwm-cells = <3>; 1397 status = "disabled"; 1398 }; 1399 1400 i3c1: i3c@44330000 { 1401 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 1402 reg = <0x44330000 0x10000>; 1403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1404 #address-cells = <3>; 1405 #size-cells = <0>; 1406 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1407 <&scmi_clk IMX95_CLK_I3C1SLOW>; 1408 clock-names = "pclk", "fast_clk"; 1409 status = "disabled"; 1410 }; 1411 1412 lpi2c1: i2c@44340000 { 1413 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1414 reg = <0x44340000 0x10000>; 1415 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1416 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1417 <&scmi_clk IMX95_CLK_BUSAON>; 1418 clock-names = "per", "ipg"; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1422 dma-names = "tx", "rx"; 1423 status = "disabled"; 1424 }; 1425 1426 lpi2c2: i2c@44350000 { 1427 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1428 reg = <0x44350000 0x10000>; 1429 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1430 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1431 <&scmi_clk IMX95_CLK_BUSAON>; 1432 clock-names = "per", "ipg"; 1433 #address-cells = <1>; 1434 #size-cells = <0>; 1435 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1436 dma-names = "tx", "rx"; 1437 status = "disabled"; 1438 }; 1439 1440 lpspi1: spi@44360000 { 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1444 reg = <0x44360000 0x10000>; 1445 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1447 <&scmi_clk IMX95_CLK_BUSAON>; 1448 clock-names = "per", "ipg"; 1449 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1450 dma-names = "tx", "rx"; 1451 status = "disabled"; 1452 }; 1453 1454 lpspi2: spi@44370000 { 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1458 reg = <0x44370000 0x10000>; 1459 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1460 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1461 <&scmi_clk IMX95_CLK_BUSAON>; 1462 clock-names = "per", "ipg"; 1463 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1464 dma-names = "tx", "rx"; 1465 status = "disabled"; 1466 }; 1467 1468 lpuart1: serial@44380000 { 1469 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1470 "fsl,imx7ulp-lpuart"; 1471 reg = <0x44380000 0x1000>; 1472 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1473 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1474 clock-names = "ipg"; 1475 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1476 dma-names = "rx", "tx"; 1477 status = "disabled"; 1478 }; 1479 1480 lpuart2: serial@44390000 { 1481 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1482 "fsl,imx7ulp-lpuart"; 1483 reg = <0x44390000 0x1000>; 1484 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1486 clock-names = "ipg"; 1487 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1488 dma-names = "rx", "tx"; 1489 status = "disabled"; 1490 }; 1491 1492 flexcan1: can@443a0000 { 1493 compatible = "fsl,imx95-flexcan"; 1494 reg = <0x443a0000 0x10000>; 1495 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1497 <&scmi_clk IMX95_CLK_CAN1>; 1498 clock-names = "ipg", "per"; 1499 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1500 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1501 assigned-clock-rates = <40000000>; 1502 fsl,clk-source = /bits/ 8 <0>; 1503 status = "disabled"; 1504 }; 1505 1506 sai1: sai@443b0000 { 1507 compatible = "fsl,imx95-sai"; 1508 reg = <0x443b0000 0x10000>; 1509 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1510 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1511 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1512 <&dummy>; 1513 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1514 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1515 dma-names = "rx", "tx"; 1516 status = "disabled"; 1517 }; 1518 1519 micfil: micfil@44520000 { 1520 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1521 reg = <0x44520000 0x10000>; 1522 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1527 <&scmi_clk IMX95_CLK_PDM>, 1528 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1529 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1530 <&dummy>; 1531 clock-names = "ipg_clk", "ipg_clk_app", 1532 "pll8k", "pll11k", "clkext3"; 1533 dmas = <&edma1 6 0 5>; 1534 dma-names = "rx"; 1535 status = "disabled"; 1536 }; 1537 1538 adc1: adc@44530000 { 1539 compatible = "nxp,imx93-adc"; 1540 reg = <0x44530000 0x10000>; 1541 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&scmi_clk IMX95_CLK_ADC>; 1545 clock-names = "ipg"; 1546 #io-channel-cells = <1>; 1547 status = "disabled"; 1548 }; 1549 1550 mu2: mailbox@445b0000 { 1551 compatible = "fsl,imx95-mu"; 1552 reg = <0x445b0000 0x1000>; 1553 ranges; 1554 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1555 #address-cells = <1>; 1556 #size-cells = <1>; 1557 #mbox-cells = <2>; 1558 1559 sram0: sram@445b1000 { 1560 compatible = "mmio-sram"; 1561 reg = <0x445b1000 0x400>; 1562 ranges = <0x0 0x445b1000 0x400>; 1563 #address-cells = <1>; 1564 #size-cells = <1>; 1565 1566 scmi_buf0: scmi-sram-section@0 { 1567 compatible = "arm,scmi-shmem"; 1568 reg = <0x0 0x80>; 1569 }; 1570 1571 scmi_buf1: scmi-sram-section@80 { 1572 compatible = "arm,scmi-shmem"; 1573 reg = <0x80 0x80>; 1574 }; 1575 }; 1576 1577 }; 1578 1579 mu3: mailbox@445d0000 { 1580 compatible = "fsl,imx95-mu"; 1581 reg = <0x445d0000 0x10000>; 1582 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1584 #mbox-cells = <2>; 1585 status = "disabled"; 1586 }; 1587 1588 mu4: mailbox@445f0000 { 1589 compatible = "fsl,imx95-mu"; 1590 reg = <0x445f0000 0x10000>; 1591 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1592 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1593 #mbox-cells = <2>; 1594 status = "disabled"; 1595 }; 1596 1597 mu6: mailbox@44630000 { 1598 compatible = "fsl,imx95-mu"; 1599 reg = <0x44630000 0x10000>; 1600 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1601 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1602 #mbox-cells = <2>; 1603 status = "disabled"; 1604 }; 1605 }; 1606 1607 mailbox@47300000 { 1608 compatible = "fsl,imx95-mu-v2x"; 1609 reg = <0x0 0x47300000 0x0 0x10000>; 1610 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1611 #mbox-cells = <2>; 1612 }; 1613 1614 mailbox@47320000 { 1615 compatible = "fsl,imx95-mu-v2x"; 1616 reg = <0x0 0x47320000 0x0 0x10000>; 1617 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1618 #mbox-cells = <2>; 1619 }; 1620 1621 mailbox@47330000 { 1622 compatible = "fsl,imx95-mu-v2x"; 1623 reg = <0x0 0x47330000 0x0 0x10000>; 1624 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1625 #mbox-cells = <2>; 1626 }; 1627 1628 mailbox@47340000 { 1629 compatible = "fsl,imx95-mu-v2x"; 1630 reg = <0x0 0x47340000 0x0 0x10000>; 1631 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1632 #mbox-cells = <2>; 1633 }; 1634 1635 mailbox@47350000 { 1636 compatible = "fsl,imx95-mu-v2x"; 1637 reg = <0x0 0x47350000 0x0 0x10000>; 1638 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1639 #mbox-cells = <2>; 1640 }; 1641 1642 /* GPIO1 is under exclusive control of System Manager */ 1643 gpio1: gpio@47400000 { 1644 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1645 reg = <0x0 0x47400000 0x0 0x1000>; 1646 gpio-controller; 1647 #gpio-cells = <2>; 1648 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1650 interrupt-controller; 1651 #interrupt-cells = <2>; 1652 clocks = <&scmi_clk IMX95_CLK_M33>, 1653 <&scmi_clk IMX95_CLK_M33>; 1654 clock-names = "gpio", "port"; 1655 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1656 ngpios = <16>; 1657 status = "disabled"; 1658 }; 1659 1660 ocotp: efuse@47510000 { 1661 compatible = "fsl,imx95-ocotp", "syscon"; 1662 reg = <0x0 0x47510000 0x0 0x10000>; 1663 #address-cells = <1>; 1664 #size-cells = <1>; 1665 1666 eth_mac0: mac-address@0 { 1667 reg = <0x0514 0x6>; 1668 }; 1669 1670 eth_mac1: mac-address@1 { 1671 reg = <0x1514 0x6>; 1672 }; 1673 1674 eth_mac2: mac-address@2 { 1675 reg = <0x2514 0x6>; 1676 }; 1677 }; 1678 1679 elemu0: mailbox@47520000 { 1680 compatible = "fsl,imx95-mu-ele"; 1681 reg = <0x0 0x47520000 0x0 0x10000>; 1682 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1683 #mbox-cells = <2>; 1684 status = "disabled"; 1685 }; 1686 1687 elemu1: mailbox@47530000 { 1688 compatible = "fsl,imx95-mu-ele"; 1689 reg = <0x0 0x47530000 0x0 0x10000>; 1690 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1691 #mbox-cells = <2>; 1692 status = "disabled"; 1693 }; 1694 1695 elemu2: mailbox@47540000 { 1696 compatible = "fsl,imx95-mu-ele"; 1697 reg = <0x0 0x47540000 0x0 0x10000>; 1698 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1699 #mbox-cells = <2>; 1700 status = "disabled"; 1701 }; 1702 1703 elemu3: mailbox@47550000 { 1704 compatible = "fsl,imx95-mu-ele"; 1705 reg = <0x0 0x47550000 0x0 0x10000>; 1706 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1707 #mbox-cells = <2>; 1708 }; 1709 1710 elemu4: mailbox@47560000 { 1711 compatible = "fsl,imx95-mu-ele"; 1712 reg = <0x0 0x47560000 0x0 0x10000>; 1713 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1714 #mbox-cells = <2>; 1715 status = "disabled"; 1716 }; 1717 1718 elemu5: mailbox@47570000 { 1719 compatible = "fsl,imx95-mu-ele"; 1720 reg = <0x0 0x47570000 0x0 0x10000>; 1721 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1722 #mbox-cells = <2>; 1723 status = "disabled"; 1724 }; 1725 1726 aips4: bus@49000000 { 1727 compatible = "fsl,aips-bus", "simple-bus"; 1728 reg = <0x0 0x49000000 0x0 0x800000>; 1729 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1730 #address-cells = <1>; 1731 #size-cells = <1>; 1732 1733 smmu: iommu@490d0000 { 1734 compatible = "arm,smmu-v3"; 1735 reg = <0x490d0000 0x100000>; 1736 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1737 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1738 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1739 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1740 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1741 #iommu-cells = <1>; 1742 status = "disabled"; 1743 }; 1744 }; 1745 1746 usb3: usb@4c010010 { 1747 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; 1748 reg = <0x0 0x4c010010 0x0 0x04>, 1749 <0x0 0x4c1f0000 0x0 0x20>; 1750 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1751 <&scmi_clk IMX95_CLK_32K>; 1752 clock-names = "hsio", "suspend"; 1753 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1754 #address-cells = <2>; 1755 #size-cells = <2>; 1756 ranges; 1757 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1758 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 1759 status = "disabled"; 1760 1761 usb3_dwc3: usb@4c100000 { 1762 compatible = "snps,dwc3"; 1763 reg = <0x0 0x4c100000 0x0 0x10000>; 1764 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1765 <&scmi_clk IMX95_CLK_24M>, 1766 <&scmi_clk IMX95_CLK_32K>; 1767 clock-names = "bus_early", "ref", "suspend"; 1768 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1769 phys = <&usb3_phy>, <&usb3_phy>; 1770 phy-names = "usb2-phy", "usb3-phy"; 1771 snps,gfladj-refclk-lpm-sel-quirk; 1772 snps,parkmode-disable-ss-quirk; 1773 iommus = <&smmu 0xe>; 1774 }; 1775 }; 1776 1777 hsio_blk_ctl: syscon@4c0100c0 { 1778 compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; 1779 reg = <0x0 0x4c0100c0 0x0 0x1>; 1780 #clock-cells = <1>; 1781 clocks = <&clk_sys100m>; 1782 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1783 }; 1784 1785 usb3_phy: phy@4c1f0040 { 1786 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; 1787 reg = <0x0 0x4c1f0040 0x0 0x40>, 1788 <0x0 0x4c1fc000 0x0 0x100>; 1789 clocks = <&scmi_clk IMX95_CLK_HSIO>; 1790 clock-names = "phy"; 1791 #phy-cells = <0>; 1792 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1793 status = "disabled"; 1794 }; 1795 1796 usb2: usb@4c200000 { 1797 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1798 reg = <0x0 0x4c200000 0x0 0x200>; 1799 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1802 <&scmi_clk IMX95_CLK_32K>; 1803 clock-names = "usb_ctrl_root", "usb_wakeup"; 1804 iommus = <&smmu 0xf>; 1805 phys = <&usbphynop>; 1806 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1807 fsl,usbmisc = <&usbmisc 0>; 1808 status = "disabled"; 1809 }; 1810 1811 usbmisc: usbmisc@4c200200 { 1812 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", 1813 "fsl,imx6q-usbmisc"; 1814 reg = <0x0 0x4c200200 0x0 0x200>, 1815 <0x0 0x4c010014 0x0 0x04>; 1816 #index-cells = <1>; 1817 }; 1818 1819 pcie0: pcie@4c300000 { 1820 compatible = "fsl,imx95-pcie"; 1821 reg = <0 0x4c300000 0 0x10000>, 1822 <0 0x60100000 0 0xfe00000>, 1823 <0 0x4c360000 0 0x10000>, 1824 <0 0x4c340000 0 0x4000>; 1825 reg-names = "dbi", "config", "atu", "app"; 1826 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1827 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1828 #address-cells = <3>; 1829 #size-cells = <2>; 1830 device_type = "pci"; 1831 linux,pci-domain = <0>; 1832 bus-range = <0x00 0xff>; 1833 num-lanes = <1>; 1834 num-viewport = <8>; 1835 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1836 interrupt-names = "msi"; 1837 #interrupt-cells = <1>; 1838 interrupt-map-mask = <0 0 0 0x7>; 1839 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1840 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1841 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1842 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1843 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1844 <&scmi_clk IMX95_CLK_HSIOPLL>, 1845 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1846 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1847 <&hsio_blk_ctl 0>; 1848 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1849 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1850 <&scmi_clk IMX95_CLK_HSIOPLL>, 1851 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1852 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1853 assigned-clock-parents = <0>, <0>, 1854 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1855 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1856 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ 1857 msi-map = <0x0 &its 0x10 0x1>, 1858 <0x100 &its 0x11 0x7>; 1859 iommu-map = <0x000 &smmu 0x10 0x1>, 1860 <0x100 &smmu 0x11 0x7>; 1861 iommu-map-mask = <0x1ff>; 1862 fsl,max-link-speed = <3>; 1863 status = "disabled"; 1864 }; 1865 1866 pcie0_ep: pcie-ep@4c300000 { 1867 compatible = "fsl,imx95-pcie-ep"; 1868 reg = <0 0x4c300000 0 0x10000>, 1869 <0 0x4c360000 0 0x1000>, 1870 <0 0x4c320000 0 0x1000>, 1871 <0 0x4c340000 0 0x4000>, 1872 <0 0x4c370000 0 0x10000>, 1873 <0x9 0 1 0>; 1874 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1875 num-lanes = <1>; 1876 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1877 interrupt-names = "dma"; 1878 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1879 <&scmi_clk IMX95_CLK_HSIOPLL>, 1880 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1881 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1882 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1883 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1884 <&scmi_clk IMX95_CLK_HSIOPLL>, 1885 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1886 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1887 assigned-clock-parents = <0>, <0>, 1888 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1889 msi-map = <0x0 &its 0x98 0x1>; 1890 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1891 status = "disabled"; 1892 }; 1893 1894 pcie1: pcie@4c380000 { 1895 compatible = "fsl,imx95-pcie"; 1896 reg = <0 0x4c380000 0 0x10000>, 1897 <8 0x80100000 0 0xfe00000>, 1898 <0 0x4c3e0000 0 0x10000>, 1899 <0 0x4c3c0000 0 0x4000>; 1900 reg-names = "dbi", "config", "atu", "app"; 1901 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1902 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1903 #address-cells = <3>; 1904 #size-cells = <2>; 1905 device_type = "pci"; 1906 linux,pci-domain = <1>; 1907 bus-range = <0x00 0xff>; 1908 num-lanes = <1>; 1909 num-viewport = <8>; 1910 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1911 interrupt-names = "msi"; 1912 #interrupt-cells = <1>; 1913 interrupt-map-mask = <0 0 0 0x7>; 1914 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1915 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1916 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1917 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1918 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1919 <&scmi_clk IMX95_CLK_HSIOPLL>, 1920 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1921 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1922 <&hsio_blk_ctl 0>; 1923 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1924 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1925 <&scmi_clk IMX95_CLK_HSIOPLL>, 1926 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1927 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1928 assigned-clock-parents = <0>, <0>, 1929 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1930 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1931 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ 1932 msi-map = <0x0 &its 0x98 0x1>, 1933 <0x100 &its 0x99 0x7>; 1934 msi-map-mask = <0x1ff>; 1935 /* smmu have not Devid(BIT[7:6]) */ 1936 iommu-map = <0x000 &smmu 0x18 0x1>, 1937 <0x100 &smmu 0x19 0x7>; 1938 iommu-map-mask = <0x1ff>; 1939 fsl,max-link-speed = <3>; 1940 status = "disabled"; 1941 }; 1942 1943 pcie1_ep: pcie-ep@4c380000 { 1944 compatible = "fsl,imx95-pcie-ep"; 1945 reg = <0 0x4c380000 0 0x10000>, 1946 <0 0x4c3e0000 0 0x1000>, 1947 <0 0x4c3a0000 0 0x1000>, 1948 <0 0x4c3c0000 0 0x4000>, 1949 <0 0x4c3f0000 0 0x10000>, 1950 <0xa 0 1 0>; 1951 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1952 num-lanes = <1>; 1953 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1954 interrupt-names = "dma"; 1955 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1956 <&scmi_clk IMX95_CLK_HSIOPLL>, 1957 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1958 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1959 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1960 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1961 <&scmi_clk IMX95_CLK_HSIOPLL>, 1962 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1963 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1964 assigned-clock-parents = <0>, <0>, 1965 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1966 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1967 status = "disabled"; 1968 }; 1969 1970 vpu_blk_ctrl: clock-controller@4c410000 { 1971 compatible = "nxp,imx95-vpu-csr", "syscon"; 1972 reg = <0x0 0x4c410000 0x0 0x10000>; 1973 #clock-cells = <1>; 1974 clocks = <&scmi_clk IMX95_CLK_VPUAPB>; 1975 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1976 assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>, 1977 <&scmi_clk IMX95_CLK_VPU>, 1978 <&scmi_clk IMX95_CLK_VPUJPEG>; 1979 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>, 1980 <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 1981 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 1982 assigned-clock-rates = <133333333>, <667000000>, <500000000>; 1983 }; 1984 1985 jpegdec: jpegdec@4c500000 { 1986 compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; 1987 reg = <0x0 0x4C500000 0x0 0x00050000>; 1988 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1992 clocks = <&scmi_clk IMX95_CLK_VPU>, 1993 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1994 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1995 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 1996 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1997 }; 1998 1999 jpegenc: jpegenc@4c550000 { 2000 compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc"; 2001 reg = <0x0 0x4C550000 0x0 0x00050000>; 2002 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 2006 clocks = <&scmi_clk IMX95_CLK_VPU>, 2007 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 2008 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 2009 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 2010 power-domains = <&scmi_devpd IMX95_PD_VPU>; 2011 }; 2012 2013 netcmix_blk_ctrl: syscon@4c810000 { 2014 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 2015 reg = <0x0 0x4c810000 0x0 0x8>; 2016 #clock-cells = <1>; 2017 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 2018 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 2019 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 2020 assigned-clock-rates = <133333333>; 2021 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2022 status = "disabled"; 2023 }; 2024 2025 sai2: sai@4c880000 { 2026 compatible = "fsl,imx95-sai"; 2027 reg = <0x0 0x4c880000 0x0 0x10000>; 2028 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 2030 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 2031 <&dummy>; 2032 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2033 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2034 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 2035 dma-names = "rx", "tx"; 2036 status = "disabled"; 2037 }; 2038 2039 netc_blk_ctrl: system-controller@4cde0000 { 2040 compatible = "nxp,imx95-netc-blk-ctrl"; 2041 reg = <0x0 0x4cde0000 0x0 0x10000>, 2042 <0x0 0x4cdf0000 0x0 0x10000>, 2043 <0x0 0x4c81000c 0x0 0x18>; 2044 reg-names = "ierb", "prb", "netcmix"; 2045 #address-cells = <2>; 2046 #size-cells = <2>; 2047 ranges; 2048 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2049 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, 2050 <&scmi_clk IMX95_CLK_ENETREF>; 2051 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 2052 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 2053 assigned-clock-rates = <666666666>, <250000000>; 2054 clocks = <&scmi_clk IMX95_CLK_ENET>; 2055 clock-names = "ipg"; 2056 status = "disabled"; 2057 2058 netc_bus0: pcie@4ca00000 { 2059 compatible = "pci-host-ecam-generic"; 2060 reg = <0x0 0x4ca00000 0x0 0x100000>; 2061 #address-cells = <3>; 2062 #size-cells = <2>; 2063 device_type = "pci"; 2064 bus-range = <0x0 0x0>; 2065 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 2066 <0x10 &its 0x61 0x1>, //ENETC0 VF0 2067 <0x20 &its 0x62 0x1>, //ENETC0 VF1 2068 <0x40 &its 0x63 0x1>, //ENETC1 PF 2069 <0x80 &its 0x64 0x1>, //ENETC2 PF 2070 <0x90 &its 0x65 0x1>, //ENETC2 VF0 2071 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 2072 <0xc0 &its 0x67 0x1>; //NETC Timer 2073 iommu-map = <0x0 &smmu 0x20 0x1>, 2074 <0x10 &smmu 0x21 0x1>, 2075 <0x20 &smmu 0x22 0x1>, 2076 <0x40 &smmu 0x23 0x1>, 2077 <0x80 &smmu 0x24 0x1>, 2078 <0x90 &smmu 0x25 0x1>, 2079 <0xa0 &smmu 0x26 0x1>, 2080 <0xc0 &smmu 0x27 0x1>; 2081 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ 2082 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 2083 /* Timer BAR2 - prefetchable memory */ 2084 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 2085 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ 2086 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 2087 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ 2088 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; 2089 2090 enetc_port0: ethernet@0,0 { 2091 compatible = "pci1131,e101"; 2092 reg = <0x000000 0 0 0 0>; 2093 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 2094 clock-names = "ref"; 2095 status = "disabled"; 2096 }; 2097 2098 enetc_port1: ethernet@8,0 { 2099 compatible = "pci1131,e101"; 2100 reg = <0x004000 0 0 0 0>; 2101 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 2102 clock-names = "ref"; 2103 status = "disabled"; 2104 }; 2105 2106 enetc_port2: ethernet@10,0 { 2107 compatible = "pci1131,e101"; 2108 reg = <0x008000 0 0 0 0>; 2109 status = "disabled"; 2110 }; 2111 2112 netc_timer: ethernet@18,0 { 2113 compatible = "pci1131,ee02"; 2114 reg = <0x00c000 0 0 0 0>; 2115 status = "disabled"; 2116 }; 2117 }; 2118 2119 netc_bus1: pcie@4cb00000 { 2120 compatible = "pci-host-ecam-generic"; 2121 reg = <0x0 0x4cb00000 0x0 0x100000>; 2122 #address-cells = <3>; 2123 #size-cells = <2>; 2124 device_type = "pci"; 2125 bus-range = <0x1 0x1>; 2126 /* EMDIO BAR0 - non-prefetchable memory */ 2127 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 2128 /* EMDIO BAR2 - prefetchable memory */ 2129 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; 2130 2131 netc_emdio: mdio@0,0 { 2132 compatible = "pci1131,ee00"; 2133 reg = <0x010000 0 0 0 0>; 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 status = "disabled"; 2137 }; 2138 }; 2139 }; 2140 2141 ddr-pmu@4e090dc0 { 2142 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 2143 reg = <0x0 0x4e090dc0 0x0 0x200>; 2144 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2145 }; 2146 }; 2147}; 2148