1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clocks = <&clks IMX7D_CLK_ARM>; 77 cpu-idle-states = <&cpu_sleep_wait>; 78 operating-points-v2 = <&cpu0_opp_table>; 79 #cooling-cells = <2>; 80 nvmem-cells = <&fuse_grade>; 81 nvmem-cell-names = "speed_grade"; 82 }; 83 }; 84 85 cpu0_opp_table: opp-table { 86 compatible = "operating-points-v2"; 87 opp-shared; 88 89 opp-792000000 { 90 opp-hz = /bits/ 64 <792000000>; 91 opp-microvolt = <1000000>; 92 clock-latency-ns = <150000>; 93 opp-supported-hw = <0xf>, <0xf>; 94 }; 95 }; 96 97 ckil: clock-cki { 98 compatible = "fixed-clock"; 99 #clock-cells = <0>; 100 clock-frequency = <32768>; 101 clock-output-names = "ckil"; 102 }; 103 104 osc: clock-osc { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <24000000>; 108 clock-output-names = "osc"; 109 }; 110 111 usbphynop1: usbphynop1 { 112 compatible = "usb-nop-xceiv"; 113 clocks = <&clks IMX7D_USB_PHY1_CLK>; 114 clock-names = "main_clk"; 115 #phy-cells = <0>; 116 }; 117 118 usbphynop3: usbphynop3 { 119 compatible = "usb-nop-xceiv"; 120 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 121 clock-names = "main_clk"; 122 power-domains = <&pgc_hsic_phy>; 123 #phy-cells = <0>; 124 }; 125 126 pmu { 127 compatible = "arm,cortex-a7-pmu"; 128 interrupt-parent = <&gpc>; 129 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 130 interrupt-affinity = <&cpu0>; 131 }; 132 133 replicator { 134 /* 135 * non-configurable replicators don't show up on the 136 * AMBA bus. As such no need to add "arm,primecell" 137 */ 138 compatible = "arm,coresight-static-replicator"; 139 140 out-ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 /* replicator output ports */ 144 port@0 { 145 reg = <0>; 146 replicator_out_port0: endpoint { 147 remote-endpoint = <&tpiu_in_port>; 148 }; 149 }; 150 151 port@1 { 152 reg = <1>; 153 replicator_out_port1: endpoint { 154 remote-endpoint = <&etr_in_port>; 155 }; 156 }; 157 }; 158 159 in-ports { 160 port { 161 replicator_in_port0: endpoint { 162 remote-endpoint = <&etf_out_port>; 163 }; 164 }; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv7-timer"; 170 arm,cpu-registers-not-fw-configured; 171 interrupt-parent = <&intc>; 172 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 173 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 174 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 175 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 176 }; 177 178 video_mux: csi-mux { 179 compatible = "video-mux"; 180 mux-controls = <&mux 0>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 status = "disabled"; 184 185 port@0 { 186 reg = <0>; 187 }; 188 189 port@1 { 190 reg = <1>; 191 192 csi_mux_from_mipi_vc0: endpoint { 193 remote-endpoint = <&mipi_vc0_to_csi_mux>; 194 }; 195 }; 196 197 port@2 { 198 reg = <2>; 199 200 csi_mux_to_csi: endpoint { 201 remote-endpoint = <&csi_from_csi_mux>; 202 }; 203 }; 204 }; 205 206 soc: soc { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 compatible = "simple-bus"; 210 interrupt-parent = <&gpc>; 211 ranges; 212 bootph-pre-ram; 213 214 ocram: sram@900000 { 215 compatible = "mmio-sram"; 216 reg = <0x00900000 0x20000>; 217 ranges = <0 0x00900000 0x20000>; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 clocks = <&clks IMX7D_OCRAM_CLK>; 221 }; 222 223 funnel@30041000 { 224 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 225 reg = <0x30041000 0x1000>; 226 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 227 clock-names = "apb_pclk"; 228 229 ca_funnel_in_ports: in-ports { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 233 port@0 { 234 reg = <0>; 235 ca_funnel_in_port0: endpoint { 236 remote-endpoint = <&etm0_out_port>; 237 }; 238 }; 239 240 /* the other input ports are not connect to anything */ 241 }; 242 243 out-ports { 244 port { 245 ca_funnel_out_port0: endpoint { 246 remote-endpoint = <&hugo_funnel_in_port0>; 247 }; 248 }; 249 250 }; 251 }; 252 253 etm@3007c000 { 254 compatible = "arm,coresight-etm3x", "arm,primecell"; 255 reg = <0x3007c000 0x1000>; 256 cpu = <&cpu0>; 257 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 258 clock-names = "apb_pclk"; 259 260 out-ports { 261 port { 262 etm0_out_port: endpoint { 263 remote-endpoint = <&ca_funnel_in_port0>; 264 }; 265 }; 266 }; 267 }; 268 269 funnel@30083000 { 270 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 271 reg = <0x30083000 0x1000>; 272 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 273 clock-names = "apb_pclk"; 274 275 in-ports { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 port@0 { 280 reg = <0>; 281 hugo_funnel_in_port0: endpoint { 282 remote-endpoint = <&ca_funnel_out_port0>; 283 }; 284 }; 285 286 port@1 { 287 reg = <1>; 288 hugo_funnel_in_port1: endpoint { 289 /* M4 input */ 290 }; 291 }; 292 /* the other input ports are not connect to anything */ 293 }; 294 295 out-ports { 296 port { 297 hugo_funnel_out_port0: endpoint { 298 remote-endpoint = <&etf_in_port>; 299 }; 300 }; 301 }; 302 }; 303 304 etf@30084000 { 305 compatible = "arm,coresight-tmc", "arm,primecell"; 306 reg = <0x30084000 0x1000>; 307 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 308 clock-names = "apb_pclk"; 309 310 in-ports { 311 port { 312 etf_in_port: endpoint { 313 remote-endpoint = <&hugo_funnel_out_port0>; 314 }; 315 }; 316 }; 317 318 out-ports { 319 port { 320 etf_out_port: endpoint { 321 remote-endpoint = <&replicator_in_port0>; 322 }; 323 }; 324 }; 325 }; 326 327 etr@30086000 { 328 compatible = "arm,coresight-tmc", "arm,primecell"; 329 reg = <0x30086000 0x1000>; 330 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 331 clock-names = "apb_pclk"; 332 333 in-ports { 334 port { 335 etr_in_port: endpoint { 336 remote-endpoint = <&replicator_out_port1>; 337 }; 338 }; 339 }; 340 }; 341 342 tpiu@30087000 { 343 compatible = "arm,coresight-tpiu", "arm,primecell"; 344 reg = <0x30087000 0x1000>; 345 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 346 clock-names = "apb_pclk"; 347 348 in-ports { 349 port { 350 tpiu_in_port: endpoint { 351 remote-endpoint = <&replicator_out_port0>; 352 }; 353 }; 354 }; 355 }; 356 357 intc: interrupt-controller@31001000 { 358 compatible = "arm,cortex-a7-gic"; 359 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 360 #interrupt-cells = <3>; 361 interrupt-controller; 362 interrupt-parent = <&intc>; 363 reg = <0x31001000 0x1000>, 364 <0x31002000 0x2000>, 365 <0x31004000 0x2000>, 366 <0x31006000 0x2000>; 367 }; 368 369 aips1: bus@30000000 { 370 compatible = "fsl,aips-bus", "simple-bus"; 371 #address-cells = <1>; 372 #size-cells = <1>; 373 reg = <0x30000000 0x400000>; 374 ranges; 375 bootph-pre-ram; 376 377 gpio1: gpio@30200000 { 378 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 379 reg = <0x30200000 0x10000>; 380 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 381 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 382 gpio-controller; 383 #gpio-cells = <2>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 387 }; 388 389 gpio2: gpio@30210000 { 390 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 391 reg = <0x30210000 0x10000>; 392 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 394 gpio-controller; 395 #gpio-cells = <2>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 gpio-ranges = <&iomuxc 0 13 32>; 399 }; 400 401 gpio3: gpio@30220000 { 402 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 403 reg = <0x30220000 0x10000>; 404 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 406 gpio-controller; 407 #gpio-cells = <2>; 408 interrupt-controller; 409 #interrupt-cells = <2>; 410 gpio-ranges = <&iomuxc 0 45 29>; 411 }; 412 413 gpio4: gpio@30230000 { 414 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 415 reg = <0x30230000 0x10000>; 416 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 418 gpio-controller; 419 #gpio-cells = <2>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 gpio-ranges = <&iomuxc 0 74 24>; 423 }; 424 425 gpio5: gpio@30240000 { 426 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 427 reg = <0x30240000 0x10000>; 428 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 gpio-ranges = <&iomuxc 0 98 18>; 435 }; 436 437 gpio6: gpio@30250000 { 438 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 439 reg = <0x30250000 0x10000>; 440 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 gpio-ranges = <&iomuxc 0 116 23>; 447 }; 448 449 gpio7: gpio@30260000 { 450 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 451 reg = <0x30260000 0x10000>; 452 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 gpio-ranges = <&iomuxc 0 139 16>; 459 }; 460 461 wdog1: watchdog@30280000 { 462 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 463 reg = <0x30280000 0x10000>; 464 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 466 }; 467 468 wdog2: watchdog@30290000 { 469 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 470 reg = <0x30290000 0x10000>; 471 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 473 status = "disabled"; 474 }; 475 476 wdog3: watchdog@302a0000 { 477 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 478 reg = <0x302a0000 0x10000>; 479 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 481 status = "disabled"; 482 }; 483 484 wdog4: watchdog@302b0000 { 485 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 486 reg = <0x302b0000 0x10000>; 487 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 489 status = "disabled"; 490 }; 491 492 iomuxc_lpsr: pinctrl@302c0000 { 493 compatible = "fsl,imx7d-iomuxc-lpsr"; 494 reg = <0x302c0000 0x10000>; 495 fsl,input-sel = <&iomuxc>; 496 }; 497 498 gpt1: timer@302d0000 { 499 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 500 reg = <0x302d0000 0x10000>; 501 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 503 <&clks IMX7D_GPT1_ROOT_CLK>; 504 clock-names = "ipg", "per"; 505 }; 506 507 gpt2: timer@302e0000 { 508 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 509 reg = <0x302e0000 0x10000>; 510 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 512 <&clks IMX7D_GPT2_ROOT_CLK>; 513 clock-names = "ipg", "per"; 514 status = "disabled"; 515 }; 516 517 gpt3: timer@302f0000 { 518 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 519 reg = <0x302f0000 0x10000>; 520 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 522 <&clks IMX7D_GPT3_ROOT_CLK>; 523 clock-names = "ipg", "per"; 524 status = "disabled"; 525 }; 526 527 gpt4: timer@30300000 { 528 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 529 reg = <0x30300000 0x10000>; 530 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 532 <&clks IMX7D_GPT4_ROOT_CLK>; 533 clock-names = "ipg", "per"; 534 status = "disabled"; 535 }; 536 537 kpp: keypad@30320000 { 538 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 539 reg = <0x30320000 0x10000>; 540 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 542 status = "disabled"; 543 }; 544 545 iomuxc: pinctrl@30330000 { 546 compatible = "fsl,imx7d-iomuxc"; 547 reg = <0x30330000 0x10000>; 548 bootph-pre-ram; 549 }; 550 551 gpr: iomuxc-gpr@30340000 { 552 compatible = "fsl,imx7d-iomuxc-gpr", 553 "fsl,imx6q-iomuxc-gpr", "syscon", 554 "simple-mfd"; 555 reg = <0x30340000 0x10000>; 556 557 mux: mux-controller { 558 compatible = "mmio-mux"; 559 #mux-control-cells = <1>; 560 mux-reg-masks = <0x14 0x00000010>; 561 }; 562 }; 563 564 ocotp: efuse@30350000 { 565 #address-cells = <1>; 566 #size-cells = <1>; 567 compatible = "fsl,imx7d-ocotp", "syscon"; 568 reg = <0x30350000 0x10000>; 569 clocks = <&clks IMX7D_OCOTP_CLK>; 570 571 tempmon_calib: calib@3c { 572 reg = <0x3c 0x4>; 573 }; 574 575 fuse_grade: fuse-grade@10 { 576 reg = <0x10 0x4>; 577 }; 578 }; 579 580 anatop: anatop@30360000 { 581 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 582 "syscon", "simple-mfd"; 583 reg = <0x30360000 0x10000>; 584 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 586 587 reg_1p0d: regulator-vdd1p0d { 588 compatible = "fsl,anatop-regulator"; 589 regulator-name = "vdd1p0d"; 590 regulator-min-microvolt = <800000>; 591 regulator-max-microvolt = <1200000>; 592 anatop-reg-offset = <0x210>; 593 anatop-vol-bit-shift = <8>; 594 anatop-vol-bit-width = <5>; 595 anatop-min-bit-val = <8>; 596 anatop-min-voltage = <800000>; 597 anatop-max-voltage = <1200000>; 598 anatop-enable-bit = <0>; 599 }; 600 601 reg_1p2: regulator-vdd1p2 { 602 compatible = "fsl,anatop-regulator"; 603 regulator-name = "vdd1p2"; 604 regulator-min-microvolt = <1100000>; 605 regulator-max-microvolt = <1300000>; 606 anatop-reg-offset = <0x220>; 607 anatop-vol-bit-shift = <8>; 608 anatop-vol-bit-width = <5>; 609 anatop-min-bit-val = <0x14>; 610 anatop-min-voltage = <1100000>; 611 anatop-max-voltage = <1300000>; 612 anatop-enable-bit = <0>; 613 }; 614 615 tempmon: tempmon { 616 compatible = "fsl,imx7d-tempmon"; 617 interrupt-parent = <&gpc>; 618 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 619 fsl,tempmon = <&anatop>; 620 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 621 nvmem-cell-names = "calib", "temp_grade"; 622 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 623 #thermal-sensor-cells = <0>; 624 }; 625 }; 626 627 snvs: snvs@30370000 { 628 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 629 reg = <0x30370000 0x10000>; 630 631 snvs_rtc: snvs-rtc-lp { 632 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 633 regmap = <&snvs>; 634 offset = <0x34>; 635 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&clks IMX7D_SNVS_CLK>; 638 clock-names = "snvs-rtc"; 639 }; 640 641 snvs_poweroff: snvs-poweroff { 642 compatible = "syscon-poweroff"; 643 regmap = <&snvs>; 644 offset = <0x38>; 645 value = <0x60>; 646 mask = <0x60>; 647 status = "disabled"; 648 }; 649 650 snvs_pwrkey: snvs-powerkey { 651 compatible = "fsl,sec-v4.0-pwrkey"; 652 regmap = <&snvs>; 653 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&clks IMX7D_SNVS_CLK>; 655 clock-names = "snvs-pwrkey"; 656 linux,keycode = <KEY_POWER>; 657 wakeup-source; 658 status = "disabled"; 659 }; 660 }; 661 662 clks: clock-controller@30380000 { 663 compatible = "fsl,imx7d-ccm"; 664 reg = <0x30380000 0x10000>; 665 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 667 #clock-cells = <1>; 668 clocks = <&ckil>, <&osc>; 669 clock-names = "ckil", "osc"; 670 }; 671 672 src: reset-controller@30390000 { 673 compatible = "fsl,imx7d-src", "syscon"; 674 reg = <0x30390000 0x10000>; 675 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 676 #reset-cells = <1>; 677 }; 678 679 gpc: gpc@303a0000 { 680 compatible = "fsl,imx7d-gpc"; 681 reg = <0x303a0000 0x10000>; 682 interrupt-controller; 683 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 684 #interrupt-cells = <3>; 685 interrupt-parent = <&intc>; 686 687 pgc { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 691 pgc_mipi_phy: power-domain@0 { 692 #power-domain-cells = <0>; 693 reg = <0>; 694 power-supply = <®_1p0d>; 695 }; 696 697 pgc_pcie_phy: power-domain@1 { 698 #power-domain-cells = <0>; 699 reg = <1>; 700 power-supply = <®_1p0d>; 701 }; 702 703 pgc_hsic_phy: power-domain@2 { 704 #power-domain-cells = <0>; 705 reg = <2>; 706 power-supply = <®_1p2>; 707 }; 708 }; 709 }; 710 }; 711 712 aips2: bus@30400000 { 713 compatible = "fsl,aips-bus", "simple-bus"; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 reg = <0x30400000 0x400000>; 717 ranges; 718 bootph-pre-ram; 719 720 adc1: adc@30610000 { 721 compatible = "fsl,imx7d-adc"; 722 reg = <0x30610000 0x10000>; 723 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 725 clock-names = "adc"; 726 #io-channel-cells = <1>; 727 status = "disabled"; 728 }; 729 730 adc2: adc@30620000 { 731 compatible = "fsl,imx7d-adc"; 732 reg = <0x30620000 0x10000>; 733 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 735 clock-names = "adc"; 736 #io-channel-cells = <1>; 737 status = "disabled"; 738 }; 739 740 ecspi4: spi@30630000 { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 744 reg = <0x30630000 0x10000>; 745 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 747 <&clks IMX7D_ECSPI4_ROOT_CLK>; 748 clock-names = "ipg", "per"; 749 dma-names = "rx", "tx"; 750 dmas = <&sdma 6 7 1>, <&sdma 7 7 2>; 751 status = "disabled"; 752 }; 753 754 ftm1: pwm@30640000 { 755 compatible = "fsl,vf610-ftm-pwm"; 756 reg = <0x30640000 0x10000>; 757 #pwm-cells = <3>; 758 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 759 clock-names = "ftm_sys", "ftm_ext", 760 "ftm_fix", "ftm_cnt_clk_en"; 761 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 762 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 763 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 764 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; 765 status = "disabled"; 766 }; 767 768 ftm2: pwm@30650000 { 769 compatible = "fsl,vf610-ftm-pwm"; 770 reg = <0x30650000 0x10000>; 771 #pwm-cells = <3>; 772 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 773 clock-names = "ftm_sys", "ftm_ext", 774 "ftm_fix", "ftm_cnt_clk_en"; 775 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 776 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 777 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 778 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; 779 status = "disabled"; 780 }; 781 782 pwm1: pwm@30660000 { 783 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 784 reg = <0x30660000 0x10000>; 785 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 787 <&clks IMX7D_PWM1_ROOT_CLK>; 788 clock-names = "ipg", "per"; 789 #pwm-cells = <3>; 790 status = "disabled"; 791 }; 792 793 pwm2: pwm@30670000 { 794 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 795 reg = <0x30670000 0x10000>; 796 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 798 <&clks IMX7D_PWM2_ROOT_CLK>; 799 clock-names = "ipg", "per"; 800 #pwm-cells = <3>; 801 status = "disabled"; 802 }; 803 804 pwm3: pwm@30680000 { 805 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 806 reg = <0x30680000 0x10000>; 807 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 809 <&clks IMX7D_PWM3_ROOT_CLK>; 810 clock-names = "ipg", "per"; 811 #pwm-cells = <3>; 812 status = "disabled"; 813 }; 814 815 pwm4: pwm@30690000 { 816 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 817 reg = <0x30690000 0x10000>; 818 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 820 <&clks IMX7D_PWM4_ROOT_CLK>; 821 clock-names = "ipg", "per"; 822 #pwm-cells = <3>; 823 status = "disabled"; 824 }; 825 826 csi: csi@30710000 { 827 compatible = "fsl,imx7-csi"; 828 reg = <0x30710000 0x10000>; 829 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>; 831 clock-names = "mclk"; 832 status = "disabled"; 833 834 port { 835 csi_from_csi_mux: endpoint { 836 remote-endpoint = <&csi_mux_to_csi>; 837 }; 838 }; 839 }; 840 841 lcdif: lcdif@30730000 { 842 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; 843 reg = <0x30730000 0x10000>; 844 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 846 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 847 clock-names = "pix", "axi"; 848 status = "disabled"; 849 }; 850 851 mipi_csi: mipi-csi@30750000 { 852 compatible = "fsl,imx7-mipi-csi2"; 853 reg = <0x30750000 0x10000>; 854 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 856 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 857 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 858 clock-names = "pclk", "wrap", "phy"; 859 power-domains = <&pgc_mipi_phy>; 860 phy-supply = <®_1p0d>; 861 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 862 status = "disabled"; 863 864 ports { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 868 port@0 { 869 reg = <0>; 870 }; 871 872 port@1 { 873 reg = <1>; 874 875 mipi_vc0_to_csi_mux: endpoint { 876 remote-endpoint = <&csi_mux_from_mipi_vc0>; 877 }; 878 }; 879 }; 880 }; 881 882 mipi_dsi: dsi@30760000 { 883 compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 reg = <0x30760000 0x400>; 887 clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, 888 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 889 clock-names = "bus_clk", "sclk_mipi"; 890 assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>, 891 <&clks IMX7D_PLL_SYS_PFD5_CLK>; 892 assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>; 893 assigned-clock-rates = <0>, <333000000>; 894 power-domains = <&pgc_mipi_phy>; 895 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 896 samsung,burst-clock-frequency = <891000000>; 897 samsung,esc-clock-frequency = <20000000>; 898 samsung,pll-clock-frequency = <24000000>; 899 status = "disabled"; 900 }; 901 }; 902 903 aips3: bus@30800000 { 904 compatible = "fsl,aips-bus", "simple-bus"; 905 #address-cells = <1>; 906 #size-cells = <1>; 907 reg = <0x30800000 0x400000>; 908 ranges; 909 bootph-pre-ram; 910 911 spba-bus@30800000 { 912 compatible = "fsl,spba-bus", "simple-bus"; 913 #address-cells = <1>; 914 #size-cells = <1>; 915 reg = <0x30800000 0x100000>; 916 ranges; 917 918 ecspi1: spi@30820000 { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 922 reg = <0x30820000 0x10000>; 923 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 925 <&clks IMX7D_ECSPI1_ROOT_CLK>; 926 clock-names = "ipg", "per"; 927 dma-names = "rx", "tx"; 928 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; 929 status = "disabled"; 930 }; 931 932 ecspi2: spi@30830000 { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 936 reg = <0x30830000 0x10000>; 937 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 939 <&clks IMX7D_ECSPI2_ROOT_CLK>; 940 clock-names = "ipg", "per"; 941 dma-names = "rx", "tx"; 942 dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; 943 status = "disabled"; 944 }; 945 946 ecspi3: spi@30840000 { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 950 reg = <0x30840000 0x10000>; 951 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 953 <&clks IMX7D_ECSPI3_ROOT_CLK>; 954 clock-names = "ipg", "per"; 955 dma-names = "rx", "tx"; 956 dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; 957 status = "disabled"; 958 }; 959 960 uart1: serial@30860000 { 961 compatible = "fsl,imx7d-uart", 962 "fsl,imx6q-uart"; 963 reg = <0x30860000 0x10000>; 964 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 966 <&clks IMX7D_UART1_ROOT_CLK>; 967 clock-names = "ipg", "per"; 968 status = "disabled"; 969 }; 970 971 uart2: serial@30890000 { 972 compatible = "fsl,imx7d-uart", 973 "fsl,imx6q-uart"; 974 reg = <0x30890000 0x10000>; 975 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 977 <&clks IMX7D_UART2_ROOT_CLK>; 978 clock-names = "ipg", "per"; 979 status = "disabled"; 980 }; 981 982 uart3: serial@30880000 { 983 compatible = "fsl,imx7d-uart", 984 "fsl,imx6q-uart"; 985 reg = <0x30880000 0x10000>; 986 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 988 <&clks IMX7D_UART3_ROOT_CLK>; 989 clock-names = "ipg", "per"; 990 status = "disabled"; 991 }; 992 993 sai1: sai@308a0000 { 994 #sound-dai-cells = <0>; 995 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 996 reg = <0x308a0000 0x10000>; 997 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 999 <&clks IMX7D_SAI1_ROOT_CLK>, 1000 <&clks IMX7D_CLK_DUMMY>, 1001 <&clks IMX7D_CLK_DUMMY>; 1002 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1003 dma-names = "rx", "tx"; 1004 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 1005 status = "disabled"; 1006 }; 1007 1008 sai2: sai@308b0000 { 1009 #sound-dai-cells = <0>; 1010 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1011 reg = <0x308b0000 0x10000>; 1012 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 1014 <&clks IMX7D_SAI2_ROOT_CLK>, 1015 <&clks IMX7D_CLK_DUMMY>, 1016 <&clks IMX7D_CLK_DUMMY>; 1017 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1018 dma-names = "rx", "tx"; 1019 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 1020 status = "disabled"; 1021 }; 1022 1023 sai3: sai@308c0000 { 1024 #sound-dai-cells = <0>; 1025 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 1026 reg = <0x308c0000 0x10000>; 1027 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 1029 <&clks IMX7D_SAI3_ROOT_CLK>, 1030 <&clks IMX7D_CLK_DUMMY>, 1031 <&clks IMX7D_CLK_DUMMY>; 1032 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1033 dma-names = "rx", "tx"; 1034 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 1035 status = "disabled"; 1036 }; 1037 }; 1038 1039 crypto: crypto@30900000 { 1040 compatible = "fsl,sec-v4.0"; 1041 #address-cells = <1>; 1042 #size-cells = <1>; 1043 reg = <0x30900000 0x40000>; 1044 ranges = <0 0x30900000 0x40000>; 1045 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&clks IMX7D_CAAM_CLK>, 1047 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 1048 clock-names = "ipg", "aclk"; 1049 1050 sec_jr0: jr@1000 { 1051 compatible = "fsl,sec-v4.0-job-ring"; 1052 reg = <0x1000 0x1000>; 1053 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1054 }; 1055 1056 sec_jr1: jr@2000 { 1057 compatible = "fsl,sec-v4.0-job-ring"; 1058 reg = <0x2000 0x1000>; 1059 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1060 }; 1061 1062 sec_jr2: jr@3000 { 1063 compatible = "fsl,sec-v4.0-job-ring"; 1064 reg = <0x3000 0x1000>; 1065 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1066 }; 1067 }; 1068 1069 flexcan1: can@30a00000 { 1070 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1071 reg = <0x30a00000 0x10000>; 1072 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&clks IMX7D_CLK_DUMMY>, 1074 <&clks IMX7D_CAN1_ROOT_CLK>; 1075 clock-names = "ipg", "per"; 1076 fsl,stop-mode = <&gpr 0x10 1>; 1077 status = "disabled"; 1078 }; 1079 1080 flexcan2: can@30a10000 { 1081 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1082 reg = <0x30a10000 0x10000>; 1083 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&clks IMX7D_CLK_DUMMY>, 1085 <&clks IMX7D_CAN2_ROOT_CLK>; 1086 clock-names = "ipg", "per"; 1087 fsl,stop-mode = <&gpr 0x10 2>; 1088 status = "disabled"; 1089 }; 1090 1091 i2c1: i2c@30a20000 { 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1095 reg = <0x30a20000 0x10000>; 1096 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 1098 status = "disabled"; 1099 }; 1100 1101 i2c2: i2c@30a30000 { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1105 reg = <0x30a30000 0x10000>; 1106 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c3: i2c@30a40000 { 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1115 reg = <0x30a40000 0x10000>; 1116 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1118 status = "disabled"; 1119 }; 1120 1121 i2c4: i2c@30a50000 { 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1125 reg = <0x30a50000 0x10000>; 1126 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1128 status = "disabled"; 1129 }; 1130 1131 uart4: serial@30a60000 { 1132 compatible = "fsl,imx7d-uart", 1133 "fsl,imx6q-uart"; 1134 reg = <0x30a60000 0x10000>; 1135 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1137 <&clks IMX7D_UART4_ROOT_CLK>; 1138 clock-names = "ipg", "per"; 1139 status = "disabled"; 1140 }; 1141 1142 uart5: serial@30a70000 { 1143 compatible = "fsl,imx7d-uart", 1144 "fsl,imx6q-uart"; 1145 reg = <0x30a70000 0x10000>; 1146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1148 <&clks IMX7D_UART5_ROOT_CLK>; 1149 clock-names = "ipg", "per"; 1150 status = "disabled"; 1151 }; 1152 1153 uart6: serial@30a80000 { 1154 compatible = "fsl,imx7d-uart", 1155 "fsl,imx6q-uart"; 1156 reg = <0x30a80000 0x10000>; 1157 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1159 <&clks IMX7D_UART6_ROOT_CLK>; 1160 clock-names = "ipg", "per"; 1161 status = "disabled"; 1162 }; 1163 1164 uart7: serial@30a90000 { 1165 compatible = "fsl,imx7d-uart", 1166 "fsl,imx6q-uart"; 1167 reg = <0x30a90000 0x10000>; 1168 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1170 <&clks IMX7D_UART7_ROOT_CLK>; 1171 clock-names = "ipg", "per"; 1172 status = "disabled"; 1173 }; 1174 1175 mu0a: mailbox@30aa0000 { 1176 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1177 reg = <0x30aa0000 0x10000>; 1178 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1180 #mbox-cells = <2>; 1181 status = "disabled"; 1182 }; 1183 1184 mu0b: mailbox@30ab0000 { 1185 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1186 reg = <0x30ab0000 0x10000>; 1187 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1189 #mbox-cells = <2>; 1190 fsl,mu-side-b; 1191 status = "disabled"; 1192 }; 1193 1194 usbotg1: usb@30b10000 { 1195 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1196 reg = <0x30b10000 0x200>; 1197 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1199 fsl,usbphy = <&usbphynop1>; 1200 fsl,usbmisc = <&usbmisc1 0>; 1201 phy-clkgate-delay-us = <400>; 1202 status = "disabled"; 1203 }; 1204 1205 usbh: usb@30b30000 { 1206 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1207 reg = <0x30b30000 0x200>; 1208 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1210 fsl,usbphy = <&usbphynop3>; 1211 fsl,usbmisc = <&usbmisc3 0>; 1212 phy_type = "hsic"; 1213 dr_mode = "host"; 1214 phy-clkgate-delay-us = <400>; 1215 status = "disabled"; 1216 }; 1217 1218 usbmisc1: usbmisc@30b10200 { 1219 #index-cells = <1>; 1220 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1221 reg = <0x30b10200 0x200>; 1222 }; 1223 1224 usbmisc3: usbmisc@30b30200 { 1225 #index-cells = <1>; 1226 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1227 reg = <0x30b30200 0x200>; 1228 }; 1229 1230 usdhc1: mmc@30b40000 { 1231 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1232 reg = <0x30b40000 0x10000>; 1233 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1235 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1236 <&clks IMX7D_USDHC1_ROOT_CLK>; 1237 clock-names = "ipg", "ahb", "per"; 1238 bus-width = <4>; 1239 fsl,tuning-step = <2>; 1240 fsl,tuning-start-tap = <20>; 1241 status = "disabled"; 1242 }; 1243 1244 usdhc2: mmc@30b50000 { 1245 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1246 reg = <0x30b50000 0x10000>; 1247 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1249 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1250 <&clks IMX7D_USDHC2_ROOT_CLK>; 1251 clock-names = "ipg", "ahb", "per"; 1252 bus-width = <4>; 1253 fsl,tuning-step = <2>; 1254 fsl,tuning-start-tap = <20>; 1255 status = "disabled"; 1256 }; 1257 1258 usdhc3: mmc@30b60000 { 1259 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1260 reg = <0x30b60000 0x10000>; 1261 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1263 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1264 <&clks IMX7D_USDHC3_ROOT_CLK>; 1265 clock-names = "ipg", "ahb", "per"; 1266 bus-width = <4>; 1267 fsl,tuning-step = <2>; 1268 fsl,tuning-start-tap = <20>; 1269 status = "disabled"; 1270 }; 1271 1272 qspi: spi@30bb0000 { 1273 compatible = "fsl,imx7d-qspi"; 1274 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1275 reg-names = "QuadSPI", "QuadSPI-memory"; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1280 <&clks IMX7D_QSPI_ROOT_CLK>; 1281 clock-names = "qspi_en", "qspi"; 1282 status = "disabled"; 1283 }; 1284 1285 sdma: dma-controller@30bd0000 { 1286 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1287 reg = <0x30bd0000 0x10000>; 1288 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1290 <&clks IMX7D_SDMA_CORE_CLK>; 1291 clock-names = "ipg", "ahb"; 1292 #dma-cells = <3>; 1293 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1294 }; 1295 1296 fec1: ethernet@30be0000 { 1297 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1298 reg = <0x30be0000 0x10000>; 1299 interrupt-names = "int0", "int1", "int2", "pps"; 1300 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1305 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1306 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1307 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1308 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1309 clock-names = "ipg", "ahb", "ptp", 1310 "enet_clk_ref", "enet_out"; 1311 fsl,num-tx-queues = <3>; 1312 fsl,num-rx-queues = <3>; 1313 fsl,stop-mode = <&gpr 0x10 3>; 1314 status = "disabled"; 1315 }; 1316 }; 1317 1318 dma_apbh: dma-controller@33000000 { 1319 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1320 reg = <0x33000000 0x2000>; 1321 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1325 #dma-cells = <1>; 1326 dma-channels = <4>; 1327 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1328 }; 1329 1330 gpmi: nand-controller@33002000 { 1331 compatible = "fsl,imx7d-gpmi-nand"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1335 reg-names = "gpmi-nand", "bch"; 1336 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1337 interrupt-names = "bch"; 1338 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1339 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1340 clock-names = "gpmi_io", "gpmi_bch_apb"; 1341 dmas = <&dma_apbh 0>; 1342 dma-names = "rx-tx"; 1343 status = "disabled"; 1344 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1345 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1346 }; 1347 }; 1348}; 1349