1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/cleanup.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spi/spi.h>
24 #include <linux/units.h>
25
26 #include <asm/div64.h>
27 #include <linux/unaligned.h>
28
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/kfifo_buf.h>
32 #include <linux/iio/sysfs.h>
33
34 #define AD4130_NAME "ad4130"
35
36 #define AD4130_COMMS_READ_MASK BIT(6)
37
38 #define AD4130_STATUS_REG 0x00
39
40 #define AD4130_ADC_CONTROL_REG 0x01
41 #define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14)
42 #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13)
43 #define AD4130_INT_REF_2_5V 2500000
44 #define AD4130_INT_REF_1_25V 1250000
45 #define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9)
46 #define AD4130_ADC_CONTROL_INT_REF_EN_MASK BIT(8)
47 #define AD4130_ADC_CONTROL_MODE_MASK GENMASK(5, 2)
48 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)
49 #define AD4130_MCLK_FREQ_76_8KHZ 76800
50 #define AD4130_MCLK_FREQ_153_6KHZ 153600
51
52 #define AD4130_DATA_REG 0x02
53
54 #define AD4130_IO_CONTROL_REG 0x03
55 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8)
56 #define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4)
57 #define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0)
58
59 #define AD4130_VBIAS_REG 0x04
60
61 #define AD4130_ID_REG 0x05
62
63 #define AD4130_ERROR_REG 0x06
64
65 #define AD4130_ERROR_EN_REG 0x07
66
67 #define AD4130_MCLK_COUNT_REG 0x08
68
69 #define AD4130_CHANNEL_X_REG(x) (0x09 + (x))
70 #define AD4130_CHANNEL_EN_MASK BIT(23)
71 #define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20)
72 #define AD4130_CHANNEL_AINP_MASK GENMASK(17, 13)
73 #define AD4130_CHANNEL_AINM_MASK GENMASK(12, 8)
74 #define AD4130_CHANNEL_IOUT1_MASK GENMASK(7, 4)
75 #define AD4130_CHANNEL_IOUT2_MASK GENMASK(3, 0)
76
77 #define AD4130_CONFIG_X_REG(x) (0x19 + (x))
78 #define AD4130_CONFIG_IOUT1_VAL_MASK GENMASK(15, 13)
79 #define AD4130_CONFIG_IOUT2_VAL_MASK GENMASK(12, 10)
80 #define AD4130_CONFIG_BURNOUT_MASK GENMASK(9, 8)
81 #define AD4130_CONFIG_REF_BUFP_MASK BIT(7)
82 #define AD4130_CONFIG_REF_BUFM_MASK BIT(6)
83 #define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4)
84 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)
85
86 #define AD4130_FILTER_X_REG(x) (0x21 + (x))
87 #define AD4130_FILTER_MODE_MASK GENMASK(15, 12)
88 #define AD4130_FILTER_SELECT_MASK GENMASK(10, 0)
89 #define AD4130_FILTER_SELECT_MIN 1
90
91 #define AD4130_OFFSET_X_REG(x) (0x29 + (x))
92
93 #define AD4130_GAIN_X_REG(x) (0x31 + (x))
94
95 #define AD4130_MISC_REG 0x39
96
97 #define AD4130_FIFO_CONTROL_REG 0x3a
98 #define AD4130_FIFO_CONTROL_HEADER_MASK BIT(18)
99 #define AD4130_FIFO_CONTROL_MODE_MASK GENMASK(17, 16)
100 #define AD4130_FIFO_CONTROL_WM_INT_EN_MASK BIT(9)
101 #define AD4130_FIFO_CONTROL_WM_MASK GENMASK(7, 0)
102 #define AD4130_WATERMARK_256 0
103
104 #define AD4130_FIFO_STATUS_REG 0x3b
105
106 #define AD4130_FIFO_THRESHOLD_REG 0x3c
107
108 #define AD4130_FIFO_DATA_REG 0x3d
109 #define AD4130_FIFO_SIZE 256
110 #define AD4130_FIFO_MAX_SAMPLE_SIZE 3
111
112 #define AD4130_MAX_ANALOG_PINS 16
113 #define AD4130_MAX_CHANNELS 16
114 #define AD4130_MAX_DIFF_INPUTS 30
115 #define AD4130_MAX_GPIOS 4
116 #define AD4130_MAX_ODR 2400
117 #define AD4130_MAX_PGA 8
118 #define AD4130_MAX_SETUPS 8
119
120 #define AD4130_AIN2_P1 0x2
121 #define AD4130_AIN3_P2 0x3
122
123 #define AD4130_RESET_BUF_SIZE 8
124 #define AD4130_RESET_SLEEP_US (160 * MICRO / AD4130_MCLK_FREQ_76_8KHZ)
125
126 #define AD4130_INVALID_SLOT -1
127
128 static const unsigned int ad4130_reg_size[] = {
129 [AD4130_STATUS_REG] = 1,
130 [AD4130_ADC_CONTROL_REG] = 2,
131 [AD4130_DATA_REG] = 3,
132 [AD4130_IO_CONTROL_REG] = 2,
133 [AD4130_VBIAS_REG] = 2,
134 [AD4130_ID_REG] = 1,
135 [AD4130_ERROR_REG] = 2,
136 [AD4130_ERROR_EN_REG] = 2,
137 [AD4130_MCLK_COUNT_REG] = 1,
138 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
139 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
140 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
142 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
143 [AD4130_MISC_REG] = 2,
144 [AD4130_FIFO_CONTROL_REG] = 3,
145 [AD4130_FIFO_STATUS_REG] = 1,
146 [AD4130_FIFO_THRESHOLD_REG] = 3,
147 [AD4130_FIFO_DATA_REG] = 3,
148 };
149
150 enum ad4130_int_ref_val {
151 AD4130_INT_REF_VAL_2_5V,
152 AD4130_INT_REF_VAL_1_25V,
153 };
154
155 enum ad4130_mclk_sel {
156 AD4130_MCLK_76_8KHZ,
157 AD4130_MCLK_76_8KHZ_OUT,
158 AD4130_MCLK_76_8KHZ_EXT,
159 AD4130_MCLK_153_6KHZ_EXT,
160 };
161
162 enum ad4130_int_pin_sel {
163 AD4130_INT_PIN_INT,
164 AD4130_INT_PIN_CLK,
165 AD4130_INT_PIN_P2,
166 AD4130_INT_PIN_DOUT,
167 };
168
169 enum ad4130_iout {
170 AD4130_IOUT_OFF,
171 AD4130_IOUT_10000NA,
172 AD4130_IOUT_20000NA,
173 AD4130_IOUT_50000NA,
174 AD4130_IOUT_100000NA,
175 AD4130_IOUT_150000NA,
176 AD4130_IOUT_200000NA,
177 AD4130_IOUT_100NA,
178 AD4130_IOUT_MAX
179 };
180
181 enum ad4130_burnout {
182 AD4130_BURNOUT_OFF,
183 AD4130_BURNOUT_500NA,
184 AD4130_BURNOUT_2000NA,
185 AD4130_BURNOUT_4000NA,
186 AD4130_BURNOUT_MAX
187 };
188
189 enum ad4130_ref_sel {
190 AD4130_REF_REFIN1,
191 AD4130_REF_REFIN2,
192 AD4130_REF_REFOUT_AVSS,
193 AD4130_REF_AVDD_AVSS,
194 AD4130_REF_SEL_MAX
195 };
196
197 enum ad4130_fifo_mode {
198 AD4130_FIFO_MODE_DISABLED = 0b00,
199 AD4130_FIFO_MODE_WM = 0b01,
200 };
201
202 enum ad4130_mode {
203 AD4130_MODE_CONTINUOUS = 0b0000,
204 AD4130_MODE_IDLE = 0b0100,
205 };
206
207 enum ad4130_filter_type {
208 AD4130_FILTER_SINC4,
209 AD4130_FILTER_SINC4_SINC1,
210 AD4130_FILTER_SINC3,
211 AD4130_FILTER_SINC3_REJ60,
212 AD4130_FILTER_SINC3_SINC1,
213 AD4130_FILTER_SINC3_PF1,
214 AD4130_FILTER_SINC3_PF2,
215 AD4130_FILTER_SINC3_PF3,
216 AD4130_FILTER_SINC3_PF4,
217 };
218
219 enum ad4130_pin_function {
220 AD4130_PIN_FN_NONE,
221 AD4130_PIN_FN_SPECIAL = BIT(0),
222 AD4130_PIN_FN_DIFF = BIT(1),
223 AD4130_PIN_FN_EXCITATION = BIT(2),
224 AD4130_PIN_FN_VBIAS = BIT(3),
225 };
226
227 /*
228 * If you make adaptations in this struct, you most likely also have to adapt
229 * ad4130_setup_info_eq(), too.
230 */
231 struct ad4130_setup_info {
232 unsigned int iout0_val;
233 unsigned int iout1_val;
234 unsigned int burnout;
235 unsigned int pga;
236 unsigned int fs;
237 u32 ref_sel;
238 enum ad4130_filter_type filter_type;
239 bool ref_bufp;
240 bool ref_bufm;
241 };
242
243 struct ad4130_slot_info {
244 struct ad4130_setup_info setup;
245 unsigned int enabled_channels;
246 unsigned int channels;
247 };
248
249 struct ad4130_chan_info {
250 struct ad4130_setup_info setup;
251 u32 iout0;
252 u32 iout1;
253 int slot;
254 bool enabled;
255 bool initialized;
256 };
257
258 struct ad4130_filter_config {
259 enum ad4130_filter_type filter_type;
260 unsigned int odr_div;
261 unsigned int fs_max;
262 enum iio_available_type samp_freq_avail_type;
263 int samp_freq_avail_len;
264 int samp_freq_avail[3][2];
265 };
266
267 struct ad4130_state {
268 struct regmap *regmap;
269 struct spi_device *spi;
270 struct clk *mclk;
271 struct regulator_bulk_data regulators[4];
272 u32 irq_trigger;
273 u32 inv_irq_trigger;
274
275 /*
276 * Synchronize access to members the of driver state, and ensure
277 * atomicity of consecutive regmap operations.
278 */
279 struct mutex lock;
280 struct completion completion;
281
282 struct iio_chan_spec chans[AD4130_MAX_CHANNELS];
283 struct ad4130_chan_info chans_info[AD4130_MAX_CHANNELS];
284 struct ad4130_slot_info slots_info[AD4130_MAX_SETUPS];
285 enum ad4130_pin_function pins_fn[AD4130_MAX_ANALOG_PINS];
286 u32 vbias_pins[AD4130_MAX_ANALOG_PINS];
287 u32 num_vbias_pins;
288 int scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2];
289 struct gpio_chip gc;
290 struct clk_hw int_clk_hw;
291
292 u32 int_pin_sel;
293 u32 int_ref_uv;
294 u32 mclk_sel;
295 bool int_ref_en;
296 bool bipolar;
297
298 unsigned int num_enabled_channels;
299 unsigned int effective_watermark;
300 unsigned int watermark;
301
302 struct spi_message fifo_msg;
303 struct spi_transfer fifo_xfer[2];
304
305 /*
306 * DMA (thus cache coherency maintenance) requires any transfer
307 * buffers to live in their own cache lines. As the use of these
308 * buffers is synchronous, all of the buffers used for DMA in this
309 * driver may share a cache line.
310 */
311 u8 reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN);
312 u8 reg_write_tx_buf[4];
313 u8 reg_read_tx_buf[1];
314 u8 reg_read_rx_buf[3];
315 u8 fifo_tx_buf[2];
316 u8 fifo_rx_buf[AD4130_FIFO_SIZE *
317 AD4130_FIFO_MAX_SAMPLE_SIZE];
318 };
319
320 static const char * const ad4130_int_pin_names[] = {
321 [AD4130_INT_PIN_INT] = "int",
322 [AD4130_INT_PIN_CLK] = "clk",
323 [AD4130_INT_PIN_P2] = "p2",
324 [AD4130_INT_PIN_DOUT] = "dout",
325 };
326
327 static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = {
328 [AD4130_IOUT_OFF] = 0,
329 [AD4130_IOUT_100NA] = 100,
330 [AD4130_IOUT_10000NA] = 10000,
331 [AD4130_IOUT_20000NA] = 20000,
332 [AD4130_IOUT_50000NA] = 50000,
333 [AD4130_IOUT_100000NA] = 100000,
334 [AD4130_IOUT_150000NA] = 150000,
335 [AD4130_IOUT_200000NA] = 200000,
336 };
337
338 static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = {
339 [AD4130_BURNOUT_OFF] = 0,
340 [AD4130_BURNOUT_500NA] = 500,
341 [AD4130_BURNOUT_2000NA] = 2000,
342 [AD4130_BURNOUT_4000NA] = 4000,
343 };
344
345 #define AD4130_VARIABLE_ODR_CONFIG(_filter_type, _odr_div, _fs_max) \
346 { \
347 .filter_type = (_filter_type), \
348 .odr_div = (_odr_div), \
349 .fs_max = (_fs_max), \
350 .samp_freq_avail_type = IIO_AVAIL_RANGE, \
351 .samp_freq_avail = { \
352 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \
353 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \
354 { AD4130_MAX_ODR, (_odr_div) }, \
355 }, \
356 }
357
358 #define AD4130_FIXED_ODR_CONFIG(_filter_type, _odr_div) \
359 { \
360 .filter_type = (_filter_type), \
361 .odr_div = (_odr_div), \
362 .fs_max = AD4130_FILTER_SELECT_MIN, \
363 .samp_freq_avail_type = IIO_AVAIL_LIST, \
364 .samp_freq_avail_len = 1, \
365 .samp_freq_avail = { \
366 { AD4130_MAX_ODR, (_odr_div) }, \
367 }, \
368 }
369
370 static const struct ad4130_filter_config ad4130_filter_configs[] = {
371 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10),
372 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4_SINC1, 11, 10),
373 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047),
374 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047),
375 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_SINC1, 10, 2047),
376 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF1, 92),
377 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF2, 100),
378 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF3, 124),
379 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF4, 148),
380 };
381
382 static const char * const ad4130_filter_types_str[] = {
383 [AD4130_FILTER_SINC4] = "sinc4",
384 [AD4130_FILTER_SINC4_SINC1] = "sinc4+sinc1",
385 [AD4130_FILTER_SINC3] = "sinc3",
386 [AD4130_FILTER_SINC3_REJ60] = "sinc3+rej60",
387 [AD4130_FILTER_SINC3_SINC1] = "sinc3+sinc1",
388 [AD4130_FILTER_SINC3_PF1] = "sinc3+pf1",
389 [AD4130_FILTER_SINC3_PF2] = "sinc3+pf2",
390 [AD4130_FILTER_SINC3_PF3] = "sinc3+pf3",
391 [AD4130_FILTER_SINC3_PF4] = "sinc3+pf4",
392 };
393
ad4130_get_reg_size(struct ad4130_state * st,unsigned int reg,unsigned int * size)394 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg,
395 unsigned int *size)
396 {
397 if (reg >= ARRAY_SIZE(ad4130_reg_size))
398 return -EINVAL;
399
400 *size = ad4130_reg_size[reg];
401
402 return 0;
403 }
404
ad4130_data_reg_size(struct ad4130_state * st)405 static unsigned int ad4130_data_reg_size(struct ad4130_state *st)
406 {
407 unsigned int data_reg_size;
408 int ret;
409
410 ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size);
411 if (ret)
412 return 0;
413
414 return data_reg_size;
415 }
416
ad4130_resolution(struct ad4130_state * st)417 static unsigned int ad4130_resolution(struct ad4130_state *st)
418 {
419 return ad4130_data_reg_size(st) * BITS_PER_BYTE;
420 }
421
ad4130_reg_write(void * context,unsigned int reg,unsigned int val)422 static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val)
423 {
424 struct ad4130_state *st = context;
425 unsigned int size;
426 int ret;
427
428 ret = ad4130_get_reg_size(st, reg, &size);
429 if (ret)
430 return ret;
431
432 st->reg_write_tx_buf[0] = reg;
433
434 switch (size) {
435 case 3:
436 put_unaligned_be24(val, &st->reg_write_tx_buf[1]);
437 break;
438 case 2:
439 put_unaligned_be16(val, &st->reg_write_tx_buf[1]);
440 break;
441 case 1:
442 st->reg_write_tx_buf[1] = val;
443 break;
444 default:
445 return -EINVAL;
446 }
447
448 return spi_write(st->spi, st->reg_write_tx_buf, size + 1);
449 }
450
ad4130_reg_read(void * context,unsigned int reg,unsigned int * val)451 static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val)
452 {
453 struct ad4130_state *st = context;
454 struct spi_transfer t[] = {
455 {
456 .tx_buf = st->reg_read_tx_buf,
457 .len = sizeof(st->reg_read_tx_buf),
458 },
459 {
460 .rx_buf = st->reg_read_rx_buf,
461 },
462 };
463 unsigned int size;
464 int ret;
465
466 ret = ad4130_get_reg_size(st, reg, &size);
467 if (ret)
468 return ret;
469
470 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg;
471 t[1].len = size;
472
473 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
474 if (ret)
475 return ret;
476
477 switch (size) {
478 case 3:
479 *val = get_unaligned_be24(st->reg_read_rx_buf);
480 break;
481 case 2:
482 *val = get_unaligned_be16(st->reg_read_rx_buf);
483 break;
484 case 1:
485 *val = st->reg_read_rx_buf[0];
486 break;
487 default:
488 return -EINVAL;
489 }
490
491 return 0;
492 }
493
494 static const struct regmap_config ad4130_regmap_config = {
495 .reg_read = ad4130_reg_read,
496 .reg_write = ad4130_reg_write,
497 };
498
ad4130_gpio_init_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)499 static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc,
500 unsigned long *valid_mask,
501 unsigned int ngpios)
502 {
503 struct ad4130_state *st = gpiochip_get_data(gc);
504 unsigned int i;
505
506 /*
507 * Output-only GPIO functionality is available on pins AIN2 through
508 * AIN5. If these pins are used for anything else, do not expose them.
509 */
510 for (i = 0; i < ngpios; i++) {
511 unsigned int pin = i + AD4130_AIN2_P1;
512 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE;
513
514 __assign_bit(i, valid_mask, valid);
515 }
516
517 return 0;
518 }
519
ad4130_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)520 static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
521 {
522 return GPIO_LINE_DIRECTION_OUT;
523 }
524
ad4130_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)525 static int ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset,
526 int value)
527 {
528 struct ad4130_state *st = gpiochip_get_data(gc);
529 unsigned int mask = FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK,
530 BIT(offset));
531
532 return regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask,
533 value ? mask : 0);
534 }
535
ad4130_set_mode(struct ad4130_state * st,enum ad4130_mode mode)536 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode)
537 {
538 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
539 AD4130_ADC_CONTROL_MODE_MASK,
540 FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode));
541 }
542
ad4130_set_watermark_interrupt_en(struct ad4130_state * st,bool en)543 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en)
544 {
545 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
546 AD4130_FIFO_CONTROL_WM_INT_EN_MASK,
547 FIELD_PREP(AD4130_FIFO_CONTROL_WM_INT_EN_MASK, en));
548 }
549
ad4130_watermark_reg_val(unsigned int val)550 static unsigned int ad4130_watermark_reg_val(unsigned int val)
551 {
552 if (val == AD4130_FIFO_SIZE)
553 val = AD4130_WATERMARK_256;
554
555 return val;
556 }
557
ad4130_set_fifo_mode(struct ad4130_state * st,enum ad4130_fifo_mode mode)558 static int ad4130_set_fifo_mode(struct ad4130_state *st,
559 enum ad4130_fifo_mode mode)
560 {
561 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
562 AD4130_FIFO_CONTROL_MODE_MASK,
563 FIELD_PREP(AD4130_FIFO_CONTROL_MODE_MASK, mode));
564 }
565
ad4130_push_fifo_data(struct iio_dev * indio_dev)566 static void ad4130_push_fifo_data(struct iio_dev *indio_dev)
567 {
568 struct ad4130_state *st = iio_priv(indio_dev);
569 unsigned int data_reg_size = ad4130_data_reg_size(st);
570 unsigned int transfer_len = st->effective_watermark * data_reg_size;
571 unsigned int set_size = st->num_enabled_channels * data_reg_size;
572 unsigned int i;
573 int ret;
574
575 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark);
576 st->fifo_xfer[1].len = transfer_len;
577
578 ret = spi_sync(st->spi, &st->fifo_msg);
579 if (ret)
580 return;
581
582 for (i = 0; i < transfer_len; i += set_size)
583 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]);
584 }
585
ad4130_irq_handler(int irq,void * private)586 static irqreturn_t ad4130_irq_handler(int irq, void *private)
587 {
588 struct iio_dev *indio_dev = private;
589 struct ad4130_state *st = iio_priv(indio_dev);
590
591 if (iio_buffer_enabled(indio_dev))
592 ad4130_push_fifo_data(indio_dev);
593 else
594 complete(&st->completion);
595
596 return IRQ_HANDLED;
597 }
598
ad4130_setup_info_eq(struct ad4130_setup_info * a,struct ad4130_setup_info * b)599 static bool ad4130_setup_info_eq(struct ad4130_setup_info *a,
600 struct ad4130_setup_info *b)
601 {
602 /*
603 * This is just to make sure that the comparison is adapted after
604 * struct ad4130_setup_info was changed.
605 */
606 static_assert(sizeof(*a) ==
607 sizeof(struct {
608 unsigned int iout0_val;
609 unsigned int iout1_val;
610 unsigned int burnout;
611 unsigned int pga;
612 unsigned int fs;
613 u32 ref_sel;
614 enum ad4130_filter_type filter_type;
615 bool ref_bufp;
616 bool ref_bufm;
617 }));
618
619 if (a->iout0_val != b->iout0_val ||
620 a->iout1_val != b->iout1_val ||
621 a->burnout != b->burnout ||
622 a->pga != b->pga ||
623 a->fs != b->fs ||
624 a->ref_sel != b->ref_sel ||
625 a->filter_type != b->filter_type ||
626 a->ref_bufp != b->ref_bufp ||
627 a->ref_bufm != b->ref_bufm)
628 return false;
629
630 return true;
631 }
632
ad4130_find_slot(struct ad4130_state * st,struct ad4130_setup_info * target_setup_info,unsigned int * slot,bool * overwrite)633 static int ad4130_find_slot(struct ad4130_state *st,
634 struct ad4130_setup_info *target_setup_info,
635 unsigned int *slot, bool *overwrite)
636 {
637 unsigned int i;
638
639 *slot = AD4130_INVALID_SLOT;
640 *overwrite = false;
641
642 for (i = 0; i < AD4130_MAX_SETUPS; i++) {
643 struct ad4130_slot_info *slot_info = &st->slots_info[i];
644
645 /* Immediately accept a matching setup info. */
646 if (ad4130_setup_info_eq(target_setup_info, &slot_info->setup)) {
647 *slot = i;
648 return 0;
649 }
650
651 /* Ignore all setups which are used by enabled channels. */
652 if (slot_info->enabled_channels)
653 continue;
654
655 /* Find the least used slot. */
656 if (*slot == AD4130_INVALID_SLOT ||
657 slot_info->channels < st->slots_info[*slot].channels)
658 *slot = i;
659 }
660
661 if (*slot == AD4130_INVALID_SLOT)
662 return -EINVAL;
663
664 *overwrite = true;
665
666 return 0;
667 }
668
ad4130_unlink_channel(struct ad4130_state * st,unsigned int channel)669 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel)
670 {
671 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
672 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot];
673
674 chan_info->slot = AD4130_INVALID_SLOT;
675 slot_info->channels--;
676 }
677
ad4130_unlink_slot(struct ad4130_state * st,unsigned int slot)678 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot)
679 {
680 unsigned int i;
681
682 for (i = 0; i < AD4130_MAX_CHANNELS; i++) {
683 struct ad4130_chan_info *chan_info = &st->chans_info[i];
684
685 if (!chan_info->initialized || chan_info->slot != slot)
686 continue;
687
688 ad4130_unlink_channel(st, i);
689 }
690
691 return 0;
692 }
693
ad4130_link_channel_slot(struct ad4130_state * st,unsigned int channel,unsigned int slot)694 static int ad4130_link_channel_slot(struct ad4130_state *st,
695 unsigned int channel, unsigned int slot)
696 {
697 struct ad4130_slot_info *slot_info = &st->slots_info[slot];
698 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
699 int ret;
700
701 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
702 AD4130_CHANNEL_SETUP_MASK,
703 FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, slot));
704 if (ret)
705 return ret;
706
707 chan_info->slot = slot;
708 slot_info->channels++;
709
710 return 0;
711 }
712
ad4130_write_slot_setup(struct ad4130_state * st,unsigned int slot,struct ad4130_setup_info * setup_info)713 static int ad4130_write_slot_setup(struct ad4130_state *st,
714 unsigned int slot,
715 struct ad4130_setup_info *setup_info)
716 {
717 unsigned int val;
718 int ret;
719
720 val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) |
721 FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) |
722 FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) |
723 FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) |
724 FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) |
725 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) |
726 FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga);
727
728 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val);
729 if (ret)
730 return ret;
731
732 val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_type) |
733 FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs);
734
735 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val);
736 if (ret)
737 return ret;
738
739 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info));
740
741 return 0;
742 }
743
ad4130_write_channel_setup(struct ad4130_state * st,unsigned int channel,bool on_enable)744 static int ad4130_write_channel_setup(struct ad4130_state *st,
745 unsigned int channel, bool on_enable)
746 {
747 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
748 struct ad4130_setup_info *setup_info = &chan_info->setup;
749 bool overwrite;
750 int slot;
751 int ret;
752
753 /*
754 * The following cases need to be handled.
755 *
756 * 1. Enabled and linked channel with setup changes:
757 * - Find a slot. If not possible, return error.
758 * - Unlink channel from current slot.
759 * - If the slot has channels linked to it, unlink all channels, and
760 * write the new setup to it.
761 * - Link channel to new slot.
762 *
763 * 2. Soon to be enabled and unlinked channel:
764 * - Find a slot. If not possible, return error.
765 * - If the slot has channels linked to it, unlink all channels, and
766 * write the new setup to it.
767 * - Link channel to the slot.
768 *
769 * 3. Disabled and linked channel with setup changes:
770 * - Unlink channel from current slot.
771 *
772 * 4. Soon to be enabled and linked channel:
773 * 5. Disabled and unlinked channel with setup changes:
774 * - Do nothing.
775 */
776
777 /* Case 4 */
778 if (on_enable && chan_info->slot != AD4130_INVALID_SLOT)
779 return 0;
780
781 if (!on_enable && !chan_info->enabled) {
782 if (chan_info->slot != AD4130_INVALID_SLOT)
783 /* Case 3 */
784 ad4130_unlink_channel(st, channel);
785
786 /* Cases 3 & 5 */
787 return 0;
788 }
789
790 /* Cases 1 & 2 */
791 ret = ad4130_find_slot(st, setup_info, &slot, &overwrite);
792 if (ret)
793 return ret;
794
795 if (chan_info->slot != AD4130_INVALID_SLOT)
796 /* Case 1 */
797 ad4130_unlink_channel(st, channel);
798
799 if (overwrite) {
800 ret = ad4130_unlink_slot(st, slot);
801 if (ret)
802 return ret;
803
804 ret = ad4130_write_slot_setup(st, slot, setup_info);
805 if (ret)
806 return ret;
807 }
808
809 return ad4130_link_channel_slot(st, channel, slot);
810 }
811
ad4130_set_channel_enable(struct ad4130_state * st,unsigned int channel,bool status)812 static int ad4130_set_channel_enable(struct ad4130_state *st,
813 unsigned int channel, bool status)
814 {
815 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
816 struct ad4130_slot_info *slot_info;
817 int ret;
818
819 if (chan_info->enabled == status)
820 return 0;
821
822 if (status) {
823 ret = ad4130_write_channel_setup(st, channel, true);
824 if (ret)
825 return ret;
826 }
827
828 slot_info = &st->slots_info[chan_info->slot];
829
830 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
831 AD4130_CHANNEL_EN_MASK,
832 FIELD_PREP(AD4130_CHANNEL_EN_MASK, status));
833 if (ret)
834 return ret;
835
836 slot_info->enabled_channels += status ? 1 : -1;
837 chan_info->enabled = status;
838
839 return 0;
840 }
841
842 /*
843 * Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes
844 * the relation between filter mode, ODR and FS.
845 *
846 * Notice that the max ODR of each filter mode is not necessarily the
847 * absolute max ODR supported by the chip.
848 *
849 * The ODR divider is not explicitly specified, but it can be deduced based
850 * on the ODR range of each filter mode.
851 *
852 * For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the
853 * absolute max ODR is divided by 11 to achieve the max ODR of this filter
854 * mode.
855 *
856 * The formulas for converting between ODR and FS for a specific filter
857 * mode can be deduced from the same table.
858 *
859 * Notice that FS = 1 actually means max ODR, and that ODR decreases by
860 * (maximum ODR / maximum FS) for each increment of FS.
861 *
862 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
863 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
864 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
865 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
866 * (used in ad4130_fs_to_freq)
867 *
868 * For the opposite formula, FS can be extracted from the last one.
869 *
870 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
871 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
872 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
873 * (used in ad4130_fs_to_freq)
874 */
875
ad4130_freq_to_fs(enum ad4130_filter_type filter_type,int val,int val2,unsigned int * fs)876 static void ad4130_freq_to_fs(enum ad4130_filter_type filter_type,
877 int val, int val2, unsigned int *fs)
878 {
879 const struct ad4130_filter_config *filter_config =
880 &ad4130_filter_configs[filter_type];
881 u64 dividend, divisor;
882 int temp;
883
884 dividend = filter_config->fs_max * filter_config->odr_div *
885 ((u64)val * NANO + val2);
886 divisor = (u64)AD4130_MAX_ODR * NANO;
887
888 temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max -
889 DIV64_U64_ROUND_CLOSEST(dividend, divisor);
890
891 if (temp < AD4130_FILTER_SELECT_MIN)
892 temp = AD4130_FILTER_SELECT_MIN;
893 else if (temp > filter_config->fs_max)
894 temp = filter_config->fs_max;
895
896 *fs = temp;
897 }
898
ad4130_fs_to_freq(enum ad4130_filter_type filter_type,unsigned int fs,int * val,int * val2)899 static void ad4130_fs_to_freq(enum ad4130_filter_type filter_type,
900 unsigned int fs, int *val, int *val2)
901 {
902 const struct ad4130_filter_config *filter_config =
903 &ad4130_filter_configs[filter_type];
904 unsigned int dividend, divisor;
905 u64 temp;
906
907 dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) *
908 AD4130_MAX_ODR;
909 divisor = filter_config->fs_max * filter_config->odr_div;
910
911 temp = div_u64((u64)dividend * NANO, divisor);
912 *val = div_u64_rem(temp, NANO, val2);
913 }
914
ad4130_set_filter_type(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int val)915 static int ad4130_set_filter_type(struct iio_dev *indio_dev,
916 const struct iio_chan_spec *chan,
917 unsigned int val)
918 {
919 struct ad4130_state *st = iio_priv(indio_dev);
920 unsigned int channel = chan->scan_index;
921 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
922 struct ad4130_setup_info *setup_info = &chan_info->setup;
923 enum ad4130_filter_type old_filter_type;
924 int freq_val, freq_val2;
925 unsigned int old_fs;
926 int ret = 0;
927
928 guard(mutex)(&st->lock);
929 if (setup_info->filter_type == val)
930 return 0;
931
932 old_fs = setup_info->fs;
933 old_filter_type = setup_info->filter_type;
934
935 /*
936 * When switching between filter modes, try to match the ODR as
937 * close as possible. To do this, convert the current FS into ODR
938 * using the old filter mode, then convert it back into FS using
939 * the new filter mode.
940 */
941 ad4130_fs_to_freq(setup_info->filter_type, setup_info->fs,
942 &freq_val, &freq_val2);
943
944 ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs);
945
946 setup_info->filter_type = val;
947
948 ret = ad4130_write_channel_setup(st, channel, false);
949 if (ret) {
950 setup_info->fs = old_fs;
951 setup_info->filter_type = old_filter_type;
952 return ret;
953 }
954
955 return 0;
956 }
957
ad4130_get_filter_type(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)958 static int ad4130_get_filter_type(struct iio_dev *indio_dev,
959 const struct iio_chan_spec *chan)
960 {
961 struct ad4130_state *st = iio_priv(indio_dev);
962 unsigned int channel = chan->scan_index;
963 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
964 enum ad4130_filter_type filter_type;
965
966 guard(mutex)(&st->lock);
967 filter_type = setup_info->filter_type;
968
969 return filter_type;
970 }
971
972 static const struct iio_enum ad4130_filter_type_enum = {
973 .items = ad4130_filter_types_str,
974 .num_items = ARRAY_SIZE(ad4130_filter_types_str),
975 .set = ad4130_set_filter_type,
976 .get = ad4130_get_filter_type,
977 };
978
979 static const struct iio_chan_spec_ext_info ad4130_ext_info[] = {
980 /*
981 * `filter_type` is the standardized IIO ABI for digital filtering.
982 * `filter_mode` is just kept for backwards compatibility.
983 */
984 IIO_ENUM("filter_mode", IIO_SEPARATE, &ad4130_filter_type_enum),
985 IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_TYPE,
986 &ad4130_filter_type_enum),
987 IIO_ENUM("filter_type", IIO_SEPARATE, &ad4130_filter_type_enum),
988 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
989 &ad4130_filter_type_enum),
990 { }
991 };
992
993 static const struct iio_chan_spec ad4130_channel_template = {
994 .type = IIO_VOLTAGE,
995 .indexed = 1,
996 .differential = 1,
997 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
998 BIT(IIO_CHAN_INFO_SCALE) |
999 BIT(IIO_CHAN_INFO_OFFSET) |
1000 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1001 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) |
1002 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1003 .ext_info = ad4130_ext_info,
1004 .scan_type = {
1005 .sign = 'u',
1006 .endianness = IIO_BE,
1007 },
1008 };
1009
ad4130_set_channel_pga(struct ad4130_state * st,unsigned int channel,int val,int val2)1010 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel,
1011 int val, int val2)
1012 {
1013 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
1014 struct ad4130_setup_info *setup_info = &chan_info->setup;
1015 unsigned int pga, old_pga;
1016 int ret;
1017
1018 for (pga = 0; pga < AD4130_MAX_PGA; pga++)
1019 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] &&
1020 val2 == st->scale_tbls[setup_info->ref_sel][pga][1])
1021 break;
1022
1023 if (pga == AD4130_MAX_PGA)
1024 return -EINVAL;
1025
1026 guard(mutex)(&st->lock);
1027 if (pga == setup_info->pga)
1028 return 0;
1029
1030 old_pga = setup_info->pga;
1031 setup_info->pga = pga;
1032
1033 ret = ad4130_write_channel_setup(st, channel, false);
1034 if (ret) {
1035 setup_info->pga = old_pga;
1036 return ret;
1037 }
1038
1039 return 0;
1040 }
1041
ad4130_set_channel_freq(struct ad4130_state * st,unsigned int channel,int val,int val2)1042 static int ad4130_set_channel_freq(struct ad4130_state *st,
1043 unsigned int channel, int val, int val2)
1044 {
1045 struct ad4130_chan_info *chan_info = &st->chans_info[channel];
1046 struct ad4130_setup_info *setup_info = &chan_info->setup;
1047 unsigned int fs, old_fs;
1048 int ret;
1049
1050 guard(mutex)(&st->lock);
1051 old_fs = setup_info->fs;
1052
1053 ad4130_freq_to_fs(setup_info->filter_type, val, val2, &fs);
1054
1055 if (fs == setup_info->fs)
1056 return 0;
1057
1058 setup_info->fs = fs;
1059
1060 ret = ad4130_write_channel_setup(st, channel, false);
1061 if (ret) {
1062 setup_info->fs = old_fs;
1063 return ret;
1064 }
1065
1066 return 0;
1067 }
1068
_ad4130_read_sample(struct iio_dev * indio_dev,unsigned int channel,int * val)1069 static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
1070 int *val)
1071 {
1072 struct ad4130_state *st = iio_priv(indio_dev);
1073 int ret;
1074
1075 ret = ad4130_set_channel_enable(st, channel, true);
1076 if (ret)
1077 return ret;
1078
1079 reinit_completion(&st->completion);
1080
1081 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
1082 if (ret)
1083 return ret;
1084
1085 ret = wait_for_completion_timeout(&st->completion,
1086 msecs_to_jiffies(1000));
1087 if (!ret)
1088 return -ETIMEDOUT;
1089
1090 ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
1091 if (ret)
1092 return ret;
1093
1094 ret = regmap_read(st->regmap, AD4130_DATA_REG, val);
1095 if (ret)
1096 return ret;
1097
1098 ret = ad4130_set_channel_enable(st, channel, false);
1099 if (ret)
1100 return ret;
1101
1102 return IIO_VAL_INT;
1103 }
1104
ad4130_read_sample(struct iio_dev * indio_dev,unsigned int channel,int * val)1105 static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
1106 int *val)
1107 {
1108 struct ad4130_state *st = iio_priv(indio_dev);
1109
1110 guard(mutex)(&st->lock);
1111
1112 return _ad4130_read_sample(indio_dev, channel, val);
1113 }
1114
ad4130_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)1115 static int ad4130_read_raw(struct iio_dev *indio_dev,
1116 struct iio_chan_spec const *chan,
1117 int *val, int *val2, long info)
1118 {
1119 struct ad4130_state *st = iio_priv(indio_dev);
1120 unsigned int channel = chan->scan_index;
1121 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
1122 int ret;
1123
1124 switch (info) {
1125 case IIO_CHAN_INFO_RAW:
1126 if (!iio_device_claim_direct(indio_dev))
1127 return -EBUSY;
1128
1129 ret = ad4130_read_sample(indio_dev, channel, val);
1130 iio_device_release_direct(indio_dev);
1131 return ret;
1132 case IIO_CHAN_INFO_SCALE: {
1133 guard(mutex)(&st->lock);
1134 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0];
1135 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1];
1136
1137 return IIO_VAL_INT_PLUS_NANO;
1138 }
1139 case IIO_CHAN_INFO_OFFSET:
1140 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0;
1141
1142 return IIO_VAL_INT;
1143 case IIO_CHAN_INFO_SAMP_FREQ: {
1144 guard(mutex)(&st->lock);
1145 ad4130_fs_to_freq(setup_info->filter_type, setup_info->fs,
1146 val, val2);
1147
1148 return IIO_VAL_INT_PLUS_NANO;
1149 }
1150 default:
1151 return -EINVAL;
1152 }
1153 }
1154
ad4130_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)1155 static int ad4130_read_avail(struct iio_dev *indio_dev,
1156 struct iio_chan_spec const *chan,
1157 const int **vals, int *type, int *length,
1158 long info)
1159 {
1160 struct ad4130_state *st = iio_priv(indio_dev);
1161 unsigned int channel = chan->scan_index;
1162 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
1163 const struct ad4130_filter_config *filter_config;
1164
1165 switch (info) {
1166 case IIO_CHAN_INFO_SCALE:
1167 *vals = (int *)st->scale_tbls[setup_info->ref_sel];
1168 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2;
1169
1170 *type = IIO_VAL_INT_PLUS_NANO;
1171
1172 return IIO_AVAIL_LIST;
1173 case IIO_CHAN_INFO_SAMP_FREQ:
1174 scoped_guard(mutex, &st->lock) {
1175 filter_config = &ad4130_filter_configs[setup_info->filter_type];
1176 }
1177
1178 *vals = (int *)filter_config->samp_freq_avail;
1179 *length = filter_config->samp_freq_avail_len * 2;
1180 *type = IIO_VAL_FRACTIONAL;
1181
1182 return filter_config->samp_freq_avail_type;
1183 default:
1184 return -EINVAL;
1185 }
1186 }
1187
ad4130_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)1188 static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev,
1189 struct iio_chan_spec const *chan,
1190 long info)
1191 {
1192 switch (info) {
1193 case IIO_CHAN_INFO_SCALE:
1194 case IIO_CHAN_INFO_SAMP_FREQ:
1195 return IIO_VAL_INT_PLUS_NANO;
1196 default:
1197 return -EINVAL;
1198 }
1199 }
1200
ad4130_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1201 static int ad4130_write_raw(struct iio_dev *indio_dev,
1202 struct iio_chan_spec const *chan,
1203 int val, int val2, long info)
1204 {
1205 struct ad4130_state *st = iio_priv(indio_dev);
1206 unsigned int channel = chan->scan_index;
1207
1208 switch (info) {
1209 case IIO_CHAN_INFO_SCALE:
1210 return ad4130_set_channel_pga(st, channel, val, val2);
1211 case IIO_CHAN_INFO_SAMP_FREQ:
1212 return ad4130_set_channel_freq(st, channel, val, val2);
1213 default:
1214 return -EINVAL;
1215 }
1216 }
1217
ad4130_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1218 static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1219 unsigned int writeval, unsigned int *readval)
1220 {
1221 struct ad4130_state *st = iio_priv(indio_dev);
1222
1223 if (readval)
1224 return regmap_read(st->regmap, reg, readval);
1225
1226 return regmap_write(st->regmap, reg, writeval);
1227 }
1228
ad4130_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1229 static int ad4130_update_scan_mode(struct iio_dev *indio_dev,
1230 const unsigned long *scan_mask)
1231 {
1232 struct ad4130_state *st = iio_priv(indio_dev);
1233 unsigned int channel;
1234 unsigned int val = 0;
1235 int ret;
1236
1237 guard(mutex)(&st->lock);
1238
1239 for_each_set_bit(channel, scan_mask, indio_dev->num_channels) {
1240 ret = ad4130_set_channel_enable(st, channel, true);
1241 if (ret)
1242 return ret;
1243
1244 val++;
1245 }
1246
1247 st->num_enabled_channels = val;
1248
1249 return 0;
1250 }
1251
ad4130_set_fifo_watermark(struct iio_dev * indio_dev,unsigned int val)1252 static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val)
1253 {
1254 struct ad4130_state *st = iio_priv(indio_dev);
1255 unsigned int eff;
1256 int ret;
1257
1258 if (val > AD4130_FIFO_SIZE)
1259 return -EINVAL;
1260
1261 eff = val * st->num_enabled_channels;
1262 if (eff > AD4130_FIFO_SIZE)
1263 /*
1264 * Always set watermark to a multiple of the number of
1265 * enabled channels to avoid making the FIFO unaligned.
1266 */
1267 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels);
1268
1269 guard(mutex)(&st->lock);
1270
1271 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
1272 AD4130_FIFO_CONTROL_WM_MASK,
1273 FIELD_PREP(AD4130_FIFO_CONTROL_WM_MASK,
1274 ad4130_watermark_reg_val(eff)));
1275 if (ret)
1276 return ret;
1277
1278 st->effective_watermark = eff;
1279 st->watermark = val;
1280
1281 return 0;
1282 }
1283
1284 static const struct iio_info ad4130_info = {
1285 .read_raw = ad4130_read_raw,
1286 .read_avail = ad4130_read_avail,
1287 .write_raw_get_fmt = ad4130_write_raw_get_fmt,
1288 .write_raw = ad4130_write_raw,
1289 .update_scan_mode = ad4130_update_scan_mode,
1290 .hwfifo_set_watermark = ad4130_set_fifo_watermark,
1291 .debugfs_reg_access = ad4130_reg_access,
1292 };
1293
ad4130_buffer_postenable(struct iio_dev * indio_dev)1294 static int ad4130_buffer_postenable(struct iio_dev *indio_dev)
1295 {
1296 struct ad4130_state *st = iio_priv(indio_dev);
1297 int ret;
1298
1299 guard(mutex)(&st->lock);
1300
1301 ret = ad4130_set_watermark_interrupt_en(st, true);
1302 if (ret)
1303 return ret;
1304
1305 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger);
1306 if (ret)
1307 return ret;
1308
1309 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM);
1310 if (ret)
1311 return ret;
1312
1313 return ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
1314 }
1315
ad4130_buffer_predisable(struct iio_dev * indio_dev)1316 static int ad4130_buffer_predisable(struct iio_dev *indio_dev)
1317 {
1318 struct ad4130_state *st = iio_priv(indio_dev);
1319 unsigned int i;
1320 int ret;
1321
1322 guard(mutex)(&st->lock);
1323
1324 ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
1325 if (ret)
1326 return ret;
1327
1328 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger);
1329 if (ret)
1330 return ret;
1331
1332 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED);
1333 if (ret)
1334 return ret;
1335
1336 ret = ad4130_set_watermark_interrupt_en(st, false);
1337 if (ret)
1338 return ret;
1339
1340 /*
1341 * update_scan_mode() is not called in the disable path, disable all
1342 * channels here.
1343 */
1344 for (i = 0; i < indio_dev->num_channels; i++) {
1345 ret = ad4130_set_channel_enable(st, i, false);
1346 if (ret)
1347 return ret;
1348 }
1349
1350 return 0;
1351 }
1352
1353 static const struct iio_buffer_setup_ops ad4130_buffer_ops = {
1354 .postenable = ad4130_buffer_postenable,
1355 .predisable = ad4130_buffer_predisable,
1356 };
1357
hwfifo_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)1358 static ssize_t hwfifo_watermark_show(struct device *dev,
1359 struct device_attribute *attr, char *buf)
1360 {
1361 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
1362 unsigned int val;
1363
1364 guard(mutex)(&st->lock);
1365 val = st->watermark;
1366
1367 return sysfs_emit(buf, "%d\n", val);
1368 }
1369
hwfifo_enabled_show(struct device * dev,struct device_attribute * attr,char * buf)1370 static ssize_t hwfifo_enabled_show(struct device *dev,
1371 struct device_attribute *attr, char *buf)
1372 {
1373 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
1374 unsigned int val;
1375 int ret;
1376
1377 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val);
1378 if (ret)
1379 return ret;
1380
1381 val = FIELD_GET(AD4130_FIFO_CONTROL_MODE_MASK, val);
1382
1383 return sysfs_emit(buf, "%d\n", val != AD4130_FIFO_MODE_DISABLED);
1384 }
1385
hwfifo_watermark_min_show(struct device * dev,struct device_attribute * attr,char * buf)1386 static ssize_t hwfifo_watermark_min_show(struct device *dev,
1387 struct device_attribute *attr,
1388 char *buf)
1389 {
1390 return sysfs_emit(buf, "%s\n", "1");
1391 }
1392
hwfifo_watermark_max_show(struct device * dev,struct device_attribute * attr,char * buf)1393 static ssize_t hwfifo_watermark_max_show(struct device *dev,
1394 struct device_attribute *attr,
1395 char *buf)
1396 {
1397 return sysfs_emit(buf, "%s\n", __stringify(AD4130_FIFO_SIZE));
1398 }
1399
1400 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
1401 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
1402 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);
1403 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);
1404
1405 static const struct iio_dev_attr *ad4130_fifo_attributes[] = {
1406 &iio_dev_attr_hwfifo_watermark_min,
1407 &iio_dev_attr_hwfifo_watermark_max,
1408 &iio_dev_attr_hwfifo_watermark,
1409 &iio_dev_attr_hwfifo_enabled,
1410 NULL
1411 };
1412
_ad4130_find_table_index(const unsigned int * tbl,size_t len,unsigned int val)1413 static int _ad4130_find_table_index(const unsigned int *tbl, size_t len,
1414 unsigned int val)
1415 {
1416 unsigned int i;
1417
1418 for (i = 0; i < len; i++)
1419 if (tbl[i] == val)
1420 return i;
1421
1422 return -EINVAL;
1423 }
1424
1425 #define ad4130_find_table_index(table, val) \
1426 _ad4130_find_table_index(table, ARRAY_SIZE(table), val)
1427
ad4130_get_ref_voltage(struct ad4130_state * st,enum ad4130_ref_sel ref_sel)1428 static int ad4130_get_ref_voltage(struct ad4130_state *st,
1429 enum ad4130_ref_sel ref_sel)
1430 {
1431 switch (ref_sel) {
1432 case AD4130_REF_REFIN1:
1433 return regulator_get_voltage(st->regulators[2].consumer);
1434 case AD4130_REF_REFIN2:
1435 return regulator_get_voltage(st->regulators[3].consumer);
1436 case AD4130_REF_AVDD_AVSS:
1437 return regulator_get_voltage(st->regulators[0].consumer);
1438 case AD4130_REF_REFOUT_AVSS:
1439 return st->int_ref_uv;
1440 default:
1441 return -EINVAL;
1442 }
1443 }
1444
ad4130_parse_fw_setup(struct ad4130_state * st,struct fwnode_handle * child,struct ad4130_setup_info * setup_info)1445 static int ad4130_parse_fw_setup(struct ad4130_state *st,
1446 struct fwnode_handle *child,
1447 struct ad4130_setup_info *setup_info)
1448 {
1449 struct device *dev = &st->spi->dev;
1450 u32 tmp;
1451 int ret;
1452
1453 tmp = 0;
1454 fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp);
1455 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
1456 if (ret < 0)
1457 return dev_err_probe(dev, ret,
1458 "Invalid excitation current %unA\n", tmp);
1459 setup_info->iout0_val = ret;
1460
1461 tmp = 0;
1462 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp);
1463 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
1464 if (ret < 0)
1465 return dev_err_probe(dev, ret,
1466 "Invalid excitation current %unA\n", tmp);
1467 setup_info->iout1_val = ret;
1468
1469 tmp = 0;
1470 fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp);
1471 ret = ad4130_find_table_index(ad4130_burnout_current_na_tbl, tmp);
1472 if (ret < 0)
1473 return dev_err_probe(dev, ret,
1474 "Invalid burnout current %unA\n", tmp);
1475 setup_info->burnout = ret;
1476
1477 setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive");
1478 setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative");
1479
1480 setup_info->ref_sel = AD4130_REF_REFIN1;
1481 fwnode_property_read_u32(child, "adi,reference-select",
1482 &setup_info->ref_sel);
1483 if (setup_info->ref_sel >= AD4130_REF_SEL_MAX)
1484 return dev_err_probe(dev, -EINVAL,
1485 "Invalid reference selected %u\n",
1486 setup_info->ref_sel);
1487
1488 if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS)
1489 st->int_ref_en = true;
1490
1491 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel);
1492 if (ret < 0)
1493 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1494 setup_info->ref_sel);
1495
1496 return 0;
1497 }
1498
ad4130_validate_diff_channel(struct ad4130_state * st,u32 pin)1499 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin)
1500 {
1501 struct device *dev = &st->spi->dev;
1502
1503 if (pin >= AD4130_MAX_DIFF_INPUTS)
1504 return dev_err_probe(dev, -EINVAL,
1505 "Invalid differential channel %u\n", pin);
1506
1507 if (pin >= AD4130_MAX_ANALOG_PINS)
1508 return 0;
1509
1510 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1511 return dev_err_probe(dev, -EINVAL,
1512 "Pin %u already used with fn %u\n", pin,
1513 st->pins_fn[pin]);
1514
1515 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF;
1516
1517 return 0;
1518 }
1519
ad4130_validate_diff_channels(struct ad4130_state * st,u32 * pins,unsigned int len)1520 static int ad4130_validate_diff_channels(struct ad4130_state *st,
1521 u32 *pins, unsigned int len)
1522 {
1523 unsigned int i;
1524 int ret;
1525
1526 for (i = 0; i < len; i++) {
1527 ret = ad4130_validate_diff_channel(st, pins[i]);
1528 if (ret)
1529 return ret;
1530 }
1531
1532 return 0;
1533 }
1534
ad4130_validate_excitation_pin(struct ad4130_state * st,u32 pin)1535 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin)
1536 {
1537 struct device *dev = &st->spi->dev;
1538
1539 if (pin >= AD4130_MAX_ANALOG_PINS)
1540 return dev_err_probe(dev, -EINVAL,
1541 "Invalid excitation pin %u\n", pin);
1542
1543 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1544 return dev_err_probe(dev, -EINVAL,
1545 "Pin %u already used with fn %u\n", pin,
1546 st->pins_fn[pin]);
1547
1548 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION;
1549
1550 return 0;
1551 }
1552
ad4130_validate_vbias_pin(struct ad4130_state * st,u32 pin)1553 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin)
1554 {
1555 struct device *dev = &st->spi->dev;
1556
1557 if (pin >= AD4130_MAX_ANALOG_PINS)
1558 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n",
1559 pin);
1560
1561 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1562 return dev_err_probe(dev, -EINVAL,
1563 "Pin %u already used with fn %u\n", pin,
1564 st->pins_fn[pin]);
1565
1566 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS;
1567
1568 return 0;
1569 }
1570
ad4130_validate_vbias_pins(struct ad4130_state * st,u32 * pins,unsigned int len)1571 static int ad4130_validate_vbias_pins(struct ad4130_state *st,
1572 u32 *pins, unsigned int len)
1573 {
1574 unsigned int i;
1575 int ret;
1576
1577 for (i = 0; i < st->num_vbias_pins; i++) {
1578 ret = ad4130_validate_vbias_pin(st, pins[i]);
1579 if (ret)
1580 return ret;
1581 }
1582
1583 return 0;
1584 }
1585
ad4130_parse_fw_channel(struct iio_dev * indio_dev,struct fwnode_handle * child)1586 static int ad4130_parse_fw_channel(struct iio_dev *indio_dev,
1587 struct fwnode_handle *child)
1588 {
1589 struct ad4130_state *st = iio_priv(indio_dev);
1590 unsigned int resolution = ad4130_resolution(st);
1591 unsigned int index = indio_dev->num_channels++;
1592 struct device *dev = &st->spi->dev;
1593 struct ad4130_chan_info *chan_info;
1594 struct iio_chan_spec *chan;
1595 u32 pins[2];
1596 int ret;
1597
1598 if (index >= AD4130_MAX_CHANNELS)
1599 return dev_err_probe(dev, -EINVAL, "Too many channels\n");
1600
1601 chan = &st->chans[index];
1602 chan_info = &st->chans_info[index];
1603
1604 *chan = ad4130_channel_template;
1605 chan->scan_type.realbits = resolution;
1606 chan->scan_type.storagebits = resolution;
1607 chan->scan_index = index;
1608
1609 chan_info->slot = AD4130_INVALID_SLOT;
1610 chan_info->setup.fs = AD4130_FILTER_SELECT_MIN;
1611 chan_info->initialized = true;
1612
1613 ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
1614 ARRAY_SIZE(pins));
1615 if (ret)
1616 return ret;
1617
1618 ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins));
1619 if (ret)
1620 return ret;
1621
1622 chan->channel = pins[0];
1623 chan->channel2 = pins[1];
1624
1625 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup);
1626 if (ret)
1627 return ret;
1628
1629 fwnode_property_read_u32(child, "adi,excitation-pin-0",
1630 &chan_info->iout0);
1631 if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) {
1632 ret = ad4130_validate_excitation_pin(st, chan_info->iout0);
1633 if (ret)
1634 return ret;
1635 }
1636
1637 fwnode_property_read_u32(child, "adi,excitation-pin-1",
1638 &chan_info->iout1);
1639 if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) {
1640 ret = ad4130_validate_excitation_pin(st, chan_info->iout1);
1641 if (ret)
1642 return ret;
1643 }
1644
1645 return 0;
1646 }
1647
ad4130_parse_fw_children(struct iio_dev * indio_dev)1648 static int ad4130_parse_fw_children(struct iio_dev *indio_dev)
1649 {
1650 struct ad4130_state *st = iio_priv(indio_dev);
1651 struct device *dev = &st->spi->dev;
1652 int ret;
1653
1654 indio_dev->channels = st->chans;
1655
1656 device_for_each_child_node_scoped(dev, child) {
1657 ret = ad4130_parse_fw_channel(indio_dev, child);
1658 if (ret)
1659 return ret;
1660 }
1661
1662 return 0;
1663 }
1664
ad4310_parse_fw(struct iio_dev * indio_dev)1665 static int ad4310_parse_fw(struct iio_dev *indio_dev)
1666 {
1667 struct ad4130_state *st = iio_priv(indio_dev);
1668 struct device *dev = &st->spi->dev;
1669 u32 ext_clk_freq = AD4130_MCLK_FREQ_76_8KHZ;
1670 unsigned int i;
1671 int avdd_uv;
1672 int irq;
1673 int ret;
1674
1675 st->mclk = devm_clk_get_optional(dev, "mclk");
1676 if (IS_ERR(st->mclk))
1677 return dev_err_probe(dev, PTR_ERR(st->mclk),
1678 "Failed to get mclk\n");
1679
1680 st->int_pin_sel = AD4130_INT_PIN_INT;
1681
1682 for (i = 0; i < ARRAY_SIZE(ad4130_int_pin_names); i++) {
1683 irq = fwnode_irq_get_byname(dev_fwnode(dev),
1684 ad4130_int_pin_names[i]);
1685 if (irq > 0) {
1686 st->int_pin_sel = i;
1687 break;
1688 }
1689 }
1690
1691 if (st->int_pin_sel == AD4130_INT_PIN_DOUT)
1692 return dev_err_probe(dev, -EINVAL,
1693 "Cannot use DOUT as interrupt pin\n");
1694
1695 if (st->int_pin_sel == AD4130_INT_PIN_P2)
1696 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL;
1697
1698 device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq);
1699 if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ &&
1700 ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ)
1701 return dev_err_probe(dev, -EINVAL,
1702 "Invalid external clock frequency %u\n",
1703 ext_clk_freq);
1704
1705 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ)
1706 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT;
1707 else if (st->mclk)
1708 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT;
1709 else
1710 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1711
1712 if (st->int_pin_sel == AD4130_INT_PIN_CLK &&
1713 st->mclk_sel != AD4130_MCLK_76_8KHZ)
1714 return dev_err_probe(dev, -EINVAL,
1715 "Invalid clock %u for interrupt pin %u\n",
1716 st->mclk_sel, st->int_pin_sel);
1717
1718 st->int_ref_uv = AD4130_INT_REF_2_5V;
1719
1720 /*
1721 * When the AVDD supply is set to below 2.5V the internal reference of
1722 * 1.25V should be selected.
1723 * See datasheet page 37, section ADC REFERENCE.
1724 */
1725 avdd_uv = regulator_get_voltage(st->regulators[0].consumer);
1726 if (avdd_uv > 0 && avdd_uv < AD4130_INT_REF_2_5V)
1727 st->int_ref_uv = AD4130_INT_REF_1_25V;
1728
1729 st->bipolar = device_property_read_bool(dev, "adi,bipolar");
1730
1731 ret = device_property_count_u32(dev, "adi,vbias-pins");
1732 if (ret > 0) {
1733 if (ret > AD4130_MAX_ANALOG_PINS)
1734 return dev_err_probe(dev, -EINVAL,
1735 "Too many vbias pins %u\n", ret);
1736
1737 st->num_vbias_pins = ret;
1738
1739 ret = device_property_read_u32_array(dev, "adi,vbias-pins",
1740 st->vbias_pins,
1741 st->num_vbias_pins);
1742 if (ret)
1743 return dev_err_probe(dev, ret,
1744 "Failed to read vbias pins\n");
1745
1746 ret = ad4130_validate_vbias_pins(st, st->vbias_pins,
1747 st->num_vbias_pins);
1748 if (ret)
1749 return ret;
1750 }
1751
1752 ret = ad4130_parse_fw_children(indio_dev);
1753 if (ret)
1754 return ret;
1755
1756 return 0;
1757 }
1758
ad4130_fill_scale_tbls(struct ad4130_state * st)1759 static void ad4130_fill_scale_tbls(struct ad4130_state *st)
1760 {
1761 unsigned int pow = ad4130_resolution(st) - st->bipolar;
1762 unsigned int i, j;
1763
1764 for (i = 0; i < AD4130_REF_SEL_MAX; i++) {
1765 int ret;
1766 u64 nv;
1767
1768 ret = ad4130_get_ref_voltage(st, i);
1769 if (ret < 0)
1770 continue;
1771
1772 nv = (u64)ret * NANO;
1773
1774 for (j = 0; j < AD4130_MAX_PGA; j++)
1775 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI);
1776 }
1777 }
1778
ad4130_clk_disable_unprepare(void * clk)1779 static void ad4130_clk_disable_unprepare(void *clk)
1780 {
1781 clk_disable_unprepare(clk);
1782 }
1783
ad4130_set_mclk_sel(struct ad4130_state * st,enum ad4130_mclk_sel mclk_sel)1784 static int ad4130_set_mclk_sel(struct ad4130_state *st,
1785 enum ad4130_mclk_sel mclk_sel)
1786 {
1787 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
1788 AD4130_ADC_CONTROL_MCLK_SEL_MASK,
1789 FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK,
1790 mclk_sel));
1791 }
1792
ad4130_int_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1793 static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw,
1794 unsigned long parent_rate)
1795 {
1796 return AD4130_MCLK_FREQ_76_8KHZ;
1797 }
1798
ad4130_int_clk_is_enabled(struct clk_hw * hw)1799 static int ad4130_int_clk_is_enabled(struct clk_hw *hw)
1800 {
1801 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1802
1803 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT;
1804 }
1805
ad4130_int_clk_prepare(struct clk_hw * hw)1806 static int ad4130_int_clk_prepare(struct clk_hw *hw)
1807 {
1808 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1809 int ret;
1810
1811 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT);
1812 if (ret)
1813 return ret;
1814
1815 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT;
1816
1817 return 0;
1818 }
1819
ad4130_int_clk_unprepare(struct clk_hw * hw)1820 static void ad4130_int_clk_unprepare(struct clk_hw *hw)
1821 {
1822 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1823 int ret;
1824
1825 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ);
1826 if (ret)
1827 return;
1828
1829 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1830 }
1831
1832 static const struct clk_ops ad4130_int_clk_ops = {
1833 .recalc_rate = ad4130_int_clk_recalc_rate,
1834 .is_enabled = ad4130_int_clk_is_enabled,
1835 .prepare = ad4130_int_clk_prepare,
1836 .unprepare = ad4130_int_clk_unprepare,
1837 };
1838
ad4130_setup_int_clk(struct ad4130_state * st)1839 static int ad4130_setup_int_clk(struct ad4130_state *st)
1840 {
1841 struct device *dev = &st->spi->dev;
1842 struct device_node *of_node = dev_of_node(dev);
1843 struct clk_init_data init = {};
1844 const char *clk_name;
1845 int ret;
1846
1847 if (st->int_pin_sel == AD4130_INT_PIN_CLK ||
1848 st->mclk_sel != AD4130_MCLK_76_8KHZ)
1849 return 0;
1850
1851 if (!of_node)
1852 return 0;
1853
1854 clk_name = of_node->name;
1855 of_property_read_string(of_node, "clock-output-names", &clk_name);
1856
1857 init.name = clk_name;
1858 init.ops = &ad4130_int_clk_ops;
1859
1860 st->int_clk_hw.init = &init;
1861 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1862 if (ret)
1863 return ret;
1864
1865 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1866 &st->int_clk_hw);
1867 }
1868
ad4130_setup(struct iio_dev * indio_dev)1869 static int ad4130_setup(struct iio_dev *indio_dev)
1870 {
1871 struct ad4130_state *st = iio_priv(indio_dev);
1872 struct device *dev = &st->spi->dev;
1873 unsigned int int_ref_val;
1874 unsigned long rate = AD4130_MCLK_FREQ_76_8KHZ;
1875 unsigned int val;
1876 unsigned int i;
1877 int ret;
1878
1879 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT)
1880 rate = AD4130_MCLK_FREQ_153_6KHZ;
1881
1882 ret = clk_set_rate(st->mclk, rate);
1883 if (ret)
1884 return ret;
1885
1886 ret = clk_prepare_enable(st->mclk);
1887 if (ret)
1888 return ret;
1889
1890 ret = devm_add_action_or_reset(dev, ad4130_clk_disable_unprepare,
1891 st->mclk);
1892 if (ret)
1893 return ret;
1894
1895 if (st->int_ref_uv == AD4130_INT_REF_2_5V)
1896 int_ref_val = AD4130_INT_REF_VAL_2_5V;
1897 else
1898 int_ref_val = AD4130_INT_REF_VAL_1_25V;
1899
1900 /* Switch to SPI 4-wire mode. */
1901 val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1);
1902 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar);
1903 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en);
1904 val |= FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, AD4130_MODE_IDLE);
1905 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel);
1906 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, int_ref_val);
1907
1908 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val);
1909 if (ret)
1910 return ret;
1911
1912 /*
1913 * Configure unused GPIOs for output. If configured, the interrupt
1914 * function of P2 takes priority over the GPIO out function.
1915 */
1916 val = 0;
1917 for (i = 0; i < AD4130_MAX_GPIOS; i++)
1918 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE)
1919 val |= FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i));
1920
1921 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel);
1922
1923 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val);
1924 if (ret)
1925 return ret;
1926
1927 val = 0;
1928 for (i = 0; i < st->num_vbias_pins; i++)
1929 val |= BIT(st->vbias_pins[i]);
1930
1931 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val);
1932 if (ret)
1933 return ret;
1934
1935 ret = regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
1936 AD4130_FIFO_CONTROL_HEADER_MASK);
1937 if (ret)
1938 return ret;
1939
1940 /* FIFO watermark interrupt starts out as enabled, disable it. */
1941 ret = ad4130_set_watermark_interrupt_en(st, false);
1942 if (ret)
1943 return ret;
1944
1945 /* Setup channels. */
1946 for (i = 0; i < indio_dev->num_channels; i++) {
1947 struct ad4130_chan_info *chan_info = &st->chans_info[i];
1948 struct iio_chan_spec *chan = &st->chans[i];
1949 unsigned int val;
1950
1951 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) |
1952 FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) |
1953 FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) |
1954 FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1);
1955
1956 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val);
1957 if (ret)
1958 return ret;
1959 }
1960
1961 return 0;
1962 }
1963
ad4130_soft_reset(struct ad4130_state * st)1964 static int ad4130_soft_reset(struct ad4130_state *st)
1965 {
1966 int ret;
1967
1968 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf));
1969 if (ret)
1970 return ret;
1971
1972 fsleep(AD4130_RESET_SLEEP_US);
1973
1974 return 0;
1975 }
1976
ad4130_disable_regulators(void * data)1977 static void ad4130_disable_regulators(void *data)
1978 {
1979 struct ad4130_state *st = data;
1980
1981 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1982 }
1983
ad4130_probe(struct spi_device * spi)1984 static int ad4130_probe(struct spi_device *spi)
1985 {
1986 struct device *dev = &spi->dev;
1987 struct iio_dev *indio_dev;
1988 struct ad4130_state *st;
1989 int ret;
1990
1991 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1992 if (!indio_dev)
1993 return -ENOMEM;
1994
1995 st = iio_priv(indio_dev);
1996
1997 memset(st->reset_buf, 0xff, sizeof(st->reset_buf));
1998 init_completion(&st->completion);
1999 mutex_init(&st->lock);
2000 st->spi = spi;
2001
2002 /*
2003 * Xfer: [ XFR1 ] [ XFR2 ]
2004 * Master: 0x7D N ......................
2005 * Slave: ...... DATA1 DATA2 ... DATAN
2006 */
2007 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG;
2008 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
2009 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
2010 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf;
2011 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer,
2012 ARRAY_SIZE(st->fifo_xfer));
2013
2014 indio_dev->name = AD4130_NAME;
2015 indio_dev->modes = INDIO_DIRECT_MODE;
2016 indio_dev->info = &ad4130_info;
2017
2018 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config);
2019 if (IS_ERR(st->regmap))
2020 return PTR_ERR(st->regmap);
2021
2022 st->regulators[0].supply = "avdd";
2023 st->regulators[1].supply = "iovdd";
2024 st->regulators[2].supply = "refin1";
2025 st->regulators[3].supply = "refin2";
2026
2027 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
2028 st->regulators);
2029 if (ret)
2030 return dev_err_probe(dev, ret, "Failed to get regulators\n");
2031
2032 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
2033 if (ret)
2034 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
2035
2036 ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st);
2037 if (ret)
2038 return dev_err_probe(dev, ret,
2039 "Failed to add regulators disable action\n");
2040
2041 ret = ad4130_soft_reset(st);
2042 if (ret)
2043 return ret;
2044
2045 ret = ad4310_parse_fw(indio_dev);
2046 if (ret)
2047 return ret;
2048
2049 ret = ad4130_setup(indio_dev);
2050 if (ret)
2051 return ret;
2052
2053 ret = ad4130_setup_int_clk(st);
2054 if (ret)
2055 return ret;
2056
2057 ad4130_fill_scale_tbls(st);
2058
2059 st->gc.owner = THIS_MODULE;
2060 st->gc.label = AD4130_NAME;
2061 st->gc.base = -1;
2062 st->gc.ngpio = AD4130_MAX_GPIOS;
2063 st->gc.parent = dev;
2064 st->gc.can_sleep = true;
2065 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask;
2066 st->gc.get_direction = ad4130_gpio_get_direction;
2067 st->gc.set_rv = ad4130_gpio_set;
2068
2069 ret = devm_gpiochip_add_data(dev, &st->gc, st);
2070 if (ret)
2071 return ret;
2072
2073 ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev,
2074 &ad4130_buffer_ops,
2075 ad4130_fifo_attributes);
2076 if (ret)
2077 return ret;
2078
2079 ret = devm_request_threaded_irq(dev, spi->irq, NULL,
2080 ad4130_irq_handler, IRQF_ONESHOT,
2081 indio_dev->name, indio_dev);
2082 if (ret)
2083 return dev_err_probe(dev, ret, "Failed to request irq\n");
2084
2085 /*
2086 * When the chip enters FIFO mode, IRQ polarity is inverted.
2087 * When the chip exits FIFO mode, IRQ polarity returns to normal.
2088 * See datasheet pages: 65, FIFO Watermark Interrupt section,
2089 * and 71, Bit Descriptions for STATUS Register, RDYB.
2090 * Cache the normal and inverted IRQ triggers to set them when
2091 * entering and exiting FIFO mode.
2092 */
2093 st->irq_trigger = irq_get_trigger_type(spi->irq);
2094 if (st->irq_trigger & IRQF_TRIGGER_RISING)
2095 st->inv_irq_trigger = IRQF_TRIGGER_FALLING;
2096 else if (st->irq_trigger & IRQF_TRIGGER_FALLING)
2097 st->inv_irq_trigger = IRQF_TRIGGER_RISING;
2098 else
2099 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n",
2100 st->irq_trigger);
2101
2102 return devm_iio_device_register(dev, indio_dev);
2103 }
2104
2105 static const struct of_device_id ad4130_of_match[] = {
2106 {
2107 .compatible = "adi,ad4130",
2108 },
2109 { }
2110 };
2111 MODULE_DEVICE_TABLE(of, ad4130_of_match);
2112
2113 static struct spi_driver ad4130_driver = {
2114 .driver = {
2115 .name = AD4130_NAME,
2116 .of_match_table = ad4130_of_match,
2117 },
2118 .probe = ad4130_probe,
2119 };
2120 module_spi_driver(ad4130_driver);
2121
2122 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
2123 MODULE_DESCRIPTION("Analog Devices AD4130 SPI driver");
2124 MODULE_LICENSE("GPL");
2125