1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34 #include <sys/cdefs.h>
35 #include "opt_inet.h"
36
37 #ifdef TCP_OFFLOAD
38 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/socket.h>
41 #include <sys/socketvar.h>
42 #include <sys/sockio.h>
43 #include <sys/taskqueue.h>
44 #include <netinet/in.h>
45 #include <net/route.h>
46
47 #include <netinet/in_systm.h>
48 #include <netinet/in_pcb.h>
49 #include <netinet/ip.h>
50 #include <netinet/ip_var.h>
51 #include <netinet/tcp_var.h>
52 #include <netinet/tcp.h>
53 #include <netinet/tcpip.h>
54
55 #include <netinet/toecore.h>
56
57 struct sge_iq;
58 struct rss_header;
59 struct cpl_set_tcb_rpl;
60 #include <linux/types.h>
61 #include "offload.h"
62 #include "tom/t4_tom.h"
63
64 #include "iw_cxgbe.h"
65 #include "user.h"
66
67 static int creds(struct toepcb *toep, struct tcpcb *tp, size_t wrsize);
68 static int max_fr_immd = T4_MAX_FR_IMMD;//SYSCTL parameter later...
69
alloc_ird(struct c4iw_dev * dev,u32 ird)70 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
71 {
72 int ret = 0;
73
74 xa_lock_irq(&dev->qps);
75 if (ird <= dev->avail_ird)
76 dev->avail_ird -= ird;
77 else
78 ret = -ENOMEM;
79 xa_unlock_irq(&dev->qps);
80
81 if (ret)
82 log(LOG_WARNING, "%s: device IRD resources exhausted\n",
83 device_get_nameunit(dev->rdev.adap->dev));
84
85 return ret;
86 }
87
free_ird(struct c4iw_dev * dev,int ird)88 static void free_ird(struct c4iw_dev *dev, int ird)
89 {
90 xa_lock_irq(&dev->qps);
91 dev->avail_ird += ird;
92 xa_unlock_irq(&dev->qps);
93 }
94
set_state(struct c4iw_qp * qhp,enum c4iw_qp_state state)95 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
96 {
97 unsigned long flag;
98 spin_lock_irqsave(&qhp->lock, flag);
99 qhp->attr.state = state;
100 spin_unlock_irqrestore(&qhp->lock, flag);
101 }
102
destroy_qp(struct c4iw_rdev * rdev,struct t4_wq * wq,struct c4iw_dev_ucontext * uctx)103 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
104 struct c4iw_dev_ucontext *uctx)
105 {
106 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev);
107 /*
108 * uP clears EQ contexts when the connection exits rdma mode,
109 * so no need to post a RESET WR for these EQs.
110 */
111 dma_free_coherent(rhp->ibdev.dma_device,
112 wq->rq.memsize, wq->rq.queue,
113 dma_unmap_addr(&wq->rq, mapping));
114 dma_free_coherent(rhp->ibdev.dma_device,
115 wq->sq.memsize, wq->sq.queue,
116 dma_unmap_addr(&wq->sq, mapping));
117 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
118 kfree(wq->rq.sw_rq);
119 kfree(wq->sq.sw_sq);
120 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
121 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
122 return 0;
123 }
124
create_qp(struct c4iw_rdev * rdev,struct t4_wq * wq,struct t4_cq * rcq,struct t4_cq * scq,struct c4iw_dev_ucontext * uctx,struct c4iw_wr_wait * wr_waitp)125 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
126 struct t4_cq *rcq, struct t4_cq *scq,
127 struct c4iw_dev_ucontext *uctx,
128 struct c4iw_wr_wait *wr_waitp)
129 {
130 struct adapter *sc = rdev->adap;
131 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev);
132 int user = (uctx != &rdev->uctx);
133 struct fw_ri_res_wr *res_wr;
134 struct fw_ri_res *res;
135 int wr_len;
136 int ret = 0;
137 int eqsize;
138 struct wrqe *wr;
139 u64 sq_bar2_qoffset = 0, rq_bar2_qoffset = 0;
140
141 if (__predict_false(c4iw_stopped(rdev)))
142 return -EIO;
143
144 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
145 if (!wq->sq.qid)
146 return -ENOMEM;
147
148 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
149 if (!wq->rq.qid) {
150 ret = -ENOMEM;
151 goto free_sq_qid;
152 }
153
154 if (!user) {
155 wq->sq.sw_sq = kcalloc(wq->sq.size, sizeof(*wq->sq.sw_sq),
156 GFP_KERNEL);
157 if (!wq->sq.sw_sq) {
158 ret = -ENOMEM;
159 goto free_rq_qid;
160 }
161
162 wq->rq.sw_rq = kcalloc(wq->rq.size, sizeof(*wq->rq.sw_rq),
163 GFP_KERNEL);
164 if (!wq->rq.sw_rq) {
165 ret = -ENOMEM;
166 goto free_sw_sq;
167 }
168 }
169
170 /*
171 * RQT must be a power of 2 and at least 16 deep.
172 */
173 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
174 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
175 if (!wq->rq.rqt_hwaddr) {
176 ret = -ENOMEM;
177 goto free_sw_rq;
178 }
179
180 /*QP memory, allocate DMAable memory for Send & Receive Queues */
181 wq->sq.queue = dma_alloc_coherent(rhp->ibdev.dma_device, wq->sq.memsize,
182 &(wq->sq.dma_addr), GFP_KERNEL);
183 if (!wq->sq.queue) {
184 ret = -ENOMEM;
185 goto free_hwaddr;
186 }
187 wq->sq.phys_addr = vtophys(wq->sq.queue);
188 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
189 memset(wq->sq.queue, 0, wq->sq.memsize);
190
191 wq->rq.queue = dma_alloc_coherent(rhp->ibdev.dma_device,
192 wq->rq.memsize, &(wq->rq.dma_addr), GFP_KERNEL);
193 if (!wq->rq.queue) {
194 ret = -ENOMEM;
195 goto free_sq_dma;
196 }
197 wq->rq.phys_addr = vtophys(wq->rq.queue);
198 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
199
200 CTR5(KTR_IW_CXGBE,
201 "%s QP sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx",
202 __func__,
203 wq->sq.queue, (unsigned long long)wq->sq.phys_addr,
204 wq->rq.queue, (unsigned long long)wq->rq.phys_addr);
205
206 /* Doorbell/WC regions, determine the BAR2 queue offset and qid. */
207 t4_bar2_sge_qregs(rdev->adap, wq->sq.qid, T4_BAR2_QTYPE_EGRESS, user,
208 &sq_bar2_qoffset, &wq->sq.bar2_qid);
209 t4_bar2_sge_qregs(rdev->adap, wq->rq.qid, T4_BAR2_QTYPE_EGRESS, user,
210 &rq_bar2_qoffset, &wq->rq.bar2_qid);
211
212 if (user) {
213 /* Compute BAR2 DB/WC physical address(page-aligned) for
214 * Userspace mapping.
215 */
216 wq->sq.bar2_pa = (rdev->bar2_pa + sq_bar2_qoffset) & PAGE_MASK;
217 wq->rq.bar2_pa = (rdev->bar2_pa + rq_bar2_qoffset) & PAGE_MASK;
218 CTR3(KTR_IW_CXGBE,
219 "%s BAR2 DB/WC sq base pa 0x%llx rq base pa 0x%llx",
220 __func__, (unsigned long long)wq->sq.bar2_pa,
221 (unsigned long long)wq->rq.bar2_pa);
222 } else {
223 /* Compute BAR2 DB/WC virtual address to access in kernel. */
224 wq->sq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
225 sq_bar2_qoffset);
226 wq->rq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
227 rq_bar2_qoffset);
228 CTR3(KTR_IW_CXGBE, "%s BAR2 DB/WC sq base va %p rq base va %p",
229 __func__, (unsigned long long)wq->sq.bar2_va,
230 (unsigned long long)wq->rq.bar2_va);
231 }
232
233 wq->rdev = rdev;
234 wq->rq.msn = 1;
235
236 /* build fw_ri_res_wr */
237 wr_len = sizeof *res_wr + 2 * sizeof *res;
238
239 wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]);
240 if (wr == NULL) {
241 ret = -ENOMEM;
242 goto free_rq_dma;
243 }
244 res_wr = wrtod(wr);
245
246 memset(res_wr, 0, wr_len);
247 res_wr->op_nres = cpu_to_be32(
248 V_FW_WR_OP(FW_RI_RES_WR) |
249 V_FW_RI_RES_WR_NRES(2) |
250 F_FW_WR_COMPL);
251 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
252 res_wr->cookie = (uintptr_t)wr_waitp;
253 res = res_wr->res;
254 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
255 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
256
257 /* eqsize is the number of 64B entries plus the status page size. */
258 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
259 rdev->hw_queue.t4_eq_status_entries;
260
261 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
262 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
263 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
264 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
265 V_FW_RI_RES_WR_IQID(scq->cqid));
266 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
267 V_FW_RI_RES_WR_DCAEN(0) |
268 V_FW_RI_RES_WR_DCACPU(0) |
269 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
270 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
271 V_FW_RI_RES_WR_FBMAX(3) |
272 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
273 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
274 V_FW_RI_RES_WR_EQSIZE(eqsize));
275 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
276 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
277 res++;
278 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
279 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
280
281 /* eqsize is the number of 64B entries plus the status page size. */
282 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
283 rdev->hw_queue.t4_eq_status_entries;
284 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
285 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
286 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
287 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
288 V_FW_RI_RES_WR_IQID(rcq->cqid));
289 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
290 V_FW_RI_RES_WR_DCAEN(0) |
291 V_FW_RI_RES_WR_DCACPU(0) |
292 V_FW_RI_RES_WR_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
293 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
294 V_FW_RI_RES_WR_FBMAX(3) |
295 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
296 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
297 V_FW_RI_RES_WR_EQSIZE(eqsize));
298 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
299 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
300
301 c4iw_init_wr_wait(wr_waitp);
302
303 ret = c4iw_ref_send_wait(rdev, wr, wr_waitp, 0, wq->sq.qid,
304 NULL, __func__);
305 if (ret)
306 goto free_rq_dma;
307
308 CTR5(KTR_IW_CXGBE,
309 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx",
310 __func__, wq->sq.qid, wq->rq.qid,
311 (unsigned long long)wq->sq.bar2_va,
312 (unsigned long long)wq->rq.bar2_va);
313
314 return 0;
315 free_rq_dma:
316 dma_free_coherent(rhp->ibdev.dma_device,
317 wq->rq.memsize, wq->rq.queue,
318 dma_unmap_addr(&wq->rq, mapping));
319 free_sq_dma:
320 dma_free_coherent(rhp->ibdev.dma_device,
321 wq->sq.memsize, wq->sq.queue,
322 dma_unmap_addr(&wq->sq, mapping));
323 free_hwaddr:
324 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
325 free_sw_rq:
326 kfree(wq->rq.sw_rq);
327 free_sw_sq:
328 kfree(wq->sq.sw_sq);
329 free_rq_qid:
330 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
331 free_sq_qid:
332 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
333 return ret;
334 }
335
build_immd(struct t4_sq * sq,struct fw_ri_immd * immdp,const struct ib_send_wr * wr,int max,u32 * plenp)336 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
337 const struct ib_send_wr *wr, int max, u32 *plenp)
338 {
339 u8 *dstp, *srcp;
340 u32 plen = 0;
341 int i;
342 int rem, len;
343
344 dstp = (u8 *)immdp->data;
345 for (i = 0; i < wr->num_sge; i++) {
346 if ((plen + wr->sg_list[i].length) > max)
347 return -EMSGSIZE;
348 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
349 plen += wr->sg_list[i].length;
350 rem = wr->sg_list[i].length;
351 while (rem) {
352 if (dstp == (u8 *)&sq->queue[sq->size])
353 dstp = (u8 *)sq->queue;
354 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
355 len = rem;
356 else
357 len = (u8 *)&sq->queue[sq->size] - dstp;
358 memcpy(dstp, srcp, len);
359 dstp += len;
360 srcp += len;
361 rem -= len;
362 }
363 }
364 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
365 if (len)
366 memset(dstp, 0, len);
367 immdp->op = FW_RI_DATA_IMMD;
368 immdp->r1 = 0;
369 immdp->r2 = 0;
370 immdp->immdlen = cpu_to_be32(plen);
371 *plenp = plen;
372 return 0;
373 }
374
build_isgl(__be64 * queue_start,__be64 * queue_end,struct fw_ri_isgl * isglp,struct ib_sge * sg_list,int num_sge,u32 * plenp)375 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
376 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
377 int num_sge, u32 *plenp)
378
379 {
380 int i;
381 u32 plen = 0;
382 __be64 *flitp;
383
384 if ((__be64 *)isglp == queue_end)
385 isglp = (struct fw_ri_isgl *)queue_start;
386
387 flitp = (__be64 *)isglp->sge;
388
389 for (i = 0; i < num_sge; i++) {
390 if ((plen + sg_list[i].length) < plen)
391 return -EMSGSIZE;
392 plen += sg_list[i].length;
393 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
394 sg_list[i].length);
395 if (++flitp == queue_end)
396 flitp = queue_start;
397 *flitp = cpu_to_be64(sg_list[i].addr);
398 if (++flitp == queue_end)
399 flitp = queue_start;
400 }
401 *flitp = (__force __be64)0;
402 isglp->op = FW_RI_DATA_ISGL;
403 isglp->r1 = 0;
404 isglp->nsge = cpu_to_be16(num_sge);
405 isglp->r2 = 0;
406 if (plenp)
407 *plenp = plen;
408 return 0;
409 }
410
build_rdma_send(struct t4_sq * sq,union t4_wr * wqe,const struct ib_send_wr * wr,u8 * len16)411 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
412 const struct ib_send_wr *wr, u8 *len16)
413 {
414 u32 plen;
415 int size;
416 int ret;
417
418 if (wr->num_sge > T4_MAX_SEND_SGE)
419 return -EINVAL;
420 switch (wr->opcode) {
421 case IB_WR_SEND:
422 if (wr->send_flags & IB_SEND_SOLICITED)
423 wqe->send.sendop_pkd = cpu_to_be32(
424 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
425 else
426 wqe->send.sendop_pkd = cpu_to_be32(
427 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
428 wqe->send.stag_inv = 0;
429 break;
430 case IB_WR_SEND_WITH_INV:
431 if (wr->send_flags & IB_SEND_SOLICITED)
432 wqe->send.sendop_pkd = cpu_to_be32(
433 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
434 else
435 wqe->send.sendop_pkd = cpu_to_be32(
436 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
437 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
438 break;
439
440 default:
441 return -EINVAL;
442 }
443 wqe->send.r3 = 0;
444 wqe->send.r4 = 0;
445
446 plen = 0;
447 if (wr->num_sge) {
448 if (wr->send_flags & IB_SEND_INLINE) {
449 ret = build_immd(sq, wqe->send.u.immd_src, wr,
450 T4_MAX_SEND_INLINE, &plen);
451 if (ret)
452 return ret;
453 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
454 plen;
455 } else {
456 ret = build_isgl((__be64 *)sq->queue,
457 (__be64 *)&sq->queue[sq->size],
458 wqe->send.u.isgl_src,
459 wr->sg_list, wr->num_sge, &plen);
460 if (ret)
461 return ret;
462 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
463 wr->num_sge * sizeof(struct fw_ri_sge);
464 }
465 } else {
466 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
467 wqe->send.u.immd_src[0].r1 = 0;
468 wqe->send.u.immd_src[0].r2 = 0;
469 wqe->send.u.immd_src[0].immdlen = 0;
470 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
471 plen = 0;
472 }
473 *len16 = DIV_ROUND_UP(size, 16);
474 wqe->send.plen = cpu_to_be32(plen);
475 return 0;
476 }
477
build_rdma_write(struct t4_sq * sq,union t4_wr * wqe,const struct ib_send_wr * wr,u8 * len16)478 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
479 const struct ib_send_wr *wr, u8 *len16)
480 {
481 u32 plen;
482 int size;
483 int ret;
484
485 if (wr->num_sge > T4_MAX_SEND_SGE)
486 return -EINVAL;
487 if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
488 wqe->write.immd_data = wr->ex.imm_data;
489 else
490 wqe->write.immd_data = 0;
491 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
492 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
493 if (wr->num_sge) {
494 if (wr->send_flags & IB_SEND_INLINE) {
495 ret = build_immd(sq, wqe->write.u.immd_src, wr,
496 T4_MAX_WRITE_INLINE, &plen);
497 if (ret)
498 return ret;
499 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
500 plen;
501 } else {
502 ret = build_isgl((__be64 *)sq->queue,
503 (__be64 *)&sq->queue[sq->size],
504 wqe->write.u.isgl_src,
505 wr->sg_list, wr->num_sge, &plen);
506 if (ret)
507 return ret;
508 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
509 wr->num_sge * sizeof(struct fw_ri_sge);
510 }
511 } else {
512 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
513 wqe->write.u.immd_src[0].r1 = 0;
514 wqe->write.u.immd_src[0].r2 = 0;
515 wqe->write.u.immd_src[0].immdlen = 0;
516 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
517 plen = 0;
518 }
519 *len16 = DIV_ROUND_UP(size, 16);
520 wqe->write.plen = cpu_to_be32(plen);
521 return 0;
522 }
523
build_immd_cmpl(struct t4_sq * sq,struct fw_ri_immd_cmpl * immdp,const struct ib_send_wr * wr)524 static void build_immd_cmpl(struct t4_sq *sq, struct fw_ri_immd_cmpl *immdp,
525 const struct ib_send_wr *wr)
526 {
527 memcpy((u8 *)immdp->data, (u8 *)(uintptr_t)wr->sg_list->addr, 16);
528 memset(immdp->r1, 0, 6);
529 immdp->op = FW_RI_DATA_IMMD;
530 immdp->immdlen = 16;
531 return;
532 }
533
build_rdma_write_cmpl(struct t4_sq * sq,struct fw_ri_rdma_write_cmpl_wr * wcwr,const struct ib_send_wr * wr,u8 * len16)534 static void build_rdma_write_cmpl(struct t4_sq *sq,
535 struct fw_ri_rdma_write_cmpl_wr *wcwr,
536 const struct ib_send_wr *wr, u8 *len16)
537 {
538 u32 plen;
539 int size;
540
541 /*
542 * This code assumes the struct fields preceeding the write isgl
543 * fit in one 64B WR slot. This is because the WQE is built
544 * directly in the dma queue, and wrapping is only handled
545 * by the code buildling sgls. IE the "fixed part" of the wr
546 * structs must all fit in 64B. The WQE build code should probably be
547 * redesigned to avoid this restriction, but for now just add
548 * the BUILD_BUG_ON() to catch if this WQE struct gets too big.
549 */
550 BUILD_BUG_ON(offsetof(struct fw_ri_rdma_write_cmpl_wr, u) > 64);
551
552 wcwr->stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
553 wcwr->to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
554 if (wr->next->opcode == IB_WR_SEND)
555 wcwr->stag_inv = 0;
556 else
557 wcwr->stag_inv = cpu_to_be32(wr->next->ex.invalidate_rkey);
558 wcwr->r2 = 0;
559 wcwr->r3 = 0;
560
561 /* SEND_INV SGL */
562 if (wr->next->send_flags & IB_SEND_INLINE)
563 build_immd_cmpl(sq, &wcwr->u_cmpl.immd_src, wr->next);
564 else
565 build_isgl((__be64 *)sq->queue, (__be64 *)&sq->queue[sq->size],
566 &wcwr->u_cmpl.isgl_src, wr->next->sg_list, 1, NULL);
567
568 /* WRITE SGL */
569 build_isgl((__be64 *)sq->queue, (__be64 *)&sq->queue[sq->size],
570 wcwr->u.isgl_src, wr->sg_list, wr->num_sge, &plen);
571
572 size = sizeof *wcwr + sizeof(struct fw_ri_isgl) +
573 wr->num_sge * sizeof(struct fw_ri_sge);
574 wcwr->plen = cpu_to_be32(plen);
575 *len16 = DIV_ROUND_UP(size, 16);
576
577 return;
578 }
579
build_rdma_read(union t4_wr * wqe,const struct ib_send_wr * wr,u8 * len16)580 static int build_rdma_read(union t4_wr *wqe, const struct ib_send_wr *wr, u8 *len16)
581 {
582 if (wr->num_sge > 1)
583 return -EINVAL;
584 if (wr->num_sge && wr->sg_list[0].length) {
585 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
586 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
587 >> 32));
588 wqe->read.to_src_lo =
589 cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
590 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
591 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
592 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
593 >> 32));
594 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
595 } else {
596 wqe->read.stag_src = cpu_to_be32(2);
597 wqe->read.to_src_hi = 0;
598 wqe->read.to_src_lo = 0;
599 wqe->read.stag_sink = cpu_to_be32(2);
600 wqe->read.plen = 0;
601 wqe->read.to_sink_hi = 0;
602 wqe->read.to_sink_lo = 0;
603 }
604 wqe->read.r2 = 0;
605 wqe->read.r5 = 0;
606 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
607 return 0;
608 }
609
build_rdma_recv(struct c4iw_qp * qhp,union t4_recv_wr * wqe,const struct ib_recv_wr * wr,u8 * len16)610 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
611 const struct ib_recv_wr *wr, u8 *len16)
612 {
613 int ret;
614
615 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
616 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
617 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
618 if (ret)
619 return ret;
620 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
621 wr->num_sge * sizeof(struct fw_ri_sge), 16);
622 return 0;
623 }
624
build_inv_stag(union t4_wr * wqe,const struct ib_send_wr * wr,u8 * len16)625 static int build_inv_stag(union t4_wr *wqe, const struct ib_send_wr *wr,
626 u8 *len16)
627 {
628 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
629 wqe->inv.r2 = 0;
630 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
631 return 0;
632 }
633
c4iw_qp_add_ref(struct ib_qp * qp)634 void c4iw_qp_add_ref(struct ib_qp *qp)
635 {
636 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp);
637 refcount_inc(&to_c4iw_qp(qp)->qp_refcnt);
638 }
639
c4iw_qp_rem_ref(struct ib_qp * qp)640 void c4iw_qp_rem_ref(struct ib_qp *qp)
641 {
642 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp);
643 if (refcount_dec_and_test(&to_c4iw_qp(qp)->qp_refcnt))
644 complete(&to_c4iw_qp(qp)->qp_rel_comp);
645 }
646
ib_to_fw_opcode(int ib_opcode)647 static int ib_to_fw_opcode(int ib_opcode)
648 {
649 int opcode;
650
651 switch (ib_opcode) {
652 case IB_WR_SEND_WITH_INV:
653 opcode = FW_RI_SEND_WITH_INV;
654 break;
655 case IB_WR_SEND:
656 opcode = FW_RI_SEND;
657 break;
658 case IB_WR_RDMA_WRITE:
659 opcode = FW_RI_RDMA_WRITE;
660 break;
661 case IB_WR_RDMA_WRITE_WITH_IMM:
662 opcode = FW_RI_WRITE_IMMEDIATE;
663 break;
664 case IB_WR_RDMA_READ:
665 case IB_WR_RDMA_READ_WITH_INV:
666 opcode = FW_RI_READ_REQ;
667 break;
668 case IB_WR_REG_MR:
669 opcode = FW_RI_FAST_REGISTER;
670 break;
671 case IB_WR_LOCAL_INV:
672 opcode = FW_RI_LOCAL_INV;
673 break;
674 default:
675 opcode = -EINVAL;
676 }
677 return opcode;
678 }
679
complete_sq_drain_wr(struct c4iw_qp * qhp,const struct ib_send_wr * wr)680 static int complete_sq_drain_wr(struct c4iw_qp *qhp,
681 const struct ib_send_wr *wr)
682 {
683 struct t4_cqe cqe = {};
684 struct c4iw_cq *schp;
685 unsigned long flag;
686 struct t4_cq *cq;
687 int opcode;
688
689 schp = to_c4iw_cq(qhp->ibqp.send_cq);
690 cq = &schp->cq;
691
692 opcode = ib_to_fw_opcode(wr->opcode);
693 if (opcode < 0)
694 return opcode;
695
696 PDBG("%s drain sq id %u\n", __func__, qhp->wq.sq.qid);
697 cqe.u.drain_cookie = wr->wr_id;
698 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
699 V_CQE_OPCODE(opcode) |
700 V_CQE_TYPE(1) |
701 V_CQE_SWCQE(1) |
702 V_CQE_DRAIN(1) |
703 V_CQE_QPID(qhp->wq.sq.qid));
704
705 spin_lock_irqsave(&schp->lock, flag);
706 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
707 cq->sw_queue[cq->sw_pidx] = cqe;
708 t4_swcq_produce(cq);
709 spin_unlock_irqrestore(&schp->lock, flag);
710
711 spin_lock_irqsave(&schp->comp_handler_lock, flag);
712 (*schp->ibcq.comp_handler)(&schp->ibcq,
713 schp->ibcq.cq_context);
714 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
715 return 0;
716 }
717
complete_sq_drain_wrs(struct c4iw_qp * qhp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)718 static int complete_sq_drain_wrs(struct c4iw_qp *qhp, const struct ib_send_wr *wr,
719 const struct ib_send_wr **bad_wr)
720 {
721 int ret = 0;
722
723 while (wr) {
724 ret = complete_sq_drain_wr(qhp, wr);
725 if (ret) {
726 *bad_wr = wr;
727 break;
728 }
729 wr = wr->next;
730 }
731 return ret;
732 }
733
complete_rq_drain_wr(struct c4iw_qp * qhp,const struct ib_recv_wr * wr)734 static void complete_rq_drain_wr(struct c4iw_qp *qhp,
735 const struct ib_recv_wr *wr)
736 {
737 struct t4_cqe cqe = {};
738 struct c4iw_cq *rchp;
739 unsigned long flag;
740 struct t4_cq *cq;
741
742 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
743 cq = &rchp->cq;
744
745 PDBG("%s drain rq id %u\n", __func__, qhp->wq.sq.qid);
746 cqe.u.drain_cookie = wr->wr_id;
747 cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
748 V_CQE_OPCODE(FW_RI_SEND) |
749 V_CQE_TYPE(0) |
750 V_CQE_SWCQE(1) |
751 V_CQE_DRAIN(1) |
752 V_CQE_QPID(qhp->wq.sq.qid));
753
754 spin_lock_irqsave(&rchp->lock, flag);
755 cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
756 cq->sw_queue[cq->sw_pidx] = cqe;
757 t4_swcq_produce(cq);
758 spin_unlock_irqrestore(&rchp->lock, flag);
759
760 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
761 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
762 rchp->ibcq.cq_context);
763 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
764 }
765
complete_rq_drain_wrs(struct c4iw_qp * qhp,const struct ib_recv_wr * wr)766 static void complete_rq_drain_wrs(struct c4iw_qp *qhp,
767 const struct ib_recv_wr *wr)
768 {
769 while (wr) {
770 complete_rq_drain_wr(qhp, wr);
771 wr = wr->next;
772 }
773 }
774
post_write_cmpl(struct c4iw_qp * qhp,const struct ib_send_wr * wr)775 static void post_write_cmpl(struct c4iw_qp *qhp, const struct ib_send_wr *wr)
776 {
777 bool send_signaled = (wr->next->send_flags & IB_SEND_SIGNALED) ||
778 qhp->sq_sig_all;
779 bool write_signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
780 qhp->sq_sig_all;
781 struct t4_swsqe *swsqe;
782 union t4_wr *wqe;
783 u16 write_wrid;
784 u8 len16;
785 u16 idx;
786
787 /*
788 * The sw_sq entries still look like a WRITE and a SEND and consume
789 * 2 slots. The FW WR, however, will be a single uber-WR.
790 */
791 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
792 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
793 build_rdma_write_cmpl(&qhp->wq.sq, &wqe->write_cmpl, wr, &len16);
794
795 /* WRITE swsqe */
796 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
797 swsqe->opcode = FW_RI_RDMA_WRITE;
798 swsqe->idx = qhp->wq.sq.pidx;
799 swsqe->complete = 0;
800 swsqe->signaled = write_signaled;
801 swsqe->flushed = 0;
802 swsqe->wr_id = wr->wr_id;
803
804 write_wrid = qhp->wq.sq.pidx;
805
806 /* just bump the sw_sq */
807 qhp->wq.sq.in_use++;
808 if (++qhp->wq.sq.pidx == qhp->wq.sq.size)
809 qhp->wq.sq.pidx = 0;
810
811 /* SEND_WITH_INV swsqe */
812 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
813 if (wr->next->opcode == IB_WR_SEND)
814 swsqe->opcode = FW_RI_SEND;
815 else
816 swsqe->opcode = FW_RI_SEND_WITH_INV;
817 swsqe->idx = qhp->wq.sq.pidx;
818 swsqe->complete = 0;
819 swsqe->signaled = send_signaled;
820 swsqe->flushed = 0;
821 swsqe->wr_id = wr->next->wr_id;
822
823 wqe->write_cmpl.flags_send = send_signaled ? FW_RI_COMPLETION_FLAG : 0;
824 wqe->write_cmpl.wrid_send = qhp->wq.sq.pidx;
825
826 init_wr_hdr(wqe, write_wrid, FW_RI_RDMA_WRITE_CMPL_WR,
827 write_signaled ? FW_RI_COMPLETION_FLAG : 0, len16);
828 t4_sq_produce(&qhp->wq, len16);
829 idx = DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
830
831 t4_ring_sq_db(&qhp->wq, idx, wqe, qhp->rhp->rdev.adap->iwt.wc_en);
832 return;
833 }
834
build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr * fr,const struct ib_reg_wr * wr,struct c4iw_mr * mhp,u8 * len16)835 static int build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
836 const struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16)
837 {
838 __be64 *p = (__be64 *)fr->pbl;
839
840 if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE)
841 return -EINVAL;
842
843 fr->r2 = cpu_to_be32(0);
844 fr->stag = cpu_to_be32(mhp->ibmr.rkey);
845
846 fr->tpte.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID |
847 V_FW_RI_TPTE_STAGKEY((mhp->ibmr.rkey & M_FW_RI_TPTE_STAGKEY)) |
848 V_FW_RI_TPTE_STAGSTATE(1) |
849 V_FW_RI_TPTE_STAGTYPE(FW_RI_STAG_NSMR) |
850 V_FW_RI_TPTE_PDID(mhp->attr.pdid));
851 fr->tpte.locread_to_qpid = cpu_to_be32(
852 V_FW_RI_TPTE_PERM(c4iw_ib_to_tpt_access(wr->access)) |
853 V_FW_RI_TPTE_ADDRTYPE(FW_RI_VA_BASED_TO) |
854 V_FW_RI_TPTE_PS(ilog2(wr->mr->page_size) - 12));
855 fr->tpte.nosnoop_pbladdr = cpu_to_be32(V_FW_RI_TPTE_PBLADDR(
856 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
857 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
858 fr->tpte.len_hi = cpu_to_be32(mhp->ibmr.length >> 32);
859 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length & 0xffffffff);
860 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
861 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
862
863 p[0] = cpu_to_be64((u64)mhp->mpl[0]);
864 p[1] = cpu_to_be64((u64)mhp->mpl[1]);
865
866 *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
867 return 0;
868 }
869
build_memreg(struct t4_sq * sq,union t4_wr * wqe,const struct ib_reg_wr * wr,struct c4iw_mr * mhp,u8 * len16,bool dsgl_supported)870 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
871 const struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
872 bool dsgl_supported)
873 {
874 struct fw_ri_immd *imdp;
875 __be64 *p;
876 int i;
877 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
878 int rem;
879
880 if (mhp->mpl_len > t4_max_fr_depth(&mhp->rhp->rdev, use_dsgl))
881 return -EINVAL;
882 if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE)
883 return -EINVAL;
884
885 wqe->fr.qpbinde_to_dcacpu = 0;
886 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
887 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
888 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
889 wqe->fr.len_hi = cpu_to_be32(mhp->ibmr.length >> 32);
890 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length & 0xffffffff);
891 wqe->fr.stag = cpu_to_be32(wr->key);
892 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
893 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
894
895 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
896 struct fw_ri_dsgl *sglp;
897
898 for (i = 0; i < mhp->mpl_len; i++)
899 mhp->mpl[i] =
900 (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
901
902 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
903 sglp->op = FW_RI_DATA_DSGL;
904 sglp->r1 = 0;
905 sglp->nsge = cpu_to_be16(1);
906 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
907 sglp->len0 = cpu_to_be32(pbllen);
908
909 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
910 } else {
911 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
912 imdp->op = FW_RI_DATA_IMMD;
913 imdp->r1 = 0;
914 imdp->r2 = 0;
915 imdp->immdlen = cpu_to_be32(pbllen);
916 p = (__be64 *)(imdp + 1);
917 rem = pbllen;
918 for (i = 0; i < mhp->mpl_len; i++) {
919 *p = cpu_to_be64((u64)mhp->mpl[i]);
920 rem -= sizeof(*p);
921 if (++p == (__be64 *)&sq->queue[sq->size])
922 p = (__be64 *)sq->queue;
923 }
924 BUG_ON(rem < 0);
925 while (rem) {
926 *p = 0;
927 rem -= sizeof(*p);
928 if (++p == (__be64 *)&sq->queue[sq->size])
929 p = (__be64 *)sq->queue;
930 }
931 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
932 + pbllen, 16);
933 }
934
935 return 0;
936 }
937
c4iw_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)938 int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
939 const struct ib_send_wr **bad_wr)
940 {
941 int err = 0;
942 u8 len16 = 0;
943 enum fw_wr_opcodes fw_opcode = 0;
944 enum fw_ri_wr_flags fw_flags;
945 struct c4iw_qp *qhp;
946 union t4_wr *wqe = NULL;
947 u32 num_wrs;
948 struct t4_swsqe *swsqe;
949 unsigned long flag;
950 u16 idx = 0;
951 struct c4iw_rdev *rdev;
952
953 qhp = to_c4iw_qp(ibqp);
954 rdev = &qhp->rhp->rdev;
955 if (__predict_false(c4iw_stopped(rdev)))
956 return -EIO;
957 spin_lock_irqsave(&qhp->lock, flag);
958
959 /*
960 * If the qp has been flushed, then just insert a special
961 * drain cqe.
962 */
963 if (qhp->wq.flushed) {
964 spin_unlock_irqrestore(&qhp->lock, flag);
965 err = complete_sq_drain_wrs(qhp, wr, bad_wr);
966 return err;
967 }
968 num_wrs = t4_sq_avail(&qhp->wq);
969 if (num_wrs == 0) {
970 spin_unlock_irqrestore(&qhp->lock, flag);
971 *bad_wr = wr;
972 return -ENOMEM;
973 }
974
975 /*
976 * Fastpath for NVMe-oF target WRITE + SEND_WITH_INV wr chain which is
977 * the response for small NVMEe-oF READ requests. If the chain is
978 * exactly a WRITE->SEND_WITH_INV or a WRITE->SEND and the sgl depths
979 * and lengths meet the requirements of the fw_ri_write_cmpl_wr work
980 * request, then build and post the write_cmpl WR. If any of the tests
981 * below are not true, then we continue on with the tradtional WRITE
982 * and SEND WRs.
983 */
984 if (qhp->rhp->rdev.adap->params.write_cmpl_support &&
985 chip_id(qhp->rhp->rdev.adap) >=
986 CHELSIO_T5 &&
987 wr && wr->next && !wr->next->next &&
988 wr->opcode == IB_WR_RDMA_WRITE &&
989 wr->sg_list[0].length && wr->num_sge <= T4_WRITE_CMPL_MAX_SGL &&
990 (wr->next->opcode == IB_WR_SEND ||
991 wr->next->opcode == IB_WR_SEND_WITH_INV) &&
992 wr->next->num_sge == 1 && num_wrs >= 2) {
993 post_write_cmpl(qhp, wr);
994 spin_unlock_irqrestore(&qhp->lock, flag);
995 return 0;
996 }
997
998 while (wr) {
999 if (num_wrs == 0) {
1000 err = -ENOMEM;
1001 *bad_wr = wr;
1002 break;
1003 }
1004 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
1005 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
1006
1007 fw_flags = 0;
1008 if (wr->send_flags & IB_SEND_SOLICITED)
1009 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
1010 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
1011 fw_flags |= FW_RI_COMPLETION_FLAG;
1012 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
1013 switch (wr->opcode) {
1014 case IB_WR_SEND_WITH_INV:
1015 case IB_WR_SEND:
1016 if (wr->send_flags & IB_SEND_FENCE)
1017 fw_flags |= FW_RI_READ_FENCE_FLAG;
1018 fw_opcode = FW_RI_SEND_WR;
1019 if (wr->opcode == IB_WR_SEND)
1020 swsqe->opcode = FW_RI_SEND;
1021 else
1022 swsqe->opcode = FW_RI_SEND_WITH_INV;
1023 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
1024 break;
1025 case IB_WR_RDMA_WRITE_WITH_IMM:
1026 if (unlikely(!qhp->rhp->rdev.adap->params.write_w_imm_support)) {
1027 err = -ENOSYS;
1028 break;
1029 }
1030 fw_flags |= FW_RI_RDMA_WRITE_WITH_IMMEDIATE;
1031 /*FALLTHROUGH*/
1032 case IB_WR_RDMA_WRITE:
1033 fw_opcode = FW_RI_RDMA_WRITE_WR;
1034 swsqe->opcode = FW_RI_RDMA_WRITE;
1035 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
1036 break;
1037 case IB_WR_RDMA_READ:
1038 case IB_WR_RDMA_READ_WITH_INV:
1039 fw_opcode = FW_RI_RDMA_READ_WR;
1040 swsqe->opcode = FW_RI_READ_REQ;
1041 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
1042 c4iw_invalidate_mr(qhp->rhp,
1043 wr->sg_list[0].lkey);
1044 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
1045 } else {
1046 fw_flags = 0;
1047 }
1048 err = build_rdma_read(wqe, wr, &len16);
1049 if (err)
1050 break;
1051 swsqe->read_len = wr->sg_list[0].length;
1052 if (!qhp->wq.sq.oldest_read)
1053 qhp->wq.sq.oldest_read = swsqe;
1054 break;
1055 case IB_WR_REG_MR: {
1056 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
1057
1058 swsqe->opcode = FW_RI_FAST_REGISTER;
1059 if (rdev->adap->params.fr_nsmr_tpte_wr_support &&
1060 !mhp->attr.state && mhp->mpl_len <= 2) {
1061 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
1062 err = build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
1063 mhp, &len16);
1064 } else {
1065 fw_opcode = FW_RI_FR_NSMR_WR;
1066 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
1067 mhp, &len16,
1068 rdev->adap->params.ulptx_memwrite_dsgl);
1069 }
1070 if (err)
1071 break;
1072 mhp->attr.state = 1;
1073 break;
1074 }
1075 case IB_WR_LOCAL_INV:
1076 if (wr->send_flags & IB_SEND_FENCE)
1077 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
1078 fw_opcode = FW_RI_INV_LSTAG_WR;
1079 swsqe->opcode = FW_RI_LOCAL_INV;
1080 err = build_inv_stag(wqe, wr, &len16);
1081 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
1082 break;
1083 default:
1084 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__,
1085 wr->opcode);
1086 err = -EINVAL;
1087 }
1088 if (err) {
1089 *bad_wr = wr;
1090 break;
1091 }
1092 swsqe->idx = qhp->wq.sq.pidx;
1093 swsqe->complete = 0;
1094 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
1095 qhp->sq_sig_all;
1096 swsqe->flushed = 0;
1097 swsqe->wr_id = wr->wr_id;
1098
1099 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
1100
1101 CTR5(KTR_IW_CXGBE,
1102 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u",
1103 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
1104 swsqe->opcode, swsqe->read_len);
1105 wr = wr->next;
1106 num_wrs--;
1107 t4_sq_produce(&qhp->wq, len16);
1108 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1109 }
1110
1111 t4_ring_sq_db(&qhp->wq, idx, wqe, rdev->adap->iwt.wc_en);
1112 spin_unlock_irqrestore(&qhp->lock, flag);
1113 return err;
1114 }
1115
c4iw_post_receive(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1116 int c4iw_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1117 const struct ib_recv_wr **bad_wr)
1118 {
1119 int err = 0;
1120 struct c4iw_qp *qhp;
1121 union t4_recv_wr *wqe = NULL;
1122 u32 num_wrs;
1123 u8 len16 = 0;
1124 unsigned long flag;
1125 u16 idx = 0;
1126
1127 qhp = to_c4iw_qp(ibqp);
1128 if (__predict_false(c4iw_stopped(&qhp->rhp->rdev)))
1129 return -EIO;
1130 spin_lock_irqsave(&qhp->lock, flag);
1131
1132 /*
1133 * If the qp has been flushed, then just insert a special
1134 * drain cqe.
1135 */
1136 if (qhp->wq.flushed) {
1137 spin_unlock_irqrestore(&qhp->lock, flag);
1138 complete_rq_drain_wrs(qhp, wr);
1139 return err;
1140 }
1141 num_wrs = t4_rq_avail(&qhp->wq);
1142 if (num_wrs == 0) {
1143 spin_unlock_irqrestore(&qhp->lock, flag);
1144 *bad_wr = wr;
1145 return -ENOMEM;
1146 }
1147 while (wr) {
1148 if (wr->num_sge > T4_MAX_RECV_SGE) {
1149 err = -EINVAL;
1150 *bad_wr = wr;
1151 break;
1152 }
1153 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1154 qhp->wq.rq.wq_pidx *
1155 T4_EQ_ENTRY_SIZE);
1156 if (num_wrs)
1157 err = build_rdma_recv(qhp, wqe, wr, &len16);
1158 else
1159 err = -ENOMEM;
1160 if (err) {
1161 *bad_wr = wr;
1162 break;
1163 }
1164
1165 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1166
1167 wqe->recv.opcode = FW_RI_RECV_WR;
1168 wqe->recv.r1 = 0;
1169 wqe->recv.wrid = qhp->wq.rq.pidx;
1170 wqe->recv.r2[0] = 0;
1171 wqe->recv.r2[1] = 0;
1172 wqe->recv.r2[2] = 0;
1173 wqe->recv.len16 = len16;
1174 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__,
1175 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
1176 t4_rq_produce(&qhp->wq, len16);
1177 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1178 wr = wr->next;
1179 num_wrs--;
1180 }
1181
1182 t4_ring_rq_db(&qhp->wq, idx, wqe, qhp->rhp->rdev.adap->iwt.wc_en);
1183 spin_unlock_irqrestore(&qhp->lock, flag);
1184 return err;
1185 }
1186
build_term_codes(struct t4_cqe * err_cqe,u8 * layer_type,u8 * ecode)1187 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1188 u8 *ecode)
1189 {
1190 int status;
1191 int tagged;
1192 int opcode;
1193 int rqtype;
1194 int send_inv;
1195
1196 if (!err_cqe) {
1197 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1198 *ecode = 0;
1199 return;
1200 }
1201
1202 status = CQE_STATUS(err_cqe);
1203 opcode = CQE_OPCODE(err_cqe);
1204 rqtype = RQ_TYPE(err_cqe);
1205 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1206 (opcode == FW_RI_SEND_WITH_SE_INV);
1207 tagged = (opcode == FW_RI_RDMA_WRITE) ||
1208 (rqtype && (opcode == FW_RI_READ_RESP));
1209
1210 switch (status) {
1211 case T4_ERR_STAG:
1212 if (send_inv) {
1213 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1214 *ecode = RDMAP_CANT_INV_STAG;
1215 } else {
1216 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1217 *ecode = RDMAP_INV_STAG;
1218 }
1219 break;
1220 case T4_ERR_PDID:
1221 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1222 if ((opcode == FW_RI_SEND_WITH_INV) ||
1223 (opcode == FW_RI_SEND_WITH_SE_INV))
1224 *ecode = RDMAP_CANT_INV_STAG;
1225 else
1226 *ecode = RDMAP_STAG_NOT_ASSOC;
1227 break;
1228 case T4_ERR_QPID:
1229 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1230 *ecode = RDMAP_STAG_NOT_ASSOC;
1231 break;
1232 case T4_ERR_ACCESS:
1233 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1234 *ecode = RDMAP_ACC_VIOL;
1235 break;
1236 case T4_ERR_WRAP:
1237 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1238 *ecode = RDMAP_TO_WRAP;
1239 break;
1240 case T4_ERR_BOUND:
1241 if (tagged) {
1242 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1243 *ecode = DDPT_BASE_BOUNDS;
1244 } else {
1245 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1246 *ecode = RDMAP_BASE_BOUNDS;
1247 }
1248 break;
1249 case T4_ERR_INVALIDATE_SHARED_MR:
1250 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1251 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1252 *ecode = RDMAP_CANT_INV_STAG;
1253 break;
1254 case T4_ERR_ECC:
1255 case T4_ERR_ECC_PSTAG:
1256 case T4_ERR_INTERNAL_ERR:
1257 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1258 *ecode = 0;
1259 break;
1260 case T4_ERR_OUT_OF_RQE:
1261 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1262 *ecode = DDPU_INV_MSN_NOBUF;
1263 break;
1264 case T4_ERR_PBL_ADDR_BOUND:
1265 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1266 *ecode = DDPT_BASE_BOUNDS;
1267 break;
1268 case T4_ERR_CRC:
1269 *layer_type = LAYER_MPA|DDP_LLP;
1270 *ecode = MPA_CRC_ERR;
1271 break;
1272 case T4_ERR_MARKER:
1273 *layer_type = LAYER_MPA|DDP_LLP;
1274 *ecode = MPA_MARKER_ERR;
1275 break;
1276 case T4_ERR_PDU_LEN_ERR:
1277 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1278 *ecode = DDPU_MSG_TOOBIG;
1279 break;
1280 case T4_ERR_DDP_VERSION:
1281 if (tagged) {
1282 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1283 *ecode = DDPT_INV_VERS;
1284 } else {
1285 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1286 *ecode = DDPU_INV_VERS;
1287 }
1288 break;
1289 case T4_ERR_RDMA_VERSION:
1290 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1291 *ecode = RDMAP_INV_VERS;
1292 break;
1293 case T4_ERR_OPCODE:
1294 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1295 *ecode = RDMAP_INV_OPCODE;
1296 break;
1297 case T4_ERR_DDP_QUEUE_NUM:
1298 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1299 *ecode = DDPU_INV_QN;
1300 break;
1301 case T4_ERR_MSN:
1302 case T4_ERR_MSN_GAP:
1303 case T4_ERR_MSN_RANGE:
1304 case T4_ERR_IRD_OVERFLOW:
1305 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1306 *ecode = DDPU_INV_MSN_RANGE;
1307 break;
1308 case T4_ERR_TBIT:
1309 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1310 *ecode = 0;
1311 break;
1312 case T4_ERR_MO:
1313 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1314 *ecode = DDPU_INV_MO;
1315 break;
1316 default:
1317 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1318 *ecode = 0;
1319 break;
1320 }
1321 }
1322
post_terminate(struct c4iw_qp * qhp,struct t4_cqe * err_cqe,gfp_t gfp)1323 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1324 gfp_t gfp)
1325 {
1326 int ret;
1327 struct fw_ri_wr *wqe;
1328 struct terminate_message *term;
1329 struct wrqe *wr;
1330 struct socket *so = qhp->ep->com.so;
1331 struct inpcb *inp = sotoinpcb(so);
1332 struct tcpcb *tp = intotcpcb(inp);
1333 struct toepcb *toep = tp->t_toe;
1334
1335 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp,
1336 qhp->wq.sq.qid, qhp->ep->hwtid);
1337
1338 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq);
1339 if (wr == NULL)
1340 return;
1341 wqe = wrtod(wr);
1342
1343 memset(wqe, 0, sizeof *wqe);
1344 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR));
1345 wqe->flowid_len16 = cpu_to_be32(
1346 V_FW_WR_FLOWID(qhp->ep->hwtid) |
1347 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1348
1349 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1350 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1351 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1352 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1353 term->layer_etype = qhp->attr.layer_etype;
1354 term->ecode = qhp->attr.ecode;
1355 } else
1356 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1357 ret = creds(toep, tp, sizeof(*wqe));
1358 if (ret) {
1359 free_wrqe(wr);
1360 return;
1361 }
1362 t4_wrq_tx(qhp->rhp->rdev.adap, wr);
1363 }
1364
1365 /* Assumes qhp lock is held. */
__flush_qp(struct c4iw_qp * qhp,struct c4iw_cq * rchp,struct c4iw_cq * schp)1366 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1367 struct c4iw_cq *schp)
1368 {
1369 int count;
1370 int rq_flushed, sq_flushed;
1371 unsigned long flag;
1372
1373 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp,
1374 schp);
1375
1376 /* locking hierarchy: cq lock first, then qp lock. */
1377 spin_lock_irqsave(&rchp->lock, flag);
1378 spin_lock(&qhp->lock);
1379
1380 if (qhp->wq.flushed) {
1381 spin_unlock(&qhp->lock);
1382 spin_unlock_irqrestore(&rchp->lock, flag);
1383 return;
1384 }
1385 qhp->wq.flushed = 1;
1386
1387 c4iw_flush_hw_cq(rchp, qhp);
1388 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1389 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1390 spin_unlock(&qhp->lock);
1391 spin_unlock_irqrestore(&rchp->lock, flag);
1392
1393 /* locking hierarchy: cq lock first, then qp lock. */
1394 spin_lock_irqsave(&schp->lock, flag);
1395 spin_lock(&qhp->lock);
1396 if (schp != rchp)
1397 c4iw_flush_hw_cq(schp, qhp);
1398 sq_flushed = c4iw_flush_sq(qhp);
1399 spin_unlock(&qhp->lock);
1400 spin_unlock_irqrestore(&schp->lock, flag);
1401
1402 if (schp == rchp) {
1403 if (t4_clear_cq_armed(&rchp->cq) &&
1404 (rq_flushed || sq_flushed)) {
1405 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1406 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1407 rchp->ibcq.cq_context);
1408 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1409 }
1410 } else {
1411 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1412 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1413 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1414 rchp->ibcq.cq_context);
1415 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1416 }
1417 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1418 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1419 (*schp->ibcq.comp_handler)(&schp->ibcq,
1420 schp->ibcq.cq_context);
1421 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1422 }
1423 }
1424 }
1425
flush_qp(struct c4iw_qp * qhp)1426 static void flush_qp(struct c4iw_qp *qhp)
1427 {
1428 struct c4iw_cq *rchp, *schp;
1429 unsigned long flag;
1430
1431 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1432 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1433
1434 t4_set_wq_in_error(&qhp->wq);
1435 if (qhp->ibqp.uobject) {
1436
1437 /* qhp->wq.flush is protected by qhp->mutex */
1438 if (qhp->wq.flushed)
1439 return;
1440
1441 qhp->wq.flushed = 1;
1442 t4_set_cq_in_error(&rchp->cq);
1443 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1444 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1445 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1446 if (schp != rchp) {
1447 t4_set_cq_in_error(&schp->cq);
1448 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1449 (*schp->ibcq.comp_handler)(&schp->ibcq,
1450 schp->ibcq.cq_context);
1451 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1452 }
1453 return;
1454 }
1455 __flush_qp(qhp, rchp, schp);
1456 }
1457
1458 static int
rdma_fini(struct c4iw_dev * rhp,struct c4iw_qp * qhp,struct c4iw_ep * ep)1459 rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep)
1460 {
1461 struct c4iw_rdev *rdev = &rhp->rdev;
1462 struct fw_ri_wr *wqe;
1463 int ret;
1464 struct wrqe *wr;
1465 struct socket *so = ep->com.so;
1466 struct tcpcb *tp = intotcpcb(sotoinpcb(so));
1467 struct toepcb *toep = tp->t_toe;
1468
1469 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__));
1470
1471 CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp,
1472 qhp->wq.sq.qid, ep, ep->hwtid);
1473
1474 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq);
1475 if (wr == NULL)
1476 return (0);
1477 wqe = wrtod(wr);
1478
1479 memset(wqe, 0, sizeof *wqe);
1480
1481 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL);
1482 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) |
1483 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1484 wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1485 wqe->u.fini.type = FW_RI_TYPE_FINI;
1486
1487 c4iw_init_wr_wait(ep->com.wr_waitp);
1488
1489 ret = creds(toep, tp, sizeof(*wqe));
1490 if (ret) {
1491 free_wrqe(wr);
1492 return ret;
1493 }
1494
1495 ret = c4iw_ref_send_wait(rdev, wr, ep->com.wr_waitp, ep->hwtid,
1496 qhp->wq.sq.qid, ep->com.so, __func__);
1497 return ret;
1498 }
1499
build_rtr_msg(u8 p2p_type,struct fw_ri_init * init)1500 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1501 {
1502 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type);
1503 memset(&init->u, 0, sizeof init->u);
1504 switch (p2p_type) {
1505 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1506 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1507 init->u.write.stag_sink = cpu_to_be32(1);
1508 init->u.write.to_sink = cpu_to_be64(1);
1509 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1510 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1511 sizeof(struct fw_ri_immd),
1512 16);
1513 break;
1514 case FW_RI_INIT_P2PTYPE_READ_REQ:
1515 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1516 init->u.read.stag_src = cpu_to_be32(1);
1517 init->u.read.to_src_lo = cpu_to_be32(1);
1518 init->u.read.stag_sink = cpu_to_be32(1);
1519 init->u.read.to_sink_lo = cpu_to_be32(1);
1520 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1521 break;
1522 }
1523 }
1524
1525 static int
creds(struct toepcb * toep,struct tcpcb * tp,size_t wrsize)1526 creds(struct toepcb *toep, struct tcpcb *tp, size_t wrsize)
1527 {
1528 struct ofld_tx_sdesc *txsd;
1529
1530 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize);
1531 INP_WLOCK(tptoinpcb(tp));
1532 if (tp->t_flags & TF_DISCONNECTED) {
1533 INP_WUNLOCK(tptoinpcb(tp));
1534 return (EINVAL);
1535 }
1536 txsd = &toep->txsd[toep->txsd_pidx];
1537 KASSERT(howmany(wrsize, 16) <= MAX_OFLD_TX_SDESC_CREDITS,
1538 ("%s: tx_credits %zu too large", __func__, howmany(wrsize, 16)));
1539 txsd->tx_credits = howmany(wrsize, 16);
1540 txsd->plen = 0;
1541 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0,
1542 ("%s: not enough credits (%d)", __func__, toep->tx_credits));
1543 toep->tx_credits -= txsd->tx_credits;
1544 if (__predict_false(++toep->txsd_pidx == toep->txsd_total))
1545 toep->txsd_pidx = 0;
1546 toep->txsd_avail--;
1547 INP_WUNLOCK(tptoinpcb(tp));
1548 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep ,
1549 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx);
1550 return (0);
1551 }
1552
rdma_init(struct c4iw_dev * rhp,struct c4iw_qp * qhp)1553 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1554 {
1555 struct fw_ri_wr *wqe;
1556 int ret;
1557 struct wrqe *wr;
1558 struct c4iw_ep *ep = qhp->ep;
1559 struct c4iw_rdev *rdev = &qhp->rhp->rdev;
1560 struct adapter *sc = rdev->adap;
1561 struct socket *so = ep->com.so;
1562 struct tcpcb *tp = intotcpcb(sotoinpcb(so));
1563 struct toepcb *toep = tp->t_toe;
1564
1565 CTR5(KTR_IW_CXGBE, "%s qhp %p qid 0x%x ep %p tid %u", __func__, qhp,
1566 qhp->wq.sq.qid, ep, ep->hwtid);
1567
1568 wr = alloc_wrqe(sizeof(*wqe), &toep->ofld_txq->wrq);
1569 if (wr == NULL)
1570 return (0);
1571 wqe = wrtod(wr);
1572 ret = alloc_ird(rhp, qhp->attr.max_ird);
1573 if (ret) {
1574 qhp->attr.max_ird = 0;
1575 free_wrqe(wr);
1576 return ret;
1577 }
1578
1579 memset(wqe, 0, sizeof *wqe);
1580
1581 wqe->op_compl = cpu_to_be32(
1582 V_FW_WR_OP(FW_RI_WR) |
1583 F_FW_WR_COMPL);
1584 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) |
1585 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1586
1587 wqe->cookie = (uintptr_t)ep->com.wr_waitp;
1588
1589 wqe->u.init.type = FW_RI_TYPE_INIT;
1590 wqe->u.init.mpareqbit_p2ptype =
1591 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1592 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1593 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1594 if (qhp->attr.mpa_attr.recv_marker_enabled)
1595 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1596 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1597 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1598 if (qhp->attr.mpa_attr.crc_enabled)
1599 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1600
1601 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1602 FW_RI_QP_RDMA_WRITE_ENABLE |
1603 FW_RI_QP_BIND_ENABLE;
1604 if (!qhp->ibqp.uobject)
1605 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1606 FW_RI_QP_STAG0_ENABLE;
1607 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1608 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1609 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1610 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1611 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1612 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1613 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1614 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1615 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1616 wqe->u.init.iss = cpu_to_be32(ep->snd_seq);
1617 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq);
1618 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1619 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1620 sc->vres.rq.start);
1621 if (qhp->attr.mpa_attr.initiator)
1622 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1623
1624 c4iw_init_wr_wait(ep->com.wr_waitp);
1625
1626 ret = creds(toep, tp, sizeof(*wqe));
1627 if (ret) {
1628 free_wrqe(wr);
1629 free_ird(rhp, qhp->attr.max_ird);
1630 return ret;
1631 }
1632
1633 ret = c4iw_ref_send_wait(rdev, wr, ep->com.wr_waitp, ep->hwtid,
1634 qhp->wq.sq.qid, ep->com.so, __func__);
1635
1636 toep->params.ulp_mode = ULP_MODE_RDMA;
1637 free_ird(rhp, qhp->attr.max_ird);
1638
1639 return ret;
1640 }
1641
c4iw_modify_qp(struct c4iw_dev * rhp,struct c4iw_qp * qhp,enum c4iw_qp_attr_mask mask,struct c4iw_qp_attributes * attrs,int internal)1642 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1643 enum c4iw_qp_attr_mask mask,
1644 struct c4iw_qp_attributes *attrs,
1645 int internal)
1646 {
1647 int ret = 0;
1648 struct c4iw_qp_attributes newattr = qhp->attr;
1649 int disconnect = 0;
1650 int terminate = 0;
1651 int abort = 0;
1652 int free = 0;
1653 struct c4iw_ep *ep = NULL;
1654
1655 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp,
1656 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep);
1657 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state,
1658 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1659
1660 mutex_lock(&qhp->mutex);
1661
1662 /* Process attr changes if in IDLE */
1663 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1664 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1665 ret = -EIO;
1666 goto out;
1667 }
1668 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1669 newattr.enable_rdma_read = attrs->enable_rdma_read;
1670 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1671 newattr.enable_rdma_write = attrs->enable_rdma_write;
1672 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1673 newattr.enable_bind = attrs->enable_bind;
1674 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1675 if (attrs->max_ord > c4iw_max_read_depth) {
1676 ret = -EINVAL;
1677 goto out;
1678 }
1679 newattr.max_ord = attrs->max_ord;
1680 }
1681 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1682 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1683 ret = -EINVAL;
1684 goto out;
1685 }
1686 newattr.max_ird = attrs->max_ird;
1687 }
1688 qhp->attr = newattr;
1689 }
1690
1691 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1692 goto out;
1693 if (qhp->attr.state == attrs->next_state)
1694 goto out;
1695
1696 /* Return EINPROGRESS if QP is already in transition state.
1697 * Eg: CLOSING->IDLE transition or *->ERROR transition.
1698 * This can happen while connection is switching(due to rdma_fini)
1699 * from iWARP/RDDP to TOE mode and any inflight RDMA RX data will
1700 * reach TOE driver -> TCP stack -> iWARP driver. In this way
1701 * iWARP driver keep receiving inflight RDMA RX data until socket
1702 * is closed or aborted. And if iWARP CM is in FPDU sate, then
1703 * it tries to put QP in TERM state and disconnects endpoint.
1704 * But as QP is already in transition state, this event is ignored.
1705 */
1706 if ((qhp->attr.state >= C4IW_QP_STATE_ERROR) &&
1707 (attrs->next_state == C4IW_QP_STATE_TERMINATE)) {
1708 ret = -EINPROGRESS;
1709 goto out;
1710 }
1711
1712 switch (qhp->attr.state) {
1713 case C4IW_QP_STATE_IDLE:
1714 switch (attrs->next_state) {
1715 case C4IW_QP_STATE_RTS:
1716 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1717 ret = -EINVAL;
1718 goto out;
1719 }
1720 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1721 ret = -EINVAL;
1722 goto out;
1723 }
1724 qhp->attr.mpa_attr = attrs->mpa_attr;
1725 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1726 qhp->ep = qhp->attr.llp_stream_handle;
1727 set_state(qhp, C4IW_QP_STATE_RTS);
1728
1729 /*
1730 * Ref the endpoint here and deref when we
1731 * disassociate the endpoint from the QP. This
1732 * happens in CLOSING->IDLE transition or *->ERROR
1733 * transition.
1734 */
1735 c4iw_get_ep(&qhp->ep->com);
1736 ret = rdma_init(rhp, qhp);
1737 if (ret)
1738 goto err;
1739 break;
1740 case C4IW_QP_STATE_ERROR:
1741 set_state(qhp, C4IW_QP_STATE_ERROR);
1742 flush_qp(qhp);
1743 break;
1744 default:
1745 ret = -EINVAL;
1746 goto out;
1747 }
1748 break;
1749 case C4IW_QP_STATE_RTS:
1750 switch (attrs->next_state) {
1751 case C4IW_QP_STATE_CLOSING:
1752 BUG_ON(kref_read(&qhp->ep->com.kref) < 2);
1753 t4_set_wq_in_error(&qhp->wq);
1754 set_state(qhp, C4IW_QP_STATE_CLOSING);
1755 ep = qhp->ep;
1756 if (!internal) {
1757 abort = 0;
1758 disconnect = 1;
1759 c4iw_get_ep(&qhp->ep->com);
1760 }
1761 ret = rdma_fini(rhp, qhp, ep);
1762 if (ret)
1763 goto err;
1764 break;
1765 case C4IW_QP_STATE_TERMINATE:
1766 t4_set_wq_in_error(&qhp->wq);
1767 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1768 qhp->attr.layer_etype = attrs->layer_etype;
1769 qhp->attr.ecode = attrs->ecode;
1770 ep = qhp->ep;
1771 if (!internal) {
1772 c4iw_get_ep(&qhp->ep->com);
1773 terminate = 1;
1774 disconnect = 1;
1775 } else {
1776 terminate = qhp->attr.send_term;
1777 ret = rdma_fini(rhp, qhp, ep);
1778 if (ret)
1779 goto err;
1780 }
1781 break;
1782 case C4IW_QP_STATE_ERROR:
1783 t4_set_wq_in_error(&qhp->wq);
1784 set_state(qhp, C4IW_QP_STATE_ERROR);
1785 if (!internal) {
1786 abort = 1;
1787 disconnect = 1;
1788 ep = qhp->ep;
1789 c4iw_get_ep(&qhp->ep->com);
1790 }
1791 goto err;
1792 break;
1793 default:
1794 ret = -EINVAL;
1795 goto out;
1796 }
1797 break;
1798 case C4IW_QP_STATE_CLOSING:
1799
1800 /*
1801 * Allow kernel users to move to ERROR for qp draining.
1802 */
1803 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1804 C4IW_QP_STATE_ERROR)) {
1805 ret = -EINVAL;
1806 goto out;
1807 }
1808 switch (attrs->next_state) {
1809 case C4IW_QP_STATE_IDLE:
1810 flush_qp(qhp);
1811 set_state(qhp, C4IW_QP_STATE_IDLE);
1812 qhp->attr.llp_stream_handle = NULL;
1813 c4iw_put_ep(&qhp->ep->com);
1814 qhp->ep = NULL;
1815 wake_up(&qhp->wait);
1816 break;
1817 case C4IW_QP_STATE_ERROR:
1818 goto err;
1819 default:
1820 ret = -EINVAL;
1821 goto err;
1822 }
1823 break;
1824 case C4IW_QP_STATE_ERROR:
1825 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1826 ret = -EINVAL;
1827 goto out;
1828 }
1829 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1830 ret = -EINVAL;
1831 goto out;
1832 }
1833 set_state(qhp, C4IW_QP_STATE_IDLE);
1834 break;
1835 case C4IW_QP_STATE_TERMINATE:
1836 if (!internal) {
1837 ret = -EINVAL;
1838 goto out;
1839 }
1840 goto err;
1841 break;
1842 default:
1843 printf("%s in a bad state %d\n",
1844 __func__, qhp->attr.state);
1845 ret = -EINVAL;
1846 goto err;
1847 break;
1848 }
1849 goto out;
1850 err:
1851 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__,
1852 qhp->ep, qhp->wq.sq.qid);
1853
1854 /* disassociate the LLP connection */
1855 qhp->attr.llp_stream_handle = NULL;
1856 if (!ep)
1857 ep = qhp->ep;
1858 qhp->ep = NULL;
1859 set_state(qhp, C4IW_QP_STATE_ERROR);
1860 free = 1;
1861 abort = 1;
1862 BUG_ON(!ep);
1863 flush_qp(qhp);
1864 wake_up(&qhp->wait);
1865 out:
1866 mutex_unlock(&qhp->mutex);
1867
1868 if (terminate)
1869 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1870
1871 /*
1872 * If disconnect is 1, then we need to initiate a disconnect
1873 * on the EP. This can be a normal close (RTS->CLOSING) or
1874 * an abnormal close (RTS/CLOSING->ERROR).
1875 */
1876 if (disconnect) {
1877 __c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1878 GFP_KERNEL);
1879 c4iw_put_ep(&ep->com);
1880 }
1881
1882 /*
1883 * If free is 1, then we've disassociated the EP from the QP
1884 * and we need to dereference the EP.
1885 */
1886 if (free)
1887 c4iw_put_ep(&ep->com);
1888 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state);
1889 return ret;
1890 }
1891
c4iw_destroy_qp(struct ib_qp * ib_qp,struct ib_udata * udata)1892 int c4iw_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
1893 {
1894 struct c4iw_ucontext *ucontext;
1895 struct c4iw_dev *rhp;
1896 struct c4iw_qp *qhp;
1897 struct c4iw_qp_attributes attrs;
1898
1899 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp);
1900 qhp = to_c4iw_qp(ib_qp);
1901 ucontext = qhp->ucontext;
1902 rhp = qhp->rhp;
1903
1904 attrs.next_state = C4IW_QP_STATE_ERROR;
1905 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1906 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1907 else
1908 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1909 wait_event(qhp->wait, !qhp->ep);
1910
1911 xa_lock_irq(&rhp->qps);
1912 __xa_erase(&rhp->qps, qhp->wq.sq.qid);
1913 xa_unlock_irq(&rhp->qps);
1914
1915 free_ird(rhp, qhp->attr.max_ird);
1916 c4iw_qp_rem_ref(ib_qp);
1917
1918 wait_for_completion(&qhp->qp_rel_comp);
1919
1920 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp,
1921 qhp->wq.sq.qid);
1922 CTR3(KTR_IW_CXGBE, "%s qhp %p ucontext %p", __func__,
1923 qhp, ucontext);
1924 destroy_qp(&rhp->rdev, &qhp->wq,
1925 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1926
1927 c4iw_put_wr_wait(qhp->wr_waitp);
1928
1929 kfree(qhp);
1930
1931 return 0;
1932 }
1933
1934 struct ib_qp *
c4iw_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * attrs,struct ib_udata * udata)1935 c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1936 struct ib_udata *udata)
1937 {
1938 struct c4iw_dev *rhp;
1939 struct c4iw_qp *qhp;
1940 struct c4iw_pd *php;
1941 struct c4iw_cq *schp;
1942 struct c4iw_cq *rchp;
1943 struct c4iw_create_qp_resp uresp;
1944 unsigned int sqsize, rqsize;
1945 struct c4iw_ucontext *ucontext = rdma_udata_to_drv_context(
1946 udata, struct c4iw_ucontext, ibucontext);
1947 int ret;
1948 struct c4iw_mm_entry *sq_key_mm = NULL, *rq_key_mm = NULL;
1949 struct c4iw_mm_entry *sq_db_key_mm = NULL, *rq_db_key_mm = NULL;
1950
1951 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd);
1952
1953 if (attrs->qp_type != IB_QPT_RC)
1954 return ERR_PTR(-EINVAL);
1955
1956 php = to_c4iw_pd(pd);
1957 rhp = php->rhp;
1958 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1959 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1960 if (!schp || !rchp)
1961 return ERR_PTR(-EINVAL);
1962
1963 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1964 return ERR_PTR(-EINVAL);
1965
1966 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1967 return ERR_PTR(-E2BIG);
1968 rqsize = attrs->cap.max_recv_wr + 1;
1969 if (rqsize < 8)
1970 rqsize = 8;
1971
1972 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1973 return ERR_PTR(-E2BIG);
1974 sqsize = attrs->cap.max_send_wr + 1;
1975 if (sqsize < 8)
1976 sqsize = 8;
1977
1978 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1979 if (!qhp)
1980 return ERR_PTR(-ENOMEM);
1981 qhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL);
1982 if (!qhp->wr_waitp) {
1983 ret = -ENOMEM;
1984 goto err_free_qhp;
1985 }
1986
1987 qhp->wq.sq.size = sqsize;
1988 qhp->wq.sq.memsize =
1989 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1990 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1991 qhp->wq.sq.flush_cidx = -1;
1992 qhp->wq.rq.size = rqsize;
1993 qhp->wq.rq.memsize =
1994 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1995 sizeof(*qhp->wq.rq.queue);
1996
1997 if (ucontext) {
1998 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1999 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
2000 }
2001
2002 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu",
2003 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
2004
2005 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
2006 ucontext ? &ucontext->uctx : &rhp->rdev.uctx,
2007 qhp->wr_waitp);
2008 if (ret)
2009 goto err_free_wr_wait;
2010
2011 attrs->cap.max_recv_wr = rqsize - 1;
2012 attrs->cap.max_send_wr = sqsize - 1;
2013 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
2014
2015 qhp->rhp = rhp;
2016 qhp->attr.pd = php->pdid;
2017 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
2018 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
2019 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
2020 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
2021 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
2022 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
2023 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
2024 qhp->attr.state = C4IW_QP_STATE_IDLE;
2025 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
2026 qhp->attr.enable_rdma_read = 1;
2027 qhp->attr.enable_rdma_write = 1;
2028 qhp->attr.enable_bind = 1;
2029 qhp->attr.max_ord = 0;
2030 qhp->attr.max_ird = 0;
2031 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
2032 spin_lock_init(&qhp->lock);
2033 mutex_init(&qhp->mutex);
2034 init_waitqueue_head(&qhp->wait);
2035 init_completion(&qhp->qp_rel_comp);
2036 refcount_set(&qhp->qp_refcnt, 1);
2037
2038 ret = xa_insert_irq(&rhp->qps, qhp->wq.sq.qid, qhp, GFP_KERNEL);
2039 if (ret)
2040 goto err_destroy_qp;
2041
2042 if (udata) {
2043 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
2044 if (!sq_key_mm) {
2045 ret = -ENOMEM;
2046 goto err_remove_handle;
2047 }
2048 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
2049 if (!rq_key_mm) {
2050 ret = -ENOMEM;
2051 goto err_free_sq_key;
2052 }
2053 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
2054 if (!sq_db_key_mm) {
2055 ret = -ENOMEM;
2056 goto err_free_rq_key;
2057 }
2058 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
2059 if (!rq_db_key_mm) {
2060 ret = -ENOMEM;
2061 goto err_free_sq_db_key;
2062 }
2063 uresp.flags = 0;
2064 if (rhp->rdev.adap->params.write_w_imm_support)
2065 uresp.flags |= C4IW_QPF_WRITE_W_IMM;
2066 uresp.qid_mask = rhp->rdev.qpmask;
2067 uresp.sqid = qhp->wq.sq.qid;
2068 uresp.sq_size = qhp->wq.sq.size;
2069 uresp.sq_memsize = qhp->wq.sq.memsize;
2070 uresp.rqid = qhp->wq.rq.qid;
2071 uresp.rq_size = qhp->wq.rq.size;
2072 uresp.rq_memsize = qhp->wq.rq.memsize;
2073 spin_lock(&ucontext->mmap_lock);
2074 uresp.ma_sync_key = 0;
2075 uresp.sq_key = ucontext->key;
2076 ucontext->key += PAGE_SIZE;
2077 uresp.rq_key = ucontext->key;
2078 ucontext->key += PAGE_SIZE;
2079 uresp.sq_db_gts_key = ucontext->key;
2080 ucontext->key += PAGE_SIZE;
2081 uresp.rq_db_gts_key = ucontext->key;
2082 ucontext->key += PAGE_SIZE;
2083 spin_unlock(&ucontext->mmap_lock);
2084 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
2085 if (ret)
2086 goto err_free_rq_db_key;
2087 sq_key_mm->key = uresp.sq_key;
2088 sq_key_mm->addr = qhp->wq.sq.phys_addr;
2089 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
2090 CTR4(KTR_IW_CXGBE, "%s sq_key_mm %x, %x, %d", __func__,
2091 sq_key_mm->key, sq_key_mm->addr,
2092 sq_key_mm->len);
2093 insert_mmap(ucontext, sq_key_mm);
2094 rq_key_mm->key = uresp.rq_key;
2095 rq_key_mm->addr = qhp->wq.rq.phys_addr;
2096 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
2097 CTR4(KTR_IW_CXGBE, "%s rq_key_mm %x, %x, %d", __func__,
2098 rq_key_mm->key, rq_key_mm->addr,
2099 rq_key_mm->len);
2100 insert_mmap(ucontext, rq_key_mm);
2101 sq_db_key_mm->key = uresp.sq_db_gts_key;
2102 sq_db_key_mm->addr = (u64)qhp->wq.sq.bar2_pa;
2103 sq_db_key_mm->len = PAGE_SIZE;
2104 CTR4(KTR_IW_CXGBE, "%s sq_db_key_mm %x, %x, %d", __func__,
2105 sq_db_key_mm->key, sq_db_key_mm->addr,
2106 sq_db_key_mm->len);
2107 insert_mmap(ucontext, sq_db_key_mm);
2108 rq_db_key_mm->key = uresp.rq_db_gts_key;
2109 rq_db_key_mm->addr = (u64)qhp->wq.rq.bar2_pa;
2110 rq_db_key_mm->len = PAGE_SIZE;
2111 CTR4(KTR_IW_CXGBE, "%s rq_db_key_mm %x, %x, %d", __func__,
2112 rq_db_key_mm->key, rq_db_key_mm->addr,
2113 rq_db_key_mm->len);
2114 insert_mmap(ucontext, rq_db_key_mm);
2115
2116 qhp->ucontext = ucontext;
2117 }
2118 qhp->ibqp.qp_num = qhp->wq.sq.qid;
2119
2120 CTR5(KTR_IW_CXGBE, "%s sq id %u size %u memsize %zu num_entries %u",
2121 __func__, qhp->wq.sq.qid,
2122 qhp->wq.sq.size, qhp->wq.sq.memsize, attrs->cap.max_send_wr);
2123 CTR5(KTR_IW_CXGBE, "%s rq id %u size %u memsize %zu num_entries %u",
2124 __func__, qhp->wq.rq.qid,
2125 qhp->wq.rq.size, qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
2126 return &qhp->ibqp;
2127 err_free_rq_db_key:
2128 kfree(rq_db_key_mm);
2129 err_free_sq_db_key:
2130 kfree(sq_db_key_mm);
2131 err_free_rq_key:
2132 kfree(rq_key_mm);
2133 err_free_sq_key:
2134 kfree(sq_key_mm);
2135 err_remove_handle:
2136 xa_erase_irq(&rhp->qps, qhp->wq.sq.qid);
2137 err_destroy_qp:
2138 destroy_qp(&rhp->rdev, &qhp->wq,
2139 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
2140 err_free_wr_wait:
2141 c4iw_put_wr_wait(qhp->wr_waitp);
2142 err_free_qhp:
2143 kfree(qhp);
2144 return ERR_PTR(ret);
2145 }
2146
c4iw_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)2147 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2148 int attr_mask, struct ib_udata *udata)
2149 {
2150 struct c4iw_dev *rhp;
2151 struct c4iw_qp *qhp;
2152 enum c4iw_qp_attr_mask mask = 0;
2153 struct c4iw_qp_attributes attrs;
2154
2155 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp);
2156
2157 /* iwarp does not support the RTR state */
2158 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
2159 attr_mask &= ~IB_QP_STATE;
2160
2161 /* Make sure we still have something left to do */
2162 if (!attr_mask)
2163 return 0;
2164
2165 memset(&attrs, 0, sizeof attrs);
2166 qhp = to_c4iw_qp(ibqp);
2167 rhp = qhp->rhp;
2168
2169 attrs.next_state = c4iw_convert_state(attr->qp_state);
2170 attrs.enable_rdma_read = (attr->qp_access_flags &
2171 IB_ACCESS_REMOTE_READ) ? 1 : 0;
2172 attrs.enable_rdma_write = (attr->qp_access_flags &
2173 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
2174 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
2175
2176
2177 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
2178 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
2179 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2180 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2181 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2182
2183 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2184 }
2185
c4iw_get_qp(struct ib_device * dev,int qpn)2186 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2187 {
2188 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn);
2189 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2190 }
2191
c4iw_ib_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_qp_init_attr * init_attr)2192 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2193 int attr_mask, struct ib_qp_init_attr *init_attr)
2194 {
2195 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2196
2197 memset(attr, 0, sizeof *attr);
2198 memset(init_attr, 0, sizeof *init_attr);
2199 attr->qp_state = to_ib_qp_state(qhp->attr.state);
2200 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2201 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2202 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2203 init_attr->cap.max_recv_sge = qhp->attr.rq_max_sges;
2204 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2205 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
2206 return 0;
2207 }
2208 #endif
2209