1 /*
2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term
3 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Description: Slow Path Operators (header)
29 */
30
31 #ifndef __BNXT_QPLIB_SP_H__
32 #define __BNXT_QPLIB_SP_H__
33
34 #include <rdma/ib_verbs.h>
35 #include "bnxt_re-abi.h"
36
37 #define BNXT_QPLIB_RESERVED_QP_WRS 128
38
39 /* Resource maximums reported by the firmware */
40 struct bnxt_qplib_dev_attr {
41 #define FW_VER_ARR_LEN 4
42 u8 fw_ver[FW_VER_ARR_LEN];
43 u16 max_sgid;
44 u16 max_mrw;
45 u32 max_qp;
46 #define BNXT_QPLIB_MAX_OUT_RD_ATOM 126
47 u32 max_qp_rd_atom;
48 u32 max_qp_init_rd_atom;
49 u32 max_qp_wqes;
50 u32 max_qp_sges;
51 u32 max_cq;
52 /* HW supports only 8K entries in PBL.
53 * So max CQEs that can be supported per CQ is 1M.
54 */
55 #define BNXT_QPLIB_MAX_CQ_WQES 0xfffff
56 u32 max_cq_wqes;
57 u32 max_cq_sges;
58 u32 max_mr;
59 u64 max_mr_size;
60 #define BNXT_QPLIB_MAX_PD (64 * 1024)
61 u32 max_pd;
62 u32 max_mw;
63 u32 max_raw_ethy_qp;
64 u32 max_ah;
65 u32 max_fmr;
66 u32 max_map_per_fmr;
67 u32 max_srq;
68 u32 max_srq_wqes;
69 u32 max_srq_sges;
70 u32 max_pkey;
71 u32 max_inline_data;
72 u32 l2_db_size;
73 u8 tqm_alloc_reqs[MAX_TQM_ALLOC_REQ];
74 u8 is_atomic;
75 u16 dev_cap_ext_flags2;
76 u16 dev_cap_flags;
77 u64 page_size_cap;
78 u32 max_dpi;
79 };
80
81 struct bnxt_qplib_pd {
82 u32 id;
83 };
84
85 struct bnxt_qplib_gid {
86 u8 data[16];
87 };
88
89 struct bnxt_qplib_gid_info {
90 struct bnxt_qplib_gid gid;
91 u16 vlan_id;
92 };
93
94 struct bnxt_qplib_ah {
95 struct bnxt_qplib_gid dgid;
96 struct bnxt_qplib_pd *pd;
97 u32 id;
98 u8 sgid_index;
99 u8 host_sgid_index; /* For Query AH if the hw table and SW table are differnt */
100 u8 traffic_class;
101 u32 flow_label;
102 u8 hop_limit;
103 u8 sl;
104 u8 dmac[6];
105 u16 vlan_id;
106 u8 nw_type;
107 u8 enable_cc;
108 };
109
110 struct bnxt_qplib_mrw {
111 struct bnxt_qplib_pd *pd;
112 int type;
113 u32 flags;
114 #define BNXT_QPLIB_FR_PMR 0x80000000
115 u32 lkey;
116 u32 rkey;
117 #define BNXT_QPLIB_RSVD_LKEY 0xFFFFFFFF
118 u64 va;
119 u64 total_size;
120 u32 npages;
121 u64 mr_handle;
122 struct bnxt_qplib_hwq hwq;
123 };
124
125 struct bnxt_qplib_mrinfo {
126 struct bnxt_qplib_mrw *mrw;
127 struct bnxt_qplib_sg_info sg;
128 u64 *ptes;
129 bool is_dma;
130 };
131
132 struct bnxt_qplib_frpl {
133 int max_pg_ptrs;
134 struct bnxt_qplib_hwq hwq;
135 };
136
137 struct bnxt_qplib_cc_param_ext {
138 u64 ext_mask;
139 u16 inact_th_hi;
140 u16 min_delta_cnp;
141 u16 init_cp;
142 u8 tr_update_mode;
143 u8 tr_update_cyls;
144 u8 fr_rtt;
145 u8 ai_rate_incr;
146 u16 rr_rtt_th;
147 u16 ar_cr_th;
148 u16 cr_min_th;
149 u8 bw_avg_weight;
150 u8 cr_factor;
151 u16 cr_th_max_cp;
152 u8 cp_bias_en;
153 u8 cp_bias;
154 u8 cnp_ecn;
155 u8 rtt_jitter_en;
156 u16 bytes_per_usec;
157 u16 cc_cr_reset_th;
158 u8 cr_width;
159 u8 min_quota;
160 u8 max_quota;
161 u8 abs_max_quota;
162 u16 tr_lb;
163 u8 cr_prob_fac;
164 u8 tr_prob_fac;
165 u16 fair_cr_th;
166 u8 red_div;
167 u8 cnp_ratio_th;
168 u16 ai_ext_rtt;
169 u8 exp_crcp_ratio;
170 u8 low_rate_en;
171 u16 cpcr_update_th;
172 u16 ai_rtt_th1;
173 u16 ai_rtt_th2;
174 u16 cf_rtt_th;
175 u16 sc_cr_th1; /* severe congestion cr threshold 1 */
176 u16 sc_cr_th2; /* severe congestion cr threshold 2 */
177 u32 l64B_per_rtt;
178 u8 cc_ack_bytes;
179 u16 reduce_cf_rtt_th;
180 };
181
182 struct bnxt_qplib_cc_param {
183 u8 alt_vlan_pcp;
184 u16 alt_tos_dscp;
185 #define BNXT_QPLIB_USER_DSCP_VALID 0x80
186 u8 cnp_dscp_user;
187 u8 roce_dscp_user;
188 u8 cc_mode;
189 u8 enable;
190 u16 inact_th;
191 u16 init_cr;
192 u16 init_tr;
193 u16 rtt;
194 u8 g;
195 u8 nph_per_state;
196 u8 time_pph;
197 u8 pkts_pph;
198 u8 tos_ecn;
199 u8 tos_dscp;
200 u8 qp1_tos_dscp;
201 u16 tcp_cp;
202 struct bnxt_qplib_cc_param_ext cc_ext;
203 u8 disable_prio_vlan_tx;
204 /* Mask used while programming the configfs values */
205 u32 mask;
206 /* Mask used while displaying the configfs values */
207 u32 cur_mask;
208 u8 roce_pri;
209 #define BNXT_QPLIB_CC_PARAM_MASK_VLAN_TX_DISABLE 0x40000
210 #define BNXT_QPLIB_CC_PARAM_MASK_ROCE_PRI 0x80000
211 /* prev value to clear dscp table */
212 u8 prev_roce_pri;
213 u8 prev_alt_vlan_pcp;
214 u8 prev_tos_dscp;
215 u16 prev_alt_tos_dscp;
216 /* To track if admin has enabled ECN explicitly */
217 u8 admin_enable;
218 };
219
220 struct bnxt_qplib_roce_stats {
221 u64 to_retransmits;
222 u64 seq_err_naks_rcvd;
223 /* seq_err_naks_rcvd is 64 b */
224 u64 max_retry_exceeded;
225 /* max_retry_exceeded is 64 b */
226 u64 rnr_naks_rcvd;
227 /* rnr_naks_rcvd is 64 b */
228 u64 missing_resp;
229 u64 unrecoverable_err;
230 /* unrecoverable_err is 64 b */
231 u64 bad_resp_err;
232 /* bad_resp_err is 64 b */
233 u64 local_qp_op_err;
234 /* local_qp_op_err is 64 b */
235 u64 local_protection_err;
236 /* local_protection_err is 64 b */
237 u64 mem_mgmt_op_err;
238 /* mem_mgmt_op_err is 64 b */
239 u64 remote_invalid_req_err;
240 /* remote_invalid_req_err is 64 b */
241 u64 remote_access_err;
242 /* remote_access_err is 64 b */
243 u64 remote_op_err;
244 /* remote_op_err is 64 b */
245 u64 dup_req;
246 /* dup_req is 64 b */
247 u64 res_exceed_max;
248 /* res_exceed_max is 64 b */
249 u64 res_length_mismatch;
250 /* res_length_mismatch is 64 b */
251 u64 res_exceeds_wqe;
252 /* res_exceeds_wqe is 64 b */
253 u64 res_opcode_err;
254 /* res_opcode_err is 64 b */
255 u64 res_rx_invalid_rkey;
256 /* res_rx_invalid_rkey is 64 b */
257 u64 res_rx_domain_err;
258 /* res_rx_domain_err is 64 b */
259 u64 res_rx_no_perm;
260 /* res_rx_no_perm is 64 b */
261 u64 res_rx_range_err;
262 /* res_rx_range_err is 64 b */
263 u64 res_tx_invalid_rkey;
264 /* res_tx_invalid_rkey is 64 b */
265 u64 res_tx_domain_err;
266 /* res_tx_domain_err is 64 b */
267 u64 res_tx_no_perm;
268 /* res_tx_no_perm is 64 b */
269 u64 res_tx_range_err;
270 /* res_tx_range_err is 64 b */
271 u64 res_irrq_oflow;
272 /* res_irrq_oflow is 64 b */
273 u64 res_unsup_opcode;
274 /* res_unsup_opcode is 64 b */
275 u64 res_unaligned_atomic;
276 /* res_unaligned_atomic is 64 b */
277 u64 res_rem_inv_err;
278 /* res_rem_inv_err is 64 b */
279 u64 res_mem_error;
280 /* res_mem_error is 64 b */
281 u64 res_srq_err;
282 /* res_srq_err is 64 b */
283 u64 res_cmp_err;
284 /* res_cmp_err is 64 b */
285 u64 res_invalid_dup_rkey;
286 /* res_invalid_dup_rkey is 64 b */
287 u64 res_wqe_format_err;
288 /* res_wqe_format_err is 64 b */
289 u64 res_cq_load_err;
290 /* res_cq_load_err is 64 b */
291 u64 res_srq_load_err;
292 /* res_srq_load_err is 64 b */
293 u64 res_tx_pci_err;
294 /* res_tx_pci_err is 64 b */
295 u64 res_rx_pci_err;
296 /* res_rx_pci_err is 64 b */
297 u64 res_oos_drop_count;
298 /* res_oos_drop_count */
299 u64 active_qp_count_p0;
300 /* port 0 active qps */
301 u64 active_qp_count_p1;
302 /* port 1 active qps */
303 u64 active_qp_count_p2;
304 /* port 2 active qps */
305 u64 active_qp_count_p3;
306 /* port 3 active qps */
307 };
308
309 struct bnxt_qplib_ext_stat {
310 u64 tx_atomic_req;
311 u64 tx_read_req;
312 u64 tx_read_res;
313 u64 tx_write_req;
314 u64 tx_send_req;
315 u64 tx_roce_pkts;
316 u64 tx_roce_bytes;
317 u64 rx_atomic_req;
318 u64 rx_read_req;
319 u64 rx_read_res;
320 u64 rx_write_req;
321 u64 rx_send_req;
322 u64 rx_roce_pkts;
323 u64 rx_roce_bytes;
324 u64 rx_roce_good_pkts;
325 u64 rx_roce_good_bytes;
326 u64 rx_out_of_buffer;
327 u64 rx_out_of_sequence;
328 u64 tx_cnp;
329 u64 rx_cnp;
330 u64 rx_ecn_marked;
331 u64 seq_err_naks_rcvd;
332 u64 rnr_naks_rcvd;
333 u64 missing_resp;
334 u64 to_retransmits;
335 u64 dup_req;
336 u64 rx_dcn_payload_cut;
337 u64 te_bypassed;
338 };
339
340 #define BNXT_QPLIB_ACCESS_LOCAL_WRITE (1 << 0)
341 #define BNXT_QPLIB_ACCESS_REMOTE_READ (1 << 1)
342 #define BNXT_QPLIB_ACCESS_REMOTE_WRITE (1 << 2)
343 #define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC (1 << 3)
344 #define BNXT_QPLIB_ACCESS_MW_BIND (1 << 4)
345 #define BNXT_QPLIB_ACCESS_ZERO_BASED (1 << 5)
346 #define BNXT_QPLIB_ACCESS_ON_DEMAND (1 << 6)
347
348 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res,
349 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index,
350 struct bnxt_qplib_gid *gid);
351 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
352 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update);
353 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
354 const union ib_gid *gid, const u8 *mac, u16 vlan_id,
355 bool update, u32 *index);
356 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
357 struct bnxt_qplib_gid *gid, u16 gid_idx, const u8 *smac);
358 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw);
359 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res);
360 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
361 bool block);
362 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
363 bool block);
364 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw);
365 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw,
366 bool block);
367 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res,
368 struct bnxt_qplib_mrinfo *mrinfo, bool block);
369 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr);
370 int bnxt_qplib_alloc_fast_reg_mr(struct bnxt_qplib_res *res,
371 struct bnxt_qplib_mrw *mr, int max);
372 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res,
373 struct bnxt_qplib_frpl *frpl, int max);
374 void bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res,
375 struct bnxt_qplib_frpl *frpl);
376 int bnxt_qplib_map_tc2cos(struct bnxt_qplib_res *res, u16 *cids);
377 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res,
378 struct bnxt_qplib_cc_param *cc_param);
379 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res,
380 struct bnxt_qplib_cc_param *cc_param);
381 int bnxt_qplib_set_link_aggr_mode(struct bnxt_qplib_res *res,
382 u8 aggr_mode, u8 member_port_map,
383 u8 active_port_map, bool aggr_en,
384 u32 stats_fw_id);
385 int bnxt_qplib_get_roce_error_stats(struct bnxt_qplib_rcfw *rcfw,
386 struct bnxt_qplib_roce_stats *stats,
387 struct bnxt_qplib_query_stats_info *sinfo);
388 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid,
389 struct bnxt_qplib_ext_stat *estat,
390 struct bnxt_qplib_query_stats_info *sinfo);
391 static inline void bnxt_re_set_max_gid(u16 *max_sgid);
392 bool ib_modify_qp_is_ok_compat(enum ib_qp_state cur_state, enum ib_qp_state next_state,
393 enum ib_qp_type type, enum ib_qp_attr_mask mask);
394
395 #define BNXT_MAX_SQ_SIZE 0xFFFF
396 #define BNXT_MAX_VAR_WQE_SIZE 512
397 #define BNXT_SGE_SIZE 16
398
399 #define BNXT_VAR_MAX_WQE 4352
400 #define BNXT_VAR_MAX_SLOT_ALIGN 256
401 #define BNXT_VAR_MAX_SGE 13
402 #define BNXT_RE_MAX_RQ_WQES 65536
403
404 #define BNXT_STATIC_MAX_SGE 6
405
406 /* PF defines */
407 #define BNXT_RE_MAX_QP_SUPPORTED(chip_gen) \
408 chip_gen == BNXT_RE_DEFAULT ? (64 * 1024) : 0
409
410 #define BNXT_RE_MAX_MRW_SUPPORTED(chip_gen) \
411 chip_gen == BNXT_RE_DEFAULT ? (256 * 1024) : 0
412
413 #define BNXT_RE_MAX_CQ_SUPPORTED(chip_gen) \
414 chip_gen == BNXT_RE_DEFAULT ? (64 * 1024) : 0
415
416 #define BNXT_RE_MAX_SRQ_SUPPORTED(chip_gen) \
417 chip_gen == BNXT_RE_DEFAULT ? (4 * 1024) : 0
418
419 #define BNXT_RE_MAX_AH_SUPPORTED(chip_gen) \
420 chip_gen == BNXT_RE_DEFAULT ? (64 * 1024) : 0
421
422 /* VF defines */
423 #define BNXT_RE_VF_MAX_QP_SUPPORTED(chip_gen) \
424 chip_gen == BNXT_RE_DEFAULT ? (6 * 1024) : 0
425
426 #define BNXT_RE_VF_MAX_MRW_SUPPORTED(chip_gen) \
427 chip_gen == BNXT_RE_DEFAULT ? (6 * 1024) : 0
428
429 #define BNXT_RE_VF_MAX_CQ_SUPPORTED(chip_gen) \
430 chip_gen == BNXT_RE_DEFAULT ? (6 * 1024) : 0
431
432 #define BNXT_RE_VF_MAX_SRQ_SUPPORTED(chip_gen) \
433 chip_gen == BNXT_RE_DEFAULT ? (4 * 1024) : 0
434
bnxt_re_set_max_gid(u16 * max_sgid)435 static inline void bnxt_re_set_max_gid(u16 *max_sgid)
436 {
437 *max_sgid = max_t(u32, 256, *max_sgid);
438 *max_sgid = min_t(u32, 256, *max_sgid);
439 }
440
441 #endif
442