1 //===-- RegisterContextPOSIXCore_arm64.cpp --------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "RegisterContextPOSIXCore_arm64.h"
10 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
11
12 #include "Plugins/Process/Utility/AuxVector.h"
13 #include "Plugins/Process/Utility/RegisterFlagsDetector_arm64.h"
14 #include "Plugins/Process/elf-core/ProcessElfCore.h"
15 #include "Plugins/Process/elf-core/RegisterUtilities.h"
16 #include "lldb/Target/Thread.h"
17 #include "lldb/Utility/RegisterValue.h"
18
19 #include <memory>
20
21 using namespace lldb_private;
22
23 std::unique_ptr<RegisterContextCorePOSIX_arm64>
Create(Thread & thread,const ArchSpec & arch,const DataExtractor & gpregset,llvm::ArrayRef<CoreNote> notes)24 RegisterContextCorePOSIX_arm64::Create(Thread &thread, const ArchSpec &arch,
25 const DataExtractor &gpregset,
26 llvm::ArrayRef<CoreNote> notes) {
27 Flags opt_regsets = RegisterInfoPOSIX_arm64::eRegsetMaskDefault;
28
29 DataExtractor ssve_data =
30 getRegset(notes, arch.GetTriple(), AARCH64_SSVE_Desc);
31 if (ssve_data.GetByteSize() >= sizeof(sve::user_sve_header))
32 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSSVE);
33
34 DataExtractor sve_data = getRegset(notes, arch.GetTriple(), AARCH64_SVE_Desc);
35 if (sve_data.GetByteSize() >= sizeof(sve::user_sve_header))
36 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSVE);
37
38 // Pointer Authentication register set data is based on struct
39 // user_pac_mask declared in ptrace.h. See reference implementation
40 // in Linux kernel source at arch/arm64/include/uapi/asm/ptrace.h.
41 DataExtractor pac_data = getRegset(notes, arch.GetTriple(), AARCH64_PAC_Desc);
42 if (pac_data.GetByteSize() >= sizeof(uint64_t) * 2)
43 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPAuth);
44
45 DataExtractor tls_data = getRegset(notes, arch.GetTriple(), AARCH64_TLS_Desc);
46 // A valid note will always contain at least one register, "tpidr". It may
47 // expand in future.
48 if (tls_data.GetByteSize() >= sizeof(uint64_t))
49 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskTLS);
50
51 DataExtractor za_data = getRegset(notes, arch.GetTriple(), AARCH64_ZA_Desc);
52 // Nothing if ZA is not present, just the header if it is disabled.
53 if (za_data.GetByteSize() >= sizeof(sve::user_za_header))
54 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskZA);
55
56 DataExtractor mte_data = getRegset(notes, arch.GetTriple(), AARCH64_MTE_Desc);
57 if (mte_data.GetByteSize() >= sizeof(uint64_t))
58 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskMTE);
59
60 DataExtractor zt_data = getRegset(notes, arch.GetTriple(), AARCH64_ZT_Desc);
61 // Although ZT0 can be in a disabled state like ZA can, the kernel reports
62 // its content as 0s in that state. Therefore even a disabled ZT0 will have
63 // a note containing those 0s. ZT0 is a 512 bit / 64 byte register.
64 if (zt_data.GetByteSize() >= 64)
65 opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskZT);
66
67 auto register_info_up =
68 std::make_unique<RegisterInfoPOSIX_arm64>(arch, opt_regsets);
69 return std::unique_ptr<RegisterContextCorePOSIX_arm64>(
70 new RegisterContextCorePOSIX_arm64(thread, std::move(register_info_up),
71 gpregset, notes));
72 }
73
RegisterContextCorePOSIX_arm64(Thread & thread,std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,const DataExtractor & gpregset,llvm::ArrayRef<CoreNote> notes)74 RegisterContextCorePOSIX_arm64::RegisterContextCorePOSIX_arm64(
75 Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
76 const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
77 : RegisterContextPOSIX_arm64(thread, std::move(register_info)) {
78 ::memset(&m_sme_pseudo_regs, 0, sizeof(m_sme_pseudo_regs));
79
80 ProcessElfCore *process =
81 static_cast<ProcessElfCore *>(thread.GetProcess().get());
82 llvm::Triple::OSType os = process->GetArchitecture().GetTriple().getOS();
83 if ((os == llvm::Triple::Linux) || (os == llvm::Triple::FreeBSD)) {
84 AuxVector aux_vec(process->GetAuxvData());
85 std::optional<uint64_t> auxv_at_hwcap = aux_vec.GetAuxValue(
86 os == llvm::Triple::FreeBSD ? AuxVector::AUXV_FREEBSD_AT_HWCAP
87 : AuxVector::AUXV_AT_HWCAP);
88 std::optional<uint64_t> auxv_at_hwcap2 =
89 aux_vec.GetAuxValue(AuxVector::AUXV_AT_HWCAP2);
90
91 m_register_flags_detector.DetectFields(auxv_at_hwcap.value_or(0),
92 auxv_at_hwcap2.value_or(0));
93 m_register_flags_detector.UpdateRegisterInfo(GetRegisterInfo(),
94 GetRegisterCount());
95 }
96
97 m_gpr_data.SetData(std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
98 gpregset.GetByteSize()));
99 m_gpr_data.SetByteOrder(gpregset.GetByteOrder());
100
101 const llvm::Triple &target_triple =
102 m_register_info_up->GetTargetArchitecture().GetTriple();
103 m_fpr_data = getRegset(notes, target_triple, FPR_Desc);
104
105 if (m_register_info_up->IsSSVEPresent()) {
106 m_sve_data = getRegset(notes, target_triple, AARCH64_SSVE_Desc);
107 lldb::offset_t flags_offset = 12;
108 uint16_t flags = m_sve_data.GetU32(&flags_offset);
109 if ((flags & sve::ptrace_regs_mask) == sve::ptrace_regs_sve)
110 m_sve_state = SVEState::Streaming;
111 }
112
113 if (m_sve_state != SVEState::Streaming && m_register_info_up->IsSVEPresent())
114 m_sve_data = getRegset(notes, target_triple, AARCH64_SVE_Desc);
115
116 if (m_register_info_up->IsPAuthPresent())
117 m_pac_data = getRegset(notes, target_triple, AARCH64_PAC_Desc);
118
119 if (m_register_info_up->IsTLSPresent())
120 m_tls_data = getRegset(notes, target_triple, AARCH64_TLS_Desc);
121
122 if (m_register_info_up->IsZAPresent())
123 m_za_data = getRegset(notes, target_triple, AARCH64_ZA_Desc);
124
125 if (m_register_info_up->IsMTEPresent())
126 m_mte_data = getRegset(notes, target_triple, AARCH64_MTE_Desc);
127
128 if (m_register_info_up->IsZTPresent())
129 m_zt_data = getRegset(notes, target_triple, AARCH64_ZT_Desc);
130
131 ConfigureRegisterContext();
132 }
133
134 RegisterContextCorePOSIX_arm64::~RegisterContextCorePOSIX_arm64() = default;
135
ReadGPR()136 bool RegisterContextCorePOSIX_arm64::ReadGPR() { return true; }
137
ReadFPR()138 bool RegisterContextCorePOSIX_arm64::ReadFPR() { return false; }
139
WriteGPR()140 bool RegisterContextCorePOSIX_arm64::WriteGPR() {
141 assert(0);
142 return false;
143 }
144
WriteFPR()145 bool RegisterContextCorePOSIX_arm64::WriteFPR() {
146 assert(0);
147 return false;
148 }
149
GetSVEBuffer(uint64_t offset)150 const uint8_t *RegisterContextCorePOSIX_arm64::GetSVEBuffer(uint64_t offset) {
151 return m_sve_data.GetDataStart() + offset;
152 }
153
ConfigureRegisterContext()154 void RegisterContextCorePOSIX_arm64::ConfigureRegisterContext() {
155 if (m_sve_data.GetByteSize() > sizeof(sve::user_sve_header)) {
156 uint64_t sve_header_field_offset = 8;
157 m_sve_vector_length = m_sve_data.GetU16(&sve_header_field_offset);
158
159 if (m_sve_state != SVEState::Streaming) {
160 sve_header_field_offset = 12;
161 uint16_t sve_header_flags_field =
162 m_sve_data.GetU16(&sve_header_field_offset);
163 if ((sve_header_flags_field & sve::ptrace_regs_mask) ==
164 sve::ptrace_regs_fpsimd)
165 m_sve_state = SVEState::FPSIMD;
166 else if ((sve_header_flags_field & sve::ptrace_regs_mask) ==
167 sve::ptrace_regs_sve)
168 m_sve_state = SVEState::Full;
169 }
170
171 if (!sve::vl_valid(m_sve_vector_length)) {
172 m_sve_state = SVEState::Disabled;
173 m_sve_vector_length = 0;
174 }
175 } else
176 m_sve_state = SVEState::Disabled;
177
178 if (m_sve_state != SVEState::Disabled)
179 m_register_info_up->ConfigureVectorLengthSVE(
180 sve::vq_from_vl(m_sve_vector_length));
181
182 if (m_sve_state == SVEState::Streaming)
183 m_sme_pseudo_regs.ctrl_reg |= 1;
184
185 if (m_za_data.GetByteSize() >= sizeof(sve::user_za_header)) {
186 lldb::offset_t vlen_offset = 8;
187 uint16_t svl = m_za_data.GetU16(&vlen_offset);
188 m_sme_pseudo_regs.svg_reg = svl / 8;
189 m_register_info_up->ConfigureVectorLengthZA(svl / 16);
190
191 // If there is register data then ZA is active. The size of the note may be
192 // misleading here so we use the size field of the embedded header.
193 lldb::offset_t size_offset = 0;
194 uint32_t size = m_za_data.GetU32(&size_offset);
195 if (size > sizeof(sve::user_za_header))
196 m_sme_pseudo_regs.ctrl_reg |= 1 << 1;
197 }
198 }
199
CalculateSVEOffset(const RegisterInfo * reg_info)200 uint32_t RegisterContextCorePOSIX_arm64::CalculateSVEOffset(
201 const RegisterInfo *reg_info) {
202 // Start of Z0 data is after GPRs plus 8 bytes of vg register
203 uint32_t sve_reg_offset = LLDB_INVALID_INDEX32;
204 if (m_sve_state == SVEState::FPSIMD) {
205 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
206 sve_reg_offset = sve::ptrace_fpsimd_offset + (reg - GetRegNumSVEZ0()) * 16;
207 } else if (m_sve_state == SVEState::Full ||
208 m_sve_state == SVEState::Streaming) {
209 uint32_t sve_z0_offset = GetGPRSize() + 16;
210 sve_reg_offset =
211 sve::SigRegsOffset() + reg_info->byte_offset - sve_z0_offset;
212 }
213
214 return sve_reg_offset;
215 }
216
ReadRegister(const RegisterInfo * reg_info,RegisterValue & value)217 bool RegisterContextCorePOSIX_arm64::ReadRegister(const RegisterInfo *reg_info,
218 RegisterValue &value) {
219 Status error;
220 lldb::offset_t offset;
221
222 offset = reg_info->byte_offset;
223 if (offset + reg_info->byte_size <= GetGPRSize()) {
224 value.SetFromMemoryData(*reg_info, m_gpr_data.GetDataStart() + offset,
225 reg_info->byte_size, lldb::eByteOrderLittle, error);
226 return error.Success();
227 }
228
229 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
230 if (reg == LLDB_INVALID_REGNUM)
231 return false;
232
233 if (IsFPR(reg)) {
234 if (m_sve_state == SVEState::Disabled) {
235 // SVE is disabled take legacy route for FPU register access
236 offset -= GetGPRSize();
237 if (offset < m_fpr_data.GetByteSize()) {
238 value.SetFromMemoryData(*reg_info, m_fpr_data.GetDataStart() + offset,
239 reg_info->byte_size, lldb::eByteOrderLittle,
240 error);
241 return error.Success();
242 }
243 } else {
244 // FPSR and FPCR will be located right after Z registers in
245 // SVEState::FPSIMD while in SVEState::Full/SVEState::Streaming they will
246 // be located at the end of register data after an alignment correction
247 // based on currently selected vector length.
248 uint32_t sve_reg_num = LLDB_INVALID_REGNUM;
249 if (reg == GetRegNumFPSR()) {
250 sve_reg_num = reg;
251 if (m_sve_state == SVEState::Full || m_sve_state == SVEState::Streaming)
252 offset = sve::PTraceFPSROffset(sve::vq_from_vl(m_sve_vector_length));
253 else if (m_sve_state == SVEState::FPSIMD)
254 offset = sve::ptrace_fpsimd_offset + (32 * 16);
255 } else if (reg == GetRegNumFPCR()) {
256 sve_reg_num = reg;
257 if (m_sve_state == SVEState::Full || m_sve_state == SVEState::Streaming)
258 offset = sve::PTraceFPCROffset(sve::vq_from_vl(m_sve_vector_length));
259 else if (m_sve_state == SVEState::FPSIMD)
260 offset = sve::ptrace_fpsimd_offset + (32 * 16) + 4;
261 } else {
262 // Extract SVE Z register value register number for this reg_info
263 if (reg_info->value_regs &&
264 reg_info->value_regs[0] != LLDB_INVALID_REGNUM)
265 sve_reg_num = reg_info->value_regs[0];
266 offset = CalculateSVEOffset(GetRegisterInfoAtIndex(sve_reg_num));
267 }
268
269 assert(sve_reg_num != LLDB_INVALID_REGNUM);
270 assert(offset < m_sve_data.GetByteSize());
271 value.SetFromMemoryData(*reg_info, GetSVEBuffer(offset),
272 reg_info->byte_size, lldb::eByteOrderLittle,
273 error);
274 }
275 } else if (IsSVE(reg)) {
276 if (IsSVEVG(reg)) {
277 value = GetSVERegVG();
278 return true;
279 }
280
281 switch (m_sve_state) {
282 case SVEState::FPSIMD: {
283 // In FPSIMD state SVE payload mirrors legacy fpsimd struct and so just
284 // copy 16 bytes of v register to the start of z register. All other
285 // SVE register will be set to zero.
286 uint64_t byte_size = 1;
287 uint8_t zeros = 0;
288 const uint8_t *src = &zeros;
289 if (IsSVEZ(reg)) {
290 byte_size = 16;
291 offset = CalculateSVEOffset(reg_info);
292 assert(offset < m_sve_data.GetByteSize());
293 src = GetSVEBuffer(offset);
294 }
295 value.SetFromMemoryData(*reg_info, src, byte_size, lldb::eByteOrderLittle,
296 error);
297 } break;
298 case SVEState::Full:
299 case SVEState::Streaming:
300 offset = CalculateSVEOffset(reg_info);
301 assert(offset < m_sve_data.GetByteSize());
302 value.SetFromMemoryData(*reg_info, GetSVEBuffer(offset),
303 reg_info->byte_size, lldb::eByteOrderLittle,
304 error);
305 break;
306 case SVEState::Disabled:
307 default:
308 return false;
309 }
310 } else if (IsPAuth(reg)) {
311 offset = reg_info->byte_offset - m_register_info_up->GetPAuthOffset();
312 assert(offset < m_pac_data.GetByteSize());
313 value.SetFromMemoryData(*reg_info, m_pac_data.GetDataStart() + offset,
314 reg_info->byte_size, lldb::eByteOrderLittle, error);
315 } else if (IsTLS(reg)) {
316 offset = reg_info->byte_offset - m_register_info_up->GetTLSOffset();
317 assert(offset < m_tls_data.GetByteSize());
318 value.SetFromMemoryData(*reg_info, m_tls_data.GetDataStart() + offset,
319 reg_info->byte_size, lldb::eByteOrderLittle, error);
320 } else if (IsMTE(reg)) {
321 offset = reg_info->byte_offset - m_register_info_up->GetMTEOffset();
322 assert(offset < m_mte_data.GetByteSize());
323 value.SetFromMemoryData(*reg_info, m_mte_data.GetDataStart() + offset,
324 reg_info->byte_size, lldb::eByteOrderLittle, error);
325 } else if (IsSME(reg)) {
326 // If you had SME in the process, active or otherwise, there will at least
327 // be a ZA header. No header, no SME at all.
328 if (m_za_data.GetByteSize() < sizeof(sve::user_za_header))
329 return false;
330
331 if (m_register_info_up->IsSMERegZA(reg)) {
332 // Don't use the size of the note to tell whether ZA is enabled. There may
333 // be non-register padding data after the header. Use the embedded
334 // header's size field instead.
335 lldb::offset_t size_offset = 0;
336 uint32_t size = m_za_data.GetU32(&size_offset);
337 bool za_enabled = size > sizeof(sve::user_za_header);
338
339 size_t za_note_size = m_za_data.GetByteSize();
340 // For a disabled ZA we fake a value of all 0s.
341 if (!za_enabled) {
342 uint64_t svl = m_sme_pseudo_regs.svg_reg * 8;
343 za_note_size = sizeof(sve::user_za_header) + (svl * svl);
344 }
345
346 const uint8_t *src = nullptr;
347 std::vector<uint8_t> disabled_za_data;
348
349 if (za_enabled)
350 src = m_za_data.GetDataStart();
351 else {
352 disabled_za_data.resize(za_note_size);
353 std::fill(disabled_za_data.begin(), disabled_za_data.end(), 0);
354 src = disabled_za_data.data();
355 }
356
357 value.SetFromMemoryData(*reg_info, src + sizeof(sve::user_za_header),
358 reg_info->byte_size, lldb::eByteOrderLittle,
359 error);
360 } else if (m_register_info_up->IsSMERegZT(reg)) {
361 value.SetFromMemoryData(*reg_info, m_zt_data.GetDataStart(),
362 reg_info->byte_size, lldb::eByteOrderLittle,
363 error);
364 } else {
365 offset = reg_info->byte_offset - m_register_info_up->GetSMEOffset();
366 assert(offset < sizeof(m_sme_pseudo_regs));
367 // Host endian since these values are derived instead of being read from a
368 // core file note.
369 value.SetFromMemoryData(
370 *reg_info, reinterpret_cast<uint8_t *>(&m_sme_pseudo_regs) + offset,
371 reg_info->byte_size, lldb_private::endian::InlHostByteOrder(), error);
372 }
373 } else
374 return false;
375
376 return error.Success();
377 }
378
ReadAllRegisterValues(lldb::WritableDataBufferSP & data_sp)379 bool RegisterContextCorePOSIX_arm64::ReadAllRegisterValues(
380 lldb::WritableDataBufferSP &data_sp) {
381 return false;
382 }
383
WriteRegister(const RegisterInfo * reg_info,const RegisterValue & value)384 bool RegisterContextCorePOSIX_arm64::WriteRegister(const RegisterInfo *reg_info,
385 const RegisterValue &value) {
386 return false;
387 }
388
WriteAllRegisterValues(const lldb::DataBufferSP & data_sp)389 bool RegisterContextCorePOSIX_arm64::WriteAllRegisterValues(
390 const lldb::DataBufferSP &data_sp) {
391 return false;
392 }
393
HardwareSingleStep(bool enable)394 bool RegisterContextCorePOSIX_arm64::HardwareSingleStep(bool enable) {
395 return false;
396 }
397