1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/firmware/qcom,scm.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 power-domains = <&cpu_pd0>; 52 power-domain-names = "psci"; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 next-level-cache = <&l2_0>; 55 capacity-dmips-mhz = <1024>; 56 dynamic-power-coefficient = <100>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 59 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 60 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 61 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 62 l2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&l3_0>; 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo"; 78 reg = <0x0 0x100>; 79 enable-method = "psci"; 80 power-domains = <&cpu_pd1>; 81 power-domain-names = "psci"; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 next-level-cache = <&l2_1>; 84 capacity-dmips-mhz = <1024>; 85 dynamic-power-coefficient = <100>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 88 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 89 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 90 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 91 l2_1: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "qcom,kryo"; 102 reg = <0x0 0x200>; 103 enable-method = "psci"; 104 power-domains = <&cpu_pd2>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 next-level-cache = <&l2_2>; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 112 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 113 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 114 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 115 l2_2: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 next-level-cache = <&l3_0>; 120 }; 121 }; 122 123 cpu3: cpu@300 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo"; 126 reg = <0x0 0x300>; 127 enable-method = "psci"; 128 power-domains = <&cpu_pd3>; 129 power-domain-names = "psci"; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 next-level-cache = <&l2_3>; 132 capacity-dmips-mhz = <1024>; 133 dynamic-power-coefficient = <100>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 137 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 138 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 139 l2_3: l2-cache { 140 compatible = "cache"; 141 cache-level = <2>; 142 cache-unified; 143 next-level-cache = <&l3_0>; 144 }; 145 }; 146 147 cpu4: cpu@10000 { 148 device_type = "cpu"; 149 compatible = "qcom,kryo"; 150 reg = <0x0 0x10000>; 151 enable-method = "psci"; 152 power-domains = <&cpu_pd4>; 153 power-domain-names = "psci"; 154 qcom,freq-domain = <&cpufreq_hw 1>; 155 next-level-cache = <&l2_4>; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <100>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 161 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 162 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 163 l2_4: l2-cache { 164 compatible = "cache"; 165 cache-level = <2>; 166 cache-unified; 167 next-level-cache = <&l3_1>; 168 l3_1: l3-cache { 169 compatible = "cache"; 170 cache-level = <3>; 171 cache-unified; 172 }; 173 174 }; 175 }; 176 177 cpu5: cpu@10100 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo"; 180 reg = <0x0 0x10100>; 181 enable-method = "psci"; 182 power-domains = <&cpu_pd5>; 183 power-domain-names = "psci"; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 next-level-cache = <&l2_5>; 186 capacity-dmips-mhz = <1024>; 187 dynamic-power-coefficient = <100>; 188 operating-points-v2 = <&cpu4_opp_table>; 189 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 190 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 191 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 192 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 193 l2_5: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&l3_1>; 198 }; 199 }; 200 201 cpu6: cpu@10200 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo"; 204 reg = <0x0 0x10200>; 205 enable-method = "psci"; 206 power-domains = <&cpu_pd6>; 207 power-domain-names = "psci"; 208 qcom,freq-domain = <&cpufreq_hw 1>; 209 next-level-cache = <&l2_6>; 210 capacity-dmips-mhz = <1024>; 211 dynamic-power-coefficient = <100>; 212 operating-points-v2 = <&cpu4_opp_table>; 213 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 214 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 215 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 216 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 217 l2_6: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3_1>; 222 }; 223 }; 224 225 cpu7: cpu@10300 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo"; 228 reg = <0x0 0x10300>; 229 enable-method = "psci"; 230 power-domains = <&cpu_pd7>; 231 power-domain-names = "psci"; 232 qcom,freq-domain = <&cpufreq_hw 1>; 233 next-level-cache = <&l2_7>; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <100>; 236 operating-points-v2 = <&cpu4_opp_table>; 237 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 238 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 239 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 240 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 241 l2_7: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&l3_1>; 246 }; 247 }; 248 249 cpu-map { 250 cluster0 { 251 core0 { 252 cpu = <&cpu0>; 253 }; 254 255 core1 { 256 cpu = <&cpu1>; 257 }; 258 259 core2 { 260 cpu = <&cpu2>; 261 }; 262 263 core3 { 264 cpu = <&cpu3>; 265 }; 266 }; 267 268 cluster1 { 269 core0 { 270 cpu = <&cpu4>; 271 }; 272 273 core1 { 274 cpu = <&cpu5>; 275 }; 276 277 core2 { 278 cpu = <&cpu6>; 279 }; 280 281 core3 { 282 cpu = <&cpu7>; 283 }; 284 }; 285 }; 286 287 idle-states { 288 entry-method = "psci"; 289 290 gold_cpu_sleep_0: cpu-sleep-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "gold-power-collapse"; 293 arm,psci-suspend-param = <0x40000003>; 294 entry-latency-us = <549>; 295 exit-latency-us = <901>; 296 min-residency-us = <1774>; 297 local-timer-stop; 298 }; 299 300 gold_rail_cpu_sleep_0: cpu-sleep-1 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "gold-rail-power-collapse"; 303 arm,psci-suspend-param = <0x40000004>; 304 entry-latency-us = <702>; 305 exit-latency-us = <1061>; 306 min-residency-us = <4488>; 307 local-timer-stop; 308 }; 309 }; 310 311 domain-idle-states { 312 cluster_sleep_gold: cluster-sleep-0 { 313 compatible = "domain-idle-state"; 314 arm,psci-suspend-param = <0x41000044>; 315 entry-latency-us = <2752>; 316 exit-latency-us = <3048>; 317 min-residency-us = <6118>; 318 }; 319 320 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 321 compatible = "domain-idle-state"; 322 arm,psci-suspend-param = <0x42000144>; 323 entry-latency-us = <3263>; 324 exit-latency-us = <6562>; 325 min-residency-us = <9987>; 326 }; 327 }; 328 }; 329 330 cpu0_opp_table: opp-table-cpu0 { 331 compatible = "operating-points-v2"; 332 opp-shared; 333 334 opp-1267200000 { 335 opp-hz = /bits/ 64 <1267200000>; 336 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 337 }; 338 339 opp-1363200000 { 340 opp-hz = /bits/ 64 <1363200000>; 341 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 342 }; 343 344 opp-1459200000 { 345 opp-hz = /bits/ 64 <1459200000>; 346 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 347 }; 348 349 opp-1536000000 { 350 opp-hz = /bits/ 64 <1536000000>; 351 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 352 }; 353 354 opp-1632000000 { 355 opp-hz = /bits/ 64 <1632000000>; 356 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 357 }; 358 359 opp-1708800000 { 360 opp-hz = /bits/ 64 <1708800000>; 361 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 362 }; 363 364 opp-1785600000 { 365 opp-hz = /bits/ 64 <1785600000>; 366 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 367 }; 368 369 opp-1862400000 { 370 opp-hz = /bits/ 64 <1862400000>; 371 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 372 }; 373 374 opp-1939200000 { 375 opp-hz = /bits/ 64 <1939200000>; 376 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 377 }; 378 379 opp-2016000000 { 380 opp-hz = /bits/ 64 <2016000000>; 381 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 382 }; 383 384 opp-2112000000 { 385 opp-hz = /bits/ 64 <2112000000>; 386 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 387 }; 388 389 opp-2188800000 { 390 opp-hz = /bits/ 64 <2188800000>; 391 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 392 }; 393 394 opp-2265600000 { 395 opp-hz = /bits/ 64 <2265600000>; 396 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 397 }; 398 399 opp-2361600000 { 400 opp-hz = /bits/ 64 <2361600000>; 401 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 402 }; 403 404 opp-2457600000 { 405 opp-hz = /bits/ 64 <2457600000>; 406 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 407 }; 408 409 opp-2553600000 { 410 opp-hz = /bits/ 64 <2553600000>; 411 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 412 }; 413 }; 414 415 cpu4_opp_table: opp-table-cpu4 { 416 compatible = "operating-points-v2"; 417 opp-shared; 418 419 opp-1267200000 { 420 opp-hz = /bits/ 64 <1267200000>; 421 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 422 }; 423 424 opp-1363200000 { 425 opp-hz = /bits/ 64 <1363200000>; 426 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 427 }; 428 429 opp-1459200000 { 430 opp-hz = /bits/ 64 <1459200000>; 431 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 432 }; 433 434 opp-1536000000 { 435 opp-hz = /bits/ 64 <1536000000>; 436 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 437 }; 438 439 opp-1632000000 { 440 opp-hz = /bits/ 64 <1632000000>; 441 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 442 }; 443 444 opp-1708800000 { 445 opp-hz = /bits/ 64 <1708800000>; 446 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 447 }; 448 449 opp-1785600000 { 450 opp-hz = /bits/ 64 <1785600000>; 451 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 452 }; 453 454 opp-1862400000 { 455 opp-hz = /bits/ 64 <1862400000>; 456 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 457 }; 458 459 opp-1939200000 { 460 opp-hz = /bits/ 64 <1939200000>; 461 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 462 }; 463 464 opp-2016000000 { 465 opp-hz = /bits/ 64 <2016000000>; 466 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 467 }; 468 469 opp-2112000000 { 470 opp-hz = /bits/ 64 <2112000000>; 471 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 472 }; 473 474 opp-2188800000 { 475 opp-hz = /bits/ 64 <2188800000>; 476 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 477 }; 478 479 opp-2265600000 { 480 opp-hz = /bits/ 64 <2265600000>; 481 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 482 }; 483 484 opp-2361600000 { 485 opp-hz = /bits/ 64 <2361600000>; 486 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 487 }; 488 489 opp-2457600000 { 490 opp-hz = /bits/ 64 <2457600000>; 491 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 492 }; 493 494 opp-2553600000 { 495 opp-hz = /bits/ 64 <2553600000>; 496 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 497 }; 498 }; 499 500 dummy-sink { 501 compatible = "arm,coresight-dummy-sink"; 502 503 in-ports { 504 port { 505 eud_in: endpoint { 506 remote-endpoint = 507 <&swao_rep_out1>; 508 }; 509 }; 510 }; 511 }; 512 513 firmware { 514 scm { 515 compatible = "qcom,scm-sa8775p", "qcom,scm"; 516 qcom,dload-mode = <&tcsr 0x13000>; 517 memory-region = <&tz_ffi_mem>; 518 }; 519 }; 520 521 aggre1_noc: interconnect-aggre1-noc { 522 compatible = "qcom,sa8775p-aggre1-noc"; 523 #interconnect-cells = <2>; 524 qcom,bcm-voters = <&apps_bcm_voter>; 525 }; 526 527 aggre2_noc: interconnect-aggre2-noc { 528 compatible = "qcom,sa8775p-aggre2-noc"; 529 #interconnect-cells = <2>; 530 qcom,bcm-voters = <&apps_bcm_voter>; 531 }; 532 533 clk_virt: interconnect-clk-virt { 534 compatible = "qcom,sa8775p-clk-virt"; 535 #interconnect-cells = <2>; 536 qcom,bcm-voters = <&apps_bcm_voter>; 537 }; 538 539 config_noc: interconnect-config-noc { 540 compatible = "qcom,sa8775p-config-noc"; 541 #interconnect-cells = <2>; 542 qcom,bcm-voters = <&apps_bcm_voter>; 543 }; 544 545 dc_noc: interconnect-dc-noc { 546 compatible = "qcom,sa8775p-dc-noc"; 547 #interconnect-cells = <2>; 548 qcom,bcm-voters = <&apps_bcm_voter>; 549 }; 550 551 gem_noc: interconnect-gem-noc { 552 compatible = "qcom,sa8775p-gem-noc"; 553 #interconnect-cells = <2>; 554 qcom,bcm-voters = <&apps_bcm_voter>; 555 }; 556 557 gpdsp_anoc: interconnect-gpdsp-anoc { 558 compatible = "qcom,sa8775p-gpdsp-anoc"; 559 #interconnect-cells = <2>; 560 qcom,bcm-voters = <&apps_bcm_voter>; 561 }; 562 563 lpass_ag_noc: interconnect-lpass-ag-noc { 564 compatible = "qcom,sa8775p-lpass-ag-noc"; 565 #interconnect-cells = <2>; 566 qcom,bcm-voters = <&apps_bcm_voter>; 567 }; 568 569 mc_virt: interconnect-mc-virt { 570 compatible = "qcom,sa8775p-mc-virt"; 571 #interconnect-cells = <2>; 572 qcom,bcm-voters = <&apps_bcm_voter>; 573 }; 574 575 mmss_noc: interconnect-mmss-noc { 576 compatible = "qcom,sa8775p-mmss-noc"; 577 #interconnect-cells = <2>; 578 qcom,bcm-voters = <&apps_bcm_voter>; 579 }; 580 581 nspa_noc: interconnect-nspa-noc { 582 compatible = "qcom,sa8775p-nspa-noc"; 583 #interconnect-cells = <2>; 584 qcom,bcm-voters = <&apps_bcm_voter>; 585 }; 586 587 nspb_noc: interconnect-nspb-noc { 588 compatible = "qcom,sa8775p-nspb-noc"; 589 #interconnect-cells = <2>; 590 qcom,bcm-voters = <&apps_bcm_voter>; 591 }; 592 593 pcie_anoc: interconnect-pcie-anoc { 594 compatible = "qcom,sa8775p-pcie-anoc"; 595 #interconnect-cells = <2>; 596 qcom,bcm-voters = <&apps_bcm_voter>; 597 }; 598 599 system_noc: interconnect-system-noc { 600 compatible = "qcom,sa8775p-system-noc"; 601 #interconnect-cells = <2>; 602 qcom,bcm-voters = <&apps_bcm_voter>; 603 }; 604 605 /* Will be updated by the bootloader. */ 606 memory@80000000 { 607 device_type = "memory"; 608 reg = <0x0 0x80000000 0x0 0x0>; 609 }; 610 611 qup_opp_table_100mhz: opp-table-qup100mhz { 612 compatible = "operating-points-v2"; 613 614 opp-100000000 { 615 opp-hz = /bits/ 64 <100000000>; 616 required-opps = <&rpmhpd_opp_svs_l1>; 617 }; 618 }; 619 620 pmu { 621 compatible = "arm,armv8-pmuv3"; 622 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 623 }; 624 625 psci { 626 compatible = "arm,psci-1.0"; 627 method = "smc"; 628 629 cpu_pd0: power-domain-cpu0 { 630 #power-domain-cells = <0>; 631 power-domains = <&cluster_0_pd>; 632 domain-idle-states = <&gold_cpu_sleep_0>, 633 <&gold_rail_cpu_sleep_0>; 634 }; 635 636 cpu_pd1: power-domain-cpu1 { 637 #power-domain-cells = <0>; 638 power-domains = <&cluster_0_pd>; 639 domain-idle-states = <&gold_cpu_sleep_0>, 640 <&gold_rail_cpu_sleep_0>; 641 }; 642 643 cpu_pd2: power-domain-cpu2 { 644 #power-domain-cells = <0>; 645 power-domains = <&cluster_0_pd>; 646 domain-idle-states = <&gold_cpu_sleep_0>, 647 <&gold_rail_cpu_sleep_0>; 648 }; 649 650 cpu_pd3: power-domain-cpu3 { 651 #power-domain-cells = <0>; 652 power-domains = <&cluster_0_pd>; 653 domain-idle-states = <&gold_cpu_sleep_0>, 654 <&gold_rail_cpu_sleep_0>; 655 }; 656 657 cpu_pd4: power-domain-cpu4 { 658 #power-domain-cells = <0>; 659 power-domains = <&cluster_1_pd>; 660 domain-idle-states = <&gold_cpu_sleep_0>, 661 <&gold_rail_cpu_sleep_0>; 662 }; 663 664 cpu_pd5: power-domain-cpu5 { 665 #power-domain-cells = <0>; 666 power-domains = <&cluster_1_pd>; 667 domain-idle-states = <&gold_cpu_sleep_0>, 668 <&gold_rail_cpu_sleep_0>; 669 }; 670 671 cpu_pd6: power-domain-cpu6 { 672 #power-domain-cells = <0>; 673 power-domains = <&cluster_1_pd>; 674 domain-idle-states = <&gold_cpu_sleep_0>, 675 <&gold_rail_cpu_sleep_0>; 676 }; 677 678 cpu_pd7: power-domain-cpu7 { 679 #power-domain-cells = <0>; 680 power-domains = <&cluster_1_pd>; 681 domain-idle-states = <&gold_cpu_sleep_0>, 682 <&gold_rail_cpu_sleep_0>; 683 }; 684 685 cluster_0_pd: power-domain-cluster0 { 686 #power-domain-cells = <0>; 687 domain-idle-states = <&cluster_sleep_gold>; 688 power-domains = <&system_pd>; 689 }; 690 691 cluster_1_pd: power-domain-cluster1 { 692 #power-domain-cells = <0>; 693 domain-idle-states = <&cluster_sleep_gold>; 694 power-domains = <&system_pd>; 695 }; 696 697 system_pd: power-domain-system { 698 #power-domain-cells = <0>; 699 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 700 }; 701 }; 702 703 reserved-memory { 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges; 707 708 sail_ss_mem: sail-ss@80000000 { 709 reg = <0x0 0x80000000 0x0 0x10000000>; 710 no-map; 711 }; 712 713 hyp_mem: hyp@90000000 { 714 reg = <0x0 0x90000000 0x0 0x600000>; 715 no-map; 716 }; 717 718 xbl_boot_mem: xbl-boot@90600000 { 719 reg = <0x0 0x90600000 0x0 0x200000>; 720 no-map; 721 }; 722 723 aop_image_mem: aop-image@90800000 { 724 reg = <0x0 0x90800000 0x0 0x60000>; 725 no-map; 726 }; 727 728 aop_cmd_db_mem: aop-cmd-db@90860000 { 729 compatible = "qcom,cmd-db"; 730 reg = <0x0 0x90860000 0x0 0x20000>; 731 no-map; 732 }; 733 734 uefi_log: uefi-log@908b0000 { 735 reg = <0x0 0x908b0000 0x0 0x10000>; 736 no-map; 737 }; 738 739 ddr_training_checksum: ddr-training-checksum@908c0000 { 740 reg = <0x0 0x908c0000 0x0 0x1000>; 741 no-map; 742 }; 743 744 reserved_mem: reserved@908f0000 { 745 reg = <0x0 0x908f0000 0x0 0xe000>; 746 no-map; 747 }; 748 749 secdata_apss_mem: secdata-apss@908fe000 { 750 reg = <0x0 0x908fe000 0x0 0x2000>; 751 no-map; 752 }; 753 754 smem_mem: smem@90900000 { 755 compatible = "qcom,smem"; 756 reg = <0x0 0x90900000 0x0 0x200000>; 757 no-map; 758 hwlocks = <&tcsr_mutex 3>; 759 }; 760 761 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 762 reg = <0x0 0x90c00000 0x0 0x100000>; 763 no-map; 764 }; 765 766 sail_mailbox_mem: sail-ss@90d00000 { 767 reg = <0x0 0x90d00000 0x0 0x100000>; 768 no-map; 769 }; 770 771 sail_ota_mem: sail-ss@90e00000 { 772 reg = <0x0 0x90e00000 0x0 0x300000>; 773 no-map; 774 }; 775 776 aoss_backup_mem: aoss-backup@91b00000 { 777 reg = <0x0 0x91b00000 0x0 0x40000>; 778 no-map; 779 }; 780 781 cpucp_backup_mem: cpucp-backup@91b40000 { 782 reg = <0x0 0x91b40000 0x0 0x40000>; 783 no-map; 784 }; 785 786 tz_config_backup_mem: tz-config-backup@91b80000 { 787 reg = <0x0 0x91b80000 0x0 0x10000>; 788 no-map; 789 }; 790 791 ddr_training_data_mem: ddr-training-data@91b90000 { 792 reg = <0x0 0x91b90000 0x0 0x10000>; 793 no-map; 794 }; 795 796 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 797 reg = <0x0 0x91ba0000 0x0 0x1000>; 798 no-map; 799 }; 800 801 tz_ffi_mem: tz-ffi@91c00000 { 802 compatible = "shared-dma-pool"; 803 reg = <0x0 0x91c00000 0x0 0x1400000>; 804 no-map; 805 }; 806 807 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 808 reg = <0x0 0x93b00000 0x0 0xf00000>; 809 no-map; 810 }; 811 812 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 813 reg = <0x0 0x94a00000 0x0 0x800000>; 814 no-map; 815 }; 816 817 pil_camera_mem: pil-camera@95200000 { 818 reg = <0x0 0x95200000 0x0 0x500000>; 819 no-map; 820 }; 821 822 pil_adsp_mem: pil-adsp@95c00000 { 823 reg = <0x0 0x95c00000 0x0 0x1e00000>; 824 no-map; 825 }; 826 827 pil_gdsp0_mem: pil-gdsp0@97b00000 { 828 reg = <0x0 0x97b00000 0x0 0x1e00000>; 829 no-map; 830 }; 831 832 pil_gdsp1_mem: pil-gdsp1@99900000 { 833 reg = <0x0 0x99900000 0x0 0x1e00000>; 834 no-map; 835 }; 836 837 pil_cdsp0_mem: pil-cdsp0@9b800000 { 838 reg = <0x0 0x9b800000 0x0 0x1e00000>; 839 no-map; 840 }; 841 842 pil_gpu_mem: pil-gpu@9d600000 { 843 reg = <0x0 0x9d600000 0x0 0x2000>; 844 no-map; 845 }; 846 847 pil_cdsp1_mem: pil-cdsp1@9d700000 { 848 reg = <0x0 0x9d700000 0x0 0x1e00000>; 849 no-map; 850 }; 851 852 pil_cvp_mem: pil-cvp@9f500000 { 853 reg = <0x0 0x9f500000 0x0 0x700000>; 854 no-map; 855 }; 856 857 pil_video_mem: pil-video@9fc00000 { 858 reg = <0x0 0x9fc00000 0x0 0x700000>; 859 no-map; 860 }; 861 862 audio_mdf_mem: audio-mdf-region@ae000000 { 863 reg = <0x0 0xae000000 0x0 0x1000000>; 864 no-map; 865 }; 866 867 firmware_mem: firmware-region@b0000000 { 868 reg = <0x0 0xb0000000 0x0 0x800000>; 869 no-map; 870 }; 871 872 hyptz_reserved_mem: hyptz-reserved@beb00000 { 873 reg = <0x0 0xbeb00000 0x0 0x11500000>; 874 no-map; 875 }; 876 877 scmi_mem: scmi-region@d0000000 { 878 reg = <0x0 0xd0000000 0x0 0x40000>; 879 no-map; 880 }; 881 882 firmware_logs_mem: firmware-logs@d0040000 { 883 reg = <0x0 0xd0040000 0x0 0x10000>; 884 no-map; 885 }; 886 887 firmware_audio_mem: firmware-audio@d0050000 { 888 reg = <0x0 0xd0050000 0x0 0x4000>; 889 no-map; 890 }; 891 892 firmware_reserved_mem: firmware-reserved@d0054000 { 893 reg = <0x0 0xd0054000 0x0 0x9c000>; 894 no-map; 895 }; 896 897 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 898 reg = <0x0 0xd00f0000 0x0 0x10000>; 899 no-map; 900 }; 901 902 tags_mem: tags@d0100000 { 903 reg = <0x0 0xd0100000 0x0 0x1200000>; 904 no-map; 905 }; 906 907 qtee_mem: qtee@d1300000 { 908 reg = <0x0 0xd1300000 0x0 0x500000>; 909 no-map; 910 }; 911 912 deepsleep_backup_mem: deepsleep-backup@d1800000 { 913 reg = <0x0 0xd1800000 0x0 0x100000>; 914 no-map; 915 }; 916 917 trusted_apps_mem: trusted-apps@d1900000 { 918 reg = <0x0 0xd1900000 0x0 0x3800000>; 919 no-map; 920 }; 921 922 tz_stat_mem: tz-stat@db100000 { 923 reg = <0x0 0xdb100000 0x0 0x100000>; 924 no-map; 925 }; 926 927 cpucp_fw_mem: cpucp-fw@db200000 { 928 reg = <0x0 0xdb200000 0x0 0x100000>; 929 no-map; 930 }; 931 }; 932 933 smp2p-adsp { 934 compatible = "qcom,smp2p"; 935 qcom,smem = <443>, <429>; 936 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 937 IPCC_MPROC_SIGNAL_SMP2P 938 IRQ_TYPE_EDGE_RISING>; 939 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 940 941 qcom,local-pid = <0>; 942 qcom,remote-pid = <2>; 943 944 smp2p_adsp_out: master-kernel { 945 qcom,entry-name = "master-kernel"; 946 #qcom,smem-state-cells = <1>; 947 }; 948 949 smp2p_adsp_in: slave-kernel { 950 qcom,entry-name = "slave-kernel"; 951 interrupt-controller; 952 #interrupt-cells = <2>; 953 }; 954 }; 955 956 smp2p-cdsp0 { 957 compatible = "qcom,smp2p"; 958 qcom,smem = <94>, <432>; 959 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 960 IPCC_MPROC_SIGNAL_SMP2P 961 IRQ_TYPE_EDGE_RISING>; 962 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 963 964 qcom,local-pid = <0>; 965 qcom,remote-pid = <5>; 966 967 smp2p_cdsp0_out: master-kernel { 968 qcom,entry-name = "master-kernel"; 969 #qcom,smem-state-cells = <1>; 970 }; 971 972 smp2p_cdsp0_in: slave-kernel { 973 qcom,entry-name = "slave-kernel"; 974 interrupt-controller; 975 #interrupt-cells = <2>; 976 }; 977 }; 978 979 smp2p-cdsp1 { 980 compatible = "qcom,smp2p"; 981 qcom,smem = <617>, <616>; 982 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 983 IPCC_MPROC_SIGNAL_SMP2P 984 IRQ_TYPE_EDGE_RISING>; 985 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 986 987 qcom,local-pid = <0>; 988 qcom,remote-pid = <12>; 989 990 smp2p_cdsp1_out: master-kernel { 991 qcom,entry-name = "master-kernel"; 992 #qcom,smem-state-cells = <1>; 993 }; 994 995 smp2p_cdsp1_in: slave-kernel { 996 qcom,entry-name = "slave-kernel"; 997 interrupt-controller; 998 #interrupt-cells = <2>; 999 }; 1000 }; 1001 1002 smp2p-gpdsp0 { 1003 compatible = "qcom,smp2p"; 1004 qcom,smem = <617>, <616>; 1005 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 1006 IPCC_MPROC_SIGNAL_SMP2P 1007 IRQ_TYPE_EDGE_RISING>; 1008 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 1009 1010 qcom,local-pid = <0>; 1011 qcom,remote-pid = <17>; 1012 1013 smp2p_gpdsp0_out: master-kernel { 1014 qcom,entry-name = "master-kernel"; 1015 #qcom,smem-state-cells = <1>; 1016 }; 1017 1018 smp2p_gpdsp0_in: slave-kernel { 1019 qcom,entry-name = "slave-kernel"; 1020 interrupt-controller; 1021 #interrupt-cells = <2>; 1022 }; 1023 }; 1024 1025 smp2p-gpdsp1 { 1026 compatible = "qcom,smp2p"; 1027 qcom,smem = <617>, <616>; 1028 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 1029 IPCC_MPROC_SIGNAL_SMP2P 1030 IRQ_TYPE_EDGE_RISING>; 1031 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 1032 1033 qcom,local-pid = <0>; 1034 qcom,remote-pid = <18>; 1035 1036 smp2p_gpdsp1_out: master-kernel { 1037 qcom,entry-name = "master-kernel"; 1038 #qcom,smem-state-cells = <1>; 1039 }; 1040 1041 smp2p_gpdsp1_in: slave-kernel { 1042 qcom,entry-name = "slave-kernel"; 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 }; 1046 }; 1047 1048 soc: soc@0 { 1049 compatible = "simple-bus"; 1050 #address-cells = <2>; 1051 #size-cells = <2>; 1052 ranges = <0 0 0 0 0x10 0>; 1053 1054 gcc: clock-controller@100000 { 1055 compatible = "qcom,sa8775p-gcc"; 1056 reg = <0x0 0x00100000 0x0 0xc7018>; 1057 #clock-cells = <1>; 1058 #reset-cells = <1>; 1059 #power-domain-cells = <1>; 1060 clocks = <&rpmhcc RPMH_CXO_CLK>, 1061 <&sleep_clk>, 1062 <0>, 1063 <0>, 1064 <0>, 1065 <&usb_0_qmpphy>, 1066 <&usb_1_qmpphy>, 1067 <0>, 1068 <0>, 1069 <0>, 1070 <&pcie0_phy>, 1071 <&pcie1_phy>, 1072 <0>, 1073 <0>, 1074 <0>; 1075 power-domains = <&rpmhpd SA8775P_CX>; 1076 }; 1077 1078 ipcc: mailbox@408000 { 1079 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1080 reg = <0x0 0x00408000 0x0 0x1000>; 1081 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1082 interrupt-controller; 1083 #interrupt-cells = <3>; 1084 #mbox-cells = <2>; 1085 }; 1086 1087 gpi_dma2: dma-controller@800000 { 1088 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1089 reg = <0x0 0x00800000 0x0 0x60000>; 1090 #dma-cells = <3>; 1091 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1103 dma-channels = <12>; 1104 dma-channel-mask = <0xfff>; 1105 iommus = <&apps_smmu 0x5b6 0x0>; 1106 status = "disabled"; 1107 }; 1108 1109 qupv3_id_2: geniqup@8c0000 { 1110 compatible = "qcom,geni-se-qup"; 1111 reg = <0x0 0x008c0000 0x0 0x6000>; 1112 ranges; 1113 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1114 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1115 clock-names = "m-ahb", "s-ahb"; 1116 iommus = <&apps_smmu 0x5a3 0x0>; 1117 #address-cells = <2>; 1118 #size-cells = <2>; 1119 status = "disabled"; 1120 1121 i2c14: i2c@880000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0x0 0x880000 0x0 0x4000>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1128 clock-names = "se"; 1129 pinctrl-0 = <&qup_i2c14_default>; 1130 pinctrl-names = "default"; 1131 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1132 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1133 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1134 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1135 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1137 interconnect-names = "qup-core", 1138 "qup-config", 1139 "qup-memory"; 1140 power-domains = <&rpmhpd SA8775P_CX>; 1141 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1142 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1143 dma-names = "tx", 1144 "rx"; 1145 status = "disabled"; 1146 }; 1147 1148 spi14: spi@880000 { 1149 compatible = "qcom,geni-spi"; 1150 reg = <0x0 0x880000 0x0 0x4000>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1155 clock-names = "se"; 1156 pinctrl-0 = <&qup_spi14_default>; 1157 pinctrl-names = "default"; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1159 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1160 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1161 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1162 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1163 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1164 interconnect-names = "qup-core", 1165 "qup-config", 1166 "qup-memory"; 1167 power-domains = <&rpmhpd SA8775P_CX>; 1168 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1169 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1170 dma-names = "tx", 1171 "rx"; 1172 status = "disabled"; 1173 }; 1174 1175 uart14: serial@880000 { 1176 compatible = "qcom,geni-uart"; 1177 reg = <0x0 0x00880000 0x0 0x4000>; 1178 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1180 clock-names = "se"; 1181 pinctrl-0 = <&qup_uart14_default>; 1182 pinctrl-names = "default"; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1184 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1185 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1186 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1187 interconnect-names = "qup-core", "qup-config"; 1188 power-domains = <&rpmhpd SA8775P_CX>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c15: i2c@884000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0x0 0x884000 0x0 0x4000>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1199 clock-names = "se"; 1200 pinctrl-0 = <&qup_i2c15_default>; 1201 pinctrl-names = "default"; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1203 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1204 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1205 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1206 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1207 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1208 interconnect-names = "qup-core", 1209 "qup-config", 1210 "qup-memory"; 1211 power-domains = <&rpmhpd SA8775P_CX>; 1212 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1213 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1214 dma-names = "tx", 1215 "rx"; 1216 status = "disabled"; 1217 }; 1218 1219 spi15: spi@884000 { 1220 compatible = "qcom,geni-spi"; 1221 reg = <0x0 0x884000 0x0 0x4000>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1226 clock-names = "se"; 1227 pinctrl-0 = <&qup_spi15_default>; 1228 pinctrl-names = "default"; 1229 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1230 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1231 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1232 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1233 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1234 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1235 interconnect-names = "qup-core", 1236 "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SA8775P_CX>; 1239 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1240 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1241 dma-names = "tx", 1242 "rx"; 1243 status = "disabled"; 1244 }; 1245 1246 uart15: serial@884000 { 1247 compatible = "qcom,geni-uart"; 1248 reg = <0x0 0x00884000 0x0 0x4000>; 1249 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1251 clock-names = "se"; 1252 pinctrl-0 = <&qup_uart15_default>; 1253 pinctrl-names = "default"; 1254 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1255 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1256 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1257 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 power-domains = <&rpmhpd SA8775P_CX>; 1260 status = "disabled"; 1261 }; 1262 1263 i2c16: i2c@888000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0x0 0x888000 0x0 0x4000>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1270 clock-names = "se"; 1271 pinctrl-0 = <&qup_i2c16_default>; 1272 pinctrl-names = "default"; 1273 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1274 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1275 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1276 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1277 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1278 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1279 interconnect-names = "qup-core", 1280 "qup-config", 1281 "qup-memory"; 1282 power-domains = <&rpmhpd SA8775P_CX>; 1283 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1284 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1285 dma-names = "tx", 1286 "rx"; 1287 status = "disabled"; 1288 }; 1289 1290 spi16: spi@888000 { 1291 compatible = "qcom,geni-spi"; 1292 reg = <0x0 0x00888000 0x0 0x4000>; 1293 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1295 clock-names = "se"; 1296 pinctrl-0 = <&qup_spi16_default>; 1297 pinctrl-names = "default"; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1299 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1300 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1301 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1302 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1303 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1304 interconnect-names = "qup-core", 1305 "qup-config", 1306 "qup-memory"; 1307 power-domains = <&rpmhpd SA8775P_CX>; 1308 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1309 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1310 dma-names = "tx", 1311 "rx"; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 status = "disabled"; 1315 }; 1316 1317 uart16: serial@888000 { 1318 compatible = "qcom,geni-uart"; 1319 reg = <0x0 0x00888000 0x0 0x4000>; 1320 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1322 clock-names = "se"; 1323 pinctrl-0 = <&qup_uart16_default>; 1324 pinctrl-names = "default"; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1326 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1327 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1328 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1329 interconnect-names = "qup-core", "qup-config"; 1330 power-domains = <&rpmhpd SA8775P_CX>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c17: i2c@88c000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0x0 0x88c000 0x0 0x4000>; 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1341 clock-names = "se"; 1342 pinctrl-0 = <&qup_i2c17_default>; 1343 pinctrl-names = "default"; 1344 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1345 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1346 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1347 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1348 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1349 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1350 interconnect-names = "qup-core", 1351 "qup-config", 1352 "qup-memory"; 1353 power-domains = <&rpmhpd SA8775P_CX>; 1354 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1355 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1356 dma-names = "tx", 1357 "rx"; 1358 status = "disabled"; 1359 }; 1360 1361 spi17: spi@88c000 { 1362 compatible = "qcom,geni-spi"; 1363 reg = <0x0 0x88c000 0x0 0x4000>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1367 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1368 clock-names = "se"; 1369 pinctrl-0 = <&qup_spi17_default>; 1370 pinctrl-names = "default"; 1371 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1372 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1373 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1374 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1375 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1376 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1377 interconnect-names = "qup-core", 1378 "qup-config", 1379 "qup-memory"; 1380 power-domains = <&rpmhpd SA8775P_CX>; 1381 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1382 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1383 dma-names = "tx", 1384 "rx"; 1385 status = "disabled"; 1386 }; 1387 1388 uart17: serial@88c000 { 1389 compatible = "qcom,geni-uart"; 1390 reg = <0x0 0x0088c000 0x0 0x4000>; 1391 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1393 clock-names = "se"; 1394 pinctrl-0 = <&qup_uart17_default>; 1395 pinctrl-names = "default"; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1397 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1398 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1399 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1400 interconnect-names = "qup-core", "qup-config"; 1401 power-domains = <&rpmhpd SA8775P_CX>; 1402 status = "disabled"; 1403 }; 1404 1405 i2c18: i2c@890000 { 1406 compatible = "qcom,geni-i2c"; 1407 reg = <0x0 0x00890000 0x0 0x4000>; 1408 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1409 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1410 clock-names = "se"; 1411 pinctrl-0 = <&qup_i2c18_default>; 1412 pinctrl-names = "default"; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1414 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1415 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1416 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1417 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1418 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1419 interconnect-names = "qup-core", 1420 "qup-config", 1421 "qup-memory"; 1422 power-domains = <&rpmhpd SA8775P_CX>; 1423 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1424 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1425 dma-names = "tx", 1426 "rx"; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 spi18: spi@890000 { 1433 compatible = "qcom,geni-spi"; 1434 reg = <0x0 0x890000 0x0 0x4000>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1438 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1439 clock-names = "se"; 1440 pinctrl-0 = <&qup_spi18_default>; 1441 pinctrl-names = "default"; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1443 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1444 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1445 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1446 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1448 interconnect-names = "qup-core", 1449 "qup-config", 1450 "qup-memory"; 1451 power-domains = <&rpmhpd SA8775P_CX>; 1452 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1453 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1454 dma-names = "tx", 1455 "rx"; 1456 status = "disabled"; 1457 }; 1458 1459 uart18: serial@890000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0x0 0x00890000 0x0 0x4000>; 1462 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1463 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1464 clock-names = "se"; 1465 pinctrl-0 = <&qup_uart18_default>; 1466 pinctrl-names = "default"; 1467 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1468 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1469 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1470 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 power-domains = <&rpmhpd SA8775P_CX>; 1473 status = "disabled"; 1474 }; 1475 1476 i2c19: i2c@894000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0x0 0x894000 0x0 0x4000>; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1483 clock-names = "se"; 1484 pinctrl-0 = <&qup_i2c19_default>; 1485 pinctrl-names = "default"; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1487 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1488 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1489 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1490 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1491 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1492 interconnect-names = "qup-core", 1493 "qup-config", 1494 "qup-memory"; 1495 power-domains = <&rpmhpd SA8775P_CX>; 1496 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1497 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1498 dma-names = "tx", 1499 "rx"; 1500 status = "disabled"; 1501 }; 1502 1503 spi19: spi@894000 { 1504 compatible = "qcom,geni-spi"; 1505 reg = <0x0 0x894000 0x0 0x4000>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1510 clock-names = "se"; 1511 pinctrl-0 = <&qup_spi19_default>; 1512 pinctrl-names = "default"; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1514 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1515 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1516 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1517 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1518 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1519 interconnect-names = "qup-core", 1520 "qup-config", 1521 "qup-memory"; 1522 power-domains = <&rpmhpd SA8775P_CX>; 1523 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1524 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1525 dma-names = "tx", 1526 "rx"; 1527 status = "disabled"; 1528 }; 1529 1530 uart19: serial@894000 { 1531 compatible = "qcom,geni-uart"; 1532 reg = <0x0 0x00894000 0x0 0x4000>; 1533 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1535 clock-names = "se"; 1536 pinctrl-0 = <&qup_uart19_default>; 1537 pinctrl-names = "default"; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1539 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1540 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1541 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1542 interconnect-names = "qup-core", "qup-config"; 1543 power-domains = <&rpmhpd SA8775P_CX>; 1544 status = "disabled"; 1545 }; 1546 1547 i2c20: i2c@898000 { 1548 compatible = "qcom,geni-i2c"; 1549 reg = <0x0 0x898000 0x0 0x4000>; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1553 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1554 clock-names = "se"; 1555 pinctrl-0 = <&qup_i2c20_default>; 1556 pinctrl-names = "default"; 1557 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1558 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1559 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1560 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1561 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1562 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1563 interconnect-names = "qup-core", 1564 "qup-config", 1565 "qup-memory"; 1566 power-domains = <&rpmhpd SA8775P_CX>; 1567 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1568 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1569 dma-names = "tx", 1570 "rx"; 1571 status = "disabled"; 1572 }; 1573 1574 spi20: spi@898000 { 1575 compatible = "qcom,geni-spi"; 1576 reg = <0x0 0x898000 0x0 0x4000>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1580 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1581 clock-names = "se"; 1582 pinctrl-0 = <&qup_spi20_default>; 1583 pinctrl-names = "default"; 1584 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1585 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1587 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1588 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1590 interconnect-names = "qup-core", 1591 "qup-config", 1592 "qup-memory"; 1593 power-domains = <&rpmhpd SA8775P_CX>; 1594 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1595 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1596 dma-names = "tx", 1597 "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 uart20: serial@898000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0x0 0x00898000 0x0 0x4000>; 1604 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1606 clock-names = "se"; 1607 pinctrl-0 = <&qup_uart20_default>; 1608 pinctrl-names = "default"; 1609 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1610 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1611 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1612 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 power-domains = <&rpmhpd SA8775P_CX>; 1615 status = "disabled"; 1616 }; 1617 1618 }; 1619 1620 gpi_dma0: dma-controller@900000 { 1621 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1622 reg = <0x0 0x00900000 0x0 0x60000>; 1623 #dma-cells = <3>; 1624 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1636 dma-channels = <12>; 1637 dma-channel-mask = <0xfff>; 1638 iommus = <&apps_smmu 0x416 0x0>; 1639 status = "disabled"; 1640 }; 1641 1642 qupv3_id_0: geniqup@9c0000 { 1643 compatible = "qcom,geni-se-qup"; 1644 reg = <0x0 0x9c0000 0x0 0x6000>; 1645 #address-cells = <2>; 1646 #size-cells = <2>; 1647 ranges; 1648 clock-names = "m-ahb", "s-ahb"; 1649 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1650 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1651 iommus = <&apps_smmu 0x403 0x0>; 1652 status = "disabled"; 1653 1654 i2c0: i2c@980000 { 1655 compatible = "qcom,geni-i2c"; 1656 reg = <0x0 0x980000 0x0 0x4000>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1660 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1661 clock-names = "se"; 1662 pinctrl-0 = <&qup_i2c0_default>; 1663 pinctrl-names = "default"; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1665 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1666 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1667 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1668 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1669 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1670 interconnect-names = "qup-core", 1671 "qup-config", 1672 "qup-memory"; 1673 power-domains = <&rpmhpd SA8775P_CX>; 1674 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1675 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1676 dma-names = "tx", 1677 "rx"; 1678 status = "disabled"; 1679 }; 1680 1681 spi0: spi@980000 { 1682 compatible = "qcom,geni-spi"; 1683 reg = <0x0 0x980000 0x0 0x4000>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1687 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1688 clock-names = "se"; 1689 pinctrl-0 = <&qup_spi0_default>; 1690 pinctrl-names = "default"; 1691 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1692 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1693 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1694 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1695 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1696 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1697 interconnect-names = "qup-core", 1698 "qup-config", 1699 "qup-memory"; 1700 power-domains = <&rpmhpd SA8775P_CX>; 1701 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1702 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1703 dma-names = "tx", 1704 "rx"; 1705 status = "disabled"; 1706 }; 1707 1708 uart0: serial@980000 { 1709 compatible = "qcom,geni-uart"; 1710 reg = <0x0 0x980000 0x0 0x4000>; 1711 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1712 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1713 clock-names = "se"; 1714 pinctrl-0 = <&qup_uart0_default>; 1715 pinctrl-names = "default"; 1716 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1717 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1718 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1719 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 power-domains = <&rpmhpd SA8775P_CX>; 1722 status = "disabled"; 1723 }; 1724 1725 i2c1: i2c@984000 { 1726 compatible = "qcom,geni-i2c"; 1727 reg = <0x0 0x984000 0x0 0x4000>; 1728 #address-cells = <1>; 1729 #size-cells = <0>; 1730 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1732 clock-names = "se"; 1733 pinctrl-0 = <&qup_i2c1_default>; 1734 pinctrl-names = "default"; 1735 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1736 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1737 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1738 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1739 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1741 interconnect-names = "qup-core", 1742 "qup-config", 1743 "qup-memory"; 1744 power-domains = <&rpmhpd SA8775P_CX>; 1745 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1746 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1747 dma-names = "tx", 1748 "rx"; 1749 status = "disabled"; 1750 }; 1751 1752 spi1: spi@984000 { 1753 compatible = "qcom,geni-spi"; 1754 reg = <0x0 0x984000 0x0 0x4000>; 1755 #address-cells = <1>; 1756 #size-cells = <0>; 1757 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1758 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1759 clock-names = "se"; 1760 pinctrl-0 = <&qup_spi1_default>; 1761 pinctrl-names = "default"; 1762 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1763 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1764 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1765 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1766 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1768 interconnect-names = "qup-core", 1769 "qup-config", 1770 "qup-memory"; 1771 power-domains = <&rpmhpd SA8775P_CX>; 1772 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1773 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1774 dma-names = "tx", 1775 "rx"; 1776 status = "disabled"; 1777 }; 1778 1779 uart1: serial@984000 { 1780 compatible = "qcom,geni-uart"; 1781 reg = <0x0 0x984000 0x0 0x4000>; 1782 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1783 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1784 clock-names = "se"; 1785 pinctrl-0 = <&qup_uart1_default>; 1786 pinctrl-names = "default"; 1787 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1788 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1789 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1790 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1791 interconnect-names = "qup-core", "qup-config"; 1792 power-domains = <&rpmhpd SA8775P_CX>; 1793 status = "disabled"; 1794 }; 1795 1796 i2c2: i2c@988000 { 1797 compatible = "qcom,geni-i2c"; 1798 reg = <0x0 0x988000 0x0 0x4000>; 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1802 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1803 clock-names = "se"; 1804 pinctrl-0 = <&qup_i2c2_default>; 1805 pinctrl-names = "default"; 1806 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1807 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1808 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1809 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1810 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1811 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1812 interconnect-names = "qup-core", 1813 "qup-config", 1814 "qup-memory"; 1815 power-domains = <&rpmhpd SA8775P_CX>; 1816 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1817 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1818 dma-names = "tx", 1819 "rx"; 1820 status = "disabled"; 1821 }; 1822 1823 spi2: spi@988000 { 1824 compatible = "qcom,geni-spi"; 1825 reg = <0x0 0x988000 0x0 0x4000>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1829 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1830 clock-names = "se"; 1831 pinctrl-0 = <&qup_spi2_default>; 1832 pinctrl-names = "default"; 1833 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1834 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1835 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1836 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1837 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1839 interconnect-names = "qup-core", 1840 "qup-config", 1841 "qup-memory"; 1842 power-domains = <&rpmhpd SA8775P_CX>; 1843 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1844 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1845 dma-names = "tx", 1846 "rx"; 1847 status = "disabled"; 1848 }; 1849 1850 uart2: serial@988000 { 1851 compatible = "qcom,geni-uart"; 1852 reg = <0x0 0x988000 0x0 0x4000>; 1853 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1854 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1855 clock-names = "se"; 1856 pinctrl-0 = <&qup_uart2_default>; 1857 pinctrl-names = "default"; 1858 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1859 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1860 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1861 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1862 interconnect-names = "qup-core", "qup-config"; 1863 power-domains = <&rpmhpd SA8775P_CX>; 1864 status = "disabled"; 1865 }; 1866 1867 i2c3: i2c@98c000 { 1868 compatible = "qcom,geni-i2c"; 1869 reg = <0x0 0x98c000 0x0 0x4000>; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1873 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1874 clock-names = "se"; 1875 pinctrl-0 = <&qup_i2c3_default>; 1876 pinctrl-names = "default"; 1877 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1878 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1879 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1880 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1881 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1882 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1883 interconnect-names = "qup-core", 1884 "qup-config", 1885 "qup-memory"; 1886 power-domains = <&rpmhpd SA8775P_CX>; 1887 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1888 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1889 dma-names = "tx", 1890 "rx"; 1891 status = "disabled"; 1892 }; 1893 1894 spi3: spi@98c000 { 1895 compatible = "qcom,geni-spi"; 1896 reg = <0x0 0x98c000 0x0 0x4000>; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1900 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1901 clock-names = "se"; 1902 pinctrl-0 = <&qup_spi3_default>; 1903 pinctrl-names = "default"; 1904 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1905 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1906 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1907 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1908 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1909 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1910 interconnect-names = "qup-core", 1911 "qup-config", 1912 "qup-memory"; 1913 power-domains = <&rpmhpd SA8775P_CX>; 1914 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1915 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1916 dma-names = "tx", 1917 "rx"; 1918 status = "disabled"; 1919 }; 1920 1921 uart3: serial@98c000 { 1922 compatible = "qcom,geni-uart"; 1923 reg = <0x0 0x98c000 0x0 0x4000>; 1924 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1925 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1926 clock-names = "se"; 1927 pinctrl-0 = <&qup_uart3_default>; 1928 pinctrl-names = "default"; 1929 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1930 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1931 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1932 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1933 interconnect-names = "qup-core", "qup-config"; 1934 power-domains = <&rpmhpd SA8775P_CX>; 1935 status = "disabled"; 1936 }; 1937 1938 i2c4: i2c@990000 { 1939 compatible = "qcom,geni-i2c"; 1940 reg = <0x0 0x990000 0x0 0x4000>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1944 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1945 clock-names = "se"; 1946 pinctrl-0 = <&qup_i2c4_default>; 1947 pinctrl-names = "default"; 1948 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1949 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1951 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1952 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1954 interconnect-names = "qup-core", 1955 "qup-config", 1956 "qup-memory"; 1957 power-domains = <&rpmhpd SA8775P_CX>; 1958 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1959 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1960 dma-names = "tx", 1961 "rx"; 1962 status = "disabled"; 1963 }; 1964 1965 spi4: spi@990000 { 1966 compatible = "qcom,geni-spi"; 1967 reg = <0x0 0x990000 0x0 0x4000>; 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1972 clock-names = "se"; 1973 pinctrl-0 = <&qup_spi4_default>; 1974 pinctrl-names = "default"; 1975 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1976 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1977 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1978 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1979 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1980 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1981 interconnect-names = "qup-core", 1982 "qup-config", 1983 "qup-memory"; 1984 power-domains = <&rpmhpd SA8775P_CX>; 1985 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1986 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1987 dma-names = "tx", 1988 "rx"; 1989 status = "disabled"; 1990 }; 1991 1992 uart4: serial@990000 { 1993 compatible = "qcom,geni-uart"; 1994 reg = <0x0 0x990000 0x0 0x4000>; 1995 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1996 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1997 clock-names = "se"; 1998 pinctrl-0 = <&qup_uart4_default>; 1999 pinctrl-names = "default"; 2000 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2001 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2003 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2004 interconnect-names = "qup-core", "qup-config"; 2005 power-domains = <&rpmhpd SA8775P_CX>; 2006 status = "disabled"; 2007 }; 2008 2009 i2c5: i2c@994000 { 2010 compatible = "qcom,geni-i2c"; 2011 reg = <0x0 0x994000 0x0 0x4000>; 2012 #address-cells = <1>; 2013 #size-cells = <0>; 2014 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2015 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2016 clock-names = "se"; 2017 pinctrl-0 = <&qup_i2c5_default>; 2018 pinctrl-names = "default"; 2019 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2020 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2022 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2023 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2025 interconnect-names = "qup-core", 2026 "qup-config", 2027 "qup-memory"; 2028 power-domains = <&rpmhpd SA8775P_CX>; 2029 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2030 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2031 dma-names = "tx", 2032 "rx"; 2033 status = "disabled"; 2034 }; 2035 2036 spi5: spi@994000 { 2037 compatible = "qcom,geni-spi"; 2038 reg = <0x0 0x994000 0x0 0x4000>; 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2042 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2043 clock-names = "se"; 2044 pinctrl-0 = <&qup_spi5_default>; 2045 pinctrl-names = "default"; 2046 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2047 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2048 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2049 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2050 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2052 interconnect-names = "qup-core", 2053 "qup-config", 2054 "qup-memory"; 2055 power-domains = <&rpmhpd SA8775P_CX>; 2056 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2057 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2058 dma-names = "tx", 2059 "rx"; 2060 status = "disabled"; 2061 }; 2062 2063 uart5: serial@994000 { 2064 compatible = "qcom,geni-uart"; 2065 reg = <0x0 0x994000 0x0 0x4000>; 2066 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2067 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2068 clock-names = "se"; 2069 pinctrl-0 = <&qup_uart5_default>; 2070 pinctrl-names = "default"; 2071 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2072 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2074 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2075 interconnect-names = "qup-core", "qup-config"; 2076 power-domains = <&rpmhpd SA8775P_CX>; 2077 status = "disabled"; 2078 }; 2079 }; 2080 2081 gpi_dma1: dma-controller@a00000 { 2082 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2083 reg = <0x0 0x00a00000 0x0 0x60000>; 2084 #dma-cells = <3>; 2085 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2097 iommus = <&apps_smmu 0x456 0x0>; 2098 dma-channels = <12>; 2099 dma-channel-mask = <0xfff>; 2100 status = "disabled"; 2101 }; 2102 2103 qupv3_id_1: geniqup@ac0000 { 2104 compatible = "qcom,geni-se-qup"; 2105 reg = <0x0 0x00ac0000 0x0 0x6000>; 2106 #address-cells = <2>; 2107 #size-cells = <2>; 2108 ranges; 2109 clock-names = "m-ahb", "s-ahb"; 2110 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2111 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2112 iommus = <&apps_smmu 0x443 0x0>; 2113 status = "disabled"; 2114 2115 i2c7: i2c@a80000 { 2116 compatible = "qcom,geni-i2c"; 2117 reg = <0x0 0xa80000 0x0 0x4000>; 2118 #address-cells = <1>; 2119 #size-cells = <0>; 2120 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2122 clock-names = "se"; 2123 pinctrl-0 = <&qup_i2c7_default>; 2124 pinctrl-names = "default"; 2125 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2126 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2127 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2128 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2129 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2130 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2131 interconnect-names = "qup-core", 2132 "qup-config", 2133 "qup-memory"; 2134 power-domains = <&rpmhpd SA8775P_CX>; 2135 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2136 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2137 dma-names = "tx", 2138 "rx"; 2139 status = "disabled"; 2140 }; 2141 2142 spi7: spi@a80000 { 2143 compatible = "qcom,geni-spi"; 2144 reg = <0x0 0xa80000 0x0 0x4000>; 2145 #address-cells = <1>; 2146 #size-cells = <0>; 2147 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2148 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2149 clock-names = "se"; 2150 pinctrl-0 = <&qup_spi7_default>; 2151 pinctrl-names = "default"; 2152 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2153 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2154 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2155 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2156 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2158 interconnect-names = "qup-core", 2159 "qup-config", 2160 "qup-memory"; 2161 power-domains = <&rpmhpd SA8775P_CX>; 2162 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2163 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2164 dma-names = "tx", 2165 "rx"; 2166 status = "disabled"; 2167 }; 2168 2169 uart7: serial@a80000 { 2170 compatible = "qcom,geni-uart"; 2171 reg = <0x0 0x00a80000 0x0 0x4000>; 2172 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2173 clock-names = "se"; 2174 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2175 pinctrl-0 = <&qup_uart7_default>; 2176 pinctrl-names = "default"; 2177 interconnect-names = "qup-core", "qup-config"; 2178 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2179 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2181 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2182 power-domains = <&rpmhpd SA8775P_CX>; 2183 operating-points-v2 = <&qup_opp_table_100mhz>; 2184 status = "disabled"; 2185 }; 2186 2187 i2c8: i2c@a84000 { 2188 compatible = "qcom,geni-i2c"; 2189 reg = <0x0 0xa84000 0x0 0x4000>; 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2193 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2194 clock-names = "se"; 2195 pinctrl-0 = <&qup_i2c8_default>; 2196 pinctrl-names = "default"; 2197 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2198 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2200 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2201 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2203 interconnect-names = "qup-core", 2204 "qup-config", 2205 "qup-memory"; 2206 power-domains = <&rpmhpd SA8775P_CX>; 2207 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2208 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2209 dma-names = "tx", 2210 "rx"; 2211 status = "disabled"; 2212 }; 2213 2214 spi8: spi@a84000 { 2215 compatible = "qcom,geni-spi"; 2216 reg = <0x0 0xa84000 0x0 0x4000>; 2217 #address-cells = <1>; 2218 #size-cells = <0>; 2219 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2220 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2221 clock-names = "se"; 2222 pinctrl-0 = <&qup_spi8_default>; 2223 pinctrl-names = "default"; 2224 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2225 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2227 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2228 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2230 interconnect-names = "qup-core", 2231 "qup-config", 2232 "qup-memory"; 2233 power-domains = <&rpmhpd SA8775P_CX>; 2234 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2235 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2236 dma-names = "tx", 2237 "rx"; 2238 status = "disabled"; 2239 }; 2240 2241 uart8: serial@a84000 { 2242 compatible = "qcom,geni-uart"; 2243 reg = <0x0 0x00a84000 0x0 0x4000>; 2244 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2245 clock-names = "se"; 2246 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2247 pinctrl-0 = <&qup_uart8_default>; 2248 pinctrl-names = "default"; 2249 interconnect-names = "qup-core", "qup-config"; 2250 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2251 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2252 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2253 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2254 power-domains = <&rpmhpd SA8775P_CX>; 2255 operating-points-v2 = <&qup_opp_table_100mhz>; 2256 status = "disabled"; 2257 }; 2258 2259 i2c9: i2c@a88000 { 2260 compatible = "qcom,geni-i2c"; 2261 reg = <0x0 0xa88000 0x0 0x4000>; 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2266 clock-names = "se"; 2267 pinctrl-0 = <&qup_i2c9_default>; 2268 pinctrl-names = "default"; 2269 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2270 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2271 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2272 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2273 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2275 interconnect-names = "qup-core", 2276 "qup-config", 2277 "qup-memory"; 2278 power-domains = <&rpmhpd SA8775P_CX>; 2279 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2280 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2281 dma-names = "tx", 2282 "rx"; 2283 status = "disabled"; 2284 }; 2285 2286 spi9: spi@a88000 { 2287 compatible = "qcom,geni-spi"; 2288 reg = <0x0 0xa88000 0x0 0x4000>; 2289 #address-cells = <1>; 2290 #size-cells = <0>; 2291 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2292 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2293 clock-names = "se"; 2294 pinctrl-0 = <&qup_spi9_default>; 2295 pinctrl-names = "default"; 2296 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2297 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2298 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2299 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2300 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2302 interconnect-names = "qup-core", 2303 "qup-config", 2304 "qup-memory"; 2305 power-domains = <&rpmhpd SA8775P_CX>; 2306 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2307 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2308 dma-names = "tx", 2309 "rx"; 2310 status = "disabled"; 2311 }; 2312 2313 uart9: serial@a88000 { 2314 compatible = "qcom,geni-uart"; 2315 reg = <0x0 0xa88000 0x0 0x4000>; 2316 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2317 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2318 clock-names = "se"; 2319 pinctrl-0 = <&qup_uart9_default>; 2320 pinctrl-names = "default"; 2321 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2322 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2323 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2324 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2325 interconnect-names = "qup-core", "qup-config"; 2326 power-domains = <&rpmhpd SA8775P_CX>; 2327 status = "disabled"; 2328 }; 2329 2330 i2c10: i2c@a8c000 { 2331 compatible = "qcom,geni-i2c"; 2332 reg = <0x0 0xa8c000 0x0 0x4000>; 2333 #address-cells = <1>; 2334 #size-cells = <0>; 2335 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2336 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2337 clock-names = "se"; 2338 pinctrl-0 = <&qup_i2c10_default>; 2339 pinctrl-names = "default"; 2340 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2341 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2343 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2344 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2346 interconnect-names = "qup-core", 2347 "qup-config", 2348 "qup-memory"; 2349 power-domains = <&rpmhpd SA8775P_CX>; 2350 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2351 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2352 dma-names = "tx", 2353 "rx"; 2354 status = "disabled"; 2355 }; 2356 2357 spi10: spi@a8c000 { 2358 compatible = "qcom,geni-spi"; 2359 reg = <0x0 0xa8c000 0x0 0x4000>; 2360 #address-cells = <1>; 2361 #size-cells = <0>; 2362 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2363 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2364 clock-names = "se"; 2365 pinctrl-0 = <&qup_spi10_default>; 2366 pinctrl-names = "default"; 2367 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2368 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2369 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2370 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2371 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2372 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2373 interconnect-names = "qup-core", 2374 "qup-config", 2375 "qup-memory"; 2376 power-domains = <&rpmhpd SA8775P_CX>; 2377 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2378 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2379 dma-names = "tx", 2380 "rx"; 2381 status = "disabled"; 2382 }; 2383 2384 uart10: serial@a8c000 { 2385 compatible = "qcom,geni-uart"; 2386 reg = <0x0 0x00a8c000 0x0 0x4000>; 2387 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2388 clock-names = "se"; 2389 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2390 pinctrl-0 = <&qup_uart10_default>; 2391 pinctrl-names = "default"; 2392 interconnect-names = "qup-core", "qup-config"; 2393 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2394 &clk_virt SLAVE_QUP_CORE_1 0>, 2395 <&gem_noc MASTER_APPSS_PROC 0 2396 &config_noc SLAVE_QUP_1 0>; 2397 power-domains = <&rpmhpd SA8775P_CX>; 2398 operating-points-v2 = <&qup_opp_table_100mhz>; 2399 status = "disabled"; 2400 }; 2401 2402 i2c11: i2c@a90000 { 2403 compatible = "qcom,geni-i2c"; 2404 reg = <0x0 0xa90000 0x0 0x4000>; 2405 #address-cells = <1>; 2406 #size-cells = <0>; 2407 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2409 clock-names = "se"; 2410 pinctrl-0 = <&qup_i2c11_default>; 2411 pinctrl-names = "default"; 2412 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2413 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2414 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2415 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2416 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2417 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2418 interconnect-names = "qup-core", 2419 "qup-config", 2420 "qup-memory"; 2421 power-domains = <&rpmhpd SA8775P_CX>; 2422 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2423 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2424 dma-names = "tx", 2425 "rx"; 2426 status = "disabled"; 2427 }; 2428 2429 spi11: spi@a90000 { 2430 compatible = "qcom,geni-spi"; 2431 reg = <0x0 0xa90000 0x0 0x4000>; 2432 #address-cells = <1>; 2433 #size-cells = <0>; 2434 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2435 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2436 clock-names = "se"; 2437 pinctrl-0 = <&qup_spi11_default>; 2438 pinctrl-names = "default"; 2439 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2440 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2442 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2443 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2444 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2445 interconnect-names = "qup-core", 2446 "qup-config", 2447 "qup-memory"; 2448 power-domains = <&rpmhpd SA8775P_CX>; 2449 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2450 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2451 dma-names = "tx", 2452 "rx"; 2453 status = "disabled"; 2454 }; 2455 2456 uart11: serial@a90000 { 2457 compatible = "qcom,geni-uart"; 2458 reg = <0x0 0x00a90000 0x0 0x4000>; 2459 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2460 clock-names = "se"; 2461 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2462 pinctrl-0 = <&qup_uart11_default>; 2463 pinctrl-names = "default"; 2464 interconnect-names = "qup-core", "qup-config"; 2465 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2466 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2467 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2468 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2469 power-domains = <&rpmhpd SA8775P_CX>; 2470 operating-points-v2 = <&qup_opp_table_100mhz>; 2471 status = "disabled"; 2472 }; 2473 2474 i2c12: i2c@a94000 { 2475 compatible = "qcom,geni-i2c"; 2476 reg = <0x0 0xa94000 0x0 0x4000>; 2477 #address-cells = <1>; 2478 #size-cells = <0>; 2479 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2480 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2481 clock-names = "se"; 2482 pinctrl-0 = <&qup_i2c12_default>; 2483 pinctrl-names = "default"; 2484 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2485 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2487 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2488 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2490 interconnect-names = "qup-core", 2491 "qup-config", 2492 "qup-memory"; 2493 power-domains = <&rpmhpd SA8775P_CX>; 2494 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2495 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2496 dma-names = "tx", 2497 "rx"; 2498 status = "disabled"; 2499 }; 2500 2501 spi12: spi@a94000 { 2502 compatible = "qcom,geni-spi"; 2503 reg = <0x0 0xa94000 0x0 0x4000>; 2504 #address-cells = <1>; 2505 #size-cells = <0>; 2506 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2508 clock-names = "se"; 2509 pinctrl-0 = <&qup_spi12_default>; 2510 pinctrl-names = "default"; 2511 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2512 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2513 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2514 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2515 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2516 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2517 interconnect-names = "qup-core", 2518 "qup-config", 2519 "qup-memory"; 2520 power-domains = <&rpmhpd SA8775P_CX>; 2521 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2522 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2523 dma-names = "tx", 2524 "rx"; 2525 status = "disabled"; 2526 }; 2527 2528 uart12: serial@a94000 { 2529 compatible = "qcom,geni-uart"; 2530 reg = <0x0 0x00a94000 0x0 0x4000>; 2531 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2532 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2533 clock-names = "se"; 2534 pinctrl-0 = <&qup_uart12_default>; 2535 pinctrl-names = "default"; 2536 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2537 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2538 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2539 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2540 interconnect-names = "qup-core", "qup-config"; 2541 power-domains = <&rpmhpd SA8775P_CX>; 2542 status = "disabled"; 2543 }; 2544 2545 i2c13: i2c@a98000 { 2546 compatible = "qcom,geni-i2c"; 2547 reg = <0x0 0xa98000 0x0 0x4000>; 2548 #address-cells = <1>; 2549 #size-cells = <0>; 2550 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2552 clock-names = "se"; 2553 pinctrl-0 = <&qup_i2c13_default>; 2554 pinctrl-names = "default"; 2555 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2556 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2557 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2558 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2559 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2560 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2561 interconnect-names = "qup-core", 2562 "qup-config", 2563 "qup-memory"; 2564 power-domains = <&rpmhpd SA8775P_CX>; 2565 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2566 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2567 dma-names = "tx", 2568 "rx"; 2569 status = "disabled"; 2570 2571 }; 2572 }; 2573 2574 gpi_dma3: dma-controller@b00000 { 2575 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2576 reg = <0x0 0x00b00000 0x0 0x58000>; 2577 #dma-cells = <3>; 2578 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2582 iommus = <&apps_smmu 0x056 0x0>; 2583 dma-channels = <4>; 2584 dma-channel-mask = <0xf>; 2585 status = "disabled"; 2586 }; 2587 2588 qupv3_id_3: geniqup@bc0000 { 2589 compatible = "qcom,geni-se-qup"; 2590 reg = <0x0 0xbc0000 0x0 0x6000>; 2591 #address-cells = <2>; 2592 #size-cells = <2>; 2593 ranges; 2594 clock-names = "m-ahb", "s-ahb"; 2595 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2596 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2597 iommus = <&apps_smmu 0x43 0x0>; 2598 status = "disabled"; 2599 2600 i2c21: i2c@b80000 { 2601 compatible = "qcom,geni-i2c"; 2602 reg = <0x0 0xb80000 0x0 0x4000>; 2603 #address-cells = <1>; 2604 #size-cells = <0>; 2605 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2606 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2607 clock-names = "se"; 2608 pinctrl-0 = <&qup_i2c21_default>; 2609 pinctrl-names = "default"; 2610 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2611 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2613 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2614 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2616 interconnect-names = "qup-core", 2617 "qup-config", 2618 "qup-memory"; 2619 power-domains = <&rpmhpd SA8775P_CX>; 2620 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2621 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2622 dma-names = "tx", 2623 "rx"; 2624 status = "disabled"; 2625 }; 2626 2627 spi21: spi@b80000 { 2628 compatible = "qcom,geni-spi"; 2629 reg = <0x0 0xb80000 0x0 0x4000>; 2630 #address-cells = <1>; 2631 #size-cells = <0>; 2632 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2633 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2634 clock-names = "se"; 2635 pinctrl-0 = <&qup_spi21_default>; 2636 pinctrl-names = "default"; 2637 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2638 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2639 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2640 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2641 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2643 interconnect-names = "qup-core", 2644 "qup-config", 2645 "qup-memory"; 2646 power-domains = <&rpmhpd SA8775P_CX>; 2647 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2648 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2649 dma-names = "tx", 2650 "rx"; 2651 status = "disabled"; 2652 }; 2653 2654 uart21: serial@b80000 { 2655 compatible = "qcom,geni-uart"; 2656 reg = <0x0 0x00b80000 0x0 0x4000>; 2657 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2658 clock-names = "se"; 2659 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2660 interconnect-names = "qup-core", "qup-config"; 2661 pinctrl-0 = <&qup_uart21_default>; 2662 pinctrl-names = "default"; 2663 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2664 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2665 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2666 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2667 power-domains = <&rpmhpd SA8775P_CX>; 2668 operating-points-v2 = <&qup_opp_table_100mhz>; 2669 status = "disabled"; 2670 }; 2671 }; 2672 2673 rng: rng@10d2000 { 2674 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2675 reg = <0 0x010d2000 0 0x1000>; 2676 }; 2677 2678 ufs_mem_hc: ufshc@1d84000 { 2679 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2680 reg = <0x0 0x01d84000 0x0 0x3000>; 2681 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2682 phys = <&ufs_mem_phy>; 2683 phy-names = "ufsphy"; 2684 lanes-per-direction = <2>; 2685 #reset-cells = <1>; 2686 resets = <&gcc GCC_UFS_PHY_BCR>; 2687 reset-names = "rst"; 2688 power-domains = <&gcc UFS_PHY_GDSC>; 2689 required-opps = <&rpmhpd_opp_nom>; 2690 iommus = <&apps_smmu 0x100 0x0>; 2691 dma-coherent; 2692 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2693 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2694 <&gcc GCC_UFS_PHY_AHB_CLK>, 2695 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2696 <&rpmhcc RPMH_CXO_CLK>, 2697 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2698 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2699 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2700 clock-names = "core_clk", 2701 "bus_aggr_clk", 2702 "iface_clk", 2703 "core_clk_unipro", 2704 "ref_clk", 2705 "tx_lane0_sync_clk", 2706 "rx_lane0_sync_clk", 2707 "rx_lane1_sync_clk"; 2708 freq-table-hz = <75000000 300000000>, 2709 <0 0>, 2710 <0 0>, 2711 <75000000 300000000>, 2712 <0 0>, 2713 <0 0>, 2714 <0 0>, 2715 <0 0>; 2716 qcom,ice = <&ice>; 2717 status = "disabled"; 2718 }; 2719 2720 ufs_mem_phy: phy@1d87000 { 2721 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2722 reg = <0x0 0x01d87000 0x0 0xe10>; 2723 /* 2724 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2725 * enables the CXO clock to eDP *and* UFS PHY. 2726 */ 2727 clocks = <&rpmhcc RPMH_CXO_CLK>, 2728 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2729 <&gcc GCC_EDP_REF_CLKREF_EN>; 2730 clock-names = "ref", "ref_aux", "qref"; 2731 power-domains = <&gcc UFS_PHY_GDSC>; 2732 resets = <&ufs_mem_hc 0>; 2733 reset-names = "ufsphy"; 2734 #phy-cells = <0>; 2735 status = "disabled"; 2736 }; 2737 2738 ice: crypto@1d88000 { 2739 compatible = "qcom,sa8775p-inline-crypto-engine", 2740 "qcom,inline-crypto-engine"; 2741 reg = <0x0 0x01d88000 0x0 0x18000>; 2742 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2743 }; 2744 2745 cryptobam: dma-controller@1dc4000 { 2746 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2747 reg = <0x0 0x01dc4000 0x0 0x28000>; 2748 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2749 #dma-cells = <1>; 2750 qcom,ee = <0>; 2751 qcom,num-ees = <4>; 2752 num-channels = <20>; 2753 qcom,controlled-remotely; 2754 iommus = <&apps_smmu 0x480 0x00>, 2755 <&apps_smmu 0x481 0x00>; 2756 }; 2757 2758 ctcu@4001000 { 2759 compatible = "qcom,sa8775p-ctcu"; 2760 reg = <0x0 0x04001000 0x0 0x1000>; 2761 2762 clocks = <&aoss_qmp>; 2763 clock-names = "apb"; 2764 2765 in-ports { 2766 #address-cells = <1>; 2767 #size-cells = <0>; 2768 2769 port@0 { 2770 reg = <0>; 2771 2772 ctcu_in0: endpoint { 2773 remote-endpoint = <&etr0_out>; 2774 }; 2775 }; 2776 2777 port@1 { 2778 reg = <1>; 2779 2780 ctcu_in1: endpoint { 2781 remote-endpoint = <&etr1_out>; 2782 }; 2783 }; 2784 }; 2785 }; 2786 2787 stm: stm@4002000 { 2788 compatible = "arm,coresight-stm", "arm,primecell"; 2789 reg = <0x0 0x4002000 0x0 0x1000>, 2790 <0x0 0x16280000 0x0 0x180000>; 2791 reg-names = "stm-base", "stm-stimulus-base"; 2792 2793 clocks = <&aoss_qmp>; 2794 clock-names = "apb_pclk"; 2795 2796 out-ports { 2797 port { 2798 stm_out: endpoint { 2799 remote-endpoint = 2800 <&funnel0_in7>; 2801 }; 2802 }; 2803 }; 2804 }; 2805 2806 tpdm@4003000 { 2807 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2808 reg = <0x0 0x4003000 0x0 0x1000>; 2809 2810 clocks = <&aoss_qmp>; 2811 clock-names = "apb_pclk"; 2812 2813 qcom,cmb-element-bits = <32>; 2814 qcom,cmb-msrs-num = <32>; 2815 status = "disabled"; 2816 2817 out-ports { 2818 port { 2819 qdss_tpdm0_out: endpoint { 2820 remote-endpoint = 2821 <&qdss_tpda_in0>; 2822 }; 2823 }; 2824 }; 2825 }; 2826 2827 tpda@4004000 { 2828 compatible = "qcom,coresight-tpda", "arm,primecell"; 2829 reg = <0x0 0x4004000 0x0 0x1000>; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 out-ports { 2835 port { 2836 qdss_tpda_out: endpoint { 2837 remote-endpoint = 2838 <&funnel0_in6>; 2839 }; 2840 }; 2841 }; 2842 2843 in-ports { 2844 #address-cells = <1>; 2845 #size-cells = <0>; 2846 2847 port@0 { 2848 reg = <0>; 2849 qdss_tpda_in0: endpoint { 2850 remote-endpoint = 2851 <&qdss_tpdm0_out>; 2852 }; 2853 }; 2854 2855 port@1 { 2856 reg = <1>; 2857 qdss_tpda_in1: endpoint { 2858 remote-endpoint = 2859 <&qdss_tpdm1_out>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 tpdm@400f000 { 2866 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2867 reg = <0x0 0x400f000 0x0 0x1000>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 2872 qcom,cmb-element-bits = <32>; 2873 qcom,cmb-msrs-num = <32>; 2874 2875 out-ports { 2876 port { 2877 qdss_tpdm1_out: endpoint { 2878 remote-endpoint = 2879 <&qdss_tpda_in1>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 funnel@4041000 { 2886 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2887 reg = <0x0 0x4041000 0x0 0x1000>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 2892 out-ports { 2893 port { 2894 funnel0_out: endpoint { 2895 remote-endpoint = 2896 <&qdss_funnel_in0>; 2897 }; 2898 }; 2899 }; 2900 2901 in-ports { 2902 #address-cells = <1>; 2903 #size-cells = <0>; 2904 2905 port@6 { 2906 reg = <6>; 2907 funnel0_in6: endpoint { 2908 remote-endpoint = 2909 <&qdss_tpda_out>; 2910 }; 2911 }; 2912 2913 port@7 { 2914 reg = <7>; 2915 funnel0_in7: endpoint { 2916 remote-endpoint = 2917 <&stm_out>; 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 funnel@4042000 { 2924 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2925 reg = <0x0 0x4042000 0x0 0x1000>; 2926 2927 clocks = <&aoss_qmp>; 2928 clock-names = "apb_pclk"; 2929 2930 out-ports { 2931 port { 2932 funnel1_out: endpoint { 2933 remote-endpoint = 2934 <&qdss_funnel_in1>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 #address-cells = <1>; 2941 #size-cells = <0>; 2942 2943 port@4 { 2944 reg = <4>; 2945 funnel1_in4: endpoint { 2946 remote-endpoint = 2947 <&apss_funnel1_out>; 2948 }; 2949 }; 2950 }; 2951 }; 2952 2953 funnel@4045000 { 2954 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2955 reg = <0x0 0x4045000 0x0 0x1000>; 2956 2957 clocks = <&aoss_qmp>; 2958 clock-names = "apb_pclk"; 2959 2960 out-ports { 2961 port { 2962 qdss_funnel_out: endpoint { 2963 remote-endpoint = 2964 <&aoss_funnel_in7>; 2965 }; 2966 }; 2967 }; 2968 2969 in-ports { 2970 #address-cells = <1>; 2971 #size-cells = <0>; 2972 2973 port@0 { 2974 reg = <0>; 2975 qdss_funnel_in0: endpoint { 2976 remote-endpoint = 2977 <&funnel0_out>; 2978 }; 2979 }; 2980 2981 port@1 { 2982 reg = <1>; 2983 qdss_funnel_in1: endpoint { 2984 remote-endpoint = 2985 <&funnel1_out>; 2986 }; 2987 }; 2988 }; 2989 }; 2990 2991 replicator@4046000 { 2992 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2993 reg = <0x0 0x04046000 0x0 0x1000>; 2994 2995 clocks = <&aoss_qmp>; 2996 clock-names = "apb_pclk"; 2997 2998 in-ports { 2999 port { 3000 qdss_rep_in: endpoint { 3001 remote-endpoint = <&swao_rep_out0>; 3002 }; 3003 }; 3004 }; 3005 3006 out-ports { 3007 port { 3008 qdss_rep_out0: endpoint { 3009 remote-endpoint = <&etr_rep_in>; 3010 }; 3011 }; 3012 }; 3013 }; 3014 3015 tmc_etr: tmc@4048000 { 3016 compatible = "arm,coresight-tmc", "arm,primecell"; 3017 reg = <0x0 0x04048000 0x0 0x1000>; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 iommus = <&apps_smmu 0x04c0 0x00>; 3022 3023 arm,scatter-gather; 3024 3025 in-ports { 3026 port { 3027 etr0_in: endpoint { 3028 remote-endpoint = <&etr_rep_out0>; 3029 }; 3030 }; 3031 }; 3032 3033 out-ports { 3034 port { 3035 etr0_out: endpoint { 3036 remote-endpoint = <&ctcu_in0>; 3037 }; 3038 }; 3039 }; 3040 }; 3041 3042 replicator@404e000 { 3043 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3044 reg = <0x0 0x0404e000 0x0 0x1000>; 3045 3046 clocks = <&aoss_qmp>; 3047 clock-names = "apb_pclk"; 3048 3049 in-ports { 3050 port { 3051 etr_rep_in: endpoint { 3052 remote-endpoint = <&qdss_rep_out0>; 3053 }; 3054 }; 3055 }; 3056 3057 out-ports { 3058 #address-cells = <1>; 3059 #size-cells = <0>; 3060 3061 port@0 { 3062 reg = <0>; 3063 3064 etr_rep_out0: endpoint { 3065 remote-endpoint = <&etr0_in>; 3066 }; 3067 }; 3068 3069 port@1 { 3070 reg = <1>; 3071 3072 etr_rep_out1: endpoint { 3073 remote-endpoint = <&etr1_in>; 3074 }; 3075 }; 3076 }; 3077 }; 3078 3079 tmc_etr1: tmc@404f000 { 3080 compatible = "arm,coresight-tmc", "arm,primecell"; 3081 reg = <0x0 0x0404f000 0x0 0x1000>; 3082 3083 clocks = <&aoss_qmp>; 3084 clock-names = "apb_pclk"; 3085 iommus = <&apps_smmu 0x04a0 0x40>; 3086 3087 arm,scatter-gather; 3088 arm,buffer-size = <0x400000>; 3089 3090 in-ports { 3091 port { 3092 etr1_in: endpoint { 3093 remote-endpoint = <&etr_rep_out1>; 3094 }; 3095 }; 3096 }; 3097 3098 out-ports { 3099 port { 3100 etr1_out: endpoint { 3101 remote-endpoint = <&ctcu_in1>; 3102 }; 3103 }; 3104 }; 3105 }; 3106 3107 funnel@4b04000 { 3108 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3109 reg = <0x0 0x4b04000 0x0 0x1000>; 3110 3111 clocks = <&aoss_qmp>; 3112 clock-names = "apb_pclk"; 3113 3114 out-ports { 3115 port { 3116 aoss_funnel_out: endpoint { 3117 remote-endpoint = 3118 <&etf0_in>; 3119 }; 3120 }; 3121 }; 3122 3123 in-ports { 3124 #address-cells = <1>; 3125 #size-cells = <0>; 3126 3127 port@6 { 3128 reg = <6>; 3129 aoss_funnel_in6: endpoint { 3130 remote-endpoint = 3131 <&aoss_tpda_out>; 3132 }; 3133 }; 3134 3135 port@7 { 3136 reg = <7>; 3137 aoss_funnel_in7: endpoint { 3138 remote-endpoint = 3139 <&qdss_funnel_out>; 3140 }; 3141 }; 3142 }; 3143 }; 3144 3145 tmc_etf: tmc@4b05000 { 3146 compatible = "arm,coresight-tmc", "arm,primecell"; 3147 reg = <0x0 0x4b05000 0x0 0x1000>; 3148 3149 clocks = <&aoss_qmp>; 3150 clock-names = "apb_pclk"; 3151 3152 out-ports { 3153 port { 3154 etf0_out: endpoint { 3155 remote-endpoint = 3156 <&swao_rep_in>; 3157 }; 3158 }; 3159 }; 3160 3161 in-ports { 3162 port { 3163 etf0_in: endpoint { 3164 remote-endpoint = 3165 <&aoss_funnel_out>; 3166 }; 3167 }; 3168 }; 3169 }; 3170 3171 replicator@4b06000 { 3172 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3173 reg = <0x0 0x4b06000 0x0 0x1000>; 3174 3175 clocks = <&aoss_qmp>; 3176 clock-names = "apb_pclk"; 3177 3178 out-ports { 3179 #address-cells = <1>; 3180 #size-cells = <0>; 3181 3182 port@0 { 3183 reg = <0>; 3184 3185 swao_rep_out0: endpoint { 3186 remote-endpoint = <&qdss_rep_in>; 3187 }; 3188 }; 3189 3190 port@1 { 3191 reg = <1>; 3192 swao_rep_out1: endpoint { 3193 remote-endpoint = 3194 <&eud_in>; 3195 }; 3196 }; 3197 }; 3198 3199 in-ports { 3200 port { 3201 swao_rep_in: endpoint { 3202 remote-endpoint = 3203 <&etf0_out>; 3204 }; 3205 }; 3206 }; 3207 }; 3208 3209 tpda@4b08000 { 3210 compatible = "qcom,coresight-tpda", "arm,primecell"; 3211 reg = <0x0 0x4b08000 0x0 0x1000>; 3212 3213 clocks = <&aoss_qmp>; 3214 clock-names = "apb_pclk"; 3215 3216 out-ports { 3217 port { 3218 aoss_tpda_out: endpoint { 3219 remote-endpoint = 3220 <&aoss_funnel_in6>; 3221 }; 3222 }; 3223 }; 3224 3225 in-ports { 3226 #address-cells = <1>; 3227 #size-cells = <0>; 3228 3229 port@0 { 3230 reg = <0>; 3231 aoss_tpda_in0: endpoint { 3232 remote-endpoint = 3233 <&aoss_tpdm0_out>; 3234 }; 3235 }; 3236 3237 port@1 { 3238 reg = <1>; 3239 aoss_tpda_in1: endpoint { 3240 remote-endpoint = 3241 <&aoss_tpdm1_out>; 3242 }; 3243 }; 3244 3245 port@2 { 3246 reg = <2>; 3247 aoss_tpda_in2: endpoint { 3248 remote-endpoint = 3249 <&aoss_tpdm2_out>; 3250 }; 3251 }; 3252 3253 port@3 { 3254 reg = <3>; 3255 aoss_tpda_in3: endpoint { 3256 remote-endpoint = 3257 <&aoss_tpdm3_out>; 3258 }; 3259 }; 3260 3261 port@4 { 3262 reg = <4>; 3263 aoss_tpda_in4: endpoint { 3264 remote-endpoint = 3265 <&aoss_tpdm4_out>; 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 tpdm@4b09000 { 3272 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3273 reg = <0x0 0x4b09000 0x0 0x1000>; 3274 3275 clocks = <&aoss_qmp>; 3276 clock-names = "apb_pclk"; 3277 3278 qcom,cmb-element-bits = <64>; 3279 qcom,cmb-msrs-num = <32>; 3280 3281 out-ports { 3282 port { 3283 aoss_tpdm0_out: endpoint { 3284 remote-endpoint = 3285 <&aoss_tpda_in0>; 3286 }; 3287 }; 3288 }; 3289 }; 3290 3291 tpdm@4b0a000 { 3292 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3293 reg = <0x0 0x4b0a000 0x0 0x1000>; 3294 3295 clocks = <&aoss_qmp>; 3296 clock-names = "apb_pclk"; 3297 3298 qcom,cmb-element-bits = <64>; 3299 qcom,cmb-msrs-num = <32>; 3300 3301 out-ports { 3302 port { 3303 aoss_tpdm1_out: endpoint { 3304 remote-endpoint = 3305 <&aoss_tpda_in1>; 3306 }; 3307 }; 3308 }; 3309 }; 3310 3311 tpdm@4b0b000 { 3312 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3313 reg = <0x0 0x4b0b000 0x0 0x1000>; 3314 3315 clocks = <&aoss_qmp>; 3316 clock-names = "apb_pclk"; 3317 3318 qcom,cmb-element-bits = <64>; 3319 qcom,cmb-msrs-num = <32>; 3320 3321 out-ports { 3322 port { 3323 aoss_tpdm2_out: endpoint { 3324 remote-endpoint = 3325 <&aoss_tpda_in2>; 3326 }; 3327 }; 3328 }; 3329 }; 3330 3331 tpdm@4b0c000 { 3332 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3333 reg = <0x0 0x4b0c000 0x0 0x1000>; 3334 3335 clocks = <&aoss_qmp>; 3336 clock-names = "apb_pclk"; 3337 3338 qcom,cmb-element-bits = <64>; 3339 qcom,cmb-msrs-num = <32>; 3340 3341 out-ports { 3342 port { 3343 aoss_tpdm3_out: endpoint { 3344 remote-endpoint = 3345 <&aoss_tpda_in3>; 3346 }; 3347 }; 3348 }; 3349 }; 3350 3351 tpdm@4b0d000 { 3352 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3353 reg = <0x0 0x4b0d000 0x0 0x1000>; 3354 3355 clocks = <&aoss_qmp>; 3356 clock-names = "apb_pclk"; 3357 3358 qcom,dsb-element-bits = <32>; 3359 qcom,dsb-msrs-num = <32>; 3360 3361 out-ports { 3362 port { 3363 aoss_tpdm4_out: endpoint { 3364 remote-endpoint = 3365 <&aoss_tpda_in4>; 3366 }; 3367 }; 3368 }; 3369 }; 3370 3371 aoss_cti: cti@4b13000 { 3372 compatible = "arm,coresight-cti", "arm,primecell"; 3373 reg = <0x0 0x4b13000 0x0 0x1000>; 3374 3375 clocks = <&aoss_qmp>; 3376 clock-names = "apb_pclk"; 3377 }; 3378 3379 etm@6040000 { 3380 compatible = "arm,primecell"; 3381 reg = <0x0 0x6040000 0x0 0x1000>; 3382 cpu = <&cpu0>; 3383 3384 clocks = <&aoss_qmp>; 3385 clock-names = "apb_pclk"; 3386 arm,coresight-loses-context-with-cpu; 3387 qcom,skip-power-up; 3388 3389 out-ports { 3390 port { 3391 etm0_out: endpoint { 3392 remote-endpoint = 3393 <&apss_funnel0_in0>; 3394 }; 3395 }; 3396 }; 3397 }; 3398 3399 etm@6140000 { 3400 compatible = "arm,primecell"; 3401 reg = <0x0 0x6140000 0x0 0x1000>; 3402 cpu = <&cpu1>; 3403 3404 clocks = <&aoss_qmp>; 3405 clock-names = "apb_pclk"; 3406 arm,coresight-loses-context-with-cpu; 3407 qcom,skip-power-up; 3408 3409 out-ports { 3410 port { 3411 etm1_out: endpoint { 3412 remote-endpoint = 3413 <&apss_funnel0_in1>; 3414 }; 3415 }; 3416 }; 3417 }; 3418 3419 etm@6240000 { 3420 compatible = "arm,primecell"; 3421 reg = <0x0 0x6240000 0x0 0x1000>; 3422 cpu = <&cpu2>; 3423 3424 clocks = <&aoss_qmp>; 3425 clock-names = "apb_pclk"; 3426 arm,coresight-loses-context-with-cpu; 3427 qcom,skip-power-up; 3428 3429 out-ports { 3430 port { 3431 etm2_out: endpoint { 3432 remote-endpoint = 3433 <&apss_funnel0_in2>; 3434 }; 3435 }; 3436 }; 3437 }; 3438 3439 etm@6340000 { 3440 compatible = "arm,primecell"; 3441 reg = <0x0 0x6340000 0x0 0x1000>; 3442 cpu = <&cpu3>; 3443 3444 clocks = <&aoss_qmp>; 3445 clock-names = "apb_pclk"; 3446 arm,coresight-loses-context-with-cpu; 3447 qcom,skip-power-up; 3448 3449 out-ports { 3450 port { 3451 etm3_out: endpoint { 3452 remote-endpoint = 3453 <&apss_funnel0_in3>; 3454 }; 3455 }; 3456 }; 3457 }; 3458 3459 etm@6440000 { 3460 compatible = "arm,primecell"; 3461 reg = <0x0 0x6440000 0x0 0x1000>; 3462 cpu = <&cpu4>; 3463 3464 clocks = <&aoss_qmp>; 3465 clock-names = "apb_pclk"; 3466 arm,coresight-loses-context-with-cpu; 3467 qcom,skip-power-up; 3468 3469 out-ports { 3470 port { 3471 etm4_out: endpoint { 3472 remote-endpoint = 3473 <&apss_funnel0_in4>; 3474 }; 3475 }; 3476 }; 3477 }; 3478 3479 etm@6540000 { 3480 compatible = "arm,primecell"; 3481 reg = <0x0 0x6540000 0x0 0x1000>; 3482 cpu = <&cpu5>; 3483 3484 clocks = <&aoss_qmp>; 3485 clock-names = "apb_pclk"; 3486 arm,coresight-loses-context-with-cpu; 3487 qcom,skip-power-up; 3488 3489 out-ports { 3490 port { 3491 etm5_out: endpoint { 3492 remote-endpoint = 3493 <&apss_funnel0_in5>; 3494 }; 3495 }; 3496 }; 3497 }; 3498 3499 etm@6640000 { 3500 compatible = "arm,primecell"; 3501 reg = <0x0 0x6640000 0x0 0x1000>; 3502 cpu = <&cpu6>; 3503 3504 clocks = <&aoss_qmp>; 3505 clock-names = "apb_pclk"; 3506 arm,coresight-loses-context-with-cpu; 3507 qcom,skip-power-up; 3508 3509 out-ports { 3510 port { 3511 etm6_out: endpoint { 3512 remote-endpoint = 3513 <&apss_funnel0_in6>; 3514 }; 3515 }; 3516 }; 3517 }; 3518 3519 etm@6740000 { 3520 compatible = "arm,primecell"; 3521 reg = <0x0 0x6740000 0x0 0x1000>; 3522 cpu = <&cpu7>; 3523 3524 clocks = <&aoss_qmp>; 3525 clock-names = "apb_pclk"; 3526 arm,coresight-loses-context-with-cpu; 3527 qcom,skip-power-up; 3528 3529 out-ports { 3530 port { 3531 etm7_out: endpoint { 3532 remote-endpoint = 3533 <&apss_funnel0_in7>; 3534 }; 3535 }; 3536 }; 3537 }; 3538 3539 funnel@6800000 { 3540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3541 reg = <0x0 0x6800000 0x0 0x1000>; 3542 3543 clocks = <&aoss_qmp>; 3544 clock-names = "apb_pclk"; 3545 3546 out-ports { 3547 port { 3548 apss_funnel0_out: endpoint { 3549 remote-endpoint = 3550 <&apss_funnel1_in0>; 3551 }; 3552 }; 3553 }; 3554 3555 in-ports { 3556 #address-cells = <1>; 3557 #size-cells = <0>; 3558 3559 port@0 { 3560 reg = <0>; 3561 apss_funnel0_in0: endpoint { 3562 remote-endpoint = 3563 <&etm0_out>; 3564 }; 3565 }; 3566 3567 port@1 { 3568 reg = <1>; 3569 apss_funnel0_in1: endpoint { 3570 remote-endpoint = 3571 <&etm1_out>; 3572 }; 3573 }; 3574 3575 port@2 { 3576 reg = <2>; 3577 apss_funnel0_in2: endpoint { 3578 remote-endpoint = 3579 <&etm2_out>; 3580 }; 3581 }; 3582 3583 port@3 { 3584 reg = <3>; 3585 apss_funnel0_in3: endpoint { 3586 remote-endpoint = 3587 <&etm3_out>; 3588 }; 3589 }; 3590 3591 port@4 { 3592 reg = <4>; 3593 apss_funnel0_in4: endpoint { 3594 remote-endpoint = 3595 <&etm4_out>; 3596 }; 3597 }; 3598 3599 port@5 { 3600 reg = <5>; 3601 apss_funnel0_in5: endpoint { 3602 remote-endpoint = 3603 <&etm5_out>; 3604 }; 3605 }; 3606 3607 port@6 { 3608 reg = <6>; 3609 apss_funnel0_in6: endpoint { 3610 remote-endpoint = 3611 <&etm6_out>; 3612 }; 3613 }; 3614 3615 port@7 { 3616 reg = <7>; 3617 apss_funnel0_in7: endpoint { 3618 remote-endpoint = 3619 <&etm7_out>; 3620 }; 3621 }; 3622 }; 3623 }; 3624 3625 funnel@6810000 { 3626 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3627 reg = <0x0 0x6810000 0x0 0x1000>; 3628 3629 clocks = <&aoss_qmp>; 3630 clock-names = "apb_pclk"; 3631 3632 out-ports { 3633 port { 3634 apss_funnel1_out: endpoint { 3635 remote-endpoint = 3636 <&funnel1_in4>; 3637 }; 3638 }; 3639 }; 3640 3641 in-ports { 3642 #address-cells = <1>; 3643 #size-cells = <0>; 3644 3645 port@0 { 3646 reg = <0>; 3647 apss_funnel1_in0: endpoint { 3648 remote-endpoint = 3649 <&apss_funnel0_out>; 3650 }; 3651 }; 3652 3653 port@3 { 3654 reg = <3>; 3655 apss_funnel1_in3: endpoint { 3656 remote-endpoint = 3657 <&apss_tpda_out>; 3658 }; 3659 }; 3660 }; 3661 }; 3662 3663 tpdm@6860000 { 3664 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3665 reg = <0x0 0x6860000 0x0 0x1000>; 3666 3667 clocks = <&aoss_qmp>; 3668 clock-names = "apb_pclk"; 3669 3670 qcom,cmb-element-bits = <64>; 3671 qcom,cmb-msrs-num = <32>; 3672 3673 out-ports { 3674 port { 3675 apss_tpdm3_out: endpoint { 3676 remote-endpoint = 3677 <&apss_tpda_in3>; 3678 }; 3679 }; 3680 }; 3681 }; 3682 3683 tpdm@6861000 { 3684 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3685 reg = <0x0 0x6861000 0x0 0x1000>; 3686 3687 clocks = <&aoss_qmp>; 3688 clock-names = "apb_pclk"; 3689 3690 qcom,dsb-element-bits = <32>; 3691 qcom,dsb-msrs-num = <32>; 3692 3693 out-ports { 3694 port { 3695 apss_tpdm4_out: endpoint { 3696 remote-endpoint = 3697 <&apss_tpda_in4>; 3698 }; 3699 }; 3700 }; 3701 }; 3702 3703 tpda@6863000 { 3704 compatible = "qcom,coresight-tpda", "arm,primecell"; 3705 reg = <0x0 0x6863000 0x0 0x1000>; 3706 3707 clocks = <&aoss_qmp>; 3708 clock-names = "apb_pclk"; 3709 3710 out-ports { 3711 port { 3712 apss_tpda_out: endpoint { 3713 remote-endpoint = 3714 <&apss_funnel1_in3>; 3715 }; 3716 }; 3717 }; 3718 3719 in-ports { 3720 #address-cells = <1>; 3721 #size-cells = <0>; 3722 3723 port@0 { 3724 reg = <0>; 3725 apss_tpda_in0: endpoint { 3726 remote-endpoint = 3727 <&apss_tpdm0_out>; 3728 }; 3729 }; 3730 3731 port@1 { 3732 reg = <1>; 3733 apss_tpda_in1: endpoint { 3734 remote-endpoint = 3735 <&apss_tpdm1_out>; 3736 }; 3737 }; 3738 3739 port@2 { 3740 reg = <2>; 3741 apss_tpda_in2: endpoint { 3742 remote-endpoint = 3743 <&apss_tpdm2_out>; 3744 }; 3745 }; 3746 3747 port@3 { 3748 reg = <3>; 3749 apss_tpda_in3: endpoint { 3750 remote-endpoint = 3751 <&apss_tpdm3_out>; 3752 }; 3753 }; 3754 3755 port@4 { 3756 reg = <4>; 3757 apss_tpda_in4: endpoint { 3758 remote-endpoint = 3759 <&apss_tpdm4_out>; 3760 }; 3761 }; 3762 }; 3763 }; 3764 3765 tpdm@68a0000 { 3766 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3767 reg = <0x0 0x68a0000 0x0 0x1000>; 3768 3769 clocks = <&aoss_qmp>; 3770 clock-names = "apb_pclk"; 3771 3772 qcom,cmb-element-bits = <32>; 3773 qcom,cmb-msrs-num = <32>; 3774 3775 out-ports { 3776 port { 3777 apss_tpdm0_out: endpoint { 3778 remote-endpoint = 3779 <&apss_tpda_in0>; 3780 }; 3781 }; 3782 }; 3783 }; 3784 3785 tpdm@68b0000 { 3786 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3787 reg = <0x0 0x68b0000 0x0 0x1000>; 3788 3789 clocks = <&aoss_qmp>; 3790 clock-names = "apb_pclk"; 3791 3792 qcom,cmb-element-bits = <32>; 3793 qcom,cmb-msrs-num = <32>; 3794 3795 out-ports { 3796 port { 3797 apss_tpdm1_out: endpoint { 3798 remote-endpoint = 3799 <&apss_tpda_in1>; 3800 }; 3801 }; 3802 }; 3803 }; 3804 3805 tpdm@68c0000 { 3806 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3807 reg = <0x0 0x68c0000 0x0 0x1000>; 3808 3809 clocks = <&aoss_qmp>; 3810 clock-names = "apb_pclk"; 3811 3812 qcom,dsb-element-bits = <32>; 3813 qcom,dsb-msrs-num = <32>; 3814 3815 out-ports { 3816 port { 3817 apss_tpdm2_out: endpoint { 3818 remote-endpoint = 3819 <&apss_tpda_in2>; 3820 }; 3821 }; 3822 }; 3823 }; 3824 3825 usb_0_hsphy: phy@88e4000 { 3826 compatible = "qcom,sa8775p-usb-hs-phy", 3827 "qcom,usb-snps-hs-5nm-phy"; 3828 reg = <0 0x088e4000 0 0x120>; 3829 clocks = <&rpmhcc RPMH_CXO_CLK>; 3830 clock-names = "ref"; 3831 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3832 3833 #phy-cells = <0>; 3834 3835 status = "disabled"; 3836 }; 3837 3838 usb_0_qmpphy: phy@88e8000 { 3839 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3840 reg = <0 0x088e8000 0 0x2000>; 3841 3842 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3843 <&gcc GCC_USB_CLKREF_EN>, 3844 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3845 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3846 clock-names = "aux", "ref", "com_aux", "pipe"; 3847 3848 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3849 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3850 reset-names = "phy", "phy_phy"; 3851 3852 power-domains = <&gcc USB30_PRIM_GDSC>; 3853 3854 #clock-cells = <0>; 3855 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3856 3857 #phy-cells = <0>; 3858 3859 status = "disabled"; 3860 }; 3861 3862 usb_0: usb@a6f8800 { 3863 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3864 reg = <0 0x0a6f8800 0 0x400>; 3865 #address-cells = <2>; 3866 #size-cells = <2>; 3867 ranges; 3868 3869 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3870 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3871 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3872 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3873 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3874 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3875 3876 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3877 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3878 assigned-clock-rates = <19200000>, <200000000>; 3879 3880 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 3881 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3882 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3883 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3884 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 3885 interrupt-names = "pwr_event", 3886 "hs_phy_irq", 3887 "dp_hs_phy_irq", 3888 "dm_hs_phy_irq", 3889 "ss_phy_irq"; 3890 3891 power-domains = <&gcc USB30_PRIM_GDSC>; 3892 required-opps = <&rpmhpd_opp_nom>; 3893 3894 resets = <&gcc GCC_USB30_PRIM_BCR>; 3895 3896 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3898 interconnect-names = "usb-ddr", "apps-usb"; 3899 3900 wakeup-source; 3901 3902 status = "disabled"; 3903 3904 usb_0_dwc3: usb@a600000 { 3905 compatible = "snps,dwc3"; 3906 reg = <0 0x0a600000 0 0xe000>; 3907 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 3908 iommus = <&apps_smmu 0x080 0x0>; 3909 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 3910 phy-names = "usb2-phy", "usb3-phy"; 3911 snps,dis-u1-entry-quirk; 3912 snps,dis-u2-entry-quirk; 3913 }; 3914 }; 3915 3916 usb_1_hsphy: phy@88e6000 { 3917 compatible = "qcom,sa8775p-usb-hs-phy", 3918 "qcom,usb-snps-hs-5nm-phy"; 3919 reg = <0 0x088e6000 0 0x120>; 3920 clocks = <&gcc GCC_USB_CLKREF_EN>; 3921 clock-names = "ref"; 3922 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3923 3924 #phy-cells = <0>; 3925 3926 status = "disabled"; 3927 }; 3928 3929 usb_1_qmpphy: phy@88ea000 { 3930 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3931 reg = <0 0x088ea000 0 0x2000>; 3932 3933 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3934 <&gcc GCC_USB_CLKREF_EN>, 3935 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3936 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3937 clock-names = "aux", "ref", "com_aux", "pipe"; 3938 3939 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3940 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3941 reset-names = "phy", "phy_phy"; 3942 3943 power-domains = <&gcc USB30_SEC_GDSC>; 3944 3945 #clock-cells = <0>; 3946 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 3947 3948 #phy-cells = <0>; 3949 3950 status = "disabled"; 3951 }; 3952 3953 usb_1: usb@a8f8800 { 3954 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3955 reg = <0 0x0a8f8800 0 0x400>; 3956 #address-cells = <2>; 3957 #size-cells = <2>; 3958 ranges; 3959 3960 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3961 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3962 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3963 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3964 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3965 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3966 3967 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3968 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3969 assigned-clock-rates = <19200000>, <200000000>; 3970 3971 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 3972 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 3973 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3974 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 3975 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 3976 interrupt-names = "pwr_event", 3977 "hs_phy_irq", 3978 "dp_hs_phy_irq", 3979 "dm_hs_phy_irq", 3980 "ss_phy_irq"; 3981 3982 power-domains = <&gcc USB30_SEC_GDSC>; 3983 required-opps = <&rpmhpd_opp_nom>; 3984 3985 resets = <&gcc GCC_USB30_SEC_BCR>; 3986 3987 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3989 interconnect-names = "usb-ddr", "apps-usb"; 3990 3991 wakeup-source; 3992 3993 status = "disabled"; 3994 3995 usb_1_dwc3: usb@a800000 { 3996 compatible = "snps,dwc3"; 3997 reg = <0 0x0a800000 0 0xe000>; 3998 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 3999 iommus = <&apps_smmu 0x0a0 0x0>; 4000 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4001 phy-names = "usb2-phy", "usb3-phy"; 4002 snps,dis-u1-entry-quirk; 4003 snps,dis-u2-entry-quirk; 4004 }; 4005 }; 4006 4007 usb_2_hsphy: phy@88e7000 { 4008 compatible = "qcom,sa8775p-usb-hs-phy", 4009 "qcom,usb-snps-hs-5nm-phy"; 4010 reg = <0 0x088e7000 0 0x120>; 4011 clocks = <&gcc GCC_USB_CLKREF_EN>; 4012 clock-names = "ref"; 4013 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 4014 4015 #phy-cells = <0>; 4016 4017 status = "disabled"; 4018 }; 4019 4020 usb_2: usb@a4f8800 { 4021 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 4022 reg = <0 0x0a4f8800 0 0x400>; 4023 #address-cells = <2>; 4024 #size-cells = <2>; 4025 ranges; 4026 4027 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4028 <&gcc GCC_USB20_MASTER_CLK>, 4029 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4030 <&gcc GCC_USB20_SLEEP_CLK>, 4031 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4032 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4033 4034 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4035 <&gcc GCC_USB20_MASTER_CLK>; 4036 assigned-clock-rates = <19200000>, <200000000>; 4037 4038 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4039 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4040 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4041 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4042 interrupt-names = "pwr_event", 4043 "hs_phy_irq", 4044 "dp_hs_phy_irq", 4045 "dm_hs_phy_irq"; 4046 4047 power-domains = <&gcc USB20_PRIM_GDSC>; 4048 required-opps = <&rpmhpd_opp_nom>; 4049 4050 resets = <&gcc GCC_USB20_PRIM_BCR>; 4051 4052 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4054 interconnect-names = "usb-ddr", "apps-usb"; 4055 4056 wakeup-source; 4057 4058 status = "disabled"; 4059 4060 usb_2_dwc3: usb@a400000 { 4061 compatible = "snps,dwc3"; 4062 reg = <0 0x0a400000 0 0xe000>; 4063 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 4064 iommus = <&apps_smmu 0x020 0x0>; 4065 phys = <&usb_2_hsphy>; 4066 phy-names = "usb2-phy"; 4067 snps,dis-u1-entry-quirk; 4068 snps,dis-u2-entry-quirk; 4069 }; 4070 }; 4071 4072 tcsr_mutex: hwlock@1f40000 { 4073 compatible = "qcom,tcsr-mutex"; 4074 reg = <0x0 0x01f40000 0x0 0x20000>; 4075 #hwlock-cells = <1>; 4076 }; 4077 4078 tcsr: syscon@1fc0000 { 4079 compatible = "qcom,sa8775p-tcsr", "syscon"; 4080 reg = <0x0 0x1fc0000 0x0 0x30000>; 4081 }; 4082 4083 gpucc: clock-controller@3d90000 { 4084 compatible = "qcom,sa8775p-gpucc"; 4085 reg = <0x0 0x03d90000 0x0 0xa000>; 4086 clocks = <&rpmhcc RPMH_CXO_CLK>, 4087 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4088 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4089 clock-names = "bi_tcxo", 4090 "gcc_gpu_gpll0_clk_src", 4091 "gcc_gpu_gpll0_div_clk_src"; 4092 #clock-cells = <1>; 4093 #reset-cells = <1>; 4094 #power-domain-cells = <1>; 4095 }; 4096 4097 adreno_smmu: iommu@3da0000 { 4098 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4099 "qcom,smmu-500", "arm,mmu-500"; 4100 reg = <0x0 0x03da0000 0x0 0x20000>; 4101 #iommu-cells = <2>; 4102 #global-interrupts = <2>; 4103 dma-coherent; 4104 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4105 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4106 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4107 <&gpucc GPU_CC_AHB_CLK>, 4108 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4109 <&gpucc GPU_CC_CX_GMU_CLK>, 4110 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4111 <&gpucc GPU_CC_HUB_AON_CLK>; 4112 clock-names = "gcc_gpu_memnoc_gfx_clk", 4113 "gcc_gpu_snoc_dvm_gfx_clk", 4114 "gpu_cc_ahb_clk", 4115 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4116 "gpu_cc_cx_gmu_clk", 4117 "gpu_cc_hub_cx_int_clk", 4118 "gpu_cc_hub_aon_clk"; 4119 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4131 }; 4132 4133 serdes0: phy@8901000 { 4134 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4135 reg = <0x0 0x08901000 0x0 0xe10>; 4136 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4137 clock-names = "sgmi_ref"; 4138 #phy-cells = <0>; 4139 status = "disabled"; 4140 }; 4141 4142 serdes1: phy@8902000 { 4143 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4144 reg = <0x0 0x08902000 0x0 0xe10>; 4145 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4146 clock-names = "sgmi_ref"; 4147 #phy-cells = <0>; 4148 status = "disabled"; 4149 }; 4150 4151 pmu@9091000 { 4152 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4153 reg = <0x0 0x9091000 0x0 0x1000>; 4154 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4155 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4156 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4157 4158 operating-points-v2 = <&llcc_bwmon_opp_table>; 4159 4160 llcc_bwmon_opp_table: opp-table { 4161 compatible = "operating-points-v2"; 4162 4163 opp-0 { 4164 opp-peak-kBps = <762000>; 4165 }; 4166 4167 opp-1 { 4168 opp-peak-kBps = <1720000>; 4169 }; 4170 4171 opp-2 { 4172 opp-peak-kBps = <2086000>; 4173 }; 4174 4175 opp-3 { 4176 opp-peak-kBps = <2601000>; 4177 }; 4178 4179 opp-4 { 4180 opp-peak-kBps = <2929000>; 4181 }; 4182 4183 opp-5 { 4184 opp-peak-kBps = <5931000>; 4185 }; 4186 4187 opp-6 { 4188 opp-peak-kBps = <6515000>; 4189 }; 4190 4191 opp-7 { 4192 opp-peak-kBps = <7984000>; 4193 }; 4194 4195 opp-8 { 4196 opp-peak-kBps = <10437000>; 4197 }; 4198 4199 opp-9 { 4200 opp-peak-kBps = <12195000>; 4201 }; 4202 }; 4203 }; 4204 4205 pmu@90b5400 { 4206 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4207 reg = <0x0 0x90b5400 0x0 0x600>; 4208 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4209 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4210 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4211 4212 operating-points-v2 = <&cpu_bwmon_opp_table>; 4213 4214 cpu_bwmon_opp_table: opp-table { 4215 compatible = "operating-points-v2"; 4216 4217 opp-0 { 4218 opp-peak-kBps = <9155000>; 4219 }; 4220 4221 opp-1 { 4222 opp-peak-kBps = <12298000>; 4223 }; 4224 4225 opp-2 { 4226 opp-peak-kBps = <14236000>; 4227 }; 4228 4229 opp-3 { 4230 opp-peak-kBps = <16265000>; 4231 }; 4232 }; 4233 4234 }; 4235 4236 pmu@90b6400 { 4237 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4238 reg = <0x0 0x90b6400 0x0 0x600>; 4239 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4240 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4241 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4242 4243 operating-points-v2 = <&cpu_bwmon_opp_table>; 4244 }; 4245 4246 llcc: system-cache-controller@9200000 { 4247 compatible = "qcom,sa8775p-llcc"; 4248 reg = <0x0 0x09200000 0x0 0x80000>, 4249 <0x0 0x09300000 0x0 0x80000>, 4250 <0x0 0x09400000 0x0 0x80000>, 4251 <0x0 0x09500000 0x0 0x80000>, 4252 <0x0 0x09600000 0x0 0x80000>, 4253 <0x0 0x09700000 0x0 0x80000>, 4254 <0x0 0x09a00000 0x0 0x80000>; 4255 reg-names = "llcc0_base", 4256 "llcc1_base", 4257 "llcc2_base", 4258 "llcc3_base", 4259 "llcc4_base", 4260 "llcc5_base", 4261 "llcc_broadcast_base"; 4262 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4263 }; 4264 4265 iris: video-codec@aa00000 { 4266 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4267 4268 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4269 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4270 4271 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4272 <&videocc VIDEO_CC_MVS0_GDSC>, 4273 <&rpmhpd SA8775P_MX>, 4274 <&rpmhpd SA8775P_MMCX>; 4275 power-domain-names = "venus", 4276 "vcodec0", 4277 "mxc", 4278 "mmcx"; 4279 operating-points-v2 = <&iris_opp_table>; 4280 4281 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4282 <&videocc VIDEO_CC_MVS0C_CLK>, 4283 <&videocc VIDEO_CC_MVS0_CLK>; 4284 clock-names = "iface", 4285 "core", 4286 "vcodec0_core"; 4287 4288 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4289 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4290 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4291 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4292 interconnect-names = "cpu-cfg", 4293 "video-mem"; 4294 4295 memory-region = <&pil_video_mem>; 4296 4297 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4298 reset-names = "bus"; 4299 4300 iommus = <&apps_smmu 0x0880 0x0400>, 4301 <&apps_smmu 0x0887 0x0400>; 4302 dma-coherent; 4303 4304 status = "disabled"; 4305 4306 iris_opp_table: opp-table { 4307 compatible = "operating-points-v2"; 4308 4309 opp-366000000 { 4310 opp-hz = /bits/ 64 <366000000>; 4311 required-opps = <&rpmhpd_opp_svs_l1>, 4312 <&rpmhpd_opp_svs_l1>; 4313 }; 4314 4315 opp-444000000 { 4316 opp-hz = /bits/ 64 <444000000>; 4317 required-opps = <&rpmhpd_opp_nom>, 4318 <&rpmhpd_opp_nom>; 4319 }; 4320 4321 opp-533000000 { 4322 opp-hz = /bits/ 64 <533000000>; 4323 required-opps = <&rpmhpd_opp_turbo>, 4324 <&rpmhpd_opp_turbo>; 4325 }; 4326 4327 opp-560000000 { 4328 opp-hz = /bits/ 64 <560000000>; 4329 required-opps = <&rpmhpd_opp_turbo_l1>, 4330 <&rpmhpd_opp_turbo_l1>; 4331 }; 4332 }; 4333 }; 4334 4335 videocc: clock-controller@abf0000 { 4336 compatible = "qcom,sa8775p-videocc"; 4337 reg = <0x0 0x0abf0000 0x0 0x10000>; 4338 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4339 <&rpmhcc RPMH_CXO_CLK>, 4340 <&rpmhcc RPMH_CXO_CLK_A>, 4341 <&sleep_clk>; 4342 power-domains = <&rpmhpd SA8775P_MMCX>; 4343 #clock-cells = <1>; 4344 #reset-cells = <1>; 4345 #power-domain-cells = <1>; 4346 }; 4347 4348 camcc: clock-controller@ade0000 { 4349 compatible = "qcom,sa8775p-camcc"; 4350 reg = <0x0 0x0ade0000 0x0 0x20000>; 4351 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4352 <&rpmhcc RPMH_CXO_CLK>, 4353 <&rpmhcc RPMH_CXO_CLK_A>, 4354 <&sleep_clk>; 4355 power-domains = <&rpmhpd SA8775P_MMCX>; 4356 #clock-cells = <1>; 4357 #reset-cells = <1>; 4358 #power-domain-cells = <1>; 4359 }; 4360 4361 mdss0: display-subsystem@ae00000 { 4362 compatible = "qcom,sa8775p-mdss"; 4363 reg = <0x0 0x0ae00000 0x0 0x1000>; 4364 reg-names = "mdss"; 4365 4366 /* same path used twice */ 4367 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4368 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4369 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 4370 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4371 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4372 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4373 interconnect-names = "mdp0-mem", 4374 "mdp1-mem", 4375 "cpu-cfg"; 4376 4377 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 4378 4379 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 4380 4381 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4382 <&gcc GCC_DISP_HF_AXI_CLK>, 4383 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 4384 4385 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 4386 interrupt-controller; 4387 #interrupt-cells = <1>; 4388 4389 iommus = <&apps_smmu 0x1000 0x402>; 4390 4391 #address-cells = <2>; 4392 #size-cells = <2>; 4393 ranges; 4394 4395 status = "disabled"; 4396 4397 mdss0_mdp: display-controller@ae01000 { 4398 compatible = "qcom,sa8775p-dpu"; 4399 reg = <0x0 0x0ae01000 0x0 0x8f000>, 4400 <0x0 0x0aeb0000 0x0 0x3000>; 4401 reg-names = "mdp", "vbif"; 4402 4403 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4404 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4405 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 4406 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 4407 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 4408 clock-names = "bus", 4409 "iface", 4410 "lut", 4411 "core", 4412 "vsync"; 4413 4414 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 4415 assigned-clock-rates = <19200000>; 4416 4417 operating-points-v2 = <&mdss0_mdp_opp_table>; 4418 power-domains = <&rpmhpd SA8775P_MMCX>; 4419 4420 interrupt-parent = <&mdss0>; 4421 interrupts = <0>; 4422 4423 ports { 4424 #address-cells = <1>; 4425 #size-cells = <0>; 4426 4427 port@0 { 4428 reg = <0>; 4429 4430 dpu_intf0_out: endpoint { 4431 remote-endpoint = <&mdss0_dp0_in>; 4432 }; 4433 }; 4434 4435 port@1 { 4436 reg = <1>; 4437 4438 dpu_intf4_out: endpoint { 4439 remote-endpoint = <&mdss0_dp1_in>; 4440 }; 4441 }; 4442 4443 port@2 { 4444 reg = <2>; 4445 4446 dpu_intf1_out: endpoint { 4447 remote-endpoint = <&mdss0_dsi0_in>; 4448 }; 4449 }; 4450 4451 port@3 { 4452 reg = <3>; 4453 4454 dpu_intf2_out: endpoint { 4455 remote-endpoint = <&mdss0_dsi1_in>; 4456 }; 4457 }; 4458 }; 4459 4460 mdss0_mdp_opp_table: opp-table { 4461 compatible = "operating-points-v2"; 4462 4463 opp-375000000 { 4464 opp-hz = /bits/ 64 <375000000>; 4465 required-opps = <&rpmhpd_opp_svs_l1>; 4466 }; 4467 4468 opp-500000000 { 4469 opp-hz = /bits/ 64 <500000000>; 4470 required-opps = <&rpmhpd_opp_nom>; 4471 }; 4472 4473 opp-575000000 { 4474 opp-hz = /bits/ 64 <575000000>; 4475 required-opps = <&rpmhpd_opp_turbo>; 4476 }; 4477 4478 opp-650000000 { 4479 opp-hz = /bits/ 64 <650000000>; 4480 required-opps = <&rpmhpd_opp_turbo_l1>; 4481 }; 4482 }; 4483 }; 4484 4485 mdss0_dsi0: dsi@ae94000 { 4486 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4487 reg = <0x0 0x0ae94000 0x0 0x400>; 4488 reg-names = "dsi_ctrl"; 4489 4490 interrupt-parent = <&mdss0>; 4491 interrupts = <4>; 4492 4493 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 4494 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 4495 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 4496 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 4497 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4498 <&gcc GCC_DISP_HF_AXI_CLK>; 4499 clock-names = "byte", 4500 "byte_intf", 4501 "pixel", 4502 "core", 4503 "iface", 4504 "bus"; 4505 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 4506 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 4507 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4508 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 4509 phys = <&mdss0_dsi0_phy>; 4510 4511 operating-points-v2 = <&mdss_dsi_opp_table>; 4512 power-domains = <&rpmhpd SA8775P_MMCX>; 4513 4514 #address-cells = <1>; 4515 #size-cells = <0>; 4516 4517 status = "disabled"; 4518 4519 ports { 4520 #address-cells = <1>; 4521 #size-cells = <0>; 4522 4523 port@0 { 4524 reg = <0>; 4525 4526 mdss0_dsi0_in: endpoint { 4527 remote-endpoint = <&dpu_intf1_out>; 4528 }; 4529 }; 4530 4531 port@1 { 4532 reg = <1>; 4533 4534 mdss0_dsi0_out: endpoint{ }; 4535 }; 4536 }; 4537 4538 mdss_dsi_opp_table: opp-table { 4539 compatible = "operating-points-v2"; 4540 4541 opp-358000000 { 4542 opp-hz = /bits/ 64 <358000000>; 4543 required-opps = <&rpmhpd_opp_svs_l1>; 4544 }; 4545 }; 4546 }; 4547 4548 mdss0_dsi0_phy: phy@ae94400 { 4549 compatible = "qcom,sa8775p-dsi-phy-5nm"; 4550 reg = <0x0 0x0ae94400 0x0 0x200>, 4551 <0x0 0x0ae94600 0x0 0x280>, 4552 <0x0 0x0ae94900 0x0 0x27c>; 4553 reg-names = "dsi_phy", 4554 "dsi_phy_lane", 4555 "dsi_pll"; 4556 4557 #clock-cells = <1>; 4558 #phy-cells = <0>; 4559 4560 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4561 <&rpmhcc RPMH_CXO_CLK>; 4562 clock-names = "iface", "ref"; 4563 4564 status = "disabled"; 4565 }; 4566 4567 mdss0_dsi1: dsi@ae96000 { 4568 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4569 reg = <0x0 0x0ae96000 0x0 0x400>; 4570 reg-names = "dsi_ctrl"; 4571 4572 interrupt-parent = <&mdss0>; 4573 interrupts = <5>; 4574 4575 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 4576 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 4577 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 4578 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 4579 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4580 <&gcc GCC_DISP_HF_AXI_CLK>; 4581 clock-names = "byte", 4582 "byte_intf", 4583 "pixel", 4584 "core", 4585 "iface", 4586 "bus"; 4587 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 4588 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 4589 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 4590 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 4591 phys = <&mdss0_dsi1_phy>; 4592 4593 operating-points-v2 = <&mdss_dsi_opp_table>; 4594 power-domains = <&rpmhpd SA8775P_MMCX>; 4595 4596 #address-cells = <1>; 4597 #size-cells = <0>; 4598 4599 status = "disabled"; 4600 4601 ports { 4602 #address-cells = <1>; 4603 #size-cells = <0>; 4604 4605 port@0 { 4606 reg = <0>; 4607 4608 mdss0_dsi1_in: endpoint { 4609 remote-endpoint = <&dpu_intf2_out>; 4610 }; 4611 }; 4612 4613 port@1 { 4614 reg = <1>; 4615 4616 mdss0_dsi1_out: endpoint { }; 4617 }; 4618 }; 4619 }; 4620 4621 mdss0_dsi1_phy: phy@ae96400 { 4622 compatible = "qcom,sa8775p-dsi-phy-5nm"; 4623 reg = <0x0 0x0ae96400 0x0 0x200>, 4624 <0x0 0x0ae96600 0x0 0x280>, 4625 <0x0 0x0ae96900 0x0 0x27c>; 4626 reg-names = "dsi_phy", 4627 "dsi_phy_lane", 4628 "dsi_pll"; 4629 4630 #clock-cells = <1>; 4631 #phy-cells = <0>; 4632 4633 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4634 <&rpmhcc RPMH_CXO_CLK>; 4635 clock-names = "iface", "ref"; 4636 4637 status = "disabled"; 4638 }; 4639 4640 mdss0_dp0_phy: phy@aec2a00 { 4641 compatible = "qcom,sa8775p-edp-phy"; 4642 4643 reg = <0x0 0x0aec2a00 0x0 0x200>, 4644 <0x0 0x0aec2200 0x0 0xd0>, 4645 <0x0 0x0aec2600 0x0 0xd0>, 4646 <0x0 0x0aec2000 0x0 0x1c8>; 4647 4648 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 4649 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 4650 clock-names = "aux", 4651 "cfg_ahb"; 4652 4653 #clock-cells = <1>; 4654 #phy-cells = <0>; 4655 4656 status = "disabled"; 4657 }; 4658 4659 mdss0_dp1_phy: phy@aec5a00 { 4660 compatible = "qcom,sa8775p-edp-phy"; 4661 4662 reg = <0x0 0x0aec5a00 0x0 0x200>, 4663 <0x0 0x0aec5200 0x0 0xd0>, 4664 <0x0 0x0aec5600 0x0 0xd0>, 4665 <0x0 0x0aec5000 0x0 0x1c8>; 4666 4667 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 4668 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 4669 clock-names = "aux", 4670 "cfg_ahb"; 4671 4672 #clock-cells = <1>; 4673 #phy-cells = <0>; 4674 4675 status = "disabled"; 4676 }; 4677 4678 mdss0_dp0: displayport-controller@af54000 { 4679 compatible = "qcom,sa8775p-dp"; 4680 4681 reg = <0x0 0x0af54000 0x0 0x104>, 4682 <0x0 0x0af54200 0x0 0x0c0>, 4683 <0x0 0x0af55000 0x0 0x770>, 4684 <0x0 0x0af56000 0x0 0x09c>, 4685 <0x0 0x0af57000 0x0 0x09c>; 4686 4687 interrupt-parent = <&mdss0>; 4688 interrupts = <12>; 4689 4690 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4691 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 4692 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 4693 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4694 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4695 clock-names = "core_iface", 4696 "core_aux", 4697 "ctrl_link", 4698 "ctrl_link_iface", 4699 "stream_pixel"; 4700 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4701 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4702 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; 4703 phys = <&mdss0_dp0_phy>; 4704 phy-names = "dp"; 4705 4706 operating-points-v2 = <&dp_opp_table>; 4707 power-domains = <&rpmhpd SA8775P_MMCX>; 4708 4709 #sound-dai-cells = <0>; 4710 4711 status = "disabled"; 4712 4713 ports { 4714 #address-cells = <1>; 4715 #size-cells = <0>; 4716 4717 port@0 { 4718 reg = <0>; 4719 4720 mdss0_dp0_in: endpoint { 4721 remote-endpoint = <&dpu_intf0_out>; 4722 }; 4723 }; 4724 4725 port@1 { 4726 reg = <1>; 4727 4728 mdss0_dp0_out: endpoint { }; 4729 }; 4730 }; 4731 4732 dp_opp_table: opp-table { 4733 compatible = "operating-points-v2"; 4734 4735 opp-160000000 { 4736 opp-hz = /bits/ 64 <160000000>; 4737 required-opps = <&rpmhpd_opp_low_svs>; 4738 }; 4739 4740 opp-270000000 { 4741 opp-hz = /bits/ 64 <270000000>; 4742 required-opps = <&rpmhpd_opp_svs>; 4743 }; 4744 4745 opp-540000000 { 4746 opp-hz = /bits/ 64 <540000000>; 4747 required-opps = <&rpmhpd_opp_svs_l1>; 4748 }; 4749 4750 opp-810000000 { 4751 opp-hz = /bits/ 64 <810000000>; 4752 required-opps = <&rpmhpd_opp_nom>; 4753 }; 4754 }; 4755 }; 4756 4757 mdss0_dp1: displayport-controller@af5c000 { 4758 compatible = "qcom,sa8775p-dp"; 4759 4760 reg = <0x0 0x0af5c000 0x0 0x104>, 4761 <0x0 0x0af5c200 0x0 0x0c0>, 4762 <0x0 0x0af5d000 0x0 0x770>, 4763 <0x0 0x0af5e000 0x0 0x09c>, 4764 <0x0 0x0af5f000 0x0 0x09c>; 4765 4766 interrupt-parent = <&mdss0>; 4767 interrupts = <13>; 4768 4769 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4770 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 4771 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 4772 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4773 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4774 clock-names = "core_iface", 4775 "core_aux", 4776 "ctrl_link", 4777 "ctrl_link_iface", 4778 "stream_pixel"; 4779 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4780 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4781 assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; 4782 phys = <&mdss0_dp1_phy>; 4783 phy-names = "dp"; 4784 4785 operating-points-v2 = <&dp1_opp_table>; 4786 power-domains = <&rpmhpd SA8775P_MMCX>; 4787 4788 #sound-dai-cells = <0>; 4789 4790 status = "disabled"; 4791 4792 ports { 4793 #address-cells = <1>; 4794 #size-cells = <0>; 4795 4796 port@0 { 4797 reg = <0>; 4798 4799 mdss0_dp1_in: endpoint { 4800 remote-endpoint = <&dpu_intf4_out>; 4801 }; 4802 }; 4803 4804 port@1 { 4805 reg = <1>; 4806 4807 mdss0_dp1_out: endpoint { }; 4808 }; 4809 }; 4810 4811 dp1_opp_table: opp-table { 4812 compatible = "operating-points-v2"; 4813 4814 opp-160000000 { 4815 opp-hz = /bits/ 64 <160000000>; 4816 required-opps = <&rpmhpd_opp_low_svs>; 4817 }; 4818 4819 opp-270000000 { 4820 opp-hz = /bits/ 64 <270000000>; 4821 required-opps = <&rpmhpd_opp_svs>; 4822 }; 4823 4824 opp-540000000 { 4825 opp-hz = /bits/ 64 <540000000>; 4826 required-opps = <&rpmhpd_opp_svs_l1>; 4827 }; 4828 4829 opp-810000000 { 4830 opp-hz = /bits/ 64 <810000000>; 4831 required-opps = <&rpmhpd_opp_nom>; 4832 }; 4833 }; 4834 }; 4835 }; 4836 4837 dispcc0: clock-controller@af00000 { 4838 compatible = "qcom,sa8775p-dispcc0"; 4839 reg = <0x0 0x0af00000 0x0 0x20000>; 4840 clocks = <&gcc GCC_DISP_AHB_CLK>, 4841 <&rpmhcc RPMH_CXO_CLK>, 4842 <&rpmhcc RPMH_CXO_CLK_A>, 4843 <&sleep_clk>, 4844 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 4845 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 4846 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4847 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 4848 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 4849 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 4850 power-domains = <&rpmhpd SA8775P_MMCX>; 4851 #clock-cells = <1>; 4852 #reset-cells = <1>; 4853 #power-domain-cells = <1>; 4854 }; 4855 4856 pdc: interrupt-controller@b220000 { 4857 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 4858 reg = <0x0 0x0b220000 0x0 0x30000>, 4859 <0x0 0x17c000f0 0x0 0x64>; 4860 qcom,pdc-ranges = <0 480 40>, 4861 <40 140 14>, 4862 <54 263 1>, 4863 <55 306 4>, 4864 <59 312 3>, 4865 <62 374 2>, 4866 <64 434 2>, 4867 <66 438 2>, 4868 <70 520 1>, 4869 <73 523 1>, 4870 <118 568 6>, 4871 <124 609 3>, 4872 <159 638 1>, 4873 <160 720 3>, 4874 <169 728 30>, 4875 <199 416 2>, 4876 <201 449 1>, 4877 <202 89 1>, 4878 <203 451 1>, 4879 <204 462 1>, 4880 <205 264 1>, 4881 <206 579 1>, 4882 <207 653 1>, 4883 <208 656 1>, 4884 <209 659 1>, 4885 <210 122 1>, 4886 <211 699 1>, 4887 <212 705 1>, 4888 <213 450 1>, 4889 <214 643 2>, 4890 <216 646 5>, 4891 <221 390 5>, 4892 <226 700 2>, 4893 <228 440 1>, 4894 <229 663 1>, 4895 <230 524 2>, 4896 <232 612 3>, 4897 <235 723 5>; 4898 #interrupt-cells = <2>; 4899 interrupt-parent = <&intc>; 4900 interrupt-controller; 4901 }; 4902 4903 tsens2: thermal-sensor@c251000 { 4904 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4905 reg = <0x0 0x0c251000 0x0 0x1ff>, 4906 <0x0 0x0c224000 0x0 0x8>; 4907 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 4908 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 4909 #qcom,sensors = <13>; 4910 interrupt-names = "uplow", "critical"; 4911 #thermal-sensor-cells = <1>; 4912 }; 4913 4914 tsens3: thermal-sensor@c252000 { 4915 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4916 reg = <0x0 0x0c252000 0x0 0x1ff>, 4917 <0x0 0x0c225000 0x0 0x8>; 4918 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 4920 #qcom,sensors = <13>; 4921 interrupt-names = "uplow", "critical"; 4922 #thermal-sensor-cells = <1>; 4923 }; 4924 4925 tsens0: thermal-sensor@c263000 { 4926 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4927 reg = <0x0 0x0c263000 0x0 0x1ff>, 4928 <0x0 0x0c222000 0x0 0x8>; 4929 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4930 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4931 #qcom,sensors = <12>; 4932 interrupt-names = "uplow", "critical"; 4933 #thermal-sensor-cells = <1>; 4934 }; 4935 4936 tsens1: thermal-sensor@c265000 { 4937 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4938 reg = <0x0 0x0c265000 0x0 0x1ff>, 4939 <0x0 0x0c223000 0x0 0x8>; 4940 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4942 #qcom,sensors = <12>; 4943 interrupt-names = "uplow", "critical"; 4944 #thermal-sensor-cells = <1>; 4945 }; 4946 4947 aoss_qmp: power-management@c300000 { 4948 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 4949 reg = <0x0 0x0c300000 0x0 0x400>; 4950 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4951 IPCC_MPROC_SIGNAL_GLINK_QMP 4952 IRQ_TYPE_EDGE_RISING>; 4953 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4954 #clock-cells = <0>; 4955 }; 4956 4957 sram@c3f0000 { 4958 compatible = "qcom,rpmh-stats"; 4959 reg = <0x0 0x0c3f0000 0x0 0x400>; 4960 }; 4961 4962 spmi_bus: spmi@c440000 { 4963 compatible = "qcom,spmi-pmic-arb"; 4964 reg = <0x0 0x0c440000 0x0 0x1100>, 4965 <0x0 0x0c600000 0x0 0x2000000>, 4966 <0x0 0x0e600000 0x0 0x100000>, 4967 <0x0 0x0e700000 0x0 0xa0000>, 4968 <0x0 0x0c40a000 0x0 0x26000>; 4969 reg-names = "core", 4970 "chnls", 4971 "obsrvr", 4972 "intr", 4973 "cnfg"; 4974 qcom,channel = <0>; 4975 qcom,ee = <0>; 4976 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4977 interrupt-names = "periph_irq"; 4978 interrupt-controller; 4979 #interrupt-cells = <4>; 4980 #address-cells = <2>; 4981 #size-cells = <0>; 4982 }; 4983 4984 tlmm: pinctrl@f000000 { 4985 compatible = "qcom,sa8775p-tlmm"; 4986 reg = <0x0 0x0f000000 0x0 0x1000000>; 4987 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4988 gpio-controller; 4989 #gpio-cells = <2>; 4990 interrupt-controller; 4991 #interrupt-cells = <2>; 4992 gpio-ranges = <&tlmm 0 0 149>; 4993 wakeup-parent = <&pdc>; 4994 4995 qup_i2c0_default: qup-i2c0-state { 4996 pins = "gpio20", "gpio21"; 4997 function = "qup0_se0"; 4998 }; 4999 5000 qup_i2c1_default: qup-i2c1-state { 5001 pins = "gpio24", "gpio25"; 5002 function = "qup0_se1"; 5003 }; 5004 5005 qup_i2c2_default: qup-i2c2-state { 5006 pins = "gpio36", "gpio37"; 5007 function = "qup0_se2"; 5008 }; 5009 5010 qup_i2c3_default: qup-i2c3-state { 5011 pins = "gpio28", "gpio29"; 5012 function = "qup0_se3"; 5013 }; 5014 5015 qup_i2c4_default: qup-i2c4-state { 5016 pins = "gpio32", "gpio33"; 5017 function = "qup0_se4"; 5018 }; 5019 5020 qup_i2c5_default: qup-i2c5-state { 5021 pins = "gpio36", "gpio37"; 5022 function = "qup0_se5"; 5023 }; 5024 5025 qup_i2c7_default: qup-i2c7-state { 5026 pins = "gpio40", "gpio41"; 5027 function = "qup1_se0"; 5028 }; 5029 5030 qup_i2c8_default: qup-i2c8-state { 5031 pins = "gpio42", "gpio43"; 5032 function = "qup1_se1"; 5033 }; 5034 5035 qup_i2c9_default: qup-i2c9-state { 5036 pins = "gpio46", "gpio47"; 5037 function = "qup1_se2"; 5038 }; 5039 5040 qup_i2c10_default: qup-i2c10-state { 5041 pins = "gpio44", "gpio45"; 5042 function = "qup1_se3"; 5043 }; 5044 5045 qup_i2c11_default: qup-i2c11-state { 5046 pins = "gpio48", "gpio49"; 5047 function = "qup1_se4"; 5048 }; 5049 5050 qup_i2c12_default: qup-i2c12-state { 5051 pins = "gpio52", "gpio53"; 5052 function = "qup1_se5"; 5053 }; 5054 5055 qup_i2c13_default: qup-i2c13-state { 5056 pins = "gpio56", "gpio57"; 5057 function = "qup1_se6"; 5058 }; 5059 5060 qup_i2c14_default: qup-i2c14-state { 5061 pins = "gpio80", "gpio81"; 5062 function = "qup2_se0"; 5063 }; 5064 5065 qup_i2c15_default: qup-i2c15-state { 5066 pins = "gpio84", "gpio85"; 5067 function = "qup2_se1"; 5068 }; 5069 5070 qup_i2c16_default: qup-i2c16-state { 5071 pins = "gpio86", "gpio87"; 5072 function = "qup2_se2"; 5073 }; 5074 5075 qup_i2c17_default: qup-i2c17-state { 5076 pins = "gpio91", "gpio92"; 5077 function = "qup2_se3"; 5078 }; 5079 5080 qup_i2c18_default: qup-i2c18-state { 5081 pins = "gpio95", "gpio96"; 5082 function = "qup2_se4"; 5083 }; 5084 5085 qup_i2c19_default: qup-i2c19-state { 5086 pins = "gpio99", "gpio100"; 5087 function = "qup2_se5"; 5088 }; 5089 5090 qup_i2c20_default: qup-i2c20-state { 5091 pins = "gpio97", "gpio98"; 5092 function = "qup2_se6"; 5093 }; 5094 5095 qup_i2c21_default: qup-i2c21-state { 5096 pins = "gpio13", "gpio14"; 5097 function = "qup3_se0"; 5098 }; 5099 5100 qup_spi0_default: qup-spi0-state { 5101 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 5102 function = "qup0_se0"; 5103 }; 5104 5105 qup_spi1_default: qup-spi1-state { 5106 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 5107 function = "qup0_se1"; 5108 }; 5109 5110 qup_spi2_default: qup-spi2-state { 5111 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5112 function = "qup0_se2"; 5113 }; 5114 5115 qup_spi3_default: qup-spi3-state { 5116 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 5117 function = "qup0_se3"; 5118 }; 5119 5120 qup_spi4_default: qup-spi4-state { 5121 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 5122 function = "qup0_se4"; 5123 }; 5124 5125 qup_spi5_default: qup-spi5-state { 5126 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5127 function = "qup0_se5"; 5128 }; 5129 5130 qup_spi7_default: qup-spi7-state { 5131 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 5132 function = "qup1_se0"; 5133 }; 5134 5135 qup_spi8_default: qup-spi8-state { 5136 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 5137 function = "qup1_se1"; 5138 }; 5139 5140 qup_spi9_default: qup-spi9-state { 5141 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 5142 function = "qup1_se2"; 5143 }; 5144 5145 qup_spi10_default: qup-spi10-state { 5146 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 5147 function = "qup1_se3"; 5148 }; 5149 5150 qup_spi11_default: qup-spi11-state { 5151 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 5152 function = "qup1_se4"; 5153 }; 5154 5155 qup_spi12_default: qup-spi12-state { 5156 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5157 function = "qup1_se5"; 5158 }; 5159 5160 qup_spi14_default: qup-spi14-state { 5161 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 5162 function = "qup2_se0"; 5163 }; 5164 5165 qup_spi15_default: qup-spi15-state { 5166 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 5167 function = "qup2_se1"; 5168 }; 5169 5170 qup_spi16_default: qup-spi16-state { 5171 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 5172 function = "qup2_se2"; 5173 }; 5174 5175 qup_spi17_default: qup-spi17-state { 5176 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 5177 function = "qup2_se3"; 5178 }; 5179 5180 qup_spi18_default: qup-spi18-state { 5181 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 5182 function = "qup2_se4"; 5183 }; 5184 5185 qup_spi19_default: qup-spi19-state { 5186 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 5187 function = "qup2_se5"; 5188 }; 5189 5190 qup_spi20_default: qup-spi20-state { 5191 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 5192 function = "qup2_se6"; 5193 }; 5194 5195 qup_spi21_default: qup-spi21-state { 5196 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 5197 function = "qup3_se0"; 5198 }; 5199 5200 qup_uart0_default: qup-uart0-state { 5201 qup_uart0_cts: qup-uart0-cts-pins { 5202 pins = "gpio20"; 5203 function = "qup0_se0"; 5204 }; 5205 5206 qup_uart0_rts: qup-uart0-rts-pins { 5207 pins = "gpio21"; 5208 function = "qup0_se0"; 5209 }; 5210 5211 qup_uart0_tx: qup-uart0-tx-pins { 5212 pins = "gpio22"; 5213 function = "qup0_se0"; 5214 }; 5215 5216 qup_uart0_rx: qup-uart0-rx-pins { 5217 pins = "gpio23"; 5218 function = "qup0_se0"; 5219 }; 5220 }; 5221 5222 qup_uart1_default: qup-uart1-state { 5223 qup_uart1_cts: qup-uart1-cts-pins { 5224 pins = "gpio24"; 5225 function = "qup0_se1"; 5226 }; 5227 5228 qup_uart1_rts: qup-uart1-rts-pins { 5229 pins = "gpio25"; 5230 function = "qup0_se1"; 5231 }; 5232 5233 qup_uart1_tx: qup-uart1-tx-pins { 5234 pins = "gpio26"; 5235 function = "qup0_se1"; 5236 }; 5237 5238 qup_uart1_rx: qup-uart1-rx-pins { 5239 pins = "gpio27"; 5240 function = "qup0_se1"; 5241 }; 5242 }; 5243 5244 qup_uart2_default: qup-uart2-state { 5245 qup_uart2_cts: qup-uart2-cts-pins { 5246 pins = "gpio36"; 5247 function = "qup0_se2"; 5248 }; 5249 5250 qup_uart2_rts: qup-uart2-rts-pins { 5251 pins = "gpio37"; 5252 function = "qup0_se2"; 5253 }; 5254 5255 qup_uart2_tx: qup-uart2-tx-pins { 5256 pins = "gpio38"; 5257 function = "qup0_se2"; 5258 }; 5259 5260 qup_uart2_rx: qup-uart2-rx-pins { 5261 pins = "gpio39"; 5262 function = "qup0_se2"; 5263 }; 5264 }; 5265 5266 qup_uart3_default: qup-uart3-state { 5267 qup_uart3_cts: qup-uart3-cts-pins { 5268 pins = "gpio28"; 5269 function = "qup0_se3"; 5270 }; 5271 5272 qup_uart3_rts: qup-uart3-rts-pins { 5273 pins = "gpio29"; 5274 function = "qup0_se3"; 5275 }; 5276 5277 qup_uart3_tx: qup-uart3-tx-pins { 5278 pins = "gpio30"; 5279 function = "qup0_se3"; 5280 }; 5281 5282 qup_uart3_rx: qup-uart3-rx-pins { 5283 pins = "gpio31"; 5284 function = "qup0_se3"; 5285 }; 5286 }; 5287 5288 qup_uart4_default: qup-uart4-state { 5289 qup_uart4_cts: qup-uart4-cts-pins { 5290 pins = "gpio32"; 5291 function = "qup0_se4"; 5292 }; 5293 5294 qup_uart4_rts: qup-uart4-rts-pins { 5295 pins = "gpio33"; 5296 function = "qup0_se4"; 5297 }; 5298 5299 qup_uart4_tx: qup-uart4-tx-pins { 5300 pins = "gpio34"; 5301 function = "qup0_se4"; 5302 }; 5303 5304 qup_uart4_rx: qup-uart4-rx-pins { 5305 pins = "gpio35"; 5306 function = "qup0_se4"; 5307 }; 5308 }; 5309 5310 qup_uart5_default: qup-uart5-state { 5311 qup_uart5_cts: qup-uart5-cts-pins { 5312 pins = "gpio36"; 5313 function = "qup0_se5"; 5314 }; 5315 5316 qup_uart5_rts: qup-uart5-rts-pins { 5317 pins = "gpio37"; 5318 function = "qup0_se5"; 5319 }; 5320 5321 qup_uart5_tx: qup-uart5-tx-pins { 5322 pins = "gpio38"; 5323 function = "qup0_se5"; 5324 }; 5325 5326 qup_uart5_rx: qup-uart5-rx-pins { 5327 pins = "gpio39"; 5328 function = "qup0_se5"; 5329 }; 5330 }; 5331 5332 qup_uart7_default: qup-uart7-state { 5333 qup_uart7_cts: qup-uart7-cts-pins { 5334 pins = "gpio40"; 5335 function = "qup1_se0"; 5336 }; 5337 5338 qup_uart7_rts: qup-uart7-rts-pins { 5339 pins = "gpio41"; 5340 function = "qup1_se0"; 5341 }; 5342 5343 qup_uart7_tx: qup-uart7-tx-pins { 5344 pins = "gpio42"; 5345 function = "qup1_se0"; 5346 }; 5347 5348 qup_uart7_rx: qup-uart7-rx-pins { 5349 pins = "gpio43"; 5350 function = "qup1_se0"; 5351 }; 5352 }; 5353 5354 qup_uart8_default: qup-uart8-state { 5355 qup_uart8_cts: qup-uart8-cts-pins { 5356 pins = "gpio42"; 5357 function = "qup1_se1"; 5358 }; 5359 5360 qup_uart8_rts: qup-uart8-rts-pins { 5361 pins = "gpio43"; 5362 function = "qup1_se1"; 5363 }; 5364 5365 qup_uart8_tx: qup-uart8-tx-pins { 5366 pins = "gpio40"; 5367 function = "qup1_se1"; 5368 }; 5369 5370 qup_uart8_rx: qup-uart8-rx-pins { 5371 pins = "gpio41"; 5372 function = "qup1_se1"; 5373 }; 5374 }; 5375 5376 qup_uart9_default: qup-uart9-state { 5377 qup_uart9_cts: qup-uart9-cts-pins { 5378 pins = "gpio46"; 5379 function = "qup1_se2"; 5380 }; 5381 5382 qup_uart9_rts: qup-uart9-rts-pins { 5383 pins = "gpio47"; 5384 function = "qup1_se2"; 5385 }; 5386 5387 qup_uart9_tx: qup-uart9-tx-pins { 5388 pins = "gpio44"; 5389 function = "qup1_se2"; 5390 }; 5391 5392 qup_uart9_rx: qup-uart9-rx-pins { 5393 pins = "gpio45"; 5394 function = "qup1_se2"; 5395 }; 5396 }; 5397 5398 qup_uart10_default: qup-uart10-state { 5399 pins = "gpio46", "gpio47"; 5400 function = "qup1_se3"; 5401 }; 5402 5403 qup_uart11_default: qup-uart11-state { 5404 qup_uart11_cts: qup-uart11-cts-pins { 5405 pins = "gpio48"; 5406 function = "qup1_se4"; 5407 }; 5408 5409 qup_uart11_rts: qup-uart11-rts-pins { 5410 pins = "gpio49"; 5411 function = "qup1_se4"; 5412 }; 5413 5414 qup_uart11_tx: qup-uart11-tx-pins { 5415 pins = "gpio50"; 5416 function = "qup1_se4"; 5417 }; 5418 5419 qup_uart11_rx: qup-uart11-rx-pins { 5420 pins = "gpio51"; 5421 function = "qup1_se4"; 5422 }; 5423 }; 5424 5425 qup_uart12_default: qup-uart12-state { 5426 qup_uart12_cts: qup-uart12-cts-pins { 5427 pins = "gpio52"; 5428 function = "qup1_se5"; 5429 }; 5430 5431 qup_uart12_rts: qup-uart12-rts-pins { 5432 pins = "gpio53"; 5433 function = "qup1_se5"; 5434 }; 5435 5436 qup_uart12_tx: qup-uart12-tx-pins { 5437 pins = "gpio54"; 5438 function = "qup1_se5"; 5439 }; 5440 5441 qup_uart12_rx: qup-uart12-rx-pins { 5442 pins = "gpio55"; 5443 function = "qup1_se5"; 5444 }; 5445 }; 5446 5447 qup_uart14_default: qup-uart14-state { 5448 qup_uart14_cts: qup-uart14-cts-pins { 5449 pins = "gpio80"; 5450 function = "qup2_se0"; 5451 }; 5452 5453 qup_uart14_rts: qup-uart14-rts-pins { 5454 pins = "gpio81"; 5455 function = "qup2_se0"; 5456 }; 5457 5458 qup_uart14_tx: qup-uart14-tx-pins { 5459 pins = "gpio82"; 5460 function = "qup2_se0"; 5461 }; 5462 5463 qup_uart14_rx: qup-uart14-rx-pins { 5464 pins = "gpio83"; 5465 function = "qup2_se0"; 5466 }; 5467 }; 5468 5469 qup_uart15_default: qup-uart15-state { 5470 qup_uart15_cts: qup-uart15-cts-pins { 5471 pins = "gpio84"; 5472 function = "qup2_se1"; 5473 }; 5474 5475 qup_uart15_rts: qup-uart15-rts-pins { 5476 pins = "gpio85"; 5477 function = "qup2_se1"; 5478 }; 5479 5480 qup_uart15_tx: qup-uart15-tx-pins { 5481 pins = "gpio99"; 5482 function = "qup2_se1"; 5483 }; 5484 5485 qup_uart15_rx: qup-uart15-rx-pins { 5486 pins = "gpio100"; 5487 function = "qup2_se1"; 5488 }; 5489 }; 5490 5491 qup_uart16_default: qup-uart16-state { 5492 qup_uart16_cts: qup-uart16-cts-pins { 5493 pins = "gpio86"; 5494 function = "qup2_se2"; 5495 }; 5496 5497 qup_uart16_rts: qup-uart16-rts-pins { 5498 pins = "gpio87"; 5499 function = "qup2_se2"; 5500 }; 5501 5502 qup_uart16_tx: qup-uart16-tx-pins { 5503 pins = "gpio88"; 5504 function = "qup2_se2"; 5505 }; 5506 5507 qup_uart16_rx: qup-uart16-rx-pins { 5508 pins = "gpio89"; 5509 function = "qup2_se2"; 5510 }; 5511 }; 5512 5513 qup_uart17_default: qup-uart17-state { 5514 qup_uart17_cts: qup-uart17-cts-pins { 5515 pins = "gpio91"; 5516 function = "qup2_se3"; 5517 }; 5518 5519 qup_uart17_rts: qup0-uart17-rts-pins { 5520 pins = "gpio92"; 5521 function = "qup2_se3"; 5522 }; 5523 5524 qup_uart17_tx: qup0-uart17-tx-pins { 5525 pins = "gpio93"; 5526 function = "qup2_se3"; 5527 }; 5528 5529 qup_uart17_rx: qup0-uart17-rx-pins { 5530 pins = "gpio94"; 5531 function = "qup2_se3"; 5532 }; 5533 }; 5534 5535 qup_uart18_default: qup-uart18-state { 5536 qup_uart18_cts: qup-uart18-cts-pins { 5537 pins = "gpio95"; 5538 function = "qup2_se4"; 5539 }; 5540 5541 qup_uart18_rts: qup-uart18-rts-pins { 5542 pins = "gpio96"; 5543 function = "qup2_se4"; 5544 }; 5545 5546 qup_uart18_tx: qup-uart18-tx-pins { 5547 pins = "gpio97"; 5548 function = "qup2_se4"; 5549 }; 5550 5551 qup_uart18_rx: qup-uart18-rx-pins { 5552 pins = "gpio98"; 5553 function = "qup2_se4"; 5554 }; 5555 }; 5556 5557 qup_uart19_default: qup-uart19-state { 5558 qup_uart19_cts: qup-uart19-cts-pins { 5559 pins = "gpio99"; 5560 function = "qup2_se5"; 5561 }; 5562 5563 qup_uart19_rts: qup-uart19-rts-pins { 5564 pins = "gpio100"; 5565 function = "qup2_se5"; 5566 }; 5567 5568 qup_uart19_tx: qup-uart19-tx-pins { 5569 pins = "gpio84"; 5570 function = "qup2_se5"; 5571 }; 5572 5573 qup_uart19_rx: qup-uart19-rx-pins { 5574 pins = "gpio85"; 5575 function = "qup2_se5"; 5576 }; 5577 }; 5578 5579 qup_uart20_default: qup-uart20-state { 5580 qup_uart20_cts: qup-uart20-cts-pins { 5581 pins = "gpio97"; 5582 function = "qup2_se6"; 5583 }; 5584 5585 qup_uart20_rts: qup-uart20-rts-pins { 5586 pins = "gpio98"; 5587 function = "qup2_se6"; 5588 }; 5589 5590 qup_uart20_tx: qup-uart20-tx-pins { 5591 pins = "gpio95"; 5592 function = "qup2_se6"; 5593 }; 5594 5595 qup_uart20_rx: qup-uart20-rx-pins { 5596 pins = "gpio96"; 5597 function = "qup2_se6"; 5598 }; 5599 }; 5600 5601 qup_uart21_default: qup-uart21-state { 5602 qup_uart21_cts: qup-uart21-cts-pins { 5603 pins = "gpio13"; 5604 function = "qup3_se0"; 5605 }; 5606 5607 qup_uart21_rts: qup-uart21-rts-pins { 5608 pins = "gpio14"; 5609 function = "qup3_se0"; 5610 }; 5611 5612 qup_uart21_tx: qup-uart21-tx-pins { 5613 pins = "gpio15"; 5614 function = "qup3_se0"; 5615 }; 5616 5617 qup_uart21_rx: qup-uart21-rx-pins { 5618 pins = "gpio16"; 5619 function = "qup3_se0"; 5620 }; 5621 }; 5622 }; 5623 5624 sram: sram@146d8000 { 5625 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 5626 reg = <0x0 0x146d8000 0x0 0x1000>; 5627 ranges = <0x0 0x0 0x146d8000 0x1000>; 5628 5629 #address-cells = <1>; 5630 #size-cells = <1>; 5631 5632 pil-reloc@94c { 5633 compatible = "qcom,pil-reloc-info"; 5634 reg = <0x94c 0xc8>; 5635 }; 5636 }; 5637 5638 apps_smmu: iommu@15000000 { 5639 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5640 reg = <0x0 0x15000000 0x0 0x100000>; 5641 #iommu-cells = <2>; 5642 #global-interrupts = <2>; 5643 dma-coherent; 5644 5645 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 5646 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 5647 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5648 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5649 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5650 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5651 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5652 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5653 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5654 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5655 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5657 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5658 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5659 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5660 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5661 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5662 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5663 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5664 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5665 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5666 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5667 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5668 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5669 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5670 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5671 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5672 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5673 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5674 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5675 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5676 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5677 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5678 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5679 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5680 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5681 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5682 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5683 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5684 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5685 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5686 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5687 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5688 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5689 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5690 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5691 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5692 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5693 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5694 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5695 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5696 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5697 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5698 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5699 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5700 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5701 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5702 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5703 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5704 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5705 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5706 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5707 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5708 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5709 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5710 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5711 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5712 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5713 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5714 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5717 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5718 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5719 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5720 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5768 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5769 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5770 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5771 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5772 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5773 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5774 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 5775 }; 5776 5777 pcie_smmu: iommu@15200000 { 5778 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5779 reg = <0x0 0x15200000 0x0 0x80000>; 5780 #iommu-cells = <2>; 5781 #global-interrupts = <2>; 5782 dma-coherent; 5783 5784 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 5785 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 5786 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 5787 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 5788 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 5789 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 5790 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 5791 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 5793 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 5794 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 5795 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 5796 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 5798 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 5799 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 5804 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 5805 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 5809 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5810 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 5837 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 5838 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 5839 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 5840 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 5841 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 5842 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 5843 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 5844 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 5845 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 5846 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 5847 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 5848 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 5849 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 5850 }; 5851 5852 intc: interrupt-controller@17a00000 { 5853 compatible = "arm,gic-v3"; 5854 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5855 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5856 interrupt-controller; 5857 #interrupt-cells = <3>; 5858 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5859 #redistributor-regions = <1>; 5860 redistributor-stride = <0x0 0x20000>; 5861 }; 5862 5863 watchdog@17c10000 { 5864 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 5865 reg = <0x0 0x17c10000 0x0 0x1000>; 5866 clocks = <&sleep_clk>; 5867 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5868 }; 5869 5870 memtimer: timer@17c20000 { 5871 compatible = "arm,armv7-timer-mem"; 5872 reg = <0x0 0x17c20000 0x0 0x1000>; 5873 ranges = <0x0 0x0 0x0 0x20000000>; 5874 #address-cells = <1>; 5875 #size-cells = <1>; 5876 5877 frame@17c21000 { 5878 reg = <0x17c21000 0x1000>, 5879 <0x17c22000 0x1000>; 5880 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5882 frame-number = <0>; 5883 }; 5884 5885 frame@17c23000 { 5886 reg = <0x17c23000 0x1000>; 5887 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5888 frame-number = <1>; 5889 status = "disabled"; 5890 }; 5891 5892 frame@17c25000 { 5893 reg = <0x17c25000 0x1000>; 5894 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5895 frame-number = <2>; 5896 status = "disabled"; 5897 }; 5898 5899 frame@17c27000 { 5900 reg = <0x17c27000 0x1000>; 5901 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5902 frame-number = <3>; 5903 status = "disabled"; 5904 }; 5905 5906 frame@17c29000 { 5907 reg = <0x17c29000 0x1000>; 5908 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5909 frame-number = <4>; 5910 status = "disabled"; 5911 }; 5912 5913 frame@17c2b000 { 5914 reg = <0x17c2b000 0x1000>; 5915 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5916 frame-number = <5>; 5917 status = "disabled"; 5918 }; 5919 5920 frame@17c2d000 { 5921 reg = <0x17c2d000 0x1000>; 5922 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5923 frame-number = <6>; 5924 status = "disabled"; 5925 }; 5926 }; 5927 5928 apps_rsc: rsc@18200000 { 5929 compatible = "qcom,rpmh-rsc"; 5930 reg = <0x0 0x18200000 0x0 0x10000>, 5931 <0x0 0x18210000 0x0 0x10000>, 5932 <0x0 0x18220000 0x0 0x10000>; 5933 reg-names = "drv-0", "drv-1", "drv-2"; 5934 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5937 qcom,tcs-offset = <0xd00>; 5938 qcom,drv-id = <2>; 5939 qcom,tcs-config = <ACTIVE_TCS 2>, 5940 <SLEEP_TCS 3>, 5941 <WAKE_TCS 3>, 5942 <CONTROL_TCS 0>; 5943 label = "apps_rsc"; 5944 power-domains = <&system_pd>; 5945 5946 apps_bcm_voter: bcm-voter { 5947 compatible = "qcom,bcm-voter"; 5948 }; 5949 5950 rpmhcc: clock-controller { 5951 compatible = "qcom,sa8775p-rpmh-clk"; 5952 #clock-cells = <1>; 5953 clock-names = "xo"; 5954 clocks = <&xo_board_clk>; 5955 }; 5956 5957 rpmhpd: power-controller { 5958 compatible = "qcom,sa8775p-rpmhpd"; 5959 #power-domain-cells = <1>; 5960 operating-points-v2 = <&rpmhpd_opp_table>; 5961 5962 rpmhpd_opp_table: opp-table { 5963 compatible = "operating-points-v2"; 5964 5965 rpmhpd_opp_ret: opp-0 { 5966 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5967 }; 5968 5969 rpmhpd_opp_min_svs: opp-1 { 5970 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5971 }; 5972 5973 rpmhpd_opp_low_svs: opp2 { 5974 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5975 }; 5976 5977 rpmhpd_opp_svs: opp3 { 5978 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5979 }; 5980 5981 rpmhpd_opp_svs_l1: opp-4 { 5982 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5983 }; 5984 5985 rpmhpd_opp_nom: opp-5 { 5986 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5987 }; 5988 5989 rpmhpd_opp_nom_l1: opp-6 { 5990 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5991 }; 5992 5993 rpmhpd_opp_nom_l2: opp-7 { 5994 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5995 }; 5996 5997 rpmhpd_opp_turbo: opp-8 { 5998 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5999 }; 6000 6001 rpmhpd_opp_turbo_l1: opp-9 { 6002 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6003 }; 6004 }; 6005 }; 6006 }; 6007 6008 epss_l3_cl0: interconnect@18590000 { 6009 compatible = "qcom,sa8775p-epss-l3", 6010 "qcom,epss-l3"; 6011 reg = <0x0 0x18590000 0x0 0x1000>; 6012 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6013 clock-names = "xo", "alternate"; 6014 #interconnect-cells = <1>; 6015 }; 6016 6017 cpufreq_hw: cpufreq@18591000 { 6018 compatible = "qcom,sa8775p-cpufreq-epss", 6019 "qcom,cpufreq-epss"; 6020 reg = <0x0 0x18591000 0x0 0x1000>, 6021 <0x0 0x18593000 0x0 0x1000>; 6022 reg-names = "freq-domain0", "freq-domain1"; 6023 6024 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6025 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6026 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 6027 6028 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6029 clock-names = "xo", "alternate"; 6030 6031 #freq-domain-cells = <1>; 6032 }; 6033 6034 epss_l3_cl1: interconnect@18592000 { 6035 compatible = "qcom,sa8775p-epss-l3", 6036 "qcom,epss-l3"; 6037 reg = <0x0 0x18592000 0x0 0x1000>; 6038 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6039 clock-names = "xo", "alternate"; 6040 #interconnect-cells = <1>; 6041 }; 6042 6043 remoteproc_gpdsp0: remoteproc@20c00000 { 6044 compatible = "qcom,sa8775p-gpdsp0-pas"; 6045 reg = <0x0 0x20c00000 0x0 0x10000>; 6046 6047 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6048 <&smp2p_gpdsp0_in 0 0>, 6049 <&smp2p_gpdsp0_in 1 0>, 6050 <&smp2p_gpdsp0_in 2 0>, 6051 <&smp2p_gpdsp0_in 3 0>; 6052 interrupt-names = "wdog", "fatal", "ready", 6053 "handover", "stop-ack"; 6054 6055 clocks = <&rpmhcc RPMH_CXO_CLK>; 6056 clock-names = "xo"; 6057 6058 power-domains = <&rpmhpd RPMHPD_CX>, 6059 <&rpmhpd RPMHPD_MXC>; 6060 power-domain-names = "cx", "mxc"; 6061 6062 interconnects = <&gpdsp_anoc MASTER_DSP0 0 6063 &config_noc SLAVE_CLK_CTL 0>; 6064 6065 memory-region = <&pil_gdsp0_mem>; 6066 6067 qcom,qmp = <&aoss_qmp>; 6068 6069 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 6070 qcom,smem-state-names = "stop"; 6071 6072 status = "disabled"; 6073 6074 glink-edge { 6075 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6076 IPCC_MPROC_SIGNAL_GLINK_QMP 6077 IRQ_TYPE_EDGE_RISING>; 6078 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6079 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6080 6081 label = "gpdsp0"; 6082 qcom,remote-pid = <17>; 6083 }; 6084 }; 6085 6086 remoteproc_gpdsp1: remoteproc@21c00000 { 6087 compatible = "qcom,sa8775p-gpdsp1-pas"; 6088 reg = <0x0 0x21c00000 0x0 0x10000>; 6089 6090 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 6091 <&smp2p_gpdsp1_in 0 0>, 6092 <&smp2p_gpdsp1_in 1 0>, 6093 <&smp2p_gpdsp1_in 2 0>, 6094 <&smp2p_gpdsp1_in 3 0>; 6095 interrupt-names = "wdog", "fatal", "ready", 6096 "handover", "stop-ack"; 6097 6098 clocks = <&rpmhcc RPMH_CXO_CLK>; 6099 clock-names = "xo"; 6100 6101 power-domains = <&rpmhpd RPMHPD_CX>, 6102 <&rpmhpd RPMHPD_MXC>; 6103 power-domain-names = "cx", "mxc"; 6104 6105 interconnects = <&gpdsp_anoc MASTER_DSP1 0 6106 &config_noc SLAVE_CLK_CTL 0>; 6107 6108 memory-region = <&pil_gdsp1_mem>; 6109 6110 qcom,qmp = <&aoss_qmp>; 6111 6112 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 6113 qcom,smem-state-names = "stop"; 6114 6115 status = "disabled"; 6116 6117 glink-edge { 6118 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 6119 IPCC_MPROC_SIGNAL_GLINK_QMP 6120 IRQ_TYPE_EDGE_RISING>; 6121 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 6122 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6123 6124 label = "gpdsp1"; 6125 qcom,remote-pid = <18>; 6126 }; 6127 }; 6128 6129 dispcc1: clock-controller@22100000 { 6130 compatible = "qcom,sa8775p-dispcc1"; 6131 reg = <0x0 0x22100000 0x0 0x20000>; 6132 clocks = <&gcc GCC_DISP_AHB_CLK>, 6133 <&rpmhcc RPMH_CXO_CLK>, 6134 <&rpmhcc RPMH_CXO_CLK_A>, 6135 <&sleep_clk>, 6136 <0>, <0>, <0>, <0>, 6137 <0>, <0>, <0>, <0>; 6138 power-domains = <&rpmhpd SA8775P_MMCX>; 6139 #clock-cells = <1>; 6140 #reset-cells = <1>; 6141 #power-domain-cells = <1>; 6142 status = "disabled"; 6143 }; 6144 6145 ethernet1: ethernet@23000000 { 6146 compatible = "qcom,sa8775p-ethqos"; 6147 reg = <0x0 0x23000000 0x0 0x10000>, 6148 <0x0 0x23016000 0x0 0x100>; 6149 reg-names = "stmmaceth", "rgmii"; 6150 6151 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6152 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 6153 interrupt-names = "macirq", "sfty"; 6154 6155 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6156 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6157 <&gcc GCC_EMAC1_PTP_CLK>, 6158 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 6159 clock-names = "stmmaceth", 6160 "pclk", 6161 "ptp_ref", 6162 "phyaux"; 6163 6164 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 6165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 6166 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 6167 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; 6168 interconnect-names = "mac-mem", "cpu-mac"; 6169 6170 power-domains = <&gcc EMAC1_GDSC>; 6171 6172 phys = <&serdes1>; 6173 phy-names = "serdes"; 6174 6175 iommus = <&apps_smmu 0x140 0xf>; 6176 dma-coherent; 6177 6178 snps,tso; 6179 snps,pbl = <32>; 6180 rx-fifo-depth = <16384>; 6181 tx-fifo-depth = <16384>; 6182 6183 status = "disabled"; 6184 }; 6185 6186 ethernet0: ethernet@23040000 { 6187 compatible = "qcom,sa8775p-ethqos"; 6188 reg = <0x0 0x23040000 0x0 0x10000>, 6189 <0x0 0x23056000 0x0 0x100>; 6190 reg-names = "stmmaceth", "rgmii"; 6191 6192 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 6193 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 6194 interrupt-names = "macirq", "sfty"; 6195 6196 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 6197 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 6198 <&gcc GCC_EMAC0_PTP_CLK>, 6199 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 6200 clock-names = "stmmaceth", 6201 "pclk", 6202 "ptp_ref", 6203 "phyaux"; 6204 6205 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 6206 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 6207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 6208 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; 6209 interconnect-names = "mac-mem", "cpu-mac"; 6210 6211 power-domains = <&gcc EMAC0_GDSC>; 6212 6213 phys = <&serdes0>; 6214 phy-names = "serdes"; 6215 6216 iommus = <&apps_smmu 0x120 0xf>; 6217 dma-coherent; 6218 6219 snps,tso; 6220 snps,pbl = <32>; 6221 rx-fifo-depth = <16384>; 6222 tx-fifo-depth = <16384>; 6223 6224 status = "disabled"; 6225 }; 6226 6227 remoteproc_cdsp0: remoteproc@26300000 { 6228 compatible = "qcom,sa8775p-cdsp0-pas"; 6229 reg = <0x0 0x26300000 0x0 0x10000>; 6230 6231 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6232 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 6233 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 6234 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 6235 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 6236 interrupt-names = "wdog", "fatal", "ready", 6237 "handover", "stop-ack"; 6238 6239 clocks = <&rpmhcc RPMH_CXO_CLK>; 6240 clock-names = "xo"; 6241 6242 power-domains = <&rpmhpd RPMHPD_CX>, 6243 <&rpmhpd RPMHPD_MXC>, 6244 <&rpmhpd RPMHPD_NSP0>; 6245 power-domain-names = "cx", "mxc", "nsp"; 6246 6247 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 6248 &mc_virt SLAVE_EBI1 0>; 6249 6250 memory-region = <&pil_cdsp0_mem>; 6251 6252 qcom,qmp = <&aoss_qmp>; 6253 6254 qcom,smem-states = <&smp2p_cdsp0_out 0>; 6255 qcom,smem-state-names = "stop"; 6256 6257 status = "disabled"; 6258 6259 glink-edge { 6260 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6261 IPCC_MPROC_SIGNAL_GLINK_QMP 6262 IRQ_TYPE_EDGE_RISING>; 6263 mboxes = <&ipcc IPCC_CLIENT_CDSP 6264 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6265 6266 label = "cdsp"; 6267 qcom,remote-pid = <5>; 6268 6269 fastrpc { 6270 compatible = "qcom,fastrpc"; 6271 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6272 label = "cdsp"; 6273 #address-cells = <1>; 6274 #size-cells = <0>; 6275 6276 compute-cb@1 { 6277 compatible = "qcom,fastrpc-compute-cb"; 6278 reg = <1>; 6279 iommus = <&apps_smmu 0x2141 0x04a0>, 6280 <&apps_smmu 0x2181 0x0400>; 6281 dma-coherent; 6282 }; 6283 6284 compute-cb@2 { 6285 compatible = "qcom,fastrpc-compute-cb"; 6286 reg = <2>; 6287 iommus = <&apps_smmu 0x2142 0x04a0>, 6288 <&apps_smmu 0x2182 0x0400>; 6289 dma-coherent; 6290 }; 6291 6292 compute-cb@3 { 6293 compatible = "qcom,fastrpc-compute-cb"; 6294 reg = <3>; 6295 iommus = <&apps_smmu 0x2143 0x04a0>, 6296 <&apps_smmu 0x2183 0x0400>; 6297 dma-coherent; 6298 }; 6299 6300 compute-cb@4 { 6301 compatible = "qcom,fastrpc-compute-cb"; 6302 reg = <4>; 6303 iommus = <&apps_smmu 0x2144 0x04a0>, 6304 <&apps_smmu 0x2184 0x0400>; 6305 dma-coherent; 6306 }; 6307 6308 compute-cb@5 { 6309 compatible = "qcom,fastrpc-compute-cb"; 6310 reg = <5>; 6311 iommus = <&apps_smmu 0x2145 0x04a0>, 6312 <&apps_smmu 0x2185 0x0400>; 6313 dma-coherent; 6314 }; 6315 6316 compute-cb@6 { 6317 compatible = "qcom,fastrpc-compute-cb"; 6318 reg = <6>; 6319 iommus = <&apps_smmu 0x2146 0x04a0>, 6320 <&apps_smmu 0x2186 0x0400>; 6321 dma-coherent; 6322 }; 6323 6324 compute-cb@7 { 6325 compatible = "qcom,fastrpc-compute-cb"; 6326 reg = <7>; 6327 iommus = <&apps_smmu 0x2147 0x04a0>, 6328 <&apps_smmu 0x2187 0x0400>; 6329 dma-coherent; 6330 }; 6331 6332 compute-cb@8 { 6333 compatible = "qcom,fastrpc-compute-cb"; 6334 reg = <8>; 6335 iommus = <&apps_smmu 0x2148 0x04a0>, 6336 <&apps_smmu 0x2188 0x0400>; 6337 dma-coherent; 6338 }; 6339 6340 compute-cb@9 { 6341 compatible = "qcom,fastrpc-compute-cb"; 6342 reg = <9>; 6343 iommus = <&apps_smmu 0x2149 0x04a0>, 6344 <&apps_smmu 0x2189 0x0400>; 6345 dma-coherent; 6346 }; 6347 6348 compute-cb@11 { 6349 compatible = "qcom,fastrpc-compute-cb"; 6350 reg = <11>; 6351 iommus = <&apps_smmu 0x214b 0x04a0>, 6352 <&apps_smmu 0x218b 0x0400>; 6353 dma-coherent; 6354 }; 6355 }; 6356 }; 6357 }; 6358 6359 remoteproc_cdsp1: remoteproc@2a300000 { 6360 compatible = "qcom,sa8775p-cdsp1-pas"; 6361 reg = <0x0 0x2A300000 0x0 0x10000>; 6362 6363 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 6364 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 6365 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 6366 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 6367 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 6368 interrupt-names = "wdog", "fatal", "ready", 6369 "handover", "stop-ack"; 6370 6371 clocks = <&rpmhcc RPMH_CXO_CLK>; 6372 clock-names = "xo"; 6373 6374 power-domains = <&rpmhpd RPMHPD_CX>, 6375 <&rpmhpd RPMHPD_MXC>, 6376 <&rpmhpd RPMHPD_NSP1>; 6377 power-domain-names = "cx", "mxc", "nsp"; 6378 6379 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 6380 &mc_virt SLAVE_EBI1 0>; 6381 6382 memory-region = <&pil_cdsp1_mem>; 6383 6384 qcom,qmp = <&aoss_qmp>; 6385 6386 qcom,smem-states = <&smp2p_cdsp1_out 0>; 6387 qcom,smem-state-names = "stop"; 6388 6389 status = "disabled"; 6390 6391 glink-edge { 6392 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 6393 IPCC_MPROC_SIGNAL_GLINK_QMP 6394 IRQ_TYPE_EDGE_RISING>; 6395 mboxes = <&ipcc IPCC_CLIENT_NSP1 6396 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6397 6398 label = "cdsp"; 6399 qcom,remote-pid = <12>; 6400 6401 fastrpc { 6402 compatible = "qcom,fastrpc"; 6403 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6404 label = "cdsp1"; 6405 #address-cells = <1>; 6406 #size-cells = <0>; 6407 6408 compute-cb@1 { 6409 compatible = "qcom,fastrpc-compute-cb"; 6410 reg = <1>; 6411 iommus = <&apps_smmu 0x2941 0x04a0>, 6412 <&apps_smmu 0x2981 0x0400>; 6413 dma-coherent; 6414 }; 6415 6416 compute-cb@2 { 6417 compatible = "qcom,fastrpc-compute-cb"; 6418 reg = <2>; 6419 iommus = <&apps_smmu 0x2942 0x04a0>, 6420 <&apps_smmu 0x2982 0x0400>; 6421 dma-coherent; 6422 }; 6423 6424 compute-cb@3 { 6425 compatible = "qcom,fastrpc-compute-cb"; 6426 reg = <3>; 6427 iommus = <&apps_smmu 0x2943 0x04a0>, 6428 <&apps_smmu 0x2983 0x0400>; 6429 dma-coherent; 6430 }; 6431 6432 compute-cb@4 { 6433 compatible = "qcom,fastrpc-compute-cb"; 6434 reg = <4>; 6435 iommus = <&apps_smmu 0x2944 0x04a0>, 6436 <&apps_smmu 0x2984 0x0400>; 6437 dma-coherent; 6438 }; 6439 6440 compute-cb@5 { 6441 compatible = "qcom,fastrpc-compute-cb"; 6442 reg = <5>; 6443 iommus = <&apps_smmu 0x2945 0x04a0>, 6444 <&apps_smmu 0x2985 0x0400>; 6445 dma-coherent; 6446 }; 6447 6448 compute-cb@6 { 6449 compatible = "qcom,fastrpc-compute-cb"; 6450 reg = <6>; 6451 iommus = <&apps_smmu 0x2946 0x04a0>, 6452 <&apps_smmu 0x2986 0x0400>; 6453 dma-coherent; 6454 }; 6455 6456 compute-cb@7 { 6457 compatible = "qcom,fastrpc-compute-cb"; 6458 reg = <7>; 6459 iommus = <&apps_smmu 0x2947 0x04a0>, 6460 <&apps_smmu 0x2987 0x0400>; 6461 dma-coherent; 6462 }; 6463 6464 compute-cb@8 { 6465 compatible = "qcom,fastrpc-compute-cb"; 6466 reg = <8>; 6467 iommus = <&apps_smmu 0x2948 0x04a0>, 6468 <&apps_smmu 0x2988 0x0400>; 6469 dma-coherent; 6470 }; 6471 6472 compute-cb@9 { 6473 compatible = "qcom,fastrpc-compute-cb"; 6474 reg = <9>; 6475 iommus = <&apps_smmu 0x2949 0x04a0>, 6476 <&apps_smmu 0x2989 0x0400>; 6477 dma-coherent; 6478 }; 6479 6480 compute-cb@10 { 6481 compatible = "qcom,fastrpc-compute-cb"; 6482 reg = <10>; 6483 iommus = <&apps_smmu 0x294a 0x04a0>, 6484 <&apps_smmu 0x298a 0x0400>; 6485 dma-coherent; 6486 }; 6487 6488 compute-cb@11 { 6489 compatible = "qcom,fastrpc-compute-cb"; 6490 reg = <11>; 6491 iommus = <&apps_smmu 0x294b 0x04a0>, 6492 <&apps_smmu 0x298b 0x0400>; 6493 dma-coherent; 6494 }; 6495 6496 compute-cb@12 { 6497 compatible = "qcom,fastrpc-compute-cb"; 6498 reg = <12>; 6499 iommus = <&apps_smmu 0x294c 0x04a0>, 6500 <&apps_smmu 0x298c 0x0400>; 6501 dma-coherent; 6502 }; 6503 6504 compute-cb@13 { 6505 compatible = "qcom,fastrpc-compute-cb"; 6506 reg = <13>; 6507 iommus = <&apps_smmu 0x294d 0x04a0>, 6508 <&apps_smmu 0x298d 0x0400>; 6509 dma-coherent; 6510 }; 6511 }; 6512 }; 6513 }; 6514 6515 remoteproc_adsp: remoteproc@30000000 { 6516 compatible = "qcom,sa8775p-adsp-pas"; 6517 reg = <0x0 0x30000000 0x0 0x100>; 6518 6519 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 6520 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 6521 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 6522 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 6523 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 6524 interrupt-names = "wdog", "fatal", "ready", "handover", 6525 "stop-ack"; 6526 6527 clocks = <&rpmhcc RPMH_CXO_CLK>; 6528 clock-names = "xo"; 6529 6530 power-domains = <&rpmhpd RPMHPD_LCX>, 6531 <&rpmhpd RPMHPD_LMX>; 6532 power-domain-names = "lcx", "lmx"; 6533 6534 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 6535 6536 memory-region = <&pil_adsp_mem>; 6537 6538 qcom,qmp = <&aoss_qmp>; 6539 6540 qcom,smem-states = <&smp2p_adsp_out 0>; 6541 qcom,smem-state-names = "stop"; 6542 6543 status = "disabled"; 6544 6545 remoteproc_adsp_glink: glink-edge { 6546 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 6547 IPCC_MPROC_SIGNAL_GLINK_QMP 6548 IRQ_TYPE_EDGE_RISING>; 6549 mboxes = <&ipcc IPCC_CLIENT_LPASS 6550 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6551 6552 label = "lpass"; 6553 qcom,remote-pid = <2>; 6554 6555 fastrpc { 6556 compatible = "qcom,fastrpc"; 6557 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6558 label = "adsp"; 6559 memory-region = <&adsp_rpc_remote_heap_mem>; 6560 qcom,vmids = <QCOM_SCM_VMID_LPASS 6561 QCOM_SCM_VMID_ADSP_HEAP>; 6562 #address-cells = <1>; 6563 #size-cells = <0>; 6564 6565 compute-cb@3 { 6566 compatible = "qcom,fastrpc-compute-cb"; 6567 reg = <3>; 6568 iommus = <&apps_smmu 0x3003 0x0>; 6569 dma-coherent; 6570 }; 6571 6572 compute-cb@4 { 6573 compatible = "qcom,fastrpc-compute-cb"; 6574 reg = <4>; 6575 iommus = <&apps_smmu 0x3004 0x0>; 6576 dma-coherent; 6577 }; 6578 6579 compute-cb@5 { 6580 compatible = "qcom,fastrpc-compute-cb"; 6581 reg = <5>; 6582 iommus = <&apps_smmu 0x3005 0x0>; 6583 qcom,nsessions = <5>; 6584 dma-coherent; 6585 }; 6586 }; 6587 }; 6588 }; 6589 }; 6590 6591 thermal-zones { 6592 aoss-0-thermal { 6593 thermal-sensors = <&tsens0 0>; 6594 6595 trips { 6596 trip-point0 { 6597 temperature = <105000>; 6598 hysteresis = <5000>; 6599 type = "passive"; 6600 }; 6601 6602 trip-point1 { 6603 temperature = <115000>; 6604 hysteresis = <5000>; 6605 type = "passive"; 6606 }; 6607 }; 6608 }; 6609 6610 cpu-0-0-0-thermal { 6611 polling-delay-passive = <10>; 6612 6613 thermal-sensors = <&tsens0 1>; 6614 6615 trips { 6616 trip-point0 { 6617 temperature = <105000>; 6618 hysteresis = <5000>; 6619 type = "passive"; 6620 }; 6621 6622 trip-point1 { 6623 temperature = <115000>; 6624 hysteresis = <5000>; 6625 type = "passive"; 6626 }; 6627 }; 6628 }; 6629 6630 cpu-0-1-0-thermal { 6631 polling-delay-passive = <10>; 6632 6633 thermal-sensors = <&tsens0 2>; 6634 6635 trips { 6636 trip-point0 { 6637 temperature = <105000>; 6638 hysteresis = <5000>; 6639 type = "passive"; 6640 }; 6641 6642 trip-point1 { 6643 temperature = <115000>; 6644 hysteresis = <5000>; 6645 type = "passive"; 6646 }; 6647 }; 6648 }; 6649 6650 cpu-0-2-0-thermal { 6651 polling-delay-passive = <10>; 6652 6653 thermal-sensors = <&tsens0 3>; 6654 6655 trips { 6656 trip-point0 { 6657 temperature = <105000>; 6658 hysteresis = <5000>; 6659 type = "passive"; 6660 }; 6661 6662 trip-point1 { 6663 temperature = <115000>; 6664 hysteresis = <5000>; 6665 type = "passive"; 6666 }; 6667 }; 6668 }; 6669 6670 cpu-0-3-0-thermal { 6671 polling-delay-passive = <10>; 6672 6673 thermal-sensors = <&tsens0 4>; 6674 6675 trips { 6676 trip-point0 { 6677 temperature = <105000>; 6678 hysteresis = <5000>; 6679 type = "passive"; 6680 }; 6681 6682 trip-point1 { 6683 temperature = <115000>; 6684 hysteresis = <5000>; 6685 type = "passive"; 6686 }; 6687 }; 6688 }; 6689 6690 gpuss-0-thermal { 6691 polling-delay-passive = <10>; 6692 6693 thermal-sensors = <&tsens0 5>; 6694 6695 trips { 6696 trip-point0 { 6697 temperature = <105000>; 6698 hysteresis = <5000>; 6699 type = "passive"; 6700 }; 6701 6702 trip-point1 { 6703 temperature = <115000>; 6704 hysteresis = <5000>; 6705 type = "passive"; 6706 }; 6707 }; 6708 }; 6709 6710 gpuss-1-thermal { 6711 polling-delay-passive = <10>; 6712 6713 thermal-sensors = <&tsens0 6>; 6714 6715 trips { 6716 trip-point0 { 6717 temperature = <105000>; 6718 hysteresis = <5000>; 6719 type = "passive"; 6720 }; 6721 6722 trip-point1 { 6723 temperature = <115000>; 6724 hysteresis = <5000>; 6725 type = "passive"; 6726 }; 6727 }; 6728 }; 6729 6730 gpuss-2-thermal { 6731 polling-delay-passive = <10>; 6732 6733 thermal-sensors = <&tsens0 7>; 6734 6735 trips { 6736 trip-point0 { 6737 temperature = <105000>; 6738 hysteresis = <5000>; 6739 type = "passive"; 6740 }; 6741 6742 trip-point1 { 6743 temperature = <115000>; 6744 hysteresis = <5000>; 6745 type = "passive"; 6746 }; 6747 }; 6748 }; 6749 6750 audio-thermal { 6751 thermal-sensors = <&tsens0 8>; 6752 6753 trips { 6754 trip-point0 { 6755 temperature = <105000>; 6756 hysteresis = <5000>; 6757 type = "passive"; 6758 }; 6759 6760 trip-point1 { 6761 temperature = <115000>; 6762 hysteresis = <5000>; 6763 type = "passive"; 6764 }; 6765 }; 6766 }; 6767 6768 camss-0-thermal { 6769 thermal-sensors = <&tsens0 9>; 6770 6771 trips { 6772 trip-point0 { 6773 temperature = <105000>; 6774 hysteresis = <5000>; 6775 type = "passive"; 6776 }; 6777 6778 trip-point1 { 6779 temperature = <115000>; 6780 hysteresis = <5000>; 6781 type = "passive"; 6782 }; 6783 }; 6784 }; 6785 6786 pcie-0-thermal { 6787 thermal-sensors = <&tsens0 10>; 6788 6789 trips { 6790 trip-point0 { 6791 temperature = <105000>; 6792 hysteresis = <5000>; 6793 type = "passive"; 6794 }; 6795 6796 trip-point1 { 6797 temperature = <115000>; 6798 hysteresis = <5000>; 6799 type = "passive"; 6800 }; 6801 }; 6802 }; 6803 6804 cpuss-0-0-thermal { 6805 thermal-sensors = <&tsens0 11>; 6806 6807 trips { 6808 trip-point0 { 6809 temperature = <105000>; 6810 hysteresis = <5000>; 6811 type = "passive"; 6812 }; 6813 6814 trip-point1 { 6815 temperature = <115000>; 6816 hysteresis = <5000>; 6817 type = "passive"; 6818 }; 6819 }; 6820 }; 6821 6822 aoss-1-thermal { 6823 thermal-sensors = <&tsens1 0>; 6824 6825 trips { 6826 trip-point0 { 6827 temperature = <105000>; 6828 hysteresis = <5000>; 6829 type = "passive"; 6830 }; 6831 6832 trip-point1 { 6833 temperature = <115000>; 6834 hysteresis = <5000>; 6835 type = "passive"; 6836 }; 6837 }; 6838 }; 6839 6840 cpu-0-0-1-thermal { 6841 polling-delay-passive = <10>; 6842 6843 thermal-sensors = <&tsens1 1>; 6844 6845 trips { 6846 trip-point0 { 6847 temperature = <105000>; 6848 hysteresis = <5000>; 6849 type = "passive"; 6850 }; 6851 6852 trip-point1 { 6853 temperature = <115000>; 6854 hysteresis = <5000>; 6855 type = "passive"; 6856 }; 6857 }; 6858 }; 6859 6860 cpu-0-1-1-thermal { 6861 polling-delay-passive = <10>; 6862 6863 thermal-sensors = <&tsens1 2>; 6864 6865 trips { 6866 trip-point0 { 6867 temperature = <105000>; 6868 hysteresis = <5000>; 6869 type = "passive"; 6870 }; 6871 6872 trip-point1 { 6873 temperature = <115000>; 6874 hysteresis = <5000>; 6875 type = "passive"; 6876 }; 6877 }; 6878 }; 6879 6880 cpu-0-2-1-thermal { 6881 polling-delay-passive = <10>; 6882 6883 thermal-sensors = <&tsens1 3>; 6884 6885 trips { 6886 trip-point0 { 6887 temperature = <105000>; 6888 hysteresis = <5000>; 6889 type = "passive"; 6890 }; 6891 6892 trip-point1 { 6893 temperature = <115000>; 6894 hysteresis = <5000>; 6895 type = "passive"; 6896 }; 6897 }; 6898 }; 6899 6900 cpu-0-3-1-thermal { 6901 polling-delay-passive = <10>; 6902 6903 thermal-sensors = <&tsens1 4>; 6904 6905 trips { 6906 trip-point0 { 6907 temperature = <105000>; 6908 hysteresis = <5000>; 6909 type = "passive"; 6910 }; 6911 6912 trip-point1 { 6913 temperature = <115000>; 6914 hysteresis = <5000>; 6915 type = "passive"; 6916 }; 6917 }; 6918 }; 6919 6920 gpuss-3-thermal { 6921 polling-delay-passive = <10>; 6922 6923 thermal-sensors = <&tsens1 5>; 6924 6925 trips { 6926 trip-point0 { 6927 temperature = <105000>; 6928 hysteresis = <5000>; 6929 type = "passive"; 6930 }; 6931 6932 trip-point1 { 6933 temperature = <115000>; 6934 hysteresis = <5000>; 6935 type = "passive"; 6936 }; 6937 }; 6938 }; 6939 6940 gpuss-4-thermal { 6941 polling-delay-passive = <10>; 6942 6943 thermal-sensors = <&tsens1 6>; 6944 6945 trips { 6946 trip-point0 { 6947 temperature = <105000>; 6948 hysteresis = <5000>; 6949 type = "passive"; 6950 }; 6951 6952 trip-point1 { 6953 temperature = <115000>; 6954 hysteresis = <5000>; 6955 type = "passive"; 6956 }; 6957 }; 6958 }; 6959 6960 gpuss-5-thermal { 6961 polling-delay-passive = <10>; 6962 6963 thermal-sensors = <&tsens1 7>; 6964 6965 trips { 6966 trip-point0 { 6967 temperature = <105000>; 6968 hysteresis = <5000>; 6969 type = "passive"; 6970 }; 6971 6972 trip-point1 { 6973 temperature = <115000>; 6974 hysteresis = <5000>; 6975 type = "passive"; 6976 }; 6977 }; 6978 }; 6979 6980 video-thermal { 6981 thermal-sensors = <&tsens1 8>; 6982 6983 trips { 6984 trip-point0 { 6985 temperature = <105000>; 6986 hysteresis = <5000>; 6987 type = "passive"; 6988 }; 6989 6990 trip-point1 { 6991 temperature = <115000>; 6992 hysteresis = <5000>; 6993 type = "passive"; 6994 }; 6995 }; 6996 }; 6997 6998 camss-1-thermal { 6999 thermal-sensors = <&tsens1 9>; 7000 7001 trips { 7002 trip-point0 { 7003 temperature = <105000>; 7004 hysteresis = <5000>; 7005 type = "passive"; 7006 }; 7007 7008 trip-point1 { 7009 temperature = <115000>; 7010 hysteresis = <5000>; 7011 type = "passive"; 7012 }; 7013 }; 7014 }; 7015 7016 pcie-1-thermal { 7017 thermal-sensors = <&tsens1 10>; 7018 7019 trips { 7020 trip-point0 { 7021 temperature = <105000>; 7022 hysteresis = <5000>; 7023 type = "passive"; 7024 }; 7025 7026 trip-point1 { 7027 temperature = <115000>; 7028 hysteresis = <5000>; 7029 type = "passive"; 7030 }; 7031 }; 7032 }; 7033 7034 cpuss-0-1-thermal { 7035 thermal-sensors = <&tsens1 11>; 7036 7037 trips { 7038 trip-point0 { 7039 temperature = <105000>; 7040 hysteresis = <5000>; 7041 type = "passive"; 7042 }; 7043 7044 trip-point1 { 7045 temperature = <115000>; 7046 hysteresis = <5000>; 7047 type = "passive"; 7048 }; 7049 }; 7050 }; 7051 7052 aoss-2-thermal { 7053 thermal-sensors = <&tsens2 0>; 7054 7055 trips { 7056 trip-point0 { 7057 temperature = <105000>; 7058 hysteresis = <5000>; 7059 type = "passive"; 7060 }; 7061 7062 trip-point1 { 7063 temperature = <115000>; 7064 hysteresis = <5000>; 7065 type = "passive"; 7066 }; 7067 }; 7068 }; 7069 7070 cpu-1-0-0-thermal { 7071 polling-delay-passive = <10>; 7072 7073 thermal-sensors = <&tsens2 1>; 7074 7075 trips { 7076 trip-point0 { 7077 temperature = <105000>; 7078 hysteresis = <5000>; 7079 type = "passive"; 7080 }; 7081 7082 trip-point1 { 7083 temperature = <115000>; 7084 hysteresis = <5000>; 7085 type = "passive"; 7086 }; 7087 }; 7088 }; 7089 7090 cpu-1-1-0-thermal { 7091 polling-delay-passive = <10>; 7092 7093 thermal-sensors = <&tsens2 2>; 7094 7095 trips { 7096 trip-point0 { 7097 temperature = <105000>; 7098 hysteresis = <5000>; 7099 type = "passive"; 7100 }; 7101 7102 trip-point1 { 7103 temperature = <115000>; 7104 hysteresis = <5000>; 7105 type = "passive"; 7106 }; 7107 }; 7108 }; 7109 7110 cpu-1-2-0-thermal { 7111 polling-delay-passive = <10>; 7112 7113 thermal-sensors = <&tsens2 3>; 7114 7115 trips { 7116 trip-point0 { 7117 temperature = <105000>; 7118 hysteresis = <5000>; 7119 type = "passive"; 7120 }; 7121 7122 trip-point1 { 7123 temperature = <115000>; 7124 hysteresis = <5000>; 7125 type = "passive"; 7126 }; 7127 }; 7128 }; 7129 7130 cpu-1-3-0-thermal { 7131 polling-delay-passive = <10>; 7132 7133 thermal-sensors = <&tsens2 4>; 7134 7135 trips { 7136 trip-point0 { 7137 temperature = <105000>; 7138 hysteresis = <5000>; 7139 type = "passive"; 7140 }; 7141 7142 trip-point1 { 7143 temperature = <115000>; 7144 hysteresis = <5000>; 7145 type = "passive"; 7146 }; 7147 }; 7148 }; 7149 7150 nsp-0-0-0-thermal { 7151 polling-delay-passive = <10>; 7152 7153 thermal-sensors = <&tsens2 5>; 7154 7155 trips { 7156 trip-point0 { 7157 temperature = <105000>; 7158 hysteresis = <5000>; 7159 type = "passive"; 7160 }; 7161 7162 trip-point1 { 7163 temperature = <115000>; 7164 hysteresis = <5000>; 7165 type = "passive"; 7166 }; 7167 }; 7168 }; 7169 7170 nsp-0-1-0-thermal { 7171 polling-delay-passive = <10>; 7172 7173 thermal-sensors = <&tsens2 6>; 7174 7175 trips { 7176 trip-point0 { 7177 temperature = <105000>; 7178 hysteresis = <5000>; 7179 type = "passive"; 7180 }; 7181 7182 trip-point1 { 7183 temperature = <115000>; 7184 hysteresis = <5000>; 7185 type = "passive"; 7186 }; 7187 }; 7188 }; 7189 7190 nsp-0-2-0-thermal { 7191 polling-delay-passive = <10>; 7192 7193 thermal-sensors = <&tsens2 7>; 7194 7195 trips { 7196 trip-point0 { 7197 temperature = <105000>; 7198 hysteresis = <5000>; 7199 type = "passive"; 7200 }; 7201 7202 trip-point1 { 7203 temperature = <115000>; 7204 hysteresis = <5000>; 7205 type = "passive"; 7206 }; 7207 }; 7208 }; 7209 7210 nsp-1-0-0-thermal { 7211 polling-delay-passive = <10>; 7212 7213 thermal-sensors = <&tsens2 8>; 7214 7215 trips { 7216 trip-point0 { 7217 temperature = <105000>; 7218 hysteresis = <5000>; 7219 type = "passive"; 7220 }; 7221 7222 trip-point1 { 7223 temperature = <115000>; 7224 hysteresis = <5000>; 7225 type = "passive"; 7226 }; 7227 }; 7228 }; 7229 7230 nsp-1-1-0-thermal { 7231 polling-delay-passive = <10>; 7232 7233 thermal-sensors = <&tsens2 9>; 7234 7235 trips { 7236 trip-point0 { 7237 temperature = <105000>; 7238 hysteresis = <5000>; 7239 type = "passive"; 7240 }; 7241 7242 trip-point1 { 7243 temperature = <115000>; 7244 hysteresis = <5000>; 7245 type = "passive"; 7246 }; 7247 }; 7248 }; 7249 7250 nsp-1-2-0-thermal { 7251 polling-delay-passive = <10>; 7252 7253 thermal-sensors = <&tsens2 10>; 7254 7255 trips { 7256 trip-point0 { 7257 temperature = <105000>; 7258 hysteresis = <5000>; 7259 type = "passive"; 7260 }; 7261 7262 trip-point1 { 7263 temperature = <115000>; 7264 hysteresis = <5000>; 7265 type = "passive"; 7266 }; 7267 }; 7268 }; 7269 7270 ddrss-0-thermal { 7271 thermal-sensors = <&tsens2 11>; 7272 7273 trips { 7274 trip-point0 { 7275 temperature = <105000>; 7276 hysteresis = <5000>; 7277 type = "passive"; 7278 }; 7279 7280 trip-point1 { 7281 temperature = <115000>; 7282 hysteresis = <5000>; 7283 type = "passive"; 7284 }; 7285 }; 7286 }; 7287 7288 cpuss-1-0-thermal { 7289 thermal-sensors = <&tsens2 12>; 7290 7291 trips { 7292 trip-point0 { 7293 temperature = <105000>; 7294 hysteresis = <5000>; 7295 type = "passive"; 7296 }; 7297 7298 trip-point1 { 7299 temperature = <115000>; 7300 hysteresis = <5000>; 7301 type = "passive"; 7302 }; 7303 }; 7304 }; 7305 7306 aoss-3-thermal { 7307 thermal-sensors = <&tsens3 0>; 7308 7309 trips { 7310 trip-point0 { 7311 temperature = <105000>; 7312 hysteresis = <5000>; 7313 type = "passive"; 7314 }; 7315 7316 trip-point1 { 7317 temperature = <115000>; 7318 hysteresis = <5000>; 7319 type = "passive"; 7320 }; 7321 }; 7322 }; 7323 7324 cpu-1-0-1-thermal { 7325 polling-delay-passive = <10>; 7326 7327 thermal-sensors = <&tsens3 1>; 7328 7329 trips { 7330 trip-point0 { 7331 temperature = <105000>; 7332 hysteresis = <5000>; 7333 type = "passive"; 7334 }; 7335 7336 trip-point1 { 7337 temperature = <115000>; 7338 hysteresis = <5000>; 7339 type = "passive"; 7340 }; 7341 }; 7342 }; 7343 7344 cpu-1-1-1-thermal { 7345 polling-delay-passive = <10>; 7346 7347 thermal-sensors = <&tsens3 2>; 7348 7349 trips { 7350 trip-point0 { 7351 temperature = <105000>; 7352 hysteresis = <5000>; 7353 type = "passive"; 7354 }; 7355 7356 trip-point1 { 7357 temperature = <115000>; 7358 hysteresis = <5000>; 7359 type = "passive"; 7360 }; 7361 }; 7362 }; 7363 7364 cpu-1-2-1-thermal { 7365 polling-delay-passive = <10>; 7366 7367 thermal-sensors = <&tsens3 3>; 7368 7369 trips { 7370 trip-point0 { 7371 temperature = <105000>; 7372 hysteresis = <5000>; 7373 type = "passive"; 7374 }; 7375 7376 trip-point1 { 7377 temperature = <115000>; 7378 hysteresis = <5000>; 7379 type = "passive"; 7380 }; 7381 }; 7382 }; 7383 7384 cpu-1-3-1-thermal { 7385 polling-delay-passive = <10>; 7386 7387 thermal-sensors = <&tsens3 4>; 7388 7389 trips { 7390 trip-point0 { 7391 temperature = <105000>; 7392 hysteresis = <5000>; 7393 type = "passive"; 7394 }; 7395 7396 trip-point1 { 7397 temperature = <115000>; 7398 hysteresis = <5000>; 7399 type = "passive"; 7400 }; 7401 }; 7402 }; 7403 7404 nsp-0-0-1-thermal { 7405 polling-delay-passive = <10>; 7406 7407 thermal-sensors = <&tsens3 5>; 7408 7409 trips { 7410 trip-point0 { 7411 temperature = <105000>; 7412 hysteresis = <5000>; 7413 type = "passive"; 7414 }; 7415 7416 trip-point1 { 7417 temperature = <115000>; 7418 hysteresis = <5000>; 7419 type = "passive"; 7420 }; 7421 }; 7422 }; 7423 7424 nsp-0-1-1-thermal { 7425 polling-delay-passive = <10>; 7426 7427 thermal-sensors = <&tsens3 6>; 7428 7429 trips { 7430 trip-point0 { 7431 temperature = <105000>; 7432 hysteresis = <5000>; 7433 type = "passive"; 7434 }; 7435 7436 trip-point1 { 7437 temperature = <115000>; 7438 hysteresis = <5000>; 7439 type = "passive"; 7440 }; 7441 }; 7442 }; 7443 7444 nsp-0-2-1-thermal { 7445 polling-delay-passive = <10>; 7446 7447 thermal-sensors = <&tsens3 7>; 7448 7449 trips { 7450 trip-point0 { 7451 temperature = <105000>; 7452 hysteresis = <5000>; 7453 type = "passive"; 7454 }; 7455 7456 trip-point1 { 7457 temperature = <115000>; 7458 hysteresis = <5000>; 7459 type = "passive"; 7460 }; 7461 }; 7462 }; 7463 7464 nsp-1-0-1-thermal { 7465 polling-delay-passive = <10>; 7466 7467 thermal-sensors = <&tsens3 8>; 7468 7469 trips { 7470 trip-point0 { 7471 temperature = <105000>; 7472 hysteresis = <5000>; 7473 type = "passive"; 7474 }; 7475 7476 trip-point1 { 7477 temperature = <115000>; 7478 hysteresis = <5000>; 7479 type = "passive"; 7480 }; 7481 }; 7482 }; 7483 7484 nsp-1-1-1-thermal { 7485 polling-delay-passive = <10>; 7486 7487 thermal-sensors = <&tsens3 9>; 7488 7489 trips { 7490 trip-point0 { 7491 temperature = <105000>; 7492 hysteresis = <5000>; 7493 type = "passive"; 7494 }; 7495 7496 trip-point1 { 7497 temperature = <115000>; 7498 hysteresis = <5000>; 7499 type = "passive"; 7500 }; 7501 }; 7502 }; 7503 7504 nsp-1-2-1-thermal { 7505 polling-delay-passive = <10>; 7506 7507 thermal-sensors = <&tsens3 10>; 7508 7509 trips { 7510 trip-point0 { 7511 temperature = <105000>; 7512 hysteresis = <5000>; 7513 type = "passive"; 7514 }; 7515 7516 trip-point1 { 7517 temperature = <115000>; 7518 hysteresis = <5000>; 7519 type = "passive"; 7520 }; 7521 }; 7522 }; 7523 7524 ddrss-1-thermal { 7525 thermal-sensors = <&tsens3 11>; 7526 7527 trips { 7528 trip-point0 { 7529 temperature = <105000>; 7530 hysteresis = <5000>; 7531 type = "passive"; 7532 }; 7533 7534 trip-point1 { 7535 temperature = <115000>; 7536 hysteresis = <5000>; 7537 type = "passive"; 7538 }; 7539 }; 7540 }; 7541 7542 cpuss-1-1-thermal { 7543 thermal-sensors = <&tsens3 12>; 7544 7545 trips { 7546 trip-point0 { 7547 temperature = <105000>; 7548 hysteresis = <5000>; 7549 type = "passive"; 7550 }; 7551 7552 trip-point1 { 7553 temperature = <115000>; 7554 hysteresis = <5000>; 7555 type = "passive"; 7556 }; 7557 }; 7558 }; 7559 }; 7560 7561 arch_timer: timer { 7562 compatible = "arm,armv8-timer"; 7563 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7564 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7565 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 7566 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 7567 }; 7568 7569 pcie0: pcie@1c00000 { 7570 compatible = "qcom,pcie-sa8775p"; 7571 reg = <0x0 0x01c00000 0x0 0x3000>, 7572 <0x0 0x40000000 0x0 0xf20>, 7573 <0x0 0x40000f20 0x0 0xa8>, 7574 <0x0 0x40001000 0x0 0x4000>, 7575 <0x0 0x40100000 0x0 0x100000>, 7576 <0x0 0x01c03000 0x0 0x1000>; 7577 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 7578 device_type = "pci"; 7579 7580 #address-cells = <3>; 7581 #size-cells = <2>; 7582 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 7583 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 7584 bus-range = <0x00 0xff>; 7585 7586 dma-coherent; 7587 7588 linux,pci-domain = <0>; 7589 num-lanes = <2>; 7590 7591 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 7592 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 7593 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 7594 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 7595 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 7596 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 7597 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 7598 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 7599 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 7600 interrupt-names = "msi0", 7601 "msi1", 7602 "msi2", 7603 "msi3", 7604 "msi4", 7605 "msi5", 7606 "msi6", 7607 "msi7", 7608 "global"; 7609 #interrupt-cells = <1>; 7610 interrupt-map-mask = <0 0 0 0x7>; 7611 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 7612 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 7613 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 7614 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 7615 7616 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 7617 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 7618 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 7619 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 7620 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 7621 7622 clock-names = "aux", 7623 "cfg", 7624 "bus_master", 7625 "bus_slave", 7626 "slave_q2a"; 7627 7628 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 7629 assigned-clock-rates = <19200000>; 7630 7631 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 7632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 7633 interconnect-names = "pcie-mem", "cpu-pcie"; 7634 7635 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 7636 <0x100 &pcie_smmu 0x0001 0x1>; 7637 7638 resets = <&gcc GCC_PCIE_0_BCR>; 7639 reset-names = "pci"; 7640 power-domains = <&gcc PCIE_0_GDSC>; 7641 7642 phys = <&pcie0_phy>; 7643 phy-names = "pciephy"; 7644 7645 status = "disabled"; 7646 7647 pcieport0: pcie@0 { 7648 device_type = "pci"; 7649 reg = <0x0 0x0 0x0 0x0 0x0>; 7650 bus-range = <0x01 0xff>; 7651 7652 #address-cells = <3>; 7653 #size-cells = <2>; 7654 ranges; 7655 }; 7656 }; 7657 7658 pcie0_ep: pcie-ep@1c00000 { 7659 compatible = "qcom,sa8775p-pcie-ep"; 7660 reg = <0x0 0x01c00000 0x0 0x3000>, 7661 <0x0 0x40000000 0x0 0xf20>, 7662 <0x0 0x40000f20 0x0 0xa8>, 7663 <0x0 0x40001000 0x0 0x4000>, 7664 <0x0 0x40200000 0x0 0x1fe00000>, 7665 <0x0 0x01c03000 0x0 0x1000>, 7666 <0x0 0x40005000 0x0 0x2000>; 7667 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 7668 "mmio", "dma"; 7669 7670 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 7671 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 7672 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 7673 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 7674 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 7675 7676 clock-names = "aux", 7677 "cfg", 7678 "bus_master", 7679 "bus_slave", 7680 "slave_q2a"; 7681 7682 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 7683 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 7684 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 7685 7686 interrupt-names = "global", "doorbell", "dma"; 7687 7688 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 7689 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 7690 interconnect-names = "pcie-mem", "cpu-pcie"; 7691 7692 dma-coherent; 7693 iommus = <&pcie_smmu 0x0000 0x7f>; 7694 resets = <&gcc GCC_PCIE_0_BCR>; 7695 reset-names = "core"; 7696 power-domains = <&gcc PCIE_0_GDSC>; 7697 phys = <&pcie0_phy>; 7698 phy-names = "pciephy"; 7699 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 7700 num-lanes = <2>; 7701 linux,pci-domain = <0>; 7702 7703 status = "disabled"; 7704 }; 7705 7706 pcie0_phy: phy@1c04000 { 7707 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 7708 reg = <0x0 0x1c04000 0x0 0x2000>; 7709 7710 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 7711 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 7712 <&gcc GCC_PCIE_CLKREF_EN>, 7713 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 7714 <&gcc GCC_PCIE_0_PIPE_CLK>, 7715 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 7716 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 7717 7718 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 7719 "pipediv2", "phy_aux"; 7720 7721 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 7722 assigned-clock-rates = <100000000>; 7723 7724 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 7725 reset-names = "phy"; 7726 7727 #clock-cells = <0>; 7728 clock-output-names = "pcie_0_pipe_clk"; 7729 7730 #phy-cells = <0>; 7731 7732 status = "disabled"; 7733 }; 7734 7735 pcie1: pcie@1c10000 { 7736 compatible = "qcom,pcie-sa8775p"; 7737 reg = <0x0 0x01c10000 0x0 0x3000>, 7738 <0x0 0x60000000 0x0 0xf20>, 7739 <0x0 0x60000f20 0x0 0xa8>, 7740 <0x0 0x60001000 0x0 0x4000>, 7741 <0x0 0x60100000 0x0 0x100000>, 7742 <0x0 0x01c13000 0x0 0x1000>; 7743 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 7744 device_type = "pci"; 7745 7746 #address-cells = <3>; 7747 #size-cells = <2>; 7748 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 7749 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 7750 bus-range = <0x00 0xff>; 7751 7752 dma-coherent; 7753 7754 linux,pci-domain = <1>; 7755 num-lanes = <4>; 7756 7757 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 7758 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 7759 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 7760 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 7761 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 7762 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 7763 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 7764 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 7765 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 7766 interrupt-names = "msi0", 7767 "msi1", 7768 "msi2", 7769 "msi3", 7770 "msi4", 7771 "msi5", 7772 "msi6", 7773 "msi7", 7774 "global"; 7775 #interrupt-cells = <1>; 7776 interrupt-map-mask = <0 0 0 0x7>; 7777 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 7778 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 7779 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 7780 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 7781 7782 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 7783 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 7784 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 7785 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 7786 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 7787 7788 clock-names = "aux", 7789 "cfg", 7790 "bus_master", 7791 "bus_slave", 7792 "slave_q2a"; 7793 7794 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 7795 assigned-clock-rates = <19200000>; 7796 7797 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 7798 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 7799 interconnect-names = "pcie-mem", "cpu-pcie"; 7800 7801 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 7802 <0x100 &pcie_smmu 0x0081 0x1>; 7803 7804 resets = <&gcc GCC_PCIE_1_BCR>; 7805 reset-names = "pci"; 7806 power-domains = <&gcc PCIE_1_GDSC>; 7807 7808 phys = <&pcie1_phy>; 7809 phy-names = "pciephy"; 7810 7811 status = "disabled"; 7812 7813 pcie@0 { 7814 device_type = "pci"; 7815 reg = <0x0 0x0 0x0 0x0 0x0>; 7816 bus-range = <0x01 0xff>; 7817 7818 #address-cells = <3>; 7819 #size-cells = <2>; 7820 ranges; 7821 }; 7822 }; 7823 7824 pcie1_ep: pcie-ep@1c10000 { 7825 compatible = "qcom,sa8775p-pcie-ep"; 7826 reg = <0x0 0x01c10000 0x0 0x3000>, 7827 <0x0 0x60000000 0x0 0xf20>, 7828 <0x0 0x60000f20 0x0 0xa8>, 7829 <0x0 0x60001000 0x0 0x4000>, 7830 <0x0 0x60200000 0x0 0x1fe00000>, 7831 <0x0 0x01c13000 0x0 0x1000>, 7832 <0x0 0x60005000 0x0 0x2000>; 7833 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 7834 "mmio", "dma"; 7835 7836 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 7837 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 7838 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 7839 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 7840 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 7841 7842 clock-names = "aux", 7843 "cfg", 7844 "bus_master", 7845 "bus_slave", 7846 "slave_q2a"; 7847 7848 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 7849 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 7850 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 7851 7852 interrupt-names = "global", "doorbell", "dma"; 7853 7854 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 7855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 7856 interconnect-names = "pcie-mem", "cpu-pcie"; 7857 7858 dma-coherent; 7859 iommus = <&pcie_smmu 0x80 0x7f>; 7860 resets = <&gcc GCC_PCIE_1_BCR>; 7861 reset-names = "core"; 7862 power-domains = <&gcc PCIE_1_GDSC>; 7863 phys = <&pcie1_phy>; 7864 phy-names = "pciephy"; 7865 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 7866 num-lanes = <4>; 7867 linux,pci-domain = <1>; 7868 7869 status = "disabled"; 7870 }; 7871 7872 pcie1_phy: phy@1c14000 { 7873 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 7874 reg = <0x0 0x1c14000 0x0 0x4000>; 7875 7876 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 7877 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 7878 <&gcc GCC_PCIE_CLKREF_EN>, 7879 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 7880 <&gcc GCC_PCIE_1_PIPE_CLK>, 7881 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 7882 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 7883 7884 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 7885 "pipediv2", "phy_aux"; 7886 7887 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 7888 assigned-clock-rates = <100000000>; 7889 7890 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 7891 reset-names = "phy"; 7892 7893 #clock-cells = <0>; 7894 clock-output-names = "pcie_1_pipe_clk"; 7895 7896 #phy-cells = <0>; 7897 7898 status = "disabled"; 7899 }; 7900}; 7901