1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Check for KVM_GET_REG_LIST regressions. 4 * 5 * Copyright (C) 2020, Red Hat, Inc. 6 * 7 * While the blessed list should be created from the oldest possible 8 * kernel, we can't go older than v5.2, though, because that's the first 9 * release which includes df205b5c6328 ("KVM: arm64: Filter out invalid 10 * core register IDs in KVM_GET_REG_LIST"). Without that commit the core 11 * registers won't match expectations. 12 */ 13 #include <stdio.h> 14 #include "kvm_util.h" 15 #include "test_util.h" 16 #include "processor.h" 17 18 #define SYS_REG(r) ARM64_SYS_REG(sys_reg_Op0(SYS_ ## r), \ 19 sys_reg_Op1(SYS_ ## r), \ 20 sys_reg_CRn(SYS_ ## r), \ 21 sys_reg_CRm(SYS_ ## r), \ 22 sys_reg_Op2(SYS_ ## r)) 23 24 struct feature_id_reg { 25 __u64 reg; 26 __u64 id_reg; 27 __u64 feat_shift; 28 __u64 feat_min; 29 }; 30 31 #define FEAT(id, f, v) \ 32 .id_reg = SYS_REG(id), \ 33 .feat_shift = id ## _ ## f ## _SHIFT, \ 34 .feat_min = id ## _ ## f ## _ ## v 35 36 #define REG_FEAT(r, id, f, v) \ 37 { \ 38 .reg = SYS_REG(r), \ 39 FEAT(id, f, v) \ 40 } 41 42 static struct feature_id_reg feat_id_regs[] = { 43 REG_FEAT(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), 44 REG_FEAT(TCR2_EL2, ID_AA64MMFR3_EL1, TCRX, IMP), 45 REG_FEAT(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), 46 REG_FEAT(PIRE0_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), 47 REG_FEAT(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), 48 REG_FEAT(PIR_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), 49 REG_FEAT(POR_EL1, ID_AA64MMFR3_EL1, S1POE, IMP), 50 REG_FEAT(POR_EL0, ID_AA64MMFR3_EL1, S1POE, IMP), 51 REG_FEAT(POR_EL2, ID_AA64MMFR3_EL1, S1POE, IMP), 52 REG_FEAT(HCRX_EL2, ID_AA64MMFR1_EL1, HCX, IMP), 53 REG_FEAT(HFGRTR_EL2, ID_AA64MMFR0_EL1, FGT, IMP), 54 REG_FEAT(HFGWTR_EL2, ID_AA64MMFR0_EL1, FGT, IMP), 55 REG_FEAT(HFGITR_EL2, ID_AA64MMFR0_EL1, FGT, IMP), 56 REG_FEAT(HDFGRTR_EL2, ID_AA64MMFR0_EL1, FGT, IMP), 57 REG_FEAT(HDFGWTR_EL2, ID_AA64MMFR0_EL1, FGT, IMP), 58 REG_FEAT(HAFGRTR_EL2, ID_AA64MMFR0_EL1, FGT, IMP), 59 REG_FEAT(HFGRTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), 60 REG_FEAT(HFGWTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), 61 REG_FEAT(HFGITR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), 62 REG_FEAT(HDFGRTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), 63 REG_FEAT(HDFGWTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), 64 REG_FEAT(ZCR_EL2, ID_AA64PFR0_EL1, SVE, IMP), 65 REG_FEAT(SCTLR2_EL1, ID_AA64MMFR3_EL1, SCTLRX, IMP), 66 REG_FEAT(SCTLR2_EL2, ID_AA64MMFR3_EL1, SCTLRX, IMP), 67 REG_FEAT(VDISR_EL2, ID_AA64PFR0_EL1, RAS, IMP), 68 REG_FEAT(VSESR_EL2, ID_AA64PFR0_EL1, RAS, IMP), 69 REG_FEAT(VNCR_EL2, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY), 70 REG_FEAT(NVHCR_EL2, ID_AA64MMFR4_EL1, NV_frac, NV3), 71 REG_FEAT(CNTHV_CTL_EL2, ID_AA64MMFR1_EL1, VH, IMP), 72 REG_FEAT(CNTHV_CVAL_EL2,ID_AA64MMFR1_EL1, VH, IMP), 73 REG_FEAT(ZCR_EL2, ID_AA64PFR0_EL1, SVE, IMP), 74 }; 75 76 bool filter_reg(__u64 reg) 77 { 78 /* 79 * DEMUX register presence depends on the host's CLIDR_EL1. 80 * This means there's no set of them that we can bless. 81 */ 82 if ((reg & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 83 return true; 84 85 return false; 86 } 87 88 static bool check_supported_feat_reg(struct kvm_vcpu *vcpu, __u64 reg) 89 { 90 int i, ret; 91 __u64 data, feat_val; 92 93 for (i = 0; i < ARRAY_SIZE(feat_id_regs); i++) { 94 if (feat_id_regs[i].reg == reg) { 95 ret = __vcpu_get_reg(vcpu, feat_id_regs[i].id_reg, &data); 96 if (ret < 0) 97 return false; 98 99 feat_val = ((data >> feat_id_regs[i].feat_shift) & 0xf); 100 return feat_val >= feat_id_regs[i].feat_min; 101 } 102 } 103 104 return true; 105 } 106 107 bool check_supported_reg(struct kvm_vcpu *vcpu, __u64 reg) 108 { 109 return check_supported_feat_reg(vcpu, reg); 110 } 111 112 bool check_reject_set(int err) 113 { 114 return err == EPERM; 115 } 116 117 void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) 118 { 119 struct vcpu_reg_sublist *s; 120 int feature; 121 122 for_each_sublist(c, s) { 123 if (s->finalize) { 124 feature = s->feature; 125 vcpu_ioctl(vcpu, KVM_ARM_VCPU_FINALIZE, &feature); 126 } 127 } 128 } 129 130 #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_COPROC_MASK) 131 132 #define CORE_REGS_XX_NR_WORDS 2 133 #define CORE_SPSR_XX_NR_WORDS 2 134 #define CORE_FPREGS_XX_NR_WORDS 4 135 136 static const char *core_id_to_str(const char *prefix, __u64 id) 137 { 138 __u64 core_off = id & ~REG_MASK, idx; 139 140 /* 141 * core_off is the offset into struct kvm_regs 142 */ 143 switch (core_off) { 144 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ... 145 KVM_REG_ARM_CORE_REG(regs.regs[30]): 146 idx = (core_off - KVM_REG_ARM_CORE_REG(regs.regs[0])) / CORE_REGS_XX_NR_WORDS; 147 TEST_ASSERT(idx < 31, "%s: Unexpected regs.regs index: %lld", prefix, idx); 148 return strdup_printf("KVM_REG_ARM_CORE_REG(regs.regs[%lld])", idx); 149 case KVM_REG_ARM_CORE_REG(regs.sp): 150 return "KVM_REG_ARM_CORE_REG(regs.sp)"; 151 case KVM_REG_ARM_CORE_REG(regs.pc): 152 return "KVM_REG_ARM_CORE_REG(regs.pc)"; 153 case KVM_REG_ARM_CORE_REG(regs.pstate): 154 return "KVM_REG_ARM_CORE_REG(regs.pstate)"; 155 case KVM_REG_ARM_CORE_REG(sp_el1): 156 return "KVM_REG_ARM_CORE_REG(sp_el1)"; 157 case KVM_REG_ARM_CORE_REG(elr_el1): 158 return "KVM_REG_ARM_CORE_REG(elr_el1)"; 159 case KVM_REG_ARM_CORE_REG(spsr[0]) ... 160 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]): 161 idx = (core_off - KVM_REG_ARM_CORE_REG(spsr[0])) / CORE_SPSR_XX_NR_WORDS; 162 TEST_ASSERT(idx < KVM_NR_SPSR, "%s: Unexpected spsr index: %lld", prefix, idx); 163 return strdup_printf("KVM_REG_ARM_CORE_REG(spsr[%lld])", idx); 164 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ... 165 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]): 166 idx = (core_off - KVM_REG_ARM_CORE_REG(fp_regs.vregs[0])) / CORE_FPREGS_XX_NR_WORDS; 167 TEST_ASSERT(idx < 32, "%s: Unexpected fp_regs.vregs index: %lld", prefix, idx); 168 return strdup_printf("KVM_REG_ARM_CORE_REG(fp_regs.vregs[%lld])", idx); 169 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr): 170 return "KVM_REG_ARM_CORE_REG(fp_regs.fpsr)"; 171 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr): 172 return "KVM_REG_ARM_CORE_REG(fp_regs.fpcr)"; 173 } 174 175 TEST_FAIL("%s: Unknown core reg id: 0x%llx", prefix, id); 176 return NULL; 177 } 178 179 static const char *sve_id_to_str(const char *prefix, __u64 id) 180 { 181 __u64 sve_off, n, i; 182 183 if (id == KVM_REG_ARM64_SVE_VLS) 184 return "KVM_REG_ARM64_SVE_VLS"; 185 186 sve_off = id & ~(REG_MASK | ((1ULL << 5) - 1)); 187 i = id & (KVM_ARM64_SVE_MAX_SLICES - 1); 188 189 TEST_ASSERT(i == 0, "%s: Currently we don't expect slice > 0, reg id 0x%llx", prefix, id); 190 191 switch (sve_off) { 192 case KVM_REG_ARM64_SVE_ZREG_BASE ... 193 KVM_REG_ARM64_SVE_ZREG_BASE + (1ULL << 5) * KVM_ARM64_SVE_NUM_ZREGS - 1: 194 n = (id >> 5) & (KVM_ARM64_SVE_NUM_ZREGS - 1); 195 TEST_ASSERT(id == KVM_REG_ARM64_SVE_ZREG(n, 0), 196 "%s: Unexpected bits set in SVE ZREG id: 0x%llx", prefix, id); 197 return strdup_printf("KVM_REG_ARM64_SVE_ZREG(%lld, 0)", n); 198 case KVM_REG_ARM64_SVE_PREG_BASE ... 199 KVM_REG_ARM64_SVE_PREG_BASE + (1ULL << 5) * KVM_ARM64_SVE_NUM_PREGS - 1: 200 n = (id >> 5) & (KVM_ARM64_SVE_NUM_PREGS - 1); 201 TEST_ASSERT(id == KVM_REG_ARM64_SVE_PREG(n, 0), 202 "%s: Unexpected bits set in SVE PREG id: 0x%llx", prefix, id); 203 return strdup_printf("KVM_REG_ARM64_SVE_PREG(%lld, 0)", n); 204 case KVM_REG_ARM64_SVE_FFR_BASE: 205 TEST_ASSERT(id == KVM_REG_ARM64_SVE_FFR(0), 206 "%s: Unexpected bits set in SVE FFR id: 0x%llx", prefix, id); 207 return "KVM_REG_ARM64_SVE_FFR(0)"; 208 } 209 210 return NULL; 211 } 212 213 void print_reg(const char *prefix, __u64 id) 214 { 215 unsigned op0, op1, crn, crm, op2; 216 const char *reg_size = NULL; 217 218 TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_ARM64, 219 "%s: KVM_REG_ARM64 missing in reg id: 0x%llx", prefix, id); 220 221 switch (id & KVM_REG_SIZE_MASK) { 222 case KVM_REG_SIZE_U8: 223 reg_size = "KVM_REG_SIZE_U8"; 224 break; 225 case KVM_REG_SIZE_U16: 226 reg_size = "KVM_REG_SIZE_U16"; 227 break; 228 case KVM_REG_SIZE_U32: 229 reg_size = "KVM_REG_SIZE_U32"; 230 break; 231 case KVM_REG_SIZE_U64: 232 reg_size = "KVM_REG_SIZE_U64"; 233 break; 234 case KVM_REG_SIZE_U128: 235 reg_size = "KVM_REG_SIZE_U128"; 236 break; 237 case KVM_REG_SIZE_U256: 238 reg_size = "KVM_REG_SIZE_U256"; 239 break; 240 case KVM_REG_SIZE_U512: 241 reg_size = "KVM_REG_SIZE_U512"; 242 break; 243 case KVM_REG_SIZE_U1024: 244 reg_size = "KVM_REG_SIZE_U1024"; 245 break; 246 case KVM_REG_SIZE_U2048: 247 reg_size = "KVM_REG_SIZE_U2048"; 248 break; 249 default: 250 TEST_FAIL("%s: Unexpected reg size: 0x%llx in reg id: 0x%llx", 251 prefix, (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id); 252 } 253 254 switch (id & KVM_REG_ARM_COPROC_MASK) { 255 case KVM_REG_ARM_CORE: 256 printf("\tKVM_REG_ARM64 | %s | KVM_REG_ARM_CORE | %s,\n", reg_size, core_id_to_str(prefix, id)); 257 break; 258 case KVM_REG_ARM_DEMUX: 259 TEST_ASSERT(!(id & ~(REG_MASK | KVM_REG_ARM_DEMUX_ID_MASK | KVM_REG_ARM_DEMUX_VAL_MASK)), 260 "%s: Unexpected bits set in DEMUX reg id: 0x%llx", prefix, id); 261 printf("\tKVM_REG_ARM64 | %s | KVM_REG_ARM_DEMUX | KVM_REG_ARM_DEMUX_ID_CCSIDR | %lld,\n", 262 reg_size, id & KVM_REG_ARM_DEMUX_VAL_MASK); 263 break; 264 case KVM_REG_ARM64_SYSREG: 265 op0 = (id & KVM_REG_ARM64_SYSREG_OP0_MASK) >> KVM_REG_ARM64_SYSREG_OP0_SHIFT; 266 op1 = (id & KVM_REG_ARM64_SYSREG_OP1_MASK) >> KVM_REG_ARM64_SYSREG_OP1_SHIFT; 267 crn = (id & KVM_REG_ARM64_SYSREG_CRN_MASK) >> KVM_REG_ARM64_SYSREG_CRN_SHIFT; 268 crm = (id & KVM_REG_ARM64_SYSREG_CRM_MASK) >> KVM_REG_ARM64_SYSREG_CRM_SHIFT; 269 op2 = (id & KVM_REG_ARM64_SYSREG_OP2_MASK) >> KVM_REG_ARM64_SYSREG_OP2_SHIFT; 270 TEST_ASSERT(id == ARM64_SYS_REG(op0, op1, crn, crm, op2), 271 "%s: Unexpected bits set in SYSREG reg id: 0x%llx", prefix, id); 272 printf("\tARM64_SYS_REG(%d, %d, %d, %d, %d),\n", op0, op1, crn, crm, op2); 273 break; 274 case KVM_REG_ARM_FW: 275 TEST_ASSERT(id == KVM_REG_ARM_FW_REG(id & 0xffff), 276 "%s: Unexpected bits set in FW reg id: 0x%llx", prefix, id); 277 printf("\tKVM_REG_ARM_FW_REG(%lld),\n", id & 0xffff); 278 break; 279 case KVM_REG_ARM_FW_FEAT_BMAP: 280 TEST_ASSERT(id == KVM_REG_ARM_FW_FEAT_BMAP_REG(id & 0xffff), 281 "%s: Unexpected bits set in the bitmap feature FW reg id: 0x%llx", prefix, id); 282 printf("\tKVM_REG_ARM_FW_FEAT_BMAP_REG(%lld),\n", id & 0xffff); 283 break; 284 case KVM_REG_ARM64_SVE: 285 printf("\t%s,\n", sve_id_to_str(prefix, id)); 286 break; 287 default: 288 TEST_FAIL("%s: Unexpected coproc type: 0x%llx in reg id: 0x%llx", 289 prefix, (id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT, id); 290 } 291 } 292 293 /* 294 * The original blessed list was primed with the output of kernel version 295 * v4.15 with --core-reg-fixup and then later updated with new registers. 296 * (The --core-reg-fixup option and it's fixup function have been removed 297 * from the test, as it's unlikely to use this type of test on a kernel 298 * older than v5.2.) 299 * 300 * The blessed list is up to date with kernel version v6.4 (or so we hope) 301 */ 302 static __u64 base_regs[] = { 303 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[0]), 304 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[1]), 305 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[2]), 306 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[3]), 307 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[4]), 308 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[5]), 309 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[6]), 310 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[7]), 311 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[8]), 312 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[9]), 313 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[10]), 314 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[11]), 315 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[12]), 316 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[13]), 317 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[14]), 318 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[15]), 319 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[16]), 320 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[17]), 321 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[18]), 322 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[19]), 323 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[20]), 324 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[21]), 325 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[22]), 326 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[23]), 327 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[24]), 328 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[25]), 329 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[26]), 330 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[27]), 331 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[28]), 332 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[29]), 333 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[30]), 334 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.sp), 335 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.pc), 336 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.pstate), 337 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(sp_el1), 338 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(elr_el1), 339 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(spsr[0]), 340 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(spsr[1]), 341 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(spsr[2]), 342 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(spsr[3]), 343 KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(spsr[4]), 344 KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.fpsr), 345 KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.fpcr), 346 KVM_REG_ARM_FW_REG(0), /* KVM_REG_ARM_PSCI_VERSION */ 347 KVM_REG_ARM_FW_REG(1), /* KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 */ 348 KVM_REG_ARM_FW_REG(2), /* KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 */ 349 KVM_REG_ARM_FW_REG(3), /* KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 */ 350 KVM_REG_ARM_FW_FEAT_BMAP_REG(0), /* KVM_REG_ARM_STD_BMAP */ 351 KVM_REG_ARM_FW_FEAT_BMAP_REG(1), /* KVM_REG_ARM_STD_HYP_BMAP */ 352 KVM_REG_ARM_FW_FEAT_BMAP_REG(2), /* KVM_REG_ARM_VENDOR_HYP_BMAP */ 353 KVM_REG_ARM_FW_FEAT_BMAP_REG(3), /* KVM_REG_ARM_VENDOR_HYP_BMAP_2 */ 354 355 /* 356 * EL0 Virtual Timer Registers 357 * 358 * WARNING: 359 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 360 * with the appropriate register encodings. Their values have been 361 * accidentally swapped. As this is set API, the definitions here 362 * must be used, rather than ones derived from the encodings. 363 */ 364 KVM_ARM64_SYS_REG(SYS_CNTV_CTL_EL0), 365 KVM_REG_ARM_TIMER_CVAL, 366 KVM_REG_ARM_TIMER_CNT, 367 368 ARM64_SYS_REG(3, 0, 0, 0, 0), /* MIDR_EL1 */ 369 ARM64_SYS_REG(3, 0, 0, 0, 6), /* REVIDR_EL1 */ 370 ARM64_SYS_REG(3, 1, 0, 0, 1), /* CLIDR_EL1 */ 371 ARM64_SYS_REG(3, 1, 0, 0, 7), /* AIDR_EL1 */ 372 ARM64_SYS_REG(3, 3, 0, 0, 1), /* CTR_EL0 */ 373 ARM64_SYS_REG(2, 0, 0, 0, 4), 374 ARM64_SYS_REG(2, 0, 0, 0, 5), 375 ARM64_SYS_REG(2, 0, 0, 0, 6), 376 ARM64_SYS_REG(2, 0, 0, 0, 7), 377 ARM64_SYS_REG(2, 0, 0, 1, 4), 378 ARM64_SYS_REG(2, 0, 0, 1, 5), 379 ARM64_SYS_REG(2, 0, 0, 1, 6), 380 ARM64_SYS_REG(2, 0, 0, 1, 7), 381 ARM64_SYS_REG(2, 0, 0, 2, 0), /* MDCCINT_EL1 */ 382 ARM64_SYS_REG(2, 0, 0, 2, 2), /* MDSCR_EL1 */ 383 ARM64_SYS_REG(2, 0, 0, 2, 4), 384 ARM64_SYS_REG(2, 0, 0, 2, 5), 385 ARM64_SYS_REG(2, 0, 0, 2, 6), 386 ARM64_SYS_REG(2, 0, 0, 2, 7), 387 ARM64_SYS_REG(2, 0, 0, 3, 4), 388 ARM64_SYS_REG(2, 0, 0, 3, 5), 389 ARM64_SYS_REG(2, 0, 0, 3, 6), 390 ARM64_SYS_REG(2, 0, 0, 3, 7), 391 ARM64_SYS_REG(2, 0, 0, 4, 4), 392 ARM64_SYS_REG(2, 0, 0, 4, 5), 393 ARM64_SYS_REG(2, 0, 0, 4, 6), 394 ARM64_SYS_REG(2, 0, 0, 4, 7), 395 ARM64_SYS_REG(2, 0, 0, 5, 4), 396 ARM64_SYS_REG(2, 0, 0, 5, 5), 397 ARM64_SYS_REG(2, 0, 0, 5, 6), 398 ARM64_SYS_REG(2, 0, 0, 5, 7), 399 ARM64_SYS_REG(2, 0, 0, 6, 4), 400 ARM64_SYS_REG(2, 0, 0, 6, 5), 401 ARM64_SYS_REG(2, 0, 0, 6, 6), 402 ARM64_SYS_REG(2, 0, 0, 6, 7), 403 ARM64_SYS_REG(2, 0, 0, 7, 4), 404 ARM64_SYS_REG(2, 0, 0, 7, 5), 405 ARM64_SYS_REG(2, 0, 0, 7, 6), 406 ARM64_SYS_REG(2, 0, 0, 7, 7), 407 ARM64_SYS_REG(2, 0, 0, 8, 4), 408 ARM64_SYS_REG(2, 0, 0, 8, 5), 409 ARM64_SYS_REG(2, 0, 0, 8, 6), 410 ARM64_SYS_REG(2, 0, 0, 8, 7), 411 ARM64_SYS_REG(2, 0, 0, 9, 4), 412 ARM64_SYS_REG(2, 0, 0, 9, 5), 413 ARM64_SYS_REG(2, 0, 0, 9, 6), 414 ARM64_SYS_REG(2, 0, 0, 9, 7), 415 ARM64_SYS_REG(2, 0, 0, 10, 4), 416 ARM64_SYS_REG(2, 0, 0, 10, 5), 417 ARM64_SYS_REG(2, 0, 0, 10, 6), 418 ARM64_SYS_REG(2, 0, 0, 10, 7), 419 ARM64_SYS_REG(2, 0, 0, 11, 4), 420 ARM64_SYS_REG(2, 0, 0, 11, 5), 421 ARM64_SYS_REG(2, 0, 0, 11, 6), 422 ARM64_SYS_REG(2, 0, 0, 11, 7), 423 ARM64_SYS_REG(2, 0, 0, 12, 4), 424 ARM64_SYS_REG(2, 0, 0, 12, 5), 425 ARM64_SYS_REG(2, 0, 0, 12, 6), 426 ARM64_SYS_REG(2, 0, 0, 12, 7), 427 ARM64_SYS_REG(2, 0, 0, 13, 4), 428 ARM64_SYS_REG(2, 0, 0, 13, 5), 429 ARM64_SYS_REG(2, 0, 0, 13, 6), 430 ARM64_SYS_REG(2, 0, 0, 13, 7), 431 ARM64_SYS_REG(2, 0, 0, 14, 4), 432 ARM64_SYS_REG(2, 0, 0, 14, 5), 433 ARM64_SYS_REG(2, 0, 0, 14, 6), 434 ARM64_SYS_REG(2, 0, 0, 14, 7), 435 ARM64_SYS_REG(2, 0, 0, 15, 4), 436 ARM64_SYS_REG(2, 0, 0, 15, 5), 437 ARM64_SYS_REG(2, 0, 0, 15, 6), 438 ARM64_SYS_REG(2, 0, 0, 15, 7), 439 ARM64_SYS_REG(2, 0, 1, 1, 4), /* OSLSR_EL1 */ 440 ARM64_SYS_REG(2, 4, 0, 7, 0), /* DBGVCR32_EL2 */ 441 ARM64_SYS_REG(3, 0, 0, 0, 5), /* MPIDR_EL1 */ 442 ARM64_SYS_REG(3, 0, 0, 1, 0), /* ID_PFR0_EL1 */ 443 ARM64_SYS_REG(3, 0, 0, 1, 1), /* ID_PFR1_EL1 */ 444 ARM64_SYS_REG(3, 0, 0, 1, 2), /* ID_DFR0_EL1 */ 445 ARM64_SYS_REG(3, 0, 0, 1, 3), /* ID_AFR0_EL1 */ 446 ARM64_SYS_REG(3, 0, 0, 1, 4), /* ID_MMFR0_EL1 */ 447 ARM64_SYS_REG(3, 0, 0, 1, 5), /* ID_MMFR1_EL1 */ 448 ARM64_SYS_REG(3, 0, 0, 1, 6), /* ID_MMFR2_EL1 */ 449 ARM64_SYS_REG(3, 0, 0, 1, 7), /* ID_MMFR3_EL1 */ 450 ARM64_SYS_REG(3, 0, 0, 2, 0), /* ID_ISAR0_EL1 */ 451 ARM64_SYS_REG(3, 0, 0, 2, 1), /* ID_ISAR1_EL1 */ 452 ARM64_SYS_REG(3, 0, 0, 2, 2), /* ID_ISAR2_EL1 */ 453 ARM64_SYS_REG(3, 0, 0, 2, 3), /* ID_ISAR3_EL1 */ 454 ARM64_SYS_REG(3, 0, 0, 2, 4), /* ID_ISAR4_EL1 */ 455 ARM64_SYS_REG(3, 0, 0, 2, 5), /* ID_ISAR5_EL1 */ 456 ARM64_SYS_REG(3, 0, 0, 2, 6), /* ID_MMFR4_EL1 */ 457 ARM64_SYS_REG(3, 0, 0, 2, 7), /* ID_ISAR6_EL1 */ 458 ARM64_SYS_REG(3, 0, 0, 3, 0), /* MVFR0_EL1 */ 459 ARM64_SYS_REG(3, 0, 0, 3, 1), /* MVFR1_EL1 */ 460 ARM64_SYS_REG(3, 0, 0, 3, 2), /* MVFR2_EL1 */ 461 ARM64_SYS_REG(3, 0, 0, 3, 3), 462 ARM64_SYS_REG(3, 0, 0, 3, 4), /* ID_PFR2_EL1 */ 463 ARM64_SYS_REG(3, 0, 0, 3, 5), /* ID_DFR1_EL1 */ 464 ARM64_SYS_REG(3, 0, 0, 3, 6), /* ID_MMFR5_EL1 */ 465 ARM64_SYS_REG(3, 0, 0, 3, 7), 466 ARM64_SYS_REG(3, 0, 0, 4, 0), /* ID_AA64PFR0_EL1 */ 467 ARM64_SYS_REG(3, 0, 0, 4, 1), /* ID_AA64PFR1_EL1 */ 468 ARM64_SYS_REG(3, 0, 0, 4, 2), /* ID_AA64PFR2_EL1 */ 469 ARM64_SYS_REG(3, 0, 0, 4, 3), 470 ARM64_SYS_REG(3, 0, 0, 4, 4), /* ID_AA64ZFR0_EL1 */ 471 ARM64_SYS_REG(3, 0, 0, 4, 5), /* ID_AA64SMFR0_EL1 */ 472 ARM64_SYS_REG(3, 0, 0, 4, 6), 473 ARM64_SYS_REG(3, 0, 0, 4, 7), 474 ARM64_SYS_REG(3, 0, 0, 5, 0), /* ID_AA64DFR0_EL1 */ 475 ARM64_SYS_REG(3, 0, 0, 5, 1), /* ID_AA64DFR1_EL1 */ 476 ARM64_SYS_REG(3, 0, 0, 5, 2), 477 ARM64_SYS_REG(3, 0, 0, 5, 3), 478 ARM64_SYS_REG(3, 0, 0, 5, 4), /* ID_AA64AFR0_EL1 */ 479 ARM64_SYS_REG(3, 0, 0, 5, 5), /* ID_AA64AFR1_EL1 */ 480 ARM64_SYS_REG(3, 0, 0, 5, 6), 481 ARM64_SYS_REG(3, 0, 0, 5, 7), 482 ARM64_SYS_REG(3, 0, 0, 6, 0), /* ID_AA64ISAR0_EL1 */ 483 ARM64_SYS_REG(3, 0, 0, 6, 1), /* ID_AA64ISAR1_EL1 */ 484 ARM64_SYS_REG(3, 0, 0, 6, 2), /* ID_AA64ISAR2_EL1 */ 485 ARM64_SYS_REG(3, 0, 0, 6, 3), 486 ARM64_SYS_REG(3, 0, 0, 6, 4), 487 ARM64_SYS_REG(3, 0, 0, 6, 5), 488 ARM64_SYS_REG(3, 0, 0, 6, 6), 489 ARM64_SYS_REG(3, 0, 0, 6, 7), 490 ARM64_SYS_REG(3, 0, 0, 7, 0), /* ID_AA64MMFR0_EL1 */ 491 ARM64_SYS_REG(3, 0, 0, 7, 1), /* ID_AA64MMFR1_EL1 */ 492 ARM64_SYS_REG(3, 0, 0, 7, 2), /* ID_AA64MMFR2_EL1 */ 493 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ 494 ARM64_SYS_REG(3, 0, 0, 7, 4), /* ID_AA64MMFR4_EL1 */ 495 ARM64_SYS_REG(3, 0, 0, 7, 5), 496 ARM64_SYS_REG(3, 0, 0, 7, 6), 497 ARM64_SYS_REG(3, 0, 0, 7, 7), 498 ARM64_SYS_REG(3, 0, 1, 0, 0), /* SCTLR_EL1 */ 499 ARM64_SYS_REG(3, 0, 1, 0, 1), /* ACTLR_EL1 */ 500 ARM64_SYS_REG(3, 0, 1, 0, 2), /* CPACR_EL1 */ 501 KVM_ARM64_SYS_REG(SYS_SCTLR2_EL1), 502 ARM64_SYS_REG(3, 0, 2, 0, 0), /* TTBR0_EL1 */ 503 ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ 504 ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ 505 ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ 506 ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ 507 ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ 508 ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ 509 ARM64_SYS_REG(3, 0, 6, 0, 0), /* FAR_EL1 */ 510 ARM64_SYS_REG(3, 0, 7, 4, 0), /* PAR_EL1 */ 511 ARM64_SYS_REG(3, 0, 10, 2, 0), /* MAIR_EL1 */ 512 ARM64_SYS_REG(3, 0, 10, 2, 2), /* PIRE0_EL1 */ 513 ARM64_SYS_REG(3, 0, 10, 2, 3), /* PIR_EL1 */ 514 ARM64_SYS_REG(3, 0, 10, 2, 4), /* POR_EL1 */ 515 ARM64_SYS_REG(3, 0, 10, 3, 0), /* AMAIR_EL1 */ 516 ARM64_SYS_REG(3, 0, 12, 0, 0), /* VBAR_EL1 */ 517 ARM64_SYS_REG(3, 0, 12, 1, 1), /* DISR_EL1 */ 518 ARM64_SYS_REG(3, 0, 13, 0, 1), /* CONTEXTIDR_EL1 */ 519 ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ 520 ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ 521 ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ 522 ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ 523 ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ 524 ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ 525 ARM64_SYS_REG(3, 3, 14, 0, 1), /* CNTPCT_EL0 */ 526 ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ 527 ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ 528 ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ 529 ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ 530 ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ 531 }; 532 533 static __u64 pmu_regs[] = { 534 ARM64_SYS_REG(3, 0, 9, 14, 1), /* PMINTENSET_EL1 */ 535 ARM64_SYS_REG(3, 0, 9, 14, 2), /* PMINTENCLR_EL1 */ 536 ARM64_SYS_REG(3, 0, 9, 14, 6), /* PMMIR_EL1 */ 537 ARM64_SYS_REG(3, 3, 9, 12, 0), /* PMCR_EL0 */ 538 ARM64_SYS_REG(3, 3, 9, 12, 1), /* PMCNTENSET_EL0 */ 539 ARM64_SYS_REG(3, 3, 9, 12, 2), /* PMCNTENCLR_EL0 */ 540 ARM64_SYS_REG(3, 3, 9, 12, 3), /* PMOVSCLR_EL0 */ 541 ARM64_SYS_REG(3, 3, 9, 12, 4), /* PMSWINC_EL0 */ 542 ARM64_SYS_REG(3, 3, 9, 12, 5), /* PMSELR_EL0 */ 543 ARM64_SYS_REG(3, 3, 9, 13, 0), /* PMCCNTR_EL0 */ 544 ARM64_SYS_REG(3, 3, 9, 14, 0), /* PMUSERENR_EL0 */ 545 ARM64_SYS_REG(3, 3, 9, 14, 3), /* PMOVSSET_EL0 */ 546 ARM64_SYS_REG(3, 3, 14, 8, 0), 547 ARM64_SYS_REG(3, 3, 14, 8, 1), 548 ARM64_SYS_REG(3, 3, 14, 8, 2), 549 ARM64_SYS_REG(3, 3, 14, 8, 3), 550 ARM64_SYS_REG(3, 3, 14, 8, 4), 551 ARM64_SYS_REG(3, 3, 14, 8, 5), 552 ARM64_SYS_REG(3, 3, 14, 8, 6), 553 ARM64_SYS_REG(3, 3, 14, 8, 7), 554 ARM64_SYS_REG(3, 3, 14, 9, 0), 555 ARM64_SYS_REG(3, 3, 14, 9, 1), 556 ARM64_SYS_REG(3, 3, 14, 9, 2), 557 ARM64_SYS_REG(3, 3, 14, 9, 3), 558 ARM64_SYS_REG(3, 3, 14, 9, 4), 559 ARM64_SYS_REG(3, 3, 14, 9, 5), 560 ARM64_SYS_REG(3, 3, 14, 9, 6), 561 ARM64_SYS_REG(3, 3, 14, 9, 7), 562 ARM64_SYS_REG(3, 3, 14, 10, 0), 563 ARM64_SYS_REG(3, 3, 14, 10, 1), 564 ARM64_SYS_REG(3, 3, 14, 10, 2), 565 ARM64_SYS_REG(3, 3, 14, 10, 3), 566 ARM64_SYS_REG(3, 3, 14, 10, 4), 567 ARM64_SYS_REG(3, 3, 14, 10, 5), 568 ARM64_SYS_REG(3, 3, 14, 10, 6), 569 ARM64_SYS_REG(3, 3, 14, 10, 7), 570 ARM64_SYS_REG(3, 3, 14, 11, 0), 571 ARM64_SYS_REG(3, 3, 14, 11, 1), 572 ARM64_SYS_REG(3, 3, 14, 11, 2), 573 ARM64_SYS_REG(3, 3, 14, 11, 3), 574 ARM64_SYS_REG(3, 3, 14, 11, 4), 575 ARM64_SYS_REG(3, 3, 14, 11, 5), 576 ARM64_SYS_REG(3, 3, 14, 11, 6), 577 ARM64_SYS_REG(3, 3, 14, 12, 0), 578 ARM64_SYS_REG(3, 3, 14, 12, 1), 579 ARM64_SYS_REG(3, 3, 14, 12, 2), 580 ARM64_SYS_REG(3, 3, 14, 12, 3), 581 ARM64_SYS_REG(3, 3, 14, 12, 4), 582 ARM64_SYS_REG(3, 3, 14, 12, 5), 583 ARM64_SYS_REG(3, 3, 14, 12, 6), 584 ARM64_SYS_REG(3, 3, 14, 12, 7), 585 ARM64_SYS_REG(3, 3, 14, 13, 0), 586 ARM64_SYS_REG(3, 3, 14, 13, 1), 587 ARM64_SYS_REG(3, 3, 14, 13, 2), 588 ARM64_SYS_REG(3, 3, 14, 13, 3), 589 ARM64_SYS_REG(3, 3, 14, 13, 4), 590 ARM64_SYS_REG(3, 3, 14, 13, 5), 591 ARM64_SYS_REG(3, 3, 14, 13, 6), 592 ARM64_SYS_REG(3, 3, 14, 13, 7), 593 ARM64_SYS_REG(3, 3, 14, 14, 0), 594 ARM64_SYS_REG(3, 3, 14, 14, 1), 595 ARM64_SYS_REG(3, 3, 14, 14, 2), 596 ARM64_SYS_REG(3, 3, 14, 14, 3), 597 ARM64_SYS_REG(3, 3, 14, 14, 4), 598 ARM64_SYS_REG(3, 3, 14, 14, 5), 599 ARM64_SYS_REG(3, 3, 14, 14, 6), 600 ARM64_SYS_REG(3, 3, 14, 14, 7), 601 ARM64_SYS_REG(3, 3, 14, 15, 0), 602 ARM64_SYS_REG(3, 3, 14, 15, 1), 603 ARM64_SYS_REG(3, 3, 14, 15, 2), 604 ARM64_SYS_REG(3, 3, 14, 15, 3), 605 ARM64_SYS_REG(3, 3, 14, 15, 4), 606 ARM64_SYS_REG(3, 3, 14, 15, 5), 607 ARM64_SYS_REG(3, 3, 14, 15, 6), 608 ARM64_SYS_REG(3, 3, 14, 15, 7), /* PMCCFILTR_EL0 */ 609 }; 610 611 static __u64 vregs[] = { 612 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]), 613 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[1]), 614 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[2]), 615 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[3]), 616 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[4]), 617 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[5]), 618 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[6]), 619 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[7]), 620 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[8]), 621 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[9]), 622 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[10]), 623 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[11]), 624 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[12]), 625 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[13]), 626 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[14]), 627 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[15]), 628 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[16]), 629 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[17]), 630 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[18]), 631 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[19]), 632 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[20]), 633 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[21]), 634 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[22]), 635 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[23]), 636 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[24]), 637 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[25]), 638 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[26]), 639 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[27]), 640 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[28]), 641 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[29]), 642 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[30]), 643 KVM_REG_ARM64 | KVM_REG_SIZE_U128 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]), 644 }; 645 646 static __u64 sve_regs[] = { 647 KVM_REG_ARM64_SVE_VLS, 648 KVM_REG_ARM64_SVE_ZREG(0, 0), 649 KVM_REG_ARM64_SVE_ZREG(1, 0), 650 KVM_REG_ARM64_SVE_ZREG(2, 0), 651 KVM_REG_ARM64_SVE_ZREG(3, 0), 652 KVM_REG_ARM64_SVE_ZREG(4, 0), 653 KVM_REG_ARM64_SVE_ZREG(5, 0), 654 KVM_REG_ARM64_SVE_ZREG(6, 0), 655 KVM_REG_ARM64_SVE_ZREG(7, 0), 656 KVM_REG_ARM64_SVE_ZREG(8, 0), 657 KVM_REG_ARM64_SVE_ZREG(9, 0), 658 KVM_REG_ARM64_SVE_ZREG(10, 0), 659 KVM_REG_ARM64_SVE_ZREG(11, 0), 660 KVM_REG_ARM64_SVE_ZREG(12, 0), 661 KVM_REG_ARM64_SVE_ZREG(13, 0), 662 KVM_REG_ARM64_SVE_ZREG(14, 0), 663 KVM_REG_ARM64_SVE_ZREG(15, 0), 664 KVM_REG_ARM64_SVE_ZREG(16, 0), 665 KVM_REG_ARM64_SVE_ZREG(17, 0), 666 KVM_REG_ARM64_SVE_ZREG(18, 0), 667 KVM_REG_ARM64_SVE_ZREG(19, 0), 668 KVM_REG_ARM64_SVE_ZREG(20, 0), 669 KVM_REG_ARM64_SVE_ZREG(21, 0), 670 KVM_REG_ARM64_SVE_ZREG(22, 0), 671 KVM_REG_ARM64_SVE_ZREG(23, 0), 672 KVM_REG_ARM64_SVE_ZREG(24, 0), 673 KVM_REG_ARM64_SVE_ZREG(25, 0), 674 KVM_REG_ARM64_SVE_ZREG(26, 0), 675 KVM_REG_ARM64_SVE_ZREG(27, 0), 676 KVM_REG_ARM64_SVE_ZREG(28, 0), 677 KVM_REG_ARM64_SVE_ZREG(29, 0), 678 KVM_REG_ARM64_SVE_ZREG(30, 0), 679 KVM_REG_ARM64_SVE_ZREG(31, 0), 680 KVM_REG_ARM64_SVE_PREG(0, 0), 681 KVM_REG_ARM64_SVE_PREG(1, 0), 682 KVM_REG_ARM64_SVE_PREG(2, 0), 683 KVM_REG_ARM64_SVE_PREG(3, 0), 684 KVM_REG_ARM64_SVE_PREG(4, 0), 685 KVM_REG_ARM64_SVE_PREG(5, 0), 686 KVM_REG_ARM64_SVE_PREG(6, 0), 687 KVM_REG_ARM64_SVE_PREG(7, 0), 688 KVM_REG_ARM64_SVE_PREG(8, 0), 689 KVM_REG_ARM64_SVE_PREG(9, 0), 690 KVM_REG_ARM64_SVE_PREG(10, 0), 691 KVM_REG_ARM64_SVE_PREG(11, 0), 692 KVM_REG_ARM64_SVE_PREG(12, 0), 693 KVM_REG_ARM64_SVE_PREG(13, 0), 694 KVM_REG_ARM64_SVE_PREG(14, 0), 695 KVM_REG_ARM64_SVE_PREG(15, 0), 696 KVM_REG_ARM64_SVE_FFR(0), 697 ARM64_SYS_REG(3, 0, 1, 2, 0), /* ZCR_EL1 */ 698 }; 699 700 static __u64 sve_rejects_set[] = { 701 KVM_REG_ARM64_SVE_VLS, 702 }; 703 704 static __u64 pauth_addr_regs[] = { 705 ARM64_SYS_REG(3, 0, 2, 1, 0), /* APIAKEYLO_EL1 */ 706 ARM64_SYS_REG(3, 0, 2, 1, 1), /* APIAKEYHI_EL1 */ 707 ARM64_SYS_REG(3, 0, 2, 1, 2), /* APIBKEYLO_EL1 */ 708 ARM64_SYS_REG(3, 0, 2, 1, 3), /* APIBKEYHI_EL1 */ 709 ARM64_SYS_REG(3, 0, 2, 2, 0), /* APDAKEYLO_EL1 */ 710 ARM64_SYS_REG(3, 0, 2, 2, 1), /* APDAKEYHI_EL1 */ 711 ARM64_SYS_REG(3, 0, 2, 2, 2), /* APDBKEYLO_EL1 */ 712 ARM64_SYS_REG(3, 0, 2, 2, 3) /* APDBKEYHI_EL1 */ 713 }; 714 715 static __u64 pauth_generic_regs[] = { 716 ARM64_SYS_REG(3, 0, 2, 3, 0), /* APGAKEYLO_EL1 */ 717 ARM64_SYS_REG(3, 0, 2, 3, 1), /* APGAKEYHI_EL1 */ 718 }; 719 720 static __u64 el2_regs[] = { 721 SYS_REG(VPIDR_EL2), 722 SYS_REG(VMPIDR_EL2), 723 SYS_REG(SCTLR_EL2), 724 SYS_REG(ACTLR_EL2), 725 SYS_REG(SCTLR2_EL2), 726 SYS_REG(HCR_EL2), 727 SYS_REG(MDCR_EL2), 728 SYS_REG(CPTR_EL2), 729 SYS_REG(HSTR_EL2), 730 SYS_REG(HFGRTR_EL2), 731 SYS_REG(HFGWTR_EL2), 732 SYS_REG(HFGITR_EL2), 733 SYS_REG(HACR_EL2), 734 SYS_REG(ZCR_EL2), 735 SYS_REG(HCRX_EL2), 736 SYS_REG(TTBR0_EL2), 737 SYS_REG(TTBR1_EL2), 738 SYS_REG(TCR_EL2), 739 SYS_REG(TCR2_EL2), 740 SYS_REG(VTTBR_EL2), 741 SYS_REG(VTCR_EL2), 742 SYS_REG(VNCR_EL2), 743 SYS_REG(HDFGRTR2_EL2), 744 SYS_REG(HDFGWTR2_EL2), 745 SYS_REG(HFGRTR2_EL2), 746 SYS_REG(HFGWTR2_EL2), 747 SYS_REG(HDFGRTR_EL2), 748 SYS_REG(HDFGWTR_EL2), 749 SYS_REG(HAFGRTR_EL2), 750 SYS_REG(HFGITR2_EL2), 751 SYS_REG(SPSR_EL2), 752 SYS_REG(ELR_EL2), 753 SYS_REG(AFSR0_EL2), 754 SYS_REG(AFSR1_EL2), 755 SYS_REG(ESR_EL2), 756 SYS_REG(FAR_EL2), 757 SYS_REG(HPFAR_EL2), 758 SYS_REG(MAIR_EL2), 759 SYS_REG(PIRE0_EL2), 760 SYS_REG(PIR_EL2), 761 SYS_REG(POR_EL2), 762 SYS_REG(AMAIR_EL2), 763 SYS_REG(VBAR_EL2), 764 SYS_REG(CONTEXTIDR_EL2), 765 SYS_REG(TPIDR_EL2), 766 SYS_REG(CNTVOFF_EL2), 767 SYS_REG(CNTHCTL_EL2), 768 SYS_REG(CNTHP_CTL_EL2), 769 SYS_REG(CNTHP_CVAL_EL2), 770 SYS_REG(CNTHV_CTL_EL2), 771 SYS_REG(CNTHV_CVAL_EL2), 772 SYS_REG(SP_EL2), 773 SYS_REG(VDISR_EL2), 774 SYS_REG(VSESR_EL2), 775 SYS_REG(NVHCR_EL2), 776 }; 777 778 static __u64 el2_e2h0_regs[] = { 779 /* Empty */ 780 }; 781 782 #define BASE_SUBLIST \ 783 { "base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), } 784 #define VREGS_SUBLIST \ 785 { "vregs", .regs = vregs, .regs_n = ARRAY_SIZE(vregs), } 786 #define PMU_SUBLIST \ 787 { "pmu", .capability = KVM_CAP_ARM_PMU_V3, .feature = KVM_ARM_VCPU_PMU_V3, \ 788 .regs = pmu_regs, .regs_n = ARRAY_SIZE(pmu_regs), } 789 #define SVE_SUBLIST \ 790 { "sve", .capability = KVM_CAP_ARM_SVE, .feature = KVM_ARM_VCPU_SVE, .finalize = true, \ 791 .regs = sve_regs, .regs_n = ARRAY_SIZE(sve_regs), \ 792 .rejects_set = sve_rejects_set, .rejects_set_n = ARRAY_SIZE(sve_rejects_set), } 793 #define PAUTH_SUBLIST \ 794 { \ 795 .name = "pauth_address", \ 796 .capability = KVM_CAP_ARM_PTRAUTH_ADDRESS, \ 797 .feature = KVM_ARM_VCPU_PTRAUTH_ADDRESS, \ 798 .regs = pauth_addr_regs, \ 799 .regs_n = ARRAY_SIZE(pauth_addr_regs), \ 800 }, \ 801 { \ 802 .name = "pauth_generic", \ 803 .capability = KVM_CAP_ARM_PTRAUTH_GENERIC, \ 804 .feature = KVM_ARM_VCPU_PTRAUTH_GENERIC, \ 805 .regs = pauth_generic_regs, \ 806 .regs_n = ARRAY_SIZE(pauth_generic_regs), \ 807 } 808 #define EL2_SUBLIST \ 809 { \ 810 .name = "EL2", \ 811 .capability = KVM_CAP_ARM_EL2, \ 812 .feature = KVM_ARM_VCPU_HAS_EL2, \ 813 .regs = el2_regs, \ 814 .regs_n = ARRAY_SIZE(el2_regs), \ 815 } 816 #define EL2_E2H0_SUBLIST \ 817 EL2_SUBLIST, \ 818 { \ 819 .name = "EL2 E2H0", \ 820 .capability = KVM_CAP_ARM_EL2_E2H0, \ 821 .feature = KVM_ARM_VCPU_HAS_EL2_E2H0, \ 822 .regs = el2_e2h0_regs, \ 823 .regs_n = ARRAY_SIZE(el2_e2h0_regs), \ 824 } 825 826 static struct vcpu_reg_list vregs_config = { 827 .sublists = { 828 BASE_SUBLIST, 829 VREGS_SUBLIST, 830 {0}, 831 }, 832 }; 833 static struct vcpu_reg_list vregs_pmu_config = { 834 .sublists = { 835 BASE_SUBLIST, 836 VREGS_SUBLIST, 837 PMU_SUBLIST, 838 {0}, 839 }, 840 }; 841 static struct vcpu_reg_list sve_config = { 842 .sublists = { 843 BASE_SUBLIST, 844 SVE_SUBLIST, 845 {0}, 846 }, 847 }; 848 static struct vcpu_reg_list sve_pmu_config = { 849 .sublists = { 850 BASE_SUBLIST, 851 SVE_SUBLIST, 852 PMU_SUBLIST, 853 {0}, 854 }, 855 }; 856 static struct vcpu_reg_list pauth_config = { 857 .sublists = { 858 BASE_SUBLIST, 859 VREGS_SUBLIST, 860 PAUTH_SUBLIST, 861 {0}, 862 }, 863 }; 864 static struct vcpu_reg_list pauth_pmu_config = { 865 .sublists = { 866 BASE_SUBLIST, 867 VREGS_SUBLIST, 868 PAUTH_SUBLIST, 869 PMU_SUBLIST, 870 {0}, 871 }, 872 }; 873 874 static struct vcpu_reg_list el2_vregs_config = { 875 .sublists = { 876 BASE_SUBLIST, 877 EL2_SUBLIST, 878 VREGS_SUBLIST, 879 {0}, 880 }, 881 }; 882 883 static struct vcpu_reg_list el2_vregs_pmu_config = { 884 .sublists = { 885 BASE_SUBLIST, 886 EL2_SUBLIST, 887 VREGS_SUBLIST, 888 PMU_SUBLIST, 889 {0}, 890 }, 891 }; 892 893 static struct vcpu_reg_list el2_sve_config = { 894 .sublists = { 895 BASE_SUBLIST, 896 EL2_SUBLIST, 897 SVE_SUBLIST, 898 {0}, 899 }, 900 }; 901 902 static struct vcpu_reg_list el2_sve_pmu_config = { 903 .sublists = { 904 BASE_SUBLIST, 905 EL2_SUBLIST, 906 SVE_SUBLIST, 907 PMU_SUBLIST, 908 {0}, 909 }, 910 }; 911 912 static struct vcpu_reg_list el2_pauth_config = { 913 .sublists = { 914 BASE_SUBLIST, 915 EL2_SUBLIST, 916 VREGS_SUBLIST, 917 PAUTH_SUBLIST, 918 {0}, 919 }, 920 }; 921 922 static struct vcpu_reg_list el2_pauth_pmu_config = { 923 .sublists = { 924 BASE_SUBLIST, 925 EL2_SUBLIST, 926 VREGS_SUBLIST, 927 PAUTH_SUBLIST, 928 PMU_SUBLIST, 929 {0}, 930 }, 931 }; 932 933 static struct vcpu_reg_list el2_e2h0_vregs_config = { 934 .sublists = { 935 BASE_SUBLIST, 936 EL2_E2H0_SUBLIST, 937 VREGS_SUBLIST, 938 {0}, 939 }, 940 }; 941 942 static struct vcpu_reg_list el2_e2h0_vregs_pmu_config = { 943 .sublists = { 944 BASE_SUBLIST, 945 EL2_E2H0_SUBLIST, 946 VREGS_SUBLIST, 947 PMU_SUBLIST, 948 {0}, 949 }, 950 }; 951 952 static struct vcpu_reg_list el2_e2h0_sve_config = { 953 .sublists = { 954 BASE_SUBLIST, 955 EL2_E2H0_SUBLIST, 956 SVE_SUBLIST, 957 {0}, 958 }, 959 }; 960 961 static struct vcpu_reg_list el2_e2h0_sve_pmu_config = { 962 .sublists = { 963 BASE_SUBLIST, 964 EL2_E2H0_SUBLIST, 965 SVE_SUBLIST, 966 PMU_SUBLIST, 967 {0}, 968 }, 969 }; 970 971 static struct vcpu_reg_list el2_e2h0_pauth_config = { 972 .sublists = { 973 BASE_SUBLIST, 974 EL2_E2H0_SUBLIST, 975 VREGS_SUBLIST, 976 PAUTH_SUBLIST, 977 {0}, 978 }, 979 }; 980 981 static struct vcpu_reg_list el2_e2h0_pauth_pmu_config = { 982 .sublists = { 983 BASE_SUBLIST, 984 EL2_E2H0_SUBLIST, 985 VREGS_SUBLIST, 986 PAUTH_SUBLIST, 987 PMU_SUBLIST, 988 {0}, 989 }, 990 }; 991 992 struct vcpu_reg_list *vcpu_configs[] = { 993 &vregs_config, 994 &vregs_pmu_config, 995 &sve_config, 996 &sve_pmu_config, 997 &pauth_config, 998 &pauth_pmu_config, 999 1000 &el2_vregs_config, 1001 &el2_vregs_pmu_config, 1002 &el2_sve_config, 1003 &el2_sve_pmu_config, 1004 &el2_pauth_config, 1005 &el2_pauth_pmu_config, 1006 1007 &el2_e2h0_vregs_config, 1008 &el2_e2h0_vregs_pmu_config, 1009 &el2_e2h0_sve_config, 1010 &el2_e2h0_sve_pmu_config, 1011 &el2_e2h0_pauth_config, 1012 &el2_e2h0_pauth_pmu_config, 1013 }; 1014 int vcpu_configs_n = ARRAY_SIZE(vcpu_configs); 1015