1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * (1) Redistributions of source code must retain the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer. 12 * 13 * (2) Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * (3)The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _AQ_HW_H_ 36 #define _AQ_HW_H_ 37 38 #include <sys/types.h> 39 #include <sys/cdefs.h> 40 #include <sys/bus.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <machine/atomic.h> 44 #include <machine/cpufunc.h> 45 #include <machine/bus.h> 46 #include <sys/endian.h> 47 #include <net/ethernet.h> 48 #include "aq_common.h" 49 50 #define AQ_WRITE_REG(hw, reg, value) \ 51 bus_space_write_4((hw)->hw_tag, (hw)->hw_handle, (reg), htole32(value)) 52 53 #define AQ_HW_FLAG_ERR_UNPLUG 0x1UL 54 55 struct aq_hw; 56 extern uint32_t aq_hw_read_reg(struct aq_hw *hw, uint32_t reg); 57 #define AQ_READ_REG(hw, reg) aq_hw_read_reg((hw), (reg)) 58 59 60 #define AQ_WRITE_REG_BIT(hw, reg, msk, shift, value) do { \ 61 if ((msk) ^ ~0) { \ 62 uint32_t reg_old, reg_new = 0U; \ 63 reg_old = AQ_READ_REG(hw, reg); \ 64 reg_new = (reg_old & (~(msk))) | ((value) << (shift)); \ 65 if (reg_old != reg_new) \ 66 AQ_WRITE_REG(hw, reg, reg_new); \ 67 } else { \ 68 AQ_WRITE_REG(hw, reg, value); \ 69 } \ 70 } while(0) 71 72 73 #define AQ_READ_REG_BIT(a, reg, msk, shift) ( \ 74 ((AQ_READ_REG(a, reg) & msk) >> shift)) 75 76 #define AQ_HW_FLUSH(hw) { (void)AQ_READ_REG((hw), 0x10); } 77 78 /* Driver-side per-backend statistics snapshot. */ 79 struct aq_hw_stats { 80 uint32_t uprc; 81 uint32_t mprc; 82 uint32_t bprc; 83 uint32_t erpt; 84 uint32_t uptc; 85 uint32_t mptc; 86 uint32_t bptc; 87 uint32_t erpr; 88 uint32_t mbtc; 89 uint32_t bbtc; 90 uint32_t mbrc; 91 uint32_t bbrc; 92 uint32_t ubrc; 93 uint32_t ubtc; 94 uint32_t ptc; 95 uint32_t prc; 96 uint32_t dpc; 97 uint32_t cprc; 98 uint32_t brc; /* aggregate rx octets */ 99 uint32_t btc; /* aggregate tx octets */ 100 } __packed; 101 102 union ip_addr { 103 struct { 104 uint8_t addr[16]; 105 } v6; 106 struct { 107 uint8_t padding[12]; 108 uint8_t addr[4]; 109 } v4; 110 } __packed; 111 112 /* Raw fw1x MCP mailbox stats block, in hardware order. */ 113 struct aq_fw1x_mbox_stats { 114 uint32_t uprc; 115 uint32_t mprc; 116 uint32_t bprc; 117 uint32_t erpt; 118 uint32_t uptc; 119 uint32_t mptc; 120 uint32_t bptc; 121 uint32_t erpr; 122 uint32_t mbtc; 123 uint32_t bbtc; 124 uint32_t mbrc; 125 uint32_t bbrc; 126 uint32_t ubrc; 127 uint32_t ubtc; 128 uint32_t ptc; 129 uint32_t prc; 130 uint32_t dpc; 131 uint32_t cprc; 132 } __packed; 133 134 /* fw1x MCP mailbox: raw hardware layout, read verbatim. */ 135 struct aq_hw_fw_mbox { 136 uint32_t version; 137 uint32_t transaction_id; 138 int error; 139 struct aq_fw1x_mbox_stats stats; 140 } __packed; 141 142 struct aq_hw_fw_version { 143 union { 144 struct { 145 uint16_t build_number; 146 uint8_t minor_version; 147 uint8_t major_version; 148 }; 149 uint32_t raw; 150 }; 151 }; 152 153 enum aq_hw_irq_type { 154 aq_irq_invalid = 0, 155 aq_irq_legacy = 1, 156 aq_irq_msi = 2, 157 aq_irq_msix = 3, 158 }; 159 160 struct aq_hw_fc_info { 161 bool fc_rx; 162 bool fc_tx; 163 }; 164 165 struct aq_hw_link_info { 166 bool full_duplex; 167 bool eee; 168 uint8_t state; 169 }; 170 171 struct aq_hw { 172 void *aq_dev; 173 device_t dev; 174 bus_space_tag_t hw_tag; 175 bus_space_handle_t hw_handle; 176 uint32_t regs_size; 177 178 uint8_t mac_addr[ETHER_ADDR_LEN]; 179 180 enum aq_hw_irq_type irq_type; 181 182 struct aq_hw_fc_info fc; 183 uint16_t link_rate; 184 uint16_t link_speed; /* last negotiated rate (for ITR moderation) */ 185 186 uint16_t device_id; 187 uint16_t subsystem_vendor_id; 188 uint16_t subsystem_device_id; 189 uint16_t vendor_id; 190 uint8_t revision_id; 191 192 /* Interrupt Moderation value. */ 193 int itr; 194 195 /* Firmware-related stuff. */ 196 struct aq_hw_fw_version fw_version; 197 const struct aq_firmware_ops* fw_ops; 198 bool rbl_enabled; 199 bool fast_start_enabled; 200 bool flash_present; 201 uint32_t chip_features; 202 uint64_t fw_caps; 203 204 /* Atlantic 1: MDIO port address of the PHY, discovered once. */ 205 uint8_t phy_id; 206 bool phy_id_valid; 207 208 bool lro_enabled; 209 210 uint32_t mbox_addr; 211 struct aq_hw_fw_mbox mbox; 212 213 u_long flags; 214 215 uint32_t tx_rings_count; 216 217 /* Atlantic 2: base row added to every action-resolver-table index. */ 218 uint32_t art_filter_base_index; 219 220 /* Atlantic 2: firmware statistics interface version (A0/B0). */ 221 uint32_t aq2_iface; 222 223 /* Atlantic 2: firmware banner already announced for this attach. */ 224 bool fw_announced; 225 226 /* Serialises the F/W MPI control register and mailbox. */ 227 struct mtx fw_mtx; 228 }; 229 230 #define AQ_HW_MAC 0U 231 #define AQ_HW_MAC_MIN 1U 232 #define AQ_HW_MAC_MAX 33U 233 234 #define HW_ATL_B0_MIN_RXD 32U 235 #define HW_ATL_B0_MIN_TXD 32U 236 #define HW_ATL_B0_MAX_RXD 4096U /* in fact up to 8184, but closest to power of 2 */ 237 #define HW_ATL_B0_MAX_TXD 4096U /* in fact up to 8184, but closest to power of 2 */ 238 239 #define HW_ATL_B0_MTU_JUMBO 16352U 240 #define HW_ATL_B0_TSO_SIZE (160*1024) 241 #define HW_ATL_B0_RINGS_MAX 32U 242 #define HW_ATL_B0_TCS_MAX 4U /* 4-TC mode */ 243 #define HW_ATL_B0_RINGS_PER_TC (HW_ATL_B0_RINGS_MAX / HW_ATL_B0_TCS_MAX) 244 #define HW_ATL_B0_LRO_RXD_MAX 16U 245 246 #define AQ_HW_FW_SM_RAM 0x2U 247 248 #define AQ_HW_MPI_STATE_MSK 0x00FFU 249 #define AQ_HW_MPI_STATE_SHIFT 0U 250 251 #define AQ_HW_MPI_CONTROL_ADR 0x0368U 252 #define AQ_HW_MPI_STATE_ADR 0x036CU 253 254 #define HW_ATL_RSS_INDIRECTION_TABLE_MAX 64U 255 #define HW_ATL_RSS_HASHKEY_SIZE 40U 256 #define HW_ATL_RSS_INDIRECTION_QUEUES_MAX 8U 257 #define HW_ATL_RSS_INDIRECTION_ENTRY_BITS 3U 258 259 /* PCI core control register */ 260 #define AQ_HW_PCI_REG_CONTROL_6_ADR 0x1014U 261 /* tx dma total request limit */ 262 #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20U 263 264 #define AQ_HW_TXBUF_MAX 160U 265 #define AQ_HW_RXBUF_MAX 320U 266 267 /* pct% of a kb-KB packet buffer, in 32-byte threshold units */ 268 #define AQ_BUF_THRESHOLD(kb, pct) ((kb) * (1024U / 32U) * (pct) / 100U) 269 270 #define L2_FILTER_ACTION_DISCARD (0x0) 271 #define L2_FILTER_ACTION_HOST (0x1) 272 273 #define AQ_HW_UCP_0X370_REG (0x370) 274 #define AQ_HW_CHIP_MIPS 0x00000001U 275 #define AQ_HW_CHIP_TPO2 0x00000002U 276 #define AQ_HW_CHIP_RPF2 0x00000004U 277 #define AQ_HW_CHIP_MPI_AQ 0x00000010U 278 #define AQ_HW_CHIP_REVISION_A0 0x01000000U 279 #define AQ_HW_CHIP_REVISION_B0 0x02000000U 280 #define AQ_HW_CHIP_REVISION_B1 0x04000000U 281 #define AQ_HW_CHIP_ATLANTIC2 0x08000000U 282 #define IS_CHIP_FEATURE(HW, _F_) (AQ_HW_CHIP_##_F_ & \ 283 (HW)->chip_features) 284 285 #define AQ_HW_FW_VER_EXPECTED 0x01050006U 286 287 #define AQ_RX_RSS_TYPE_NONE 0x0 288 #define AQ_RX_RSS_TYPE_IPV4 0x2 289 #define AQ_RX_RSS_TYPE_IPV6 0x3 290 #define AQ_RX_RSS_TYPE_IPV4_TCP 0x4 291 #define AQ_RX_RSS_TYPE_IPV6_TCP 0x5 292 #define AQ_RX_RSS_TYPE_IPV4_UDP 0x6 293 #define AQ_RX_RSS_TYPE_IPV6_UDP 0x7 294 295 enum hw_atl_rx_action_with_traffic { 296 HW_ATL_RX_DISCARD, 297 HW_ATL_RX_HOST, 298 HW_ATL_RX_MNGMNT, 299 HW_ATL_RX_HOST_AND_MNGMNT, 300 HW_ATL_RX_WOL 301 }; 302 303 struct aq_rx_filter_vlan { 304 uint8_t enable; 305 uint8_t location; 306 uint16_t vlan_id; 307 uint8_t queue; 308 }; 309 310 #define AQ_HW_VLAN_MAX_FILTERS 16U 311 #define AQ_HW_ETYPE_MAX_FILTERS 16U 312 313 struct aq_rx_filter_l2 { 314 uint8_t enable; 315 int8_t queue; 316 uint8_t location; 317 uint8_t user_priority_en; 318 uint8_t user_priority; 319 uint16_t ethertype; 320 }; 321 322 enum hw_atl_rx_ctrl_registers_l2 { 323 HW_ATL_RX_ENABLE_UNICAST_MNGNT_QUEUE_L2 = BIT(19), 324 HW_ATL_RX_ENABLE_UNICAST_FLTR_L2 = BIT(31) 325 }; 326 327 struct aq_rx_filter_l3l4 { 328 uint32_t cmd; 329 uint8_t location; 330 uint32_t ip_dst[4]; 331 uint32_t ip_src[4]; 332 uint16_t p_dst; 333 uint16_t p_src; 334 bool is_ipv6; 335 }; 336 337 enum hw_atl_rx_protocol_value_l3l4 { 338 HW_ATL_RX_TCP, 339 HW_ATL_RX_UDP, 340 HW_ATL_RX_SCTP, 341 HW_ATL_RX_ICMP 342 }; 343 344 enum hw_atl_rx_ctrl_registers_l3l4 { 345 HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22), 346 HW_ATL_RX_ENABLE_QUEUE_L3L4 = BIT(23), 347 HW_ATL_RX_ENABLE_ARP_FLTR_L3 = BIT(24), 348 HW_ATL_RX_ENABLE_CMP_PROT_L4 = BIT(25), 349 HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 = BIT(26), 350 HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4 = BIT(27), 351 HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 = BIT(28), 352 HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3 = BIT(29), 353 HW_ATL_RX_ENABLE_L3_IPv6 = BIT(30), 354 HW_ATL_RX_ENABLE_FLTR_L3L4 = BIT(31) 355 }; 356 357 #define HW_ATL_RX_BOFFSET_PROT_FL3L4 0U 358 #define HW_ATL_RX_BOFFSET_QUEUE_FL3L4 8U 359 #define HW_ATL_RX_BOFFSET_ACTION_FL3F4 16U 360 361 #define HW_ATL_RX_CNT_REG_ADDR_IPV6 4U 362 363 #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \ 364 ((location) - AQ_RX_FIRST_LOC_FL3L4) 365 366 enum aq_hw_fw_mpi_state { 367 MPI_DEINIT = 0, 368 MPI_RESET = 1, 369 MPI_INIT = 2, 370 MPI_POWER = 4, 371 }; 372 373 int aq_hw_get_mac_permanent(struct aq_hw *hw, uint8_t *mac); 374 375 int aq_hw_mac_addr_set(struct aq_hw *hw, uint8_t *mac_addr, uint8_t index); 376 377 /* link speed in mbps. "0" - no link detected */ 378 int aq_hw_get_link_state(struct aq_hw *hw, uint32_t *link_speed, 379 struct aq_hw_fc_info *fc_neg); 380 381 int aq_hw_set_link_speed(struct aq_hw *hw, uint32_t speed); 382 383 int aq_hw_fw_downld_dwords(struct aq_hw *hw, uint32_t a, uint32_t *p, uint32_t cnt); 384 385 int aq_hw_reset(struct aq_hw *hw, bool reboot); 386 387 int aq_hw_mpi_create(struct aq_hw *hw); 388 389 int aq_hw_mpi_read_stats(struct aq_hw *hw, struct aq_hw_stats *stats); 390 391 int aq_hw_init(struct aq_hw *hw, uint8_t *mac_addr, uint8_t adm_irq, bool msix); 392 393 int aq_hw_start(struct aq_hw *hw); 394 395 int aq_hw_interrupt_moderation_set(struct aq_hw *hw); 396 397 int aq_hw_get_fw_version(struct aq_hw *hw, uint32_t *fw_version); 398 399 int aq_hw_deinit(struct aq_hw *hw); 400 401 int aq_hw_ver_match(const struct aq_hw_fw_version* ver_expected, 402 const struct aq_hw_fw_version* ver_actual); 403 404 int aq_hw_set_promisc(struct aq_hw *hw, bool l2_promisc, bool vlan_promisc, 405 bool mc_promisc); 406 407 int aq_hw_set_power(struct aq_hw *hw, unsigned int power_state); 408 409 int aq_hw_err_from_flags(struct aq_hw *hw); 410 411 int hw_atl_b0_hw_vlan_promisc_set(struct aq_hw *hw, bool promisc); 412 413 int hw_atl_b0_hw_vlan_set(struct aq_hw *hw, 414 struct aq_rx_filter_vlan *aq_vlans); 415 416 int aq_hw_rss_hash_set(struct aq_hw *hw, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE]); 417 int aq_hw_rss_hash_get(struct aq_hw *hw, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE]); 418 int aq_hw_rss_set(struct aq_hw *hw, uint8_t rss_table[HW_ATL_RSS_INDIRECTION_TABLE_MAX]); 419 int aq_hw_udp_rss_enable(struct aq_hw *hw, bool enable); 420 u_int aq_rss_hashconfig(void); 421 422 #endif // _AQ_HW_H_ 423