1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2021 Mediatek Inc. All rights reserved.
4 //
5 // Author: YC Hung <yc.hung@mediatek.com>
6 //
7
8 /*
9 * Hardware interface for audio DSP on mt8195
10 */
11
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_platform.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/module.h>
19
20 #include <sound/sof.h>
21 #include <sound/sof/xtensa.h>
22 #include "../../ops.h"
23 #include "../../sof-of-dev.h"
24 #include "../adsp_helper.h"
25 #include "../mtk-adsp-common.h"
26 #include "mt8195.h"
27 #include "mt8195-clk.h"
28
mt8195_get_mailbox_offset(struct snd_sof_dev * sdev)29 static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev)
30 {
31 return MBOX_OFFSET;
32 }
33
mt8195_get_window_offset(struct snd_sof_dev * sdev,u32 id)34 static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id)
35 {
36 return MBOX_OFFSET;
37 }
38
39 static const struct mtk_adsp_ipc_ops dsp_ops = {
40 .handle_reply = mtk_adsp_handle_reply,
41 .handle_request = mtk_adsp_handle_request,
42 };
43
platform_parse_resource(struct platform_device * pdev,void * data)44 static int platform_parse_resource(struct platform_device *pdev, void *data)
45 {
46 struct resource *mmio;
47 struct resource res;
48 struct device *dev = &pdev->dev;
49 struct mtk_adsp_chip_info *adsp = data;
50 int ret;
51
52 ret = of_reserved_mem_device_init(dev);
53 if (ret) {
54 dev_err(dev, "of_reserved_mem_device_init failed\n");
55 return ret;
56 }
57
58 ret = of_reserved_mem_region_to_resource(dev->of_node, 1, &res);
59 if (ret) {
60 dev_err(dev, "of_address_to_resource sysmem failed\n");
61 return ret;
62 }
63
64 adsp->pa_dram = (phys_addr_t)res.start;
65 adsp->dramsize = resource_size(&res);
66 if (adsp->pa_dram & DRAM_REMAP_MASK) {
67 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
68 (u32)adsp->pa_dram);
69 return -EINVAL;
70 }
71
72 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
73 dev_err(dev, "adsp memory(%#x) is not enough for share\n",
74 adsp->dramsize);
75 return -EINVAL;
76 }
77
78 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",
79 &adsp->pa_dram, adsp->dramsize);
80
81 /* Parse CFG base */
82 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
83 if (!mmio) {
84 dev_err(dev, "no ADSP-CFG register resource\n");
85 return -ENXIO;
86 }
87 /* remap for DSP register accessing */
88 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
89 if (IS_ERR(adsp->va_cfgreg))
90 return PTR_ERR(adsp->va_cfgreg);
91
92 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
93 adsp->cfgregsize = resource_size(mmio);
94
95 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",
96 adsp->va_cfgreg, adsp->cfgregsize);
97
98 /* Parse SRAM */
99 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
100 if (!mmio) {
101 dev_err(dev, "no SRAM resource\n");
102 return -ENXIO;
103 }
104
105 adsp->pa_sram = (phys_addr_t)mmio->start;
106 adsp->sramsize = resource_size(mmio);
107
108 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);
109
110 return ret;
111 }
112
adsp_sram_power_on(struct device * dev,bool on)113 static int adsp_sram_power_on(struct device *dev, bool on)
114 {
115 void __iomem *va_dspsysreg;
116 u32 srampool_con;
117
118 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);
119 if (!va_dspsysreg) {
120 dev_err(dev, "failed to ioremap sram pool base %#x\n",
121 ADSP_SRAM_POOL_CON);
122 return -ENOMEM;
123 }
124
125 srampool_con = readl(va_dspsysreg);
126 if (on)
127 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
128 else
129 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
130
131 iounmap(va_dspsysreg);
132 return 0;
133 }
134
135 /* Init the basic DSP DRAM address */
adsp_memory_remap_init(struct device * dev,struct mtk_adsp_chip_info * adsp)136 static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)
137 {
138 void __iomem *vaddr_emi_map;
139 int offset;
140
141 if (!adsp)
142 return -ENXIO;
143
144 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);
145 if (!vaddr_emi_map) {
146 dev_err(dev, "failed to ioremap emi map base %#x\n",
147 DSP_EMI_MAP_ADDR);
148 return -ENOMEM;
149 }
150
151 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
152 adsp->dram_offset = offset;
153 offset >>= DRAM_REMAP_SHIFT;
154 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
155 writel(offset, vaddr_emi_map);
156 if (offset != readl(vaddr_emi_map)) {
157 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));
158 return -EIO;
159 }
160
161 return 0;
162 }
163
mt8195_run(struct snd_sof_dev * sdev)164 static int mt8195_run(struct snd_sof_dev *sdev)
165 {
166 u32 adsp_bootup_addr;
167
168 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
169 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
170 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
171
172 return 0;
173 }
174
mt8195_dsp_probe(struct snd_sof_dev * sdev)175 static int mt8195_dsp_probe(struct snd_sof_dev *sdev)
176 {
177 struct platform_device *pdev = to_platform_device(sdev->dev);
178 struct adsp_priv *priv;
179 int ret;
180
181 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
182 if (!priv)
183 return -ENOMEM;
184
185 sdev->pdata->hw_pdata = priv;
186 priv->dev = sdev->dev;
187 priv->sdev = sdev;
188
189 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
190 if (!priv->adsp)
191 return -ENOMEM;
192
193 ret = platform_parse_resource(pdev, priv->adsp);
194 if (ret)
195 return ret;
196
197 ret = mt8195_adsp_init_clock(sdev);
198 if (ret) {
199 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n");
200 return -EINVAL;
201 }
202
203 ret = adsp_clock_on(sdev);
204 if (ret) {
205 dev_err(sdev->dev, "adsp_clock_on fail!\n");
206 return -EINVAL;
207 }
208
209 ret = adsp_sram_power_on(sdev->dev, true);
210 if (ret) {
211 dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
212 goto exit_clk_disable;
213 }
214
215 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp);
216 if (ret) {
217 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
218 goto err_adsp_sram_power_off;
219 }
220
221 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
222 priv->adsp->pa_sram,
223 priv->adsp->sramsize);
224 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
225 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
226 &priv->adsp->pa_sram, priv->adsp->sramsize);
227 ret = -EINVAL;
228 goto err_adsp_sram_power_off;
229 }
230
231 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
232
233 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
234 priv->adsp->pa_dram,
235 priv->adsp->dramsize);
236 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
237 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
238 &priv->adsp->pa_dram, priv->adsp->dramsize);
239 ret = -EINVAL;
240 goto err_adsp_sram_power_off;
241 }
242 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
243
244 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
245
246 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
247 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
248
249 /* set default mailbox offset for FW ready message */
250 sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev);
251
252 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
253 PLATFORM_DEVID_NONE,
254 pdev, sizeof(*pdev));
255 if (IS_ERR(priv->ipc_dev)) {
256 ret = PTR_ERR(priv->ipc_dev);
257 dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n");
258 goto err_adsp_sram_power_off;
259 }
260
261 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
262 if (!priv->dsp_ipc) {
263 ret = -EPROBE_DEFER;
264 dev_err(sdev->dev, "failed to get drvdata\n");
265 goto exit_pdev_unregister;
266 }
267
268 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
269 priv->dsp_ipc->ops = &dsp_ops;
270
271 return 0;
272
273 exit_pdev_unregister:
274 platform_device_unregister(priv->ipc_dev);
275 err_adsp_sram_power_off:
276 adsp_sram_power_on(&pdev->dev, false);
277 exit_clk_disable:
278 adsp_clock_off(sdev);
279
280 return ret;
281 }
282
mt8195_dsp_shutdown(struct snd_sof_dev * sdev)283 static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev)
284 {
285 return snd_sof_suspend(sdev->dev);
286 }
287
mt8195_dsp_remove(struct snd_sof_dev * sdev)288 static void mt8195_dsp_remove(struct snd_sof_dev *sdev)
289 {
290 struct platform_device *pdev = to_platform_device(sdev->dev);
291 struct adsp_priv *priv = sdev->pdata->hw_pdata;
292
293 platform_device_unregister(priv->ipc_dev);
294 adsp_sram_power_on(&pdev->dev, false);
295 adsp_clock_off(sdev);
296 }
297
mt8195_dsp_suspend(struct snd_sof_dev * sdev,u32 target_state)298 static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
299 {
300 struct platform_device *pdev = to_platform_device(sdev->dev);
301 int ret;
302 u32 reset_sw, dbg_pc;
303
304 /* wait dsp enter idle, timeout is 1 second */
305 ret = snd_sof_dsp_read_poll_timeout(sdev, DSP_REG_BAR,
306 DSP_RESET_SW, reset_sw,
307 ((reset_sw & ADSP_PWAIT) == ADSP_PWAIT),
308 SUSPEND_DSP_IDLE_POLL_INTERVAL_US,
309 SUSPEND_DSP_IDLE_TIMEOUT_US);
310 if (ret < 0) {
311 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
312 dev_warn(sdev->dev, "dsp not idle, powering off anyway : swrest %#x, pc %#x, ret %d\n",
313 reset_sw, dbg_pc, ret);
314 }
315
316 /* stall and reset dsp */
317 sof_hifixdsp_shutdown(sdev);
318
319 /* power down adsp sram */
320 ret = adsp_sram_power_on(&pdev->dev, false);
321 if (ret) {
322 dev_err(sdev->dev, "adsp_sram_power_off fail!\n");
323 return ret;
324 }
325
326 /* turn off adsp clock */
327 return adsp_clock_off(sdev);
328 }
329
mt8195_dsp_resume(struct snd_sof_dev * sdev)330 static int mt8195_dsp_resume(struct snd_sof_dev *sdev)
331 {
332 int ret;
333
334 /* turn on adsp clock */
335 ret = adsp_clock_on(sdev);
336 if (ret) {
337 dev_err(sdev->dev, "adsp_clock_on fail!\n");
338 return ret;
339 }
340
341 /* power on adsp sram */
342 ret = adsp_sram_power_on(sdev->dev, true);
343 if (ret)
344 dev_err(sdev->dev, "adsp_sram_power_on fail!\n");
345
346 return ret;
347 }
348
mt8195_adsp_dump(struct snd_sof_dev * sdev,u32 flags)349 static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
350 {
351 u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst;
352 u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest;
353
354 /* dump debug registers */
355 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
356 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
357 dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0);
358 dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1);
359 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
360 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
361 dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT);
362 faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS);
363 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
364 swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW);
365
366 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x",
367 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest);
368 dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x",
369 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo);
370
371 mtk_adsp_dump(sdev, flags);
372 }
373
374 static struct snd_soc_dai_driver mt8195_dai[] = {
375 {
376 .name = "SOF_DL2",
377 .playback = {
378 .channels_min = 1,
379 .channels_max = 2,
380 },
381 },
382 {
383 .name = "SOF_DL3",
384 .playback = {
385 .channels_min = 1,
386 .channels_max = 2,
387 },
388 },
389 {
390 .name = "SOF_UL4",
391 .capture = {
392 .channels_min = 1,
393 .channels_max = 2,
394 },
395 },
396 {
397 .name = "SOF_UL5",
398 .capture = {
399 .channels_min = 1,
400 .channels_max = 2,
401 },
402 },
403 };
404
405 /* mt8195 ops */
406 static const struct snd_sof_dsp_ops sof_mt8195_ops = {
407 /* probe and remove */
408 .probe = mt8195_dsp_probe,
409 .remove = mt8195_dsp_remove,
410 .shutdown = mt8195_dsp_shutdown,
411
412 /* DSP core boot */
413 .run = mt8195_run,
414
415 /* Block IO */
416 .block_read = sof_block_read,
417 .block_write = sof_block_write,
418
419 /* Mailbox IO */
420 .mailbox_read = sof_mailbox_read,
421 .mailbox_write = sof_mailbox_write,
422
423 /* Register IO */
424 .write = sof_io_write,
425 .read = sof_io_read,
426 .write64 = sof_io_write64,
427 .read64 = sof_io_read64,
428
429 /* ipc */
430 .send_msg = mtk_adsp_send_msg,
431 .get_mailbox_offset = mt8195_get_mailbox_offset,
432 .get_window_offset = mt8195_get_window_offset,
433 .ipc_msg_data = sof_ipc_msg_data,
434 .set_stream_data_offset = sof_set_stream_data_offset,
435
436 /* misc */
437 .get_bar_index = mtk_adsp_get_bar_index,
438
439 /* stream callbacks */
440 .pcm_open = sof_stream_pcm_open,
441 .pcm_hw_params = mtk_adsp_stream_pcm_hw_params,
442 .pcm_pointer = mtk_adsp_stream_pcm_pointer,
443 .pcm_close = sof_stream_pcm_close,
444
445 /* firmware loading */
446 .load_firmware = snd_sof_load_firmware_memcpy,
447
448 /* Firmware ops */
449 .dsp_arch_ops = &sof_xtensa_arch_ops,
450
451 /* Debug information */
452 .dbg_dump = mt8195_adsp_dump,
453 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
454
455 /* DAI drivers */
456 .drv = mt8195_dai,
457 .num_drv = ARRAY_SIZE(mt8195_dai),
458
459 /* PM */
460 .suspend = mt8195_dsp_suspend,
461 .resume = mt8195_dsp_resume,
462
463 /* ALSA HW info flags */
464 .hw_info = SNDRV_PCM_INFO_MMAP |
465 SNDRV_PCM_INFO_MMAP_VALID |
466 SNDRV_PCM_INFO_INTERLEAVED |
467 SNDRV_PCM_INFO_PAUSE |
468 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
469 };
470
471 static struct snd_sof_of_mach sof_mt8195_machs[] = {
472 {
473 .compatible = "google,tomato",
474 .sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg"
475 }, {
476 .compatible = "google,dojo",
477 .sof_tplg_filename = "sof-mt8195-mt6359-max98390-rt5682.tplg"
478 }, {
479 .compatible = "mediatek,mt8195",
480 .sof_tplg_filename = "sof-mt8195.tplg"
481 }, {
482 /* sentinel */
483 }
484 };
485
486 static const struct sof_dev_desc sof_of_mt8195_desc = {
487 .of_machines = sof_mt8195_machs,
488 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
489 .ipc_default = SOF_IPC_TYPE_3,
490 .default_fw_path = {
491 [SOF_IPC_TYPE_3] = "mediatek/sof",
492 },
493 .default_tplg_path = {
494 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
495 },
496 .default_fw_filename = {
497 [SOF_IPC_TYPE_3] = "sof-mt8195.ri",
498 },
499 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg",
500 .ops = &sof_mt8195_ops,
501 .ipc_timeout = 1000,
502 };
503
504 static const struct of_device_id sof_of_mt8195_ids[] = {
505 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc},
506 { }
507 };
508 MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids);
509
510 /* DT driver definition */
511 static struct platform_driver snd_sof_of_mt8195_driver = {
512 .probe = sof_of_probe,
513 .remove = sof_of_remove,
514 .shutdown = sof_of_shutdown,
515 .driver = {
516 .name = "sof-audio-of-mt8195",
517 .pm = pm_ptr(&sof_of_pm),
518 .of_match_table = sof_of_mt8195_ids,
519 },
520 };
521 module_platform_driver(snd_sof_of_mt8195_driver);
522
523 MODULE_LICENSE("Dual BSD/GPL");
524 MODULE_DESCRIPTION("SOF support for MTL 8195 platforms");
525 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
526 MODULE_IMPORT_NS("SND_SOC_SOF_MTK_COMMON");
527