1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15 #if defined(__FreeBSD__)
16 #include <linux/seq_file.h>
17 #include <linux/lockdep.h>
18 #include <linux/interrupt.h>
19 #include <linux/pm.h>
20 #endif
21
22 struct rtw89_dev;
23 struct rtw89_pci_info;
24 struct rtw89_usb_info;
25 struct rtw89_mac_gen_def;
26 struct rtw89_phy_gen_def;
27 struct rtw89_fw_blacklist;
28 struct rtw89_efuse_block_cfg;
29 struct rtw89_h2c_rf_tssi;
30 struct rtw89_fw_txpwr_track_cfg;
31 struct rtw89_phy_rfk_log_fmt;
32 struct rtw89_phy_calc_efuse_gain;
33 struct rtw89_debugfs;
34 struct rtw89_regd_data;
35 struct rtw89_wow_cam_info;
36
37 extern const struct ieee80211_ops rtw89_ops;
38
39 #define MASKBYTE0 0xff
40 #define MASKBYTE1 0xff00
41 #define MASKBYTE2 0xff0000
42 #define MASKBYTE3 0xff000000
43 #define MASKBYTE4 0xff00000000ULL
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define RFREG_MASK 0xfffff
48 #define INV_RF_DATA 0xffffffff
49 #define BYPASS_CR_DATA 0xbabecafe
50 #define RTW89_R32_EA 0xEAEAEAEA
51 #define RTW89_R32_DEAD 0xDEADBEEF
52
53 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
54 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100)
55 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
56 #define RTW89_PS_HANG_MAX_CNT 3
57 #define CFO_TRACK_MAX_USER 64
58 #define MAX_RSSI 110
59 #define RSSI_FACTOR 1
60 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
61 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
62 #define DELTA_SWINGIDX_SIZE 30
63
64 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
65 #define RTW89_RADIOTAP_ROOM_EHT \
66 (sizeof(struct ieee80211_radiotap_tlv) + \
67 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
68 sizeof(struct ieee80211_radiotap_tlv) + \
69 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
70 #define RTW89_RADIOTAP_ROOM \
71 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
72
73 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
74 #define RTW89_HTC_VARIANT_HE 3
75 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
76 #define RTW89_HTC_VARIANT_HE_CID_OM 1
77 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
78 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
79
80 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
81 enum htc_om_channel_width {
82 HTC_OM_CHANNEL_WIDTH_20 = 0,
83 HTC_OM_CHANNEL_WIDTH_40 = 1,
84 HTC_OM_CHANNEL_WIDTH_80 = 2,
85 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
86 };
87 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
88 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
89 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
90 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
91 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
92 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
93
94 #define RTW89_TF_PAD GENMASK(11, 0)
95 #define RTW89_TF_BASIC_USER_INFO_SZ 6
96
97 #define RTW89_GET_TF_USER_INFO_AID12(data) \
98 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
99 #define RTW89_GET_TF_USER_INFO_RUA(data) \
100 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
101 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
102 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
103
104 enum rtw89_subband {
105 RTW89_CH_2G = 0,
106 RTW89_CH_5G_BAND_1 = 1,
107 /* RTW89_CH_5G_BAND_2 = 2, unused */
108 RTW89_CH_5G_BAND_3 = 3,
109 RTW89_CH_5G_BAND_4 = 4,
110
111 RTW89_CH_6G_BAND_IDX0, /* Low */
112 RTW89_CH_6G_BAND_IDX1, /* Low */
113 RTW89_CH_6G_BAND_IDX2, /* Mid */
114 RTW89_CH_6G_BAND_IDX3, /* Mid */
115 RTW89_CH_6G_BAND_IDX4, /* High */
116 RTW89_CH_6G_BAND_IDX5, /* High */
117 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
118 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
119
120 RTW89_SUBBAND_NR,
121 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
122 };
123
124 enum rtw89_tx_comp_band {
125 RTW89_TX_COMP_BAND_2GHZ,
126 RTW89_TX_COMP_BAND_5GHZ_L,
127 RTW89_TX_COMP_BAND_5GHZ_H,
128 RTW89_TX_COMP_BAND_6GHZ_M,
129 RTW89_TX_COMP_BAND_6GHZ_UH,
130
131 RTW89_TX_COMP_BAND_NR,
132 };
133
134 enum rtw89_gain_offset {
135 RTW89_GAIN_OFFSET_2G_CCK,
136 RTW89_GAIN_OFFSET_2G_OFDM,
137 RTW89_GAIN_OFFSET_5G_LOW,
138 RTW89_GAIN_OFFSET_5G_MID,
139 RTW89_GAIN_OFFSET_5G_HIGH,
140 RTW89_GAIN_OFFSET_6G_L0,
141 RTW89_GAIN_OFFSET_6G_L1,
142 RTW89_GAIN_OFFSET_6G_M0,
143 RTW89_GAIN_OFFSET_6G_M1,
144 RTW89_GAIN_OFFSET_6G_H0,
145 RTW89_GAIN_OFFSET_6G_H1,
146 RTW89_GAIN_OFFSET_6G_UH0,
147 RTW89_GAIN_OFFSET_6G_UH1,
148
149 RTW89_GAIN_OFFSET_NR,
150 };
151
152 enum rtw89_hci_type {
153 RTW89_HCI_TYPE_PCIE,
154 RTW89_HCI_TYPE_USB,
155 RTW89_HCI_TYPE_SDIO,
156
157 RTW89_HCI_TYPE_NUM,
158 };
159
160 enum rtw89_hci_dle_type {
161 RTW89_HCI_DLE_TYPE_PCIE,
162 RTW89_HCI_DLE_TYPE_USB2,
163 RTW89_HCI_DLE_TYPE_USB3,
164 RTW89_HCI_DLE_TYPE_SDIO,
165
166 RTW89_HCI_DLE_TYPE_NUM,
167 };
168
169 enum rtw89_core_chip_id {
170 RTL8852A,
171 RTL8852B,
172 RTL8852BT,
173 RTL8852C,
174 RTL8851B,
175 RTL8922A,
176 RTL8922D,
177 };
178
179 enum rtw89_core_chip_cid {
180 RTL8922D_CID7025 = 0x74,
181 RTL8922D_CID7090 = 0x79,
182 };
183
184 enum rtw89_core_chip_aid {
185 RTL8922D_AID1348 = 0x1348,
186 RTL8922D_AID7060 = 0x7060,
187 RTL8922D_AID7102 = 0x7102,
188 };
189
190 enum rtw89_chip_gen {
191 RTW89_CHIP_AX,
192 RTW89_CHIP_BE,
193
194 RTW89_CHIP_GEN_NUM,
195 };
196
197 enum rtw89_cv {
198 CHIP_CAV,
199 CHIP_CBV,
200 CHIP_CCV,
201 CHIP_CDV,
202 CHIP_CEV,
203 CHIP_CFV,
204 CHIP_CV_MAX,
205 CHIP_CV_INVALID = CHIP_CV_MAX,
206 };
207
208 enum rtw89_bacam_ver {
209 RTW89_BACAM_V0,
210 RTW89_BACAM_V1,
211
212 RTW89_BACAM_V0_EXT = 99,
213 };
214
215 enum rtw89_core_tx_type {
216 RTW89_CORE_TX_TYPE_DATA,
217 RTW89_CORE_TX_TYPE_MGMT,
218 RTW89_CORE_TX_TYPE_FWCMD,
219 };
220
221 enum rtw89_core_rx_type {
222 RTW89_CORE_RX_TYPE_WIFI = 0,
223 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
224 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
225 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
226 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
227 RTW89_CORE_RX_TYPE_SS2FW = 5,
228 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
229 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
230 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
231 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
232 RTW89_CORE_RX_TYPE_C2H = 10,
233 RTW89_CORE_RX_TYPE_CSI = 11,
234 RTW89_CORE_RX_TYPE_CQI = 12,
235 RTW89_CORE_RX_TYPE_H2C = 13,
236 RTW89_CORE_RX_TYPE_FWDL = 14,
237 };
238
239 enum rtw89_txq_flags {
240 RTW89_TXQ_F_AMPDU = 0,
241 RTW89_TXQ_F_BLOCK_BA = 1,
242 RTW89_TXQ_F_FORBID_BA = 2,
243 };
244
245 enum rtw89_net_type {
246 RTW89_NET_TYPE_NO_LINK = 0,
247 RTW89_NET_TYPE_AD_HOC = 1,
248 RTW89_NET_TYPE_INFRA = 2,
249 RTW89_NET_TYPE_AP_MODE = 3,
250 };
251
252 enum rtw89_wifi_role {
253 RTW89_WIFI_ROLE_NONE,
254 RTW89_WIFI_ROLE_STATION,
255 RTW89_WIFI_ROLE_AP,
256 RTW89_WIFI_ROLE_AP_VLAN,
257 RTW89_WIFI_ROLE_ADHOC,
258 RTW89_WIFI_ROLE_ADHOC_MASTER,
259 RTW89_WIFI_ROLE_MESH_POINT,
260 RTW89_WIFI_ROLE_MONITOR,
261 RTW89_WIFI_ROLE_P2P_DEVICE,
262 RTW89_WIFI_ROLE_P2P_CLIENT,
263 RTW89_WIFI_ROLE_P2P_GO,
264 RTW89_WIFI_ROLE_NAN,
265 RTW89_WIFI_ROLE_MLME_MAX
266 };
267
268 enum rtw89_upd_mode {
269 RTW89_ROLE_CREATE,
270 RTW89_ROLE_REMOVE,
271 RTW89_ROLE_TYPE_CHANGE,
272 RTW89_ROLE_INFO_CHANGE,
273 RTW89_ROLE_CON_DISCONN,
274 RTW89_ROLE_BAND_SW,
275 RTW89_ROLE_FW_RESTORE,
276 };
277
278 enum rtw89_self_role {
279 RTW89_SELF_ROLE_CLIENT,
280 RTW89_SELF_ROLE_AP,
281 RTW89_SELF_ROLE_AP_CLIENT
282 };
283
284 enum rtw89_msk_sO_el {
285 RTW89_NO_MSK,
286 RTW89_SMA,
287 RTW89_TMA,
288 RTW89_BSSID
289 };
290
291 enum rtw89_sch_tx_sel {
292 RTW89_SCH_TX_SEL_ALL,
293 RTW89_SCH_TX_SEL_HIQ,
294 RTW89_SCH_TX_SEL_MG0,
295 RTW89_SCH_TX_SEL_MACID,
296 };
297
298 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
299 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
300 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
301 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
302 */
303 enum rtw89_add_cam_sec_mode {
304 RTW89_ADDR_CAM_SEC_NONE = 0,
305 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
306 RTW89_ADDR_CAM_SEC_NORMAL = 2,
307 RTW89_ADDR_CAM_SEC_4GROUP = 3,
308 };
309
310 enum rtw89_sec_key_type {
311 RTW89_SEC_KEY_TYPE_NONE = 0,
312 RTW89_SEC_KEY_TYPE_WEP40 = 1,
313 RTW89_SEC_KEY_TYPE_WEP104 = 2,
314 RTW89_SEC_KEY_TYPE_TKIP = 3,
315 RTW89_SEC_KEY_TYPE_WAPI = 4,
316 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
317 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
318 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
319 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
320 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
321 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
322 };
323
324 enum rtw89_port {
325 RTW89_PORT_0 = 0,
326 RTW89_PORT_1 = 1,
327 RTW89_PORT_2 = 2,
328 RTW89_PORT_3 = 3,
329 RTW89_PORT_4 = 4,
330 RTW89_PORT_NUM
331 };
332
333 enum rtw89_band {
334 RTW89_BAND_2G = 0,
335 RTW89_BAND_5G = 1,
336 RTW89_BAND_6G = 2,
337 RTW89_BAND_NUM,
338 };
339
340 enum rtw89_hw_rate {
341 RTW89_HW_RATE_CCK1 = 0x0,
342 RTW89_HW_RATE_CCK2 = 0x1,
343 RTW89_HW_RATE_CCK5_5 = 0x2,
344 RTW89_HW_RATE_CCK11 = 0x3,
345 RTW89_HW_RATE_OFDM6 = 0x4,
346 RTW89_HW_RATE_OFDM9 = 0x5,
347 RTW89_HW_RATE_OFDM12 = 0x6,
348 RTW89_HW_RATE_OFDM18 = 0x7,
349 RTW89_HW_RATE_OFDM24 = 0x8,
350 RTW89_HW_RATE_OFDM36 = 0x9,
351 RTW89_HW_RATE_OFDM48 = 0xA,
352 RTW89_HW_RATE_OFDM54 = 0xB,
353 RTW89_HW_RATE_MCS0 = 0x80,
354 RTW89_HW_RATE_MCS1 = 0x81,
355 RTW89_HW_RATE_MCS2 = 0x82,
356 RTW89_HW_RATE_MCS3 = 0x83,
357 RTW89_HW_RATE_MCS4 = 0x84,
358 RTW89_HW_RATE_MCS5 = 0x85,
359 RTW89_HW_RATE_MCS6 = 0x86,
360 RTW89_HW_RATE_MCS7 = 0x87,
361 RTW89_HW_RATE_MCS8 = 0x88,
362 RTW89_HW_RATE_MCS9 = 0x89,
363 RTW89_HW_RATE_MCS10 = 0x8A,
364 RTW89_HW_RATE_MCS11 = 0x8B,
365 RTW89_HW_RATE_MCS12 = 0x8C,
366 RTW89_HW_RATE_MCS13 = 0x8D,
367 RTW89_HW_RATE_MCS14 = 0x8E,
368 RTW89_HW_RATE_MCS15 = 0x8F,
369 RTW89_HW_RATE_MCS16 = 0x90,
370 RTW89_HW_RATE_MCS17 = 0x91,
371 RTW89_HW_RATE_MCS18 = 0x92,
372 RTW89_HW_RATE_MCS19 = 0x93,
373 RTW89_HW_RATE_MCS20 = 0x94,
374 RTW89_HW_RATE_MCS21 = 0x95,
375 RTW89_HW_RATE_MCS22 = 0x96,
376 RTW89_HW_RATE_MCS23 = 0x97,
377 RTW89_HW_RATE_MCS24 = 0x98,
378 RTW89_HW_RATE_MCS25 = 0x99,
379 RTW89_HW_RATE_MCS26 = 0x9A,
380 RTW89_HW_RATE_MCS27 = 0x9B,
381 RTW89_HW_RATE_MCS28 = 0x9C,
382 RTW89_HW_RATE_MCS29 = 0x9D,
383 RTW89_HW_RATE_MCS30 = 0x9E,
384 RTW89_HW_RATE_MCS31 = 0x9F,
385 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
386 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
387 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
388 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
389 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
390 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
391 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
392 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
393 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
394 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
395 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
396 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
397 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
398 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
399 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
400 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
401 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
402 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
403 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
404 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
405 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
406 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
407 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
408 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
409 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
410 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
411 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
412 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
413 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
414 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
415 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
416 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
417 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
418 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
419 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
420 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
421 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
422 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
423 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
424 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
425 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
426 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
427 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
428 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
429 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
430 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
431 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
432 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
433 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
434 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
435 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
436 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
437 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
438 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
439 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
440 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
441 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
442 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
443 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
444 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
445 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
446 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
447 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
448 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
449 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
450 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
451 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
452 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
453 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
454 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
455 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
456 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
457 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
458 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
459 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
460 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
461 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
462 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
463 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
464 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
465 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
466 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
467 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
468 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
469 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
470 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
471 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
472 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
473
474 RTW89_HW_RATE_V1_MCS0 = 0x100,
475 RTW89_HW_RATE_V1_MCS1 = 0x101,
476 RTW89_HW_RATE_V1_MCS2 = 0x102,
477 RTW89_HW_RATE_V1_MCS3 = 0x103,
478 RTW89_HW_RATE_V1_MCS4 = 0x104,
479 RTW89_HW_RATE_V1_MCS5 = 0x105,
480 RTW89_HW_RATE_V1_MCS6 = 0x106,
481 RTW89_HW_RATE_V1_MCS7 = 0x107,
482 RTW89_HW_RATE_V1_MCS8 = 0x108,
483 RTW89_HW_RATE_V1_MCS9 = 0x109,
484 RTW89_HW_RATE_V1_MCS10 = 0x10A,
485 RTW89_HW_RATE_V1_MCS11 = 0x10B,
486 RTW89_HW_RATE_V1_MCS12 = 0x10C,
487 RTW89_HW_RATE_V1_MCS13 = 0x10D,
488 RTW89_HW_RATE_V1_MCS14 = 0x10E,
489 RTW89_HW_RATE_V1_MCS15 = 0x10F,
490 RTW89_HW_RATE_V1_MCS16 = 0x110,
491 RTW89_HW_RATE_V1_MCS17 = 0x111,
492 RTW89_HW_RATE_V1_MCS18 = 0x112,
493 RTW89_HW_RATE_V1_MCS19 = 0x113,
494 RTW89_HW_RATE_V1_MCS20 = 0x114,
495 RTW89_HW_RATE_V1_MCS21 = 0x115,
496 RTW89_HW_RATE_V1_MCS22 = 0x116,
497 RTW89_HW_RATE_V1_MCS23 = 0x117,
498 RTW89_HW_RATE_V1_MCS24 = 0x118,
499 RTW89_HW_RATE_V1_MCS25 = 0x119,
500 RTW89_HW_RATE_V1_MCS26 = 0x11A,
501 RTW89_HW_RATE_V1_MCS27 = 0x11B,
502 RTW89_HW_RATE_V1_MCS28 = 0x11C,
503 RTW89_HW_RATE_V1_MCS29 = 0x11D,
504 RTW89_HW_RATE_V1_MCS30 = 0x11E,
505 RTW89_HW_RATE_V1_MCS31 = 0x11F,
506 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
507 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
508 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
509 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
510 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
511 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
512 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
513 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
514 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
515 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
516 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
517 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
518 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
519 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
520 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
521 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
522 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
523 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
524 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
525 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
526 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
527 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
528 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
529 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
530 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
531 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
532 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
533 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
534 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
535 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
536 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
537 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
538 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
539 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
540 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
541 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
542 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
543 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
544 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
545 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
546 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
547 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
548 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
549 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
550 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
551 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
552 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
553 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
554 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
555 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
556 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
557 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
558 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
559 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
560 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
561 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
562 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
563 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
564 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
565 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
566 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
567 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
568 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
569 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
570 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
571 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
572 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
573 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
574 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
575 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
576 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
577 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
578 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
579 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
580 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
581 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
582 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
583 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
584 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
585 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
586 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
587 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
588 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
589 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
590 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
591 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
592 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
593 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
594 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
595 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
596 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
597 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
598 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
599 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
600 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
601 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
602 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
603 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
604 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
605 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
606 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
607 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
608 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
609 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
610 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
611 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
612 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
613 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
614 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
615 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
616 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
617 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
618 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
619 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
620 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
621 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
622 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
623 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
624 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
625 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
626 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
627 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
628 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
629 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
630 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
631 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
632 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
633 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
634 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
635 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
636 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
637 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
638 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
639 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
640 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
641 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
642 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
643 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
644 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
645 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
646 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
647 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
648 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
649 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
650 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
651 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
652 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
653 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
654 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
655 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
656 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
657 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
658 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
659 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
660
661 RTW89_HW_RATE_NR,
662 RTW89_HW_RATE_INVAL,
663
664 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
665 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
666 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
667 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
668 };
669
670 /* 2G channels,
671 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
672 */
673 #define RTW89_2G_CH_NUM 14
674
675 /* 5G channels,
676 * 36, 38, 40, 42, 44, 46, 48, 50,
677 * 52, 54, 56, 58, 60, 62, 64,
678 * 100, 102, 104, 106, 108, 110, 112, 114,
679 * 116, 118, 120, 122, 124, 126, 128, 130,
680 * 132, 134, 136, 138, 140, 142, 144,
681 * 149, 151, 153, 155, 157, 159, 161, 163,
682 * 165, 167, 169, 171, 173, 175, 177
683 */
684 #define RTW89_5G_CH_NUM 53
685
686 /* 6G channels,
687 * 1, 3, 5, 7, 9, 11, 13, 15,
688 * 17, 19, 21, 23, 25, 27, 29, 33,
689 * 35, 37, 39, 41, 43, 45, 47, 49,
690 * 51, 53, 55, 57, 59, 61, 65, 67,
691 * 69, 71, 73, 75, 77, 79, 81, 83,
692 * 85, 87, 89, 91, 93, 97, 99, 101,
693 * 103, 105, 107, 109, 111, 113, 115, 117,
694 * 119, 121, 123, 125, 129, 131, 133, 135,
695 * 137, 139, 141, 143, 145, 147, 149, 151,
696 * 153, 155, 157, 161, 163, 165, 167, 169,
697 * 171, 173, 175, 177, 179, 181, 183, 185,
698 * 187, 189, 193, 195, 197, 199, 201, 203,
699 * 205, 207, 209, 211, 213, 215, 217, 219,
700 * 221, 225, 227, 229, 231, 233, 235, 237,
701 * 239, 241, 243, 245, 247, 249, 251, 253,
702 */
703 #define RTW89_6G_CH_NUM 120
704
705 enum rtw89_rate_section {
706 RTW89_RS_CCK,
707 RTW89_RS_OFDM,
708 RTW89_RS_MCS, /* for HT/VHT/HE */
709 RTW89_RS_HEDCM,
710 RTW89_RS_OFFSET,
711 RTW89_RS_NUM,
712 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
713 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
714 };
715
716 enum rtw89_rate_offset_indexes {
717 RTW89_RATE_OFFSET_HE,
718 RTW89_RATE_OFFSET_VHT,
719 RTW89_RATE_OFFSET_HT,
720 RTW89_RATE_OFFSET_OFDM,
721 RTW89_RATE_OFFSET_CCK,
722 RTW89_RATE_OFFSET_DLRU_EHT,
723 RTW89_RATE_OFFSET_DLRU_HE,
724 RTW89_RATE_OFFSET_EHT,
725 __RTW89_RATE_OFFSET_NUM,
726
727 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
728 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
729 };
730
731 enum rtw89_rate_num {
732 RTW89_RATE_CCK_NUM = 4,
733 RTW89_RATE_OFDM_NUM = 8,
734 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
735
736 RTW89_RATE_MCS_NUM_AX = 12,
737 RTW89_RATE_MCS_NUM_BE = 16,
738 __RTW89_RATE_MCS_NUM = 16,
739 };
740
741 enum rtw89_nss {
742 RTW89_NSS_1 = 0,
743 RTW89_NSS_2 = 1,
744 /* HE DCM only support 1ss and 2ss */
745 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
746 RTW89_NSS_3 = 2,
747 RTW89_NSS_4 = 3,
748 RTW89_NSS_NUM,
749 };
750
751 enum rtw89_ntx {
752 RTW89_1TX = 0,
753 RTW89_2TX = 1,
754 RTW89_NTX_NUM,
755 };
756
757 enum rtw89_beamforming_type {
758 RTW89_NONBF = 0,
759 RTW89_BF = 1,
760 RTW89_BF_NUM,
761 };
762
763 enum rtw89_ofdma_type {
764 RTW89_NON_OFDMA = 0,
765 RTW89_OFDMA = 1,
766 RTW89_OFDMA_NUM,
767 };
768
769 /* neither insert new in the middle, nor change any given definition */
770 enum rtw89_regulation_type {
771 RTW89_WW = 0,
772 RTW89_ETSI = 1,
773 RTW89_FCC = 2,
774 RTW89_MKK = 3,
775 RTW89_NA = 4,
776 RTW89_IC = 5,
777 RTW89_KCC = 6,
778 RTW89_ACMA = 7,
779 RTW89_NCC = 8,
780 RTW89_MEXICO = 9,
781 RTW89_CHILE = 10,
782 RTW89_UKRAINE = 11,
783 RTW89_CN = 12,
784 RTW89_QATAR = 13,
785 RTW89_UK = 14,
786 RTW89_THAILAND = 15,
787 RTW89_REGD_NUM,
788 };
789
790 enum rtw89_reg_6ghz_power {
791 RTW89_REG_6GHZ_POWER_VLP = 0,
792 RTW89_REG_6GHZ_POWER_LPI = 1,
793 RTW89_REG_6GHZ_POWER_STD = 2,
794
795 NUM_OF_RTW89_REG_6GHZ_POWER,
796 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
797 };
798
799 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
800
801 /* calculate based on ieee80211 Transmit Power Envelope */
802 struct rtw89_reg_6ghz_tpe {
803 bool valid;
804 s8 constraint; /* unit: dBm */
805 };
806
807 enum rtw89_fw_pkt_ofld_type {
808 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
809 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
810 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
811 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
812 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
813 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
814 RTW89_PKT_OFLD_TYPE_NDP = 6,
815 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
816 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
817 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
818 RTW89_PKT_OFLD_TYPE_NUM,
819 };
820
821 struct rtw89_txpwr_byrate {
822 s8 cck[RTW89_RATE_CCK_NUM];
823 s8 ofdm[RTW89_RATE_OFDM_NUM];
824 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
825 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
826 s8 offset[__RTW89_RATE_OFFSET_NUM];
827 s8 trap;
828 };
829
830 struct rtw89_rate_desc {
831 enum rtw89_nss nss;
832 enum rtw89_rate_section rs;
833 enum rtw89_ofdma_type ofdma;
834 u8 idx;
835 };
836
837 #define PHY_STS_HDR_LEN 8
838 #define RF_PATH_MAX 4
839 #define RTW89_MAX_PPDU_CNT 8
840 struct rtw89_rx_phy_ppdu {
841 void *buf;
842 u32 len;
843 u8 rssi_avg;
844 u8 rssi[RF_PATH_MAX];
845 u8 mac_id;
846 u8 chan_idx;
847 u8 phy_idx;
848 u8 ie;
849 u16 rate;
850 u8 rpl_avg;
851 u8 rpl_path[RF_PATH_MAX];
852 u8 rpl_fd[RF_PATH_MAX];
853 u8 bw_idx;
854 u8 rx_path_en;
855 struct {
856 bool has;
857 u8 avg_snr;
858 u8 evm_max;
859 u8 evm_min;
860 } ofdm;
861 bool has_data;
862 bool has_bcn;
863 bool ldpc;
864 bool stbc;
865 bool to_self;
866 bool valid;
867 bool hdr_2_en;
868 };
869
870 enum rtw89_mac_idx {
871 RTW89_MAC_0 = 0,
872 RTW89_MAC_1 = 1,
873 RTW89_MAC_NUM,
874 };
875
876 enum rtw89_phy_idx {
877 RTW89_PHY_0 = 0,
878 RTW89_PHY_1 = 1,
879 RTW89_PHY_NUM,
880 };
881
882 #define __RTW89_MLD_MAX_LINK_NUM 2
883 #define RTW89_MLD_NON_STA_LINK_NUM 1
884
885 enum rtw89_chanctx_idx {
886 RTW89_CHANCTX_0 = 0,
887 RTW89_CHANCTX_1 = 1,
888
889 NUM_OF_RTW89_CHANCTX,
890 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
891 };
892
893 enum rtw89_rf_path {
894 RF_PATH_A = 0,
895 RF_PATH_B = 1,
896 RF_PATH_C = 2,
897 RF_PATH_D = 3,
898 RF_PATH_AB,
899 RF_PATH_AC,
900 RF_PATH_AD,
901 RF_PATH_BC,
902 RF_PATH_BD,
903 RF_PATH_CD,
904 RF_PATH_ABC,
905 RF_PATH_ABD,
906 RF_PATH_ACD,
907 RF_PATH_BCD,
908 RF_PATH_ABCD,
909 };
910
911 enum rtw89_rf_path_bit {
912 RF_A = BIT(0),
913 RF_B = BIT(1),
914 RF_C = BIT(2),
915 RF_D = BIT(3),
916
917 RF_AB = (RF_A | RF_B),
918 RF_AC = (RF_A | RF_C),
919 RF_AD = (RF_A | RF_D),
920 RF_BC = (RF_B | RF_C),
921 RF_BD = (RF_B | RF_D),
922 RF_CD = (RF_C | RF_D),
923
924 RF_ABC = (RF_A | RF_B | RF_C),
925 RF_ABD = (RF_A | RF_B | RF_D),
926 RF_ACD = (RF_A | RF_C | RF_D),
927 RF_BCD = (RF_B | RF_C | RF_D),
928
929 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
930 };
931
932 enum rtw89_bandwidth {
933 RTW89_CHANNEL_WIDTH_20 = 0,
934 RTW89_CHANNEL_WIDTH_40 = 1,
935 RTW89_CHANNEL_WIDTH_80 = 2,
936 RTW89_CHANNEL_WIDTH_160 = 3,
937 RTW89_CHANNEL_WIDTH_320 = 4,
938
939 /* keep index order above */
940 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
941
942 RTW89_CHANNEL_WIDTH_80_80 = 5,
943 RTW89_CHANNEL_WIDTH_5 = 6,
944 RTW89_CHANNEL_WIDTH_10 = 7,
945 };
946
947 enum rtw89_ps_mode {
948 RTW89_PS_MODE_NONE = 0,
949 RTW89_PS_MODE_RFOFF = 1,
950 RTW89_PS_MODE_CLK_GATED = 2,
951 RTW89_PS_MODE_PWR_GATED = 3,
952 };
953
954 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
955 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
956 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
957 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
958 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
959
960 enum rtw89_pe_duration {
961 RTW89_PE_DURATION_0 = 0,
962 RTW89_PE_DURATION_8 = 1,
963 RTW89_PE_DURATION_16 = 2,
964 RTW89_PE_DURATION_16_20 = 3,
965 };
966
967 enum rtw89_ru_bandwidth {
968 RTW89_RU26 = 0,
969 RTW89_RU52 = 1,
970 RTW89_RU106 = 2,
971 RTW89_RU52_26 = 3,
972 RTW89_RU106_26 = 4,
973 RTW89_RU_NUM,
974 };
975
976 enum rtw89_sc_offset {
977 RTW89_SC_DONT_CARE = 0,
978 RTW89_SC_20_UPPER = 1,
979 RTW89_SC_20_LOWER = 2,
980 RTW89_SC_20_UPMOST = 3,
981 RTW89_SC_20_LOWEST = 4,
982 RTW89_SC_20_UP2X = 5,
983 RTW89_SC_20_LOW2X = 6,
984 RTW89_SC_20_UP3X = 7,
985 RTW89_SC_20_LOW3X = 8,
986 RTW89_SC_40_UPPER = 9,
987 RTW89_SC_40_LOWER = 10,
988 };
989
990 /* only mgd features can be added to the enum */
991 enum rtw89_wow_flags {
992 RTW89_WOW_FLAG_EN_MAGIC_PKT,
993 RTW89_WOW_FLAG_EN_REKEY_PKT,
994 RTW89_WOW_FLAG_EN_DISCONNECT,
995 RTW89_WOW_FLAG_EN_PATTERN,
996 RTW89_WOW_FLAG_NUM,
997 };
998
999 struct rtw89_chan {
1000 u8 channel;
1001 u8 primary_channel;
1002 enum rtw89_band band_type;
1003 enum rtw89_bandwidth band_width;
1004
1005 /* The follow-up are derived from the above. We must ensure that it
1006 * is assigned correctly in rtw89_chan_create() if new one is added.
1007 */
1008 u32 freq;
1009 enum rtw89_subband subband_type;
1010 enum rtw89_tx_comp_band tx_comp_band;
1011 enum rtw89_sc_offset pri_ch_idx;
1012 u8 pri_sb_idx;
1013 };
1014
1015 struct rtw89_chan_rcd {
1016 u8 prev_primary_channel;
1017 enum rtw89_band prev_band_type;
1018 bool band_changed;
1019 };
1020
1021 struct rtw89_channel_help_params {
1022 u32 tx_en;
1023 };
1024
1025 struct rtw89_port_reg {
1026 u32 port_cfg;
1027 u32 tbtt_prohib;
1028 u32 bcn_area;
1029 u32 bcn_early;
1030 u32 tbtt_early;
1031 u32 tbtt_agg;
1032 u32 bcn_space;
1033 u32 bcn_forcetx;
1034 u32 bcn_err_cnt;
1035 u32 bcn_err_flag;
1036 u32 dtim_ctrl;
1037 u32 tbtt_shift;
1038 u32 bcn_cnt_tmr;
1039 u32 tsftr_l;
1040 u32 tsftr_h;
1041 u32 md_tsft;
1042 u32 bss_color;
1043 u32 mbssid;
1044 u32 mbssid_drop;
1045 u32 tsf_sync;
1046 u32 ptcl_dbg;
1047 u32 ptcl_dbg_info;
1048 u32 bcn_drop_all;
1049 u32 bcn_psr_rpt;
1050 u32 hiq_win[RTW89_PORT_NUM];
1051 };
1052
1053 struct rtw89_txwd_body {
1054 __le32 dword0;
1055 __le32 dword1;
1056 __le32 dword2;
1057 __le32 dword3;
1058 __le32 dword4;
1059 __le32 dword5;
1060 } __packed;
1061
1062 struct rtw89_txwd_body_v1 {
1063 __le32 dword0;
1064 __le32 dword1;
1065 __le32 dword2;
1066 __le32 dword3;
1067 __le32 dword4;
1068 __le32 dword5;
1069 __le32 dword6;
1070 __le32 dword7;
1071 } __packed;
1072
1073 struct rtw89_txwd_body_v2 {
1074 __le32 dword0;
1075 __le32 dword1;
1076 __le32 dword2;
1077 __le32 dword3;
1078 __le32 dword4;
1079 __le32 dword5;
1080 __le32 dword6;
1081 __le32 dword7;
1082 } __packed;
1083
1084 struct rtw89_txwd_info {
1085 __le32 dword0;
1086 __le32 dword1;
1087 __le32 dword2;
1088 __le32 dword3;
1089 __le32 dword4;
1090 __le32 dword5;
1091 } __packed;
1092
1093 struct rtw89_txwd_info_v2 {
1094 __le32 dword0;
1095 __le32 dword1;
1096 __le32 dword2;
1097 __le32 dword3;
1098 __le32 dword4;
1099 __le32 dword5;
1100 __le32 dword6;
1101 __le32 dword7;
1102 } __packed;
1103
1104 struct rtw89_rx_desc_info {
1105 u16 pkt_size;
1106 u8 pkt_type;
1107 u8 drv_info_size;
1108 u8 phy_rpt_size;
1109 u8 hdr_cnv_size;
1110 u8 shift;
1111 u8 wl_hd_iv_len;
1112 bool long_rxdesc;
1113 bool bb_sel;
1114 bool mac_info_valid;
1115 u16 data_rate;
1116 u8 gi_ltf;
1117 u8 bw;
1118 u32 free_run_cnt;
1119 u8 user_id;
1120 bool sr_en;
1121 u8 ppdu_cnt;
1122 u8 ppdu_type;
1123 bool icv_err;
1124 bool crc32_err;
1125 bool hw_dec;
1126 bool sw_dec;
1127 bool addr1_match;
1128 u8 frag;
1129 u16 seq;
1130 u8 frame_type;
1131 u8 rx_pl_id;
1132 bool addr_cam_valid;
1133 u8 addr_cam_id;
1134 u8 sec_cam_id;
1135 u8 mac_id;
1136 u16 offset;
1137 u16 rxd_len;
1138 bool ready;
1139 u16 rssi;
1140 };
1141
1142 struct rtw89_rxdesc_short {
1143 __le32 dword0;
1144 __le32 dword1;
1145 __le32 dword2;
1146 __le32 dword3;
1147 } __packed;
1148
1149 struct rtw89_rxdesc_short_v2 {
1150 __le32 dword0;
1151 __le32 dword1;
1152 __le32 dword2;
1153 __le32 dword3;
1154 __le32 dword4;
1155 __le32 dword5;
1156 } __packed;
1157
1158 struct rtw89_rxdesc_short_v3 {
1159 __le32 dword0;
1160 __le32 dword1;
1161 __le32 dword2;
1162 __le32 dword3;
1163 __le32 dword4;
1164 __le32 dword5;
1165 } __packed;
1166
1167 struct rtw89_rxdesc_long {
1168 __le32 dword0;
1169 __le32 dword1;
1170 __le32 dword2;
1171 __le32 dword3;
1172 __le32 dword4;
1173 __le32 dword5;
1174 __le32 dword6;
1175 __le32 dword7;
1176 } __packed;
1177
1178 struct rtw89_rxdesc_long_v2 {
1179 __le32 dword0;
1180 __le32 dword1;
1181 __le32 dword2;
1182 __le32 dword3;
1183 __le32 dword4;
1184 __le32 dword5;
1185 __le32 dword6;
1186 __le32 dword7;
1187 __le32 dword8;
1188 __le32 dword9;
1189 } __packed;
1190
1191 struct rtw89_rxdesc_long_v3 {
1192 __le32 dword0;
1193 __le32 dword1;
1194 __le32 dword2;
1195 __le32 dword3;
1196 __le32 dword4;
1197 __le32 dword5;
1198 __le32 dword6;
1199 __le32 dword7;
1200 __le32 dword8;
1201 __le32 dword9;
1202 } __packed;
1203
1204 struct rtw89_rxdesc_phy_rpt_v2 {
1205 __le32 dword0;
1206 __le32 dword1;
1207 } __packed;
1208
1209 struct rtw89_tx_desc_info {
1210 u16 pkt_size;
1211 u8 wp_offset;
1212 u8 mac_id;
1213 u8 qsel;
1214 u8 ch_dma;
1215 u8 hdr_llc_len;
1216 bool is_bmc;
1217 bool en_wd_info;
1218 bool wd_page;
1219 bool use_rate;
1220 bool dis_data_fb;
1221 bool tid_indicate;
1222 bool agg_en;
1223 bool bk;
1224 u8 ampdu_density;
1225 u8 ampdu_num;
1226 bool sec_en;
1227 bool report;
1228 bool tx_cnt_lmt_en;
1229 u8 sn: 4;
1230 u8 tx_cnt_lmt: 6;
1231 u8 addr_info_nr;
1232 u8 sec_keyid;
1233 u8 sec_type;
1234 u8 sec_cam_idx;
1235 u8 sec_seq[6];
1236 u16 data_rate;
1237 u16 data_retry_lowest_rate;
1238 u8 data_bw;
1239 u8 gi_ltf;
1240 bool fw_dl;
1241 u16 seq;
1242 bool a_ctrl_bsr;
1243 u8 hw_ssn_sel;
1244 #define RTW89_MGMT_HW_SSN_SEL 1
1245 u8 hw_seq_mode;
1246 #define RTW89_MGMT_HW_SEQ_MODE 1
1247 bool hiq;
1248 u8 port;
1249 bool er_cap;
1250 bool stbc;
1251 bool ldpc;
1252 bool upd_wlan_hdr;
1253 bool mlo;
1254 bool sw_mld;
1255 };
1256
1257 struct rtw89_core_tx_request {
1258 enum rtw89_core_tx_type tx_type;
1259
1260 struct sk_buff *skb;
1261 struct ieee80211_vif *vif;
1262 struct ieee80211_sta *sta;
1263 struct rtw89_vif_link *rtwvif_link;
1264 struct rtw89_sta_link *rtwsta_link;
1265 struct rtw89_tx_desc_info desc_info;
1266
1267 bool with_wait;
1268 };
1269
1270 struct rtw89_txq {
1271 struct list_head list;
1272 unsigned long flags;
1273 int wait_cnt;
1274 };
1275
1276 struct rtw89_mac_ax_gnt {
1277 u8 gnt_bt_sw_en;
1278 u8 gnt_bt;
1279 u8 gnt_wl_sw_en;
1280 u8 gnt_wl;
1281 } __packed;
1282
1283 struct rtw89_mac_ax_wl_act {
1284 u8 wlan_act_en;
1285 u8 wlan_act;
1286 } __packed;
1287
1288 #define RTW89_MAC_AX_COEX_GNT_NR 2
1289 struct rtw89_mac_ax_coex_gnt {
1290 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1291 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1292 };
1293
1294 enum rtw89_btc_ncnt {
1295 BTC_NCNT_POWER_ON = 0x0,
1296 BTC_NCNT_POWER_OFF,
1297 BTC_NCNT_INIT_COEX,
1298 BTC_NCNT_SCAN_START,
1299 BTC_NCNT_SCAN_FINISH,
1300 BTC_NCNT_SPECIAL_PACKET,
1301 BTC_NCNT_SWITCH_BAND,
1302 BTC_NCNT_RFK_TIMEOUT,
1303 BTC_NCNT_SHOW_COEX_INFO,
1304 BTC_NCNT_ROLE_INFO,
1305 BTC_NCNT_CONTROL,
1306 BTC_NCNT_RADIO_STATE,
1307 BTC_NCNT_CUSTOMERIZE,
1308 BTC_NCNT_WL_RFK,
1309 BTC_NCNT_WL_STA,
1310 BTC_NCNT_WL_STA_LAST,
1311 BTC_NCNT_FWINFO,
1312 BTC_NCNT_TIMER,
1313 BTC_NCNT_SWITCH_CHBW,
1314 BTC_NCNT_RESUME_DL_FW,
1315 BTC_NCNT_COUNTRYCODE,
1316 BTC_NCNT_NUM,
1317 };
1318
1319 enum rtw89_btc_btinfo {
1320 BTC_BTINFO_L0 = 0,
1321 BTC_BTINFO_L1,
1322 BTC_BTINFO_L2,
1323 BTC_BTINFO_L3,
1324 BTC_BTINFO_H0,
1325 BTC_BTINFO_H1,
1326 BTC_BTINFO_H2,
1327 BTC_BTINFO_H3,
1328 BTC_BTINFO_MAX
1329 };
1330
1331 enum rtw89_btc_dcnt {
1332 BTC_DCNT_RUN = 0x0,
1333 BTC_DCNT_CX_RUNINFO,
1334 BTC_DCNT_RPT,
1335 BTC_DCNT_RPT_HANG,
1336 BTC_DCNT_CYCLE,
1337 BTC_DCNT_CYCLE_HANG,
1338 BTC_DCNT_W1,
1339 BTC_DCNT_W1_HANG,
1340 BTC_DCNT_B1,
1341 BTC_DCNT_B1_HANG,
1342 BTC_DCNT_TDMA_NONSYNC,
1343 BTC_DCNT_SLOT_NONSYNC,
1344 BTC_DCNT_BTCNT_HANG,
1345 BTC_DCNT_BTTX_HANG,
1346 BTC_DCNT_WL_SLOT_DRIFT,
1347 BTC_DCNT_WL_STA_LAST,
1348 BTC_DCNT_BT_SLOT_DRIFT,
1349 BTC_DCNT_BT_SLOT_FLOOD,
1350 BTC_DCNT_FDDT_TRIG,
1351 BTC_DCNT_E2G,
1352 BTC_DCNT_E2G_HANG,
1353 BTC_DCNT_WL_FW_VER_MATCH,
1354 BTC_DCNT_NULL_TX_FAIL,
1355 BTC_DCNT_WL_STA_NTFY,
1356 BTC_DCNT_NUM,
1357 };
1358
1359 enum rtw89_btc_wl_state_cnt {
1360 BTC_WCNT_SCANAP = 0x0,
1361 BTC_WCNT_DHCP,
1362 BTC_WCNT_EAPOL,
1363 BTC_WCNT_ARP,
1364 BTC_WCNT_SCBDUPDATE,
1365 BTC_WCNT_RFK_REQ,
1366 BTC_WCNT_RFK_GO,
1367 BTC_WCNT_RFK_REJECT,
1368 BTC_WCNT_RFK_TIMEOUT,
1369 BTC_WCNT_CH_UPDATE,
1370 BTC_WCNT_DBCC_ALL_2G,
1371 BTC_WCNT_DBCC_CHG,
1372 BTC_WCNT_RX_OK_LAST,
1373 BTC_WCNT_RX_OK_LAST2S,
1374 BTC_WCNT_RX_ERR_LAST,
1375 BTC_WCNT_RX_ERR_LAST2S,
1376 BTC_WCNT_RX_LAST,
1377 BTC_WCNT_NUM
1378 };
1379
1380 enum rtw89_btc_bt_state_cnt {
1381 BTC_BCNT_RETRY = 0x0,
1382 BTC_BCNT_REINIT,
1383 BTC_BCNT_REENABLE,
1384 BTC_BCNT_SCBDREAD,
1385 BTC_BCNT_RELINK,
1386 BTC_BCNT_IGNOWL,
1387 BTC_BCNT_INQPAG,
1388 BTC_BCNT_INQ,
1389 BTC_BCNT_PAGE,
1390 BTC_BCNT_ROLESW,
1391 BTC_BCNT_AFH,
1392 BTC_BCNT_INFOUPDATE,
1393 BTC_BCNT_INFOSAME,
1394 BTC_BCNT_SCBDUPDATE,
1395 BTC_BCNT_HIPRI_TX,
1396 BTC_BCNT_HIPRI_RX,
1397 BTC_BCNT_LOPRI_TX,
1398 BTC_BCNT_LOPRI_RX,
1399 BTC_BCNT_POLUT,
1400 BTC_BCNT_POLUT_NOW,
1401 BTC_BCNT_POLUT_DIFF,
1402 BTC_BCNT_RATECHG,
1403 BTC_BCNT_BTTXPWR_UPDATE,
1404 BTC_BCNT_NUM,
1405 };
1406
1407 enum rtw89_btc_bt_profile {
1408 BTC_BT_NOPROFILE = 0,
1409 BTC_BT_HFP = BIT(0),
1410 BTC_BT_HID = BIT(1),
1411 BTC_BT_A2DP = BIT(2),
1412 BTC_BT_PAN = BIT(3),
1413 BTC_PROFILE_MAX = 4,
1414 };
1415
1416 struct rtw89_btc_ant_info {
1417 u8 type; /* shared, dedicated */
1418 u8 num;
1419 u8 isolation;
1420
1421 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1422 u8 diversity: 1;
1423 u8 btg_pos: 2;
1424 u8 stream_cnt: 4;
1425 };
1426
1427 struct rtw89_btc_ant_info_v7 {
1428 u8 type; /* shared, dedicated(non-shared) */
1429 u8 num; /* antenna count */
1430 u8 isolation;
1431 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1432
1433 u8 diversity; /* only for wifi use 1-antenna */
1434 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1435 u8 stream_cnt; /* spatial_stream count */
1436 u8 rsvd;
1437 } __packed;
1438
1439 enum rtw89_tfc_dir {
1440 RTW89_TFC_UL,
1441 RTW89_TFC_DL,
1442 };
1443
1444 struct rtw89_btc_wl_smap {
1445 u32 busy: 1;
1446 u32 scan: 1;
1447 u32 connecting: 1;
1448 u32 roaming: 1;
1449 u32 dbccing: 1;
1450 u32 _4way: 1;
1451 u32 rf_off: 1;
1452 u32 lps: 2;
1453 u32 ips: 1;
1454 u32 init_ok: 1;
1455 u32 traffic_dir : 2;
1456 u32 rf_off_pre: 1;
1457 u32 lps_pre: 2;
1458 u32 lps_exiting: 1;
1459 u32 emlsr: 1;
1460 };
1461
1462 enum rtw89_tfc_interval {
1463 RTW89_TFC_INTERVAL_100MS,
1464 RTW89_TFC_INTERVAL_2SEC,
1465 };
1466
1467 enum rtw89_tfc_lv {
1468 RTW89_TFC_IDLE,
1469 RTW89_TFC_ULTRA_LOW,
1470 RTW89_TFC_LOW,
1471 RTW89_TFC_MID,
1472 RTW89_TFC_HIGH,
1473 };
1474
1475 DECLARE_EWMA(tp, 10, 2);
1476
1477 struct rtw89_traffic_stats {
1478 /* units in bytes */
1479 u64 tx_unicast;
1480 u64 rx_unicast;
1481 u32 tx_avg_len;
1482 u32 rx_avg_len;
1483
1484 /* count for packets */
1485 u64 tx_cnt;
1486 u64 rx_cnt;
1487
1488 /* units in Mbps */
1489 u32 tx_throughput;
1490 u32 rx_throughput;
1491 u32 tx_throughput_raw;
1492 u32 rx_throughput_raw;
1493
1494 u32 rx_tf_acc;
1495 u32 rx_tf_periodic;
1496
1497 enum rtw89_tfc_lv tx_tfc_lv;
1498 enum rtw89_tfc_lv rx_tfc_lv;
1499 struct ewma_tp tx_ewma_tp;
1500 struct ewma_tp rx_ewma_tp;
1501
1502 u16 tx_rate;
1503 u16 rx_rate;
1504 };
1505
1506 struct rtw89_btc_chdef {
1507 u8 center_ch;
1508 u8 band;
1509 u8 chan;
1510 enum rtw89_sc_offset offset;
1511 enum rtw89_bandwidth bw;
1512 };
1513
1514 struct rtw89_btc_statistic {
1515 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1516 struct rtw89_traffic_stats traffic;
1517 };
1518
1519 #define BTC_WL_RSSI_THMAX 4
1520
1521 struct rtw89_btc_wl_link_info {
1522 struct rtw89_btc_chdef chdef;
1523 struct rtw89_btc_statistic stat;
1524 enum rtw89_tfc_dir dir;
1525 u8 rssi_state[BTC_WL_RSSI_THMAX];
1526 u8 mac_addr[ETH_ALEN];
1527 u8 busy;
1528 u8 ch;
1529 u8 bw;
1530 u8 band;
1531 u8 role;
1532 u8 pid;
1533 u8 phy;
1534 u8 dtim_period;
1535 u8 mode;
1536 u8 tx_1ss_limit;
1537
1538 u8 mac_id;
1539 u8 tx_retry;
1540
1541 u32 bcn_period;
1542 u32 busy_t;
1543 u32 tx_time;
1544 u32 client_cnt;
1545 u32 rx_rate_drop_cnt;
1546 u32 noa_duration;
1547
1548 u32 active: 1;
1549 u32 noa: 1;
1550 u32 client_ps: 1;
1551 u32 connected: 2;
1552 };
1553
1554 union rtw89_btc_wl_state_map {
1555 u32 val;
1556 struct rtw89_btc_wl_smap map;
1557 };
1558
1559 struct rtw89_btc_bt_hfp_desc {
1560 u32 exist: 1;
1561 u32 type: 2;
1562 u32 rsvd: 29;
1563 };
1564
1565 struct rtw89_btc_bt_hid_desc {
1566 u32 exist: 1;
1567 u32 slot_info: 2;
1568 u32 pair_cnt: 2;
1569 u32 type: 8;
1570 u32 rsvd: 19;
1571 };
1572
1573 struct rtw89_btc_bt_a2dp_desc {
1574 u8 exist: 1;
1575 u8 exist_last: 1;
1576 u8 play_latency: 1;
1577 u8 type: 3;
1578 u8 active: 1;
1579 u8 sink: 1;
1580 u32 handle_update: 1;
1581 u32 devinfo_query: 1;
1582 u32 no_empty_streak_2s: 8;
1583 u32 no_empty_streak_max: 8;
1584 u32 rsvd: 6;
1585
1586 u8 bitpool;
1587 u16 vendor_id;
1588 u32 device_name;
1589 u32 flush_time;
1590 };
1591
1592 struct rtw89_btc_bt_pan_desc {
1593 u32 exist: 1;
1594 u32 type: 1;
1595 u32 active: 1;
1596 u32 rsvd: 29;
1597 };
1598
1599 struct rtw89_btc_bt_rfk_info {
1600 u32 run: 1;
1601 u32 req: 1;
1602 u32 timeout: 1;
1603 u32 rsvd: 29;
1604 };
1605
1606 union rtw89_btc_bt_rfk_info_map {
1607 u32 val;
1608 struct rtw89_btc_bt_rfk_info map;
1609 };
1610
1611 struct rtw89_btc_bt_ver_info {
1612 u32 fw_coex; /* match with which coex_ver */
1613 u32 fw;
1614 };
1615
1616 struct rtw89_btc_bool_sta_chg {
1617 u32 now: 1;
1618 u32 last: 1;
1619 u32 remain: 1;
1620 u32 srvd: 29;
1621 };
1622
1623 struct rtw89_btc_u8_sta_chg {
1624 u8 now;
1625 u8 last;
1626 u8 remain;
1627 u8 rsvd;
1628 };
1629
1630 struct rtw89_btc_wl_scan_info {
1631 u8 band[RTW89_PHY_NUM];
1632 u8 phy_map;
1633 u8 rsvd;
1634 };
1635
1636 struct rtw89_btc_wl_dbcc_info {
1637 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */
1638 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */
1639 u8 real_band[RTW89_PHY_NUM];
1640 u8 role[RTW89_PHY_NUM]; /* role in each phy */
1641 };
1642
1643 struct rtw89_btc_wl_mlo_info {
1644 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */
1645 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */
1646 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */
1647 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */
1648
1649 u8 wtype; /* enum phl_mr_wtype */
1650 u8 mrcx_mode;
1651 u8 mrcx_act_hwb_map;
1652 u8 mrcx_bt_slot_rsp;
1653
1654 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */
1655 u8 mlo_en; /* MLO enable */
1656 u8 mlo_adie; /* a-die count */
1657 u8 dual_hw_band_en; /* both 2 HW-band link exist */
1658
1659 u32 link_status; /* enum mlo_dbcc_mode_type */
1660 };
1661
1662 struct rtw89_btc_wl_active_role {
1663 u8 connected: 1;
1664 u8 pid: 3;
1665 u8 phy: 1;
1666 u8 noa: 1;
1667 u8 band: 2;
1668
1669 u8 client_ps: 1;
1670 u8 bw: 7;
1671
1672 u8 role;
1673 u8 ch;
1674
1675 u16 tx_lvl;
1676 u16 rx_lvl;
1677 u16 tx_rate;
1678 u16 rx_rate;
1679 };
1680
1681 struct rtw89_btc_wl_active_role_v1 {
1682 u8 connected: 1;
1683 u8 pid: 3;
1684 u8 phy: 1;
1685 u8 noa: 1;
1686 u8 band: 2;
1687
1688 u8 client_ps: 1;
1689 u8 bw: 7;
1690
1691 u8 role;
1692 u8 ch;
1693
1694 u16 tx_lvl;
1695 u16 rx_lvl;
1696 u16 tx_rate;
1697 u16 rx_rate;
1698
1699 u32 noa_duration; /* ms */
1700 };
1701
1702 struct rtw89_btc_wl_active_role_v2 {
1703 u8 connected: 1;
1704 u8 pid: 3;
1705 u8 phy: 1;
1706 u8 noa: 1;
1707 u8 band: 2;
1708
1709 u8 client_ps: 1;
1710 u8 bw: 7;
1711
1712 u8 role;
1713 u8 ch;
1714
1715 u32 noa_duration; /* ms */
1716 };
1717
1718 struct rtw89_btc_wl_active_role_v7 {
1719 u8 connected;
1720 u8 pid;
1721 u8 phy;
1722 u8 noa;
1723
1724 u8 band;
1725 u8 client_ps;
1726 u8 bw;
1727 u8 role;
1728
1729 u8 ch;
1730 u8 noa_dur;
1731 u8 client_cnt;
1732 u8 rsvd2;
1733 } __packed;
1734
1735 struct rtw89_btc_wl_role_info_bpos {
1736 u16 none: 1;
1737 u16 station: 1;
1738 u16 ap: 1;
1739 u16 vap: 1;
1740 u16 adhoc: 1;
1741 u16 adhoc_master: 1;
1742 u16 mesh: 1;
1743 u16 moniter: 1;
1744 u16 p2p_device: 1;
1745 u16 p2p_gc: 1;
1746 u16 p2p_go: 1;
1747 u16 nan: 1;
1748 };
1749
1750 struct rtw89_btc_wl_scc_ctrl {
1751 u8 null_role1;
1752 u8 null_role2;
1753 u8 ebt_null; /* if tx null at EBT slot */
1754 };
1755
1756 union rtw89_btc_wl_role_info_map {
1757 u16 val;
1758 struct rtw89_btc_wl_role_info_bpos role;
1759 };
1760
1761 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1762 u8 connect_cnt;
1763 u8 link_mode;
1764 union rtw89_btc_wl_role_info_map role_map;
1765 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1766 };
1767
1768 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1769 u8 connect_cnt;
1770 u8 link_mode;
1771 union rtw89_btc_wl_role_info_map role_map;
1772 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1773 u32 mrole_type; /* btc_wl_mrole_type */
1774 u32 mrole_noa_duration; /* ms */
1775
1776 u32 dbcc_en: 1;
1777 u32 dbcc_chg: 1;
1778 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1779 u32 link_mode_chg: 1;
1780 u32 rsvd: 27;
1781 };
1782
1783 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1784 u8 connect_cnt;
1785 u8 link_mode;
1786 union rtw89_btc_wl_role_info_map role_map;
1787 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1788 u32 mrole_type; /* btc_wl_mrole_type */
1789 u32 mrole_noa_duration; /* ms */
1790
1791 u32 dbcc_en: 1;
1792 u32 dbcc_chg: 1;
1793 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1794 u32 link_mode_chg: 1;
1795 u32 rsvd: 27;
1796 };
1797
1798 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1799 u8 connected;
1800 u8 pid;
1801 u8 phy;
1802 u8 noa;
1803
1804 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1805 u8 active; /* 0:rlink is under doze */
1806 u8 bw; /* enum channel_width */
1807 u8 role; /*enum role_type */
1808
1809 u8 ch;
1810 u8 noa_dur; /* ms */
1811 u8 client_cnt; /* for Role = P2P-Go/AP */
1812 u8 mode; /* wifi protocol */
1813 } __packed;
1814
1815 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1816 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1817 u8 connect_cnt;
1818 u8 link_mode;
1819 u8 link_mode_chg;
1820 u8 p2p_2g;
1821
1822 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1823
1824 u32 role_map;
1825 u32 mrole_type; /* btc_wl_mrole_type */
1826 u32 mrole_noa_duration; /* ms */
1827 u32 dbcc_en;
1828 u32 dbcc_chg;
1829 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1830 } __packed;
1831
1832 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1833 u8 connect_cnt;
1834 u8 link_mode;
1835 u8 link_mode_chg;
1836 u8 p2p_2g;
1837
1838 u8 pta_req_band;
1839 u8 dbcc_en; /* 1+1 and 2.4G-included */
1840 u8 dbcc_chg;
1841 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1842
1843 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1844
1845 u32 role_map;
1846 u32 mrole_type; /* btc_wl_mrole_type */
1847 u32 mrole_noa_duration; /* ms */
1848 } __packed;
1849
1850 struct rtw89_btc_wl_ver_info {
1851 u32 fw_coex; /* match with which coex_ver */
1852 u32 fw;
1853 u32 mac;
1854 u32 bb;
1855 u32 rf;
1856 };
1857
1858 struct rtw89_btc_wl_afh_info {
1859 u8 en;
1860 u8 ch;
1861 u8 bw;
1862 u8 rsvd;
1863 } __packed;
1864
1865 struct rtw89_btc_wl_rfk_info {
1866 u32 state: 2;
1867 u32 path_map: 4;
1868 u32 phy_map: 2;
1869 u32 band: 2;
1870 u32 type: 8;
1871 u32 con_rfk: 1;
1872 u32 rsvd: 13;
1873
1874 u32 start_time;
1875 u32 proc_time;
1876 };
1877
1878 struct rtw89_btc_bt_smap {
1879 u32 connect: 1;
1880 u32 ble_connect: 1;
1881 u32 acl_busy: 1;
1882 u32 sco_busy: 1;
1883 u32 mesh_busy: 1;
1884 u32 inq_pag: 1;
1885 };
1886
1887 union rtw89_btc_bt_state_map {
1888 u32 val;
1889 struct rtw89_btc_bt_smap map;
1890 };
1891
1892 #define BTC_BT_RSSI_THMAX 4
1893 #define BTC_BT_AFH_GROUP 12
1894 #define BTC_BT_AFH_LE_GROUP 5
1895
1896 struct rtw89_btc_bt_txpwr_desc {
1897 s8 br_dbm;
1898 s8 le_dbm;
1899 u8 br_gain_index;
1900 u8 le_gain_index;
1901 };
1902
1903 struct rtw89_btc_bt_link_info {
1904 struct rtw89_btc_u8_sta_chg profile_cnt;
1905 struct rtw89_btc_bool_sta_chg multi_link;
1906 struct rtw89_btc_bool_sta_chg relink;
1907 struct rtw89_btc_bt_hfp_desc hfp_desc;
1908 struct rtw89_btc_bt_hid_desc hid_desc;
1909 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1910 struct rtw89_btc_bt_pan_desc pan_desc;
1911 union rtw89_btc_bt_state_map status;
1912 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc;
1913
1914 u8 sut_pwr_level[BTC_PROFILE_MAX];
1915 u8 golden_rx_shift[BTC_PROFILE_MAX];
1916 u8 rssi_state[BTC_BT_RSSI_THMAX];
1917 u8 afh_map[BTC_BT_AFH_GROUP];
1918 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1919
1920 u32 role_sw: 1;
1921 u32 slave_role: 1;
1922 u32 afh_update: 1;
1923 u32 cqddr: 1;
1924 u32 rssi: 8;
1925 u32 tx_3m: 1;
1926 u32 rsvd: 19;
1927 };
1928
1929 struct rtw89_btc_3rdcx_info {
1930 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1931 u8 hw_coex;
1932 u16 rsvd;
1933 };
1934
1935 struct rtw89_btc_dm_emap {
1936 u32 init: 1;
1937 u32 pta_owner: 1;
1938 u32 wl_rfk_timeout: 1;
1939 u32 bt_rfk_timeout: 1;
1940 u32 wl_fw_hang: 1;
1941 u32 cycle_hang: 1;
1942 u32 w1_hang: 1;
1943 u32 b1_hang: 1;
1944 u32 tdma_no_sync: 1;
1945 u32 slot_no_sync: 1;
1946 u32 wl_slot_drift: 1;
1947 u32 bt_slot_drift: 1;
1948 u32 role_num_mismatch: 1;
1949 u32 null1_tx_late: 1;
1950 u32 bt_afh_conflict: 1;
1951 u32 bt_leafh_conflict: 1;
1952 u32 bt_slot_flood: 1;
1953 u32 wl_e2g_hang: 1;
1954 u32 wl_ver_mismatch: 1;
1955 u32 bt_ver_mismatch: 1;
1956 u32 rfe_type0: 1;
1957 u32 h2c_buffer_over: 1;
1958 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1959 u32 wl_no_sta_ntfy: 1;
1960
1961 u32 h2c_bmap_mismatch: 1;
1962 u32 c2h_bmap_mismatch: 1;
1963 u32 h2c_struct_invalid: 1;
1964 u32 c2h_struct_invalid: 1;
1965 u32 h2c_c2h_buffer_mismatch: 1;
1966 };
1967
1968 union rtw89_btc_dm_error_map {
1969 u32 val;
1970 struct rtw89_btc_dm_emap map;
1971 };
1972
1973 struct rtw89_btc_rf_para {
1974 u32 tx_pwr_freerun;
1975 u32 rx_gain_freerun;
1976 u32 tx_pwr_perpkt;
1977 u32 rx_gain_perpkt;
1978 };
1979
1980 struct rtw89_btc_wl_nhm {
1981 u8 instant_wl_nhm_dbm;
1982 u8 instant_wl_nhm_per_mhz;
1983 u16 valid_record_times;
1984 s8 record_pwr[16];
1985 u8 record_ratio[16];
1986 s8 pwr; /* dbm_per_MHz */
1987 u8 ratio;
1988 u8 current_status;
1989 u8 refresh;
1990 bool start_flag;
1991 s8 pwr_max;
1992 s8 pwr_min;
1993 };
1994
1995 struct rtw89_btc_wl_info {
1996 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1997 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1998 struct rtw89_btc_wl_rfk_info rfk_info;
1999 struct rtw89_btc_wl_ver_info ver_info;
2000 struct rtw89_btc_wl_afh_info afh_info;
2001 struct rtw89_btc_wl_role_info role_info;
2002 struct rtw89_btc_wl_role_info_v1 role_info_v1;
2003 struct rtw89_btc_wl_role_info_v2 role_info_v2;
2004 struct rtw89_btc_wl_role_info_v7 role_info_v7;
2005 struct rtw89_btc_wl_role_info_v8 role_info_v8;
2006 struct rtw89_btc_wl_scan_info scan_info;
2007 struct rtw89_btc_wl_dbcc_info dbcc_info;
2008 struct rtw89_btc_wl_mlo_info mlo_info;
2009 struct rtw89_btc_rf_para rf_para;
2010 struct rtw89_btc_wl_nhm nhm;
2011 union rtw89_btc_wl_state_map status;
2012
2013 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
2014 u8 rssi_level;
2015 u8 cn_report;
2016 u8 coex_mode;
2017 u8 pta_req_mac;
2018 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */
2019
2020 bool is_5g_hi_channel;
2021 bool go_client_exist;
2022 bool noa_exist;
2023 bool pta_reg_mac_chg;
2024 bool bg_mode;
2025 bool he_mode;
2026 bool scbd_change;
2027 bool fw_ver_mismatch;
2028 bool client_cnt_inc_2g;
2029 bool link_mode_chg;
2030 bool dbcc_chg;
2031 u32 scbd;
2032 };
2033
2034 struct rtw89_btc_module {
2035 struct rtw89_btc_ant_info ant;
2036 u8 rfe_type;
2037 u8 cv;
2038
2039 u8 bt_solo: 1;
2040 u8 bt_pos: 1;
2041 u8 switch_type: 1;
2042 u8 wa_type: 3;
2043
2044 u8 kt_ver_adie;
2045 };
2046
2047 struct rtw89_btc_module_v7 {
2048 u8 rfe_type;
2049 u8 kt_ver;
2050 u8 bt_solo;
2051 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
2052
2053 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
2054 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
2055 u8 kt_ver_adie;
2056 u8 rsvd;
2057
2058 struct rtw89_btc_ant_info_v7 ant;
2059 } __packed;
2060
2061 union rtw89_btc_module_info {
2062 struct rtw89_btc_module md;
2063 struct rtw89_btc_module_v7 md_v7;
2064 };
2065
2066 #define RTW89_BTC_DM_MAXSTEP 30
2067 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
2068
2069 struct rtw89_btc_dm_step {
2070 u16 step[RTW89_BTC_DM_MAXSTEP];
2071 u8 step_pos;
2072 bool step_ov;
2073 };
2074
2075 struct rtw89_btc_init_info {
2076 struct rtw89_btc_module module;
2077 u8 wl_guard_ch;
2078
2079 u8 wl_only: 1;
2080 u8 wl_init_ok: 1;
2081 u8 dbcc_en: 1;
2082 u8 cx_other: 1;
2083 u8 bt_only: 1;
2084
2085 u16 rsvd;
2086 };
2087
2088 struct rtw89_btc_init_info_v7 {
2089 u8 wl_guard_ch;
2090 u8 wl_only;
2091 u8 wl_init_ok;
2092 u8 rsvd3;
2093
2094 u8 cx_other;
2095 u8 bt_only;
2096 u8 pta_mode;
2097 u8 pta_direction;
2098
2099 struct rtw89_btc_module_v7 module;
2100 } __packed;
2101
2102 union rtw89_btc_init_info_u {
2103 struct rtw89_btc_init_info init;
2104 struct rtw89_btc_init_info_v7 init_v7;
2105 };
2106
2107 struct rtw89_btc_wl_tx_limit_para {
2108 u16 enable;
2109 u32 tx_time; /* unit: us */
2110 u16 tx_retry;
2111 };
2112
2113 enum rtw89_btc_bt_scan_type {
2114 BTC_SCAN_INQ = 0,
2115 BTC_SCAN_PAGE,
2116 BTC_SCAN_BLE,
2117 BTC_SCAN_INIT,
2118 BTC_SCAN_TV,
2119 BTC_SCAN_ADV,
2120 BTC_SCAN_MAX1,
2121 };
2122
2123 enum rtw89_btc_ble_scan_type {
2124 CXSCAN_BG = 0,
2125 CXSCAN_INIT,
2126 CXSCAN_LE,
2127 CXSCAN_MAX
2128 };
2129
2130 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2131 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
2132
2133 struct rtw89_btc_bt_scan_info_v1 {
2134 __le16 win;
2135 __le16 intvl;
2136 __le32 flags;
2137 } __packed;
2138
2139 struct rtw89_btc_bt_scan_info_v2 {
2140 __le16 win;
2141 __le16 intvl;
2142 } __packed;
2143
2144 struct rtw89_btc_fbtc_btscan_v1 {
2145 u8 fver; /* btc_ver::fcxbtscan */
2146 u8 rsvd;
2147 __le16 rsvd2;
2148 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2149 } __packed;
2150
2151 struct rtw89_btc_fbtc_btscan_v2 {
2152 u8 fver; /* btc_ver::fcxbtscan */
2153 u8 type;
2154 __le16 rsvd2;
2155 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2156 } __packed;
2157
2158 struct rtw89_btc_fbtc_btscan_v7 {
2159 u8 fver; /* btc_ver::fcxbtscan */
2160 u8 type;
2161 u8 rsvd0;
2162 u8 rsvd1;
2163 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2164 } __packed;
2165
2166 union rtw89_btc_fbtc_btscan {
2167 struct rtw89_btc_fbtc_btscan_v1 v1;
2168 struct rtw89_btc_fbtc_btscan_v2 v2;
2169 struct rtw89_btc_fbtc_btscan_v7 v7;
2170 };
2171
2172 struct rtw89_btc_bt_info {
2173 struct rtw89_btc_bt_link_info link_info;
2174 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2175 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2176 struct rtw89_btc_bt_ver_info ver_info;
2177 struct rtw89_btc_bool_sta_chg enable;
2178 struct rtw89_btc_bool_sta_chg inq_pag;
2179 struct rtw89_btc_rf_para rf_para;
2180 union rtw89_btc_bt_rfk_info_map rfk_info;
2181
2182 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2183 u8 txpwr_info[BTC_BTINFO_MAX];
2184 u8 rssi_level;
2185
2186 u32 scbd;
2187 u32 feature;
2188
2189 u32 mbx_avl: 1;
2190 u32 whql_test: 1;
2191 u32 igno_wl: 1;
2192 u32 reinit: 1;
2193 u32 ble_scan_en: 1;
2194 u32 btg_type: 1;
2195 u32 inq: 1;
2196 u32 pag: 1;
2197 u32 run_patch_code: 1;
2198 u32 hi_lna_rx: 1;
2199 u32 scan_rx_low_pri: 1;
2200 u32 scan_info_update: 1;
2201 u32 lna_constrain: 3;
2202 u32 rsvd: 17;
2203 };
2204
2205 struct rtw89_btc_cx {
2206 struct rtw89_btc_wl_info wl;
2207 struct rtw89_btc_bt_info bt;
2208 struct rtw89_btc_3rdcx_info other;
2209 u32 state_map;
2210 u32 cnt_bt[BTC_BCNT_NUM];
2211 u32 cnt_wl[BTC_WCNT_NUM];
2212 };
2213
2214 struct rtw89_btc_fbtc_tdma {
2215 u8 type; /* btc_ver::fcxtdma */
2216 u8 rxflctrl;
2217 u8 txpause;
2218 u8 wtgle_n;
2219 u8 leak_n;
2220 u8 ext_ctrl;
2221 u8 rxflctrl_role;
2222 u8 option_ctrl;
2223 } __packed;
2224
2225 struct rtw89_btc_fbtc_tdma_v3 {
2226 u8 fver; /* btc_ver::fcxtdma */
2227 u8 rsvd;
2228 __le16 rsvd1;
2229 struct rtw89_btc_fbtc_tdma tdma;
2230 } __packed;
2231
2232 union rtw89_btc_fbtc_tdma_le32 {
2233 struct rtw89_btc_fbtc_tdma v1;
2234 struct rtw89_btc_fbtc_tdma_v3 v3;
2235 };
2236
2237 #define CXMREG_MAX 30
2238 #define CXMREG_MAX_V2 20
2239 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2240 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2241
2242 enum rtw89_btc_bt_sta_counter {
2243 BTC_BCNT_RFK_REQ = 0,
2244 BTC_BCNT_RFK_GO = 1,
2245 BTC_BCNT_RFK_REJECT = 2,
2246 BTC_BCNT_RFK_FAIL = 3,
2247 BTC_BCNT_RFK_TIMEOUT = 4,
2248 BTC_BCNT_HI_TX = 5,
2249 BTC_BCNT_HI_RX = 6,
2250 BTC_BCNT_LO_TX = 7,
2251 BTC_BCNT_LO_RX = 8,
2252 BTC_BCNT_POLLUTED = 9,
2253 BTC_BCNT_STA_MAX
2254 };
2255
2256 enum rtw89_btc_bt_sta_counter_v105 {
2257 BTC_BCNT_RFK_REQ_V105 = 0,
2258 BTC_BCNT_HI_TX_V105 = 1,
2259 BTC_BCNT_HI_RX_V105 = 2,
2260 BTC_BCNT_LO_TX_V105 = 3,
2261 BTC_BCNT_LO_RX_V105 = 4,
2262 BTC_BCNT_POLLUTED_V105 = 5,
2263 BTC_BCNT_STA_MAX_V105
2264 };
2265
2266 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2267 u16 fver; /* btc_ver::fcxbtcrpt */
2268 u16 rpt_cnt; /* tmr counters */
2269 u32 wl_fw_coex_ver; /* match which driver's coex version */
2270 u32 wl_fw_cx_offload;
2271 u32 wl_fw_ver;
2272 u32 rpt_enable;
2273 u32 rpt_para; /* ms */
2274 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2275 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2276 u32 mb_recv_cnt; /* fw recv mailbox counter */
2277 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2278 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2279 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2280 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2281 u32 c2h_cnt; /* fw send c2h counter */
2282 u32 h2c_cnt; /* fw recv h2c counter */
2283 } __packed;
2284
2285 struct rtw89_btc_fbtc_rpt_ctrl_info {
2286 __le32 cnt; /* fw report counter */
2287 __le32 en; /* report map */
2288 __le32 para; /* not used */
2289
2290 __le32 cnt_c2h; /* fw send c2h counter */
2291 __le32 cnt_h2c; /* fw recv h2c counter */
2292 __le32 len_c2h; /* The total length of the last C2H */
2293
2294 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2295 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2296 } __packed;
2297
2298 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2299 __le32 cx_ver; /* match which driver's coex version */
2300 __le32 fw_ver;
2301 __le32 en; /* report map */
2302
2303 __le16 cnt; /* fw report counter */
2304 __le16 cnt_c2h; /* fw send c2h counter */
2305 __le16 cnt_h2c; /* fw recv h2c counter */
2306 __le16 len_c2h; /* The total length of the last C2H */
2307
2308 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2309 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2310 } __packed;
2311
2312 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2313 __le16 cnt; /* fw report counter */
2314 __le16 cnt_c2h; /* fw send c2h counter */
2315 __le16 cnt_h2c; /* fw recv h2c counter */
2316 __le16 len_c2h; /* The total length of the last C2H */
2317
2318 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2319 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2320
2321 __le32 cx_ver; /* match which driver's coex version */
2322 __le32 fw_ver;
2323 __le32 en; /* report map */
2324 } __packed;
2325
2326 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2327 __le32 cx_ver; /* match which driver's coex version */
2328 __le32 cx_offload;
2329 __le32 fw_ver;
2330 } __packed;
2331
2332 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2333 __le32 cnt_empty; /* a2dp empty count */
2334 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2335 __le32 cnt_tx;
2336 __le32 cnt_ack;
2337 __le32 cnt_nack;
2338 } __packed;
2339
2340 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2341 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2342 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2343 __le32 cnt_recv; /* fw recv mailbox counter */
2344 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2345 } __packed;
2346
2347 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2348 u8 fver;
2349 u8 rsvd;
2350 __le16 rsvd1;
2351 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2352 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2353 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2354 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2355 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM];
2356 } __packed;
2357
2358 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2359 u8 fver;
2360 u8 rsvd;
2361 __le16 rsvd1;
2362
2363 u8 gnt_val[RTW89_PHY_NUM][4];
2364 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2365
2366 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2367 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2368 } __packed;
2369
2370 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2371 u8 fver;
2372 u8 rsvd;
2373 __le16 rsvd1;
2374
2375 u8 gnt_val[RTW89_PHY_NUM][4];
2376 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2377
2378 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2379 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2380 } __packed;
2381
2382 struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2383 u8 fver;
2384 u8 rsvd0;
2385 u8 rsvd1;
2386 u8 rsvd2;
2387
2388 u8 gnt_val[RTW89_PHY_NUM][4];
2389 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2390
2391 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2392 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2393 } __packed;
2394
2395 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2396 u8 fver;
2397 u8 rsvd0;
2398 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2399 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2400
2401 u8 gnt_val[RTW89_PHY_NUM][4];
2402 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2403
2404 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2405 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2406 } __packed;
2407
2408 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2409 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2410 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2411 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2412 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2413 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2414 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2415 };
2416
2417 enum rtw89_fbtc_ext_ctrl_type {
2418 CXECTL_OFF = 0x0, /* tdma off */
2419 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2420 CXECTL_EXT = 0x2,
2421 CXECTL_MAX
2422 };
2423
2424 union rtw89_btc_fbtc_rxflct {
2425 u8 val;
2426 u8 type: 3;
2427 u8 tgln_n: 5;
2428 };
2429
2430 enum rtw89_btc_cxst_state {
2431 CXST_OFF = 0x0,
2432 CXST_B2W = 0x1,
2433 CXST_W1 = 0x2,
2434 CXST_W2 = 0x3,
2435 CXST_W2B = 0x4,
2436 CXST_B1 = 0x5,
2437 CXST_B2 = 0x6,
2438 CXST_B3 = 0x7,
2439 CXST_B4 = 0x8,
2440 CXST_LK = 0x9,
2441 CXST_BLK = 0xa,
2442 CXST_E2G = 0xb,
2443 CXST_E5G = 0xc,
2444 CXST_EBT = 0xd,
2445 CXST_ENULL = 0xe,
2446 CXST_WLK = 0xf,
2447 CXST_W1FDD = 0x10,
2448 CXST_B1FDD = 0x11,
2449 CXST_MAX = 0x12,
2450 };
2451
2452 enum rtw89_btc_cxevnt {
2453 CXEVNT_TDMA_ENTRY = 0x0,
2454 CXEVNT_WL_TMR,
2455 CXEVNT_B1_TMR,
2456 CXEVNT_B2_TMR,
2457 CXEVNT_B3_TMR,
2458 CXEVNT_B4_TMR,
2459 CXEVNT_W2B_TMR,
2460 CXEVNT_B2W_TMR,
2461 CXEVNT_BCN_EARLY,
2462 CXEVNT_A2DP_EMPTY,
2463 CXEVNT_LK_END,
2464 CXEVNT_RX_ISR,
2465 CXEVNT_RX_FC0,
2466 CXEVNT_RX_FC1,
2467 CXEVNT_BT_RELINK,
2468 CXEVNT_BT_RETRY,
2469 CXEVNT_E2G,
2470 CXEVNT_E5G,
2471 CXEVNT_EBT,
2472 CXEVNT_ENULL,
2473 CXEVNT_DRV_WLK,
2474 CXEVNT_BCN_OK,
2475 CXEVNT_BT_CHANGE,
2476 CXEVNT_EBT_EXTEND,
2477 CXEVNT_E2G_NULL1,
2478 CXEVNT_B1FDD_TMR,
2479 CXEVNT_MAX
2480 };
2481
2482 enum {
2483 CXBCN_ALL = 0x0,
2484 CXBCN_ALL_OK,
2485 CXBCN_BT_SLOT,
2486 CXBCN_BT_OK,
2487 CXBCN_MAX
2488 };
2489
2490 enum btc_slot_type {
2491 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2492 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2493 CXSTYPE_NUM,
2494 };
2495
2496 enum { /* TIME */
2497 CXT_BT = 0x0,
2498 CXT_WL = 0x1,
2499 CXT_MAX
2500 };
2501
2502 enum { /* TIME-A2DP */
2503 CXT_FLCTRL_OFF = 0x0,
2504 CXT_FLCTRL_ON = 0x1,
2505 CXT_FLCTRL_MAX
2506 };
2507
2508 enum { /* STEP TYPE */
2509 CXSTEP_NONE = 0x0,
2510 CXSTEP_EVNT = 0x1,
2511 CXSTEP_SLOT = 0x2,
2512 CXSTEP_MAX,
2513 };
2514
2515 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2516 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2517 RPT_BT_AFH_SEQ_LE = 0x20
2518 };
2519
2520 #define BTC_DBG_MAX1 32
2521 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2522 u8 fver; /* btc_ver::fcxgpiodbg */
2523 u8 rsvd;
2524 __le16 rsvd2;
2525 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2526 __le32 pre_state; /* the debug signal is 1 or 0 */
2527 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2528 } __packed;
2529
2530 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2531 u8 fver;
2532 u8 rsvd0;
2533 u8 rsvd1;
2534 u8 rsvd2;
2535
2536 u8 gpio_map[BTC_DBG_MAX1];
2537
2538 __le32 en_map;
2539 __le32 pre_state;
2540 } __packed;
2541
2542 union rtw89_btc_fbtc_gpio_dbg {
2543 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2544 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2545 };
2546
2547 struct rtw89_btc_fbtc_mreg_val_v1 {
2548 u8 fver; /* btc_ver::fcxmreg */
2549 u8 reg_num;
2550 __le16 rsvd;
2551 __le32 mreg_val[CXMREG_MAX];
2552 } __packed;
2553
2554 struct rtw89_btc_fbtc_mreg_val_v2 {
2555 u8 fver; /* btc_ver::fcxmreg */
2556 u8 reg_num;
2557 __le16 rsvd;
2558 __le32 mreg_val[CXMREG_MAX_V2];
2559 } __packed;
2560
2561 struct rtw89_btc_fbtc_mreg_val_v7 {
2562 u8 fver;
2563 u8 reg_num;
2564 u8 rsvd0;
2565 u8 rsvd1;
2566 __le32 mreg_val[CXMREG_MAX_V2];
2567 } __packed;
2568
2569 union rtw89_btc_fbtc_mreg_val {
2570 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2571 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2572 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2573 };
2574
2575 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2576 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2577 .offset = cpu_to_le32(__offset), }
2578
2579 struct rtw89_btc_fbtc_mreg {
2580 __le16 type;
2581 __le16 bytes;
2582 __le32 offset;
2583 } __packed;
2584
2585 struct rtw89_btc_fbtc_slot {
2586 __le16 dur;
2587 __le32 cxtbl;
2588 __le16 cxtype;
2589 } __packed;
2590
2591 struct rtw89_btc_fbtc_slots {
2592 u8 fver; /* btc_ver::fcxslots */
2593 u8 tbl_num;
2594 __le16 rsvd;
2595 __le32 update_map;
2596 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2597 } __packed;
2598
2599 struct rtw89_btc_fbtc_slot_v7 {
2600 __le16 dur; /* slot duration */
2601 __le16 cxtype;
2602 __le32 cxtbl;
2603 } __packed;
2604
2605 struct rtw89_btc_fbtc_slot_u16 {
2606 __le16 dur; /* slot duration */
2607 __le16 cxtype;
2608 __le16 cxtbl_l16; /* coex table [15:0] */
2609 __le16 cxtbl_h16; /* coex table [31:16] */
2610 } __packed;
2611
2612 struct rtw89_btc_fbtc_1slot_v7 {
2613 u8 fver;
2614 u8 sid; /* slot id */
2615 __le16 rsvd;
2616 struct rtw89_btc_fbtc_slot_v7 slot;
2617 } __packed;
2618
2619 struct rtw89_btc_fbtc_slots_v7 {
2620 u8 fver;
2621 u8 slot_cnt;
2622 u8 rsvd0;
2623 u8 rsvd1;
2624 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2625 __le32 update_map;
2626 } __packed;
2627
2628 union rtw89_btc_fbtc_slots_info {
2629 struct rtw89_btc_fbtc_slots v1;
2630 struct rtw89_btc_fbtc_slots_v7 v7;
2631 } __packed;
2632
2633 struct rtw89_btc_fbtc_step {
2634 u8 type;
2635 u8 val;
2636 __le16 difft;
2637 } __packed;
2638
2639 struct rtw89_btc_fbtc_steps_v2 {
2640 u8 fver; /* btc_ver::fcxstep */
2641 u8 rsvd;
2642 __le16 cnt;
2643 __le16 pos_old;
2644 __le16 pos_new;
2645 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2646 } __packed;
2647
2648 struct rtw89_btc_fbtc_steps_v3 {
2649 u8 fver;
2650 u8 en;
2651 __le16 rsvd;
2652 __le32 cnt;
2653 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2654 } __packed;
2655
2656 union rtw89_btc_fbtc_steps_info {
2657 struct rtw89_btc_fbtc_steps_v2 v2;
2658 struct rtw89_btc_fbtc_steps_v3 v3;
2659 };
2660
2661 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2662 u8 fver; /* btc_ver::fcxcysta */
2663 u8 rsvd;
2664 __le16 cycles; /* total cycle number */
2665 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2666 __le16 a2dpept; /* a2dp empty cnt */
2667 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2668 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2669 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2670 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2671 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2672 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2673 __le16 tavg_a2dpept; /* avg a2dp empty time */
2674 __le16 tmax_a2dpept; /* max a2dp empty time */
2675 __le16 tavg_lk; /* avg leak-slot time */
2676 __le16 tmax_lk; /* max leak-slot time */
2677 __le32 slot_cnt[CXST_MAX]; /* slot count */
2678 __le32 bcn_cnt[CXBCN_MAX];
2679 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2680 __le32 collision_cnt; /* counter for event/timer occur at same time */
2681 __le32 skip_cnt;
2682 __le32 exception;
2683 __le32 except_cnt;
2684 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2685 } __packed;
2686
2687 struct rtw89_btc_fbtc_fdd_try_info {
2688 __le16 cycles[CXT_FLCTRL_MAX];
2689 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2690 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2691 } __packed;
2692
2693 struct rtw89_btc_fbtc_cycle_time_info {
2694 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2695 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2696 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2697 } __packed;
2698
2699 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2700 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2701 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2702 } __packed;
2703
2704 struct rtw89_btc_fbtc_a2dp_trx_stat {
2705 u8 empty_cnt;
2706 u8 retry_cnt;
2707 u8 tx_rate;
2708 u8 tx_cnt;
2709 u8 ack_cnt;
2710 u8 nack_cnt;
2711 u8 rsvd1;
2712 u8 rsvd2;
2713 } __packed;
2714
2715 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2716 u8 empty_cnt;
2717 u8 retry_cnt;
2718 u8 tx_rate;
2719 u8 tx_cnt;
2720 u8 ack_cnt;
2721 u8 nack_cnt;
2722 u8 no_empty_cnt;
2723 u8 rsvd;
2724 } __packed;
2725
2726 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2727 __le16 cnt; /* a2dp empty cnt */
2728 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2729 __le16 tavg; /* avg a2dp empty time */
2730 __le16 tmax; /* max a2dp empty time */
2731 } __packed;
2732
2733 struct rtw89_btc_fbtc_cycle_leak_info {
2734 __le32 cnt_rximr; /* the rximr occur at leak slot */
2735 __le16 tavg; /* avg leak-slot time */
2736 __le16 tmax; /* max leak-slot time */
2737 } __packed;
2738
2739 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2740 __le16 tavg;
2741 __le16 tamx;
2742 __le32 cnt_rximr;
2743 } __packed;
2744
2745 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2746 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2747
2748 struct rtw89_btc_fbtc_cycle_fddt_info {
2749 __le16 train_cycle;
2750 __le16 tp;
2751
2752 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2753 s8 bt_tx_power; /* decrease Tx power (dB) */
2754 s8 bt_rx_gain; /* LNA constrain level */
2755 u8 no_empty_cnt;
2756
2757 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2758 u8 cn; /* condition_num */
2759 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2760 u8 train_result; /* refer to enum btc_fddt_check_map */
2761 } __packed;
2762
2763 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2764 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2765
2766 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2767 __le16 train_cycle;
2768 __le16 tp;
2769
2770 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2771 s8 bt_tx_power; /* decrease Tx power (dB) */
2772 s8 bt_rx_gain; /* LNA constrain level */
2773 u8 no_empty_cnt;
2774
2775 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2776 u8 cn; /* condition_num */
2777 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2778 u8 train_result; /* refer to enum btc_fddt_check_map */
2779 } __packed;
2780
2781 struct rtw89_btc_fbtc_fddt_cell_status {
2782 s8 wl_tx_pwr;
2783 s8 bt_tx_pwr;
2784 s8 bt_rx_gain;
2785 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2786 } __packed;
2787
2788 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2789 u8 fver;
2790 u8 rsvd;
2791 __le16 cycles; /* total cycle number */
2792 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2793 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2794 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2795 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2796 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2797 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2798 __le32 slot_cnt[CXST_MAX]; /* slot count */
2799 __le32 bcn_cnt[CXBCN_MAX];
2800 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2801 __le32 skip_cnt;
2802 __le32 except_cnt;
2803 __le32 except_map;
2804 } __packed;
2805
2806 #define FDD_TRAIN_WL_DIRECTION 2
2807 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2808 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2809
2810 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2811 u8 fver;
2812 u8 rsvd;
2813 u8 collision_cnt; /* counter for event/timer occur at the same time */
2814 u8 except_cnt;
2815
2816 __le16 skip_cnt;
2817 __le16 cycles; /* total cycle number */
2818
2819 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2820 __le16 slot_cnt[CXST_MAX]; /* slot count */
2821 __le16 bcn_cnt[CXBCN_MAX];
2822 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2823 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2824 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2825 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2826 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2827 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2828 [FDD_TRAIN_WL_RSSI_LEVEL]
2829 [FDD_TRAIN_BT_RSSI_LEVEL];
2830 __le32 except_map;
2831 } __packed;
2832
2833 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2834 u8 fver;
2835 u8 rsvd;
2836 u8 collision_cnt; /* counter for event/timer occur at the same time */
2837 u8 except_cnt;
2838 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2839
2840 __le16 skip_cnt;
2841 __le16 cycles; /* total cycle number */
2842
2843 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2844 __le16 slot_cnt[CXST_MAX]; /* slot count */
2845 __le16 bcn_cnt[CXBCN_MAX];
2846 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2847 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2848 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2849 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2850 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2851 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2852 [FDD_TRAIN_WL_RSSI_LEVEL]
2853 [FDD_TRAIN_BT_RSSI_LEVEL];
2854 __le32 except_map;
2855 } __packed;
2856
2857 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2858 u8 fver;
2859 u8 rsvd;
2860 u8 collision_cnt; /* counter for event/timer occur at the same time */
2861 u8 except_cnt;
2862
2863 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2864
2865 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2866
2867 __le16 skip_cnt;
2868 __le16 cycles; /* total cycle number */
2869
2870 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2871 __le16 slot_cnt[CXST_MAX]; /* slot count */
2872 __le16 bcn_cnt[CXBCN_MAX];
2873
2874 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2875 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2876 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2877
2878 __le32 except_map;
2879 } __packed;
2880
2881 union rtw89_btc_fbtc_cysta_info {
2882 struct rtw89_btc_fbtc_cysta_v2 v2;
2883 struct rtw89_btc_fbtc_cysta_v3 v3;
2884 struct rtw89_btc_fbtc_cysta_v4 v4;
2885 struct rtw89_btc_fbtc_cysta_v5 v5;
2886 struct rtw89_btc_fbtc_cysta_v7 v7;
2887 };
2888
2889 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2890 u8 fver; /* btc_ver::fcxnullsta */
2891 u8 rsvd;
2892 __le16 rsvd2;
2893 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2894 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2895 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2896 } __packed;
2897
2898 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2899 u8 fver; /* btc_ver::fcxnullsta */
2900 u8 rsvd;
2901 __le16 rsvd2;
2902 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2903 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2904 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2905 } __packed;
2906
2907 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2908 u8 fver;
2909 u8 rsvd0;
2910 u8 rsvd1;
2911 u8 rsvd2;
2912
2913 __le32 tmax[2];
2914 __le32 tavg[2];
2915 __le32 result[2][5];
2916 } __packed;
2917
2918 union rtw89_btc_fbtc_cynullsta_info {
2919 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2920 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2921 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2922 };
2923
2924 struct rtw89_btc_fbtc_btver_v1 {
2925 u8 fver; /* btc_ver::fcxbtver */
2926 u8 rsvd;
2927 __le16 rsvd2;
2928 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2929 __le32 fw_ver;
2930 __le32 feature;
2931 } __packed;
2932
2933 struct rtw89_btc_fbtc_btver_v7 {
2934 u8 fver;
2935 u8 rsvd0;
2936 u8 rsvd1;
2937 u8 rsvd2;
2938
2939 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2940 __le32 fw_ver;
2941 __le32 feature;
2942 } __packed;
2943
2944 union rtw89_btc_fbtc_btver {
2945 struct rtw89_btc_fbtc_btver_v1 v1;
2946 struct rtw89_btc_fbtc_btver_v7 v7;
2947 } __packed;
2948
2949 struct rtw89_btc_fbtc_btafh {
2950 u8 fver; /* btc_ver::fcxbtafh */
2951 u8 rsvd;
2952 __le16 rsvd2;
2953 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2954 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2955 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2956 } __packed;
2957
2958 struct rtw89_btc_fbtc_btafh_v2 {
2959 u8 fver; /* btc_ver::fcxbtafh */
2960 u8 rsvd;
2961 u8 rsvd2;
2962 u8 map_type;
2963 u8 afh_l[4];
2964 u8 afh_m[4];
2965 u8 afh_h[4];
2966 u8 afh_le_a[4];
2967 u8 afh_le_b[4];
2968 } __packed;
2969
2970 struct rtw89_btc_fbtc_btafh_v7 {
2971 u8 fver;
2972 u8 map_type;
2973 u8 rsvd0;
2974 u8 rsvd1;
2975 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2976 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2977 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2978 u8 afh_le_a[4];
2979 u8 afh_le_b[4];
2980 } __packed;
2981
2982 struct rtw89_btc_fbtc_btdevinfo {
2983 u8 fver; /* btc_ver::fcxbtdevinfo */
2984 u8 rsvd;
2985 __le16 vendor_id;
2986 __le32 dev_name; /* only 24 bits valid */
2987 __le32 flush_time;
2988 } __packed;
2989
2990 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2991 struct rtw89_btc_rf_trx_para {
2992 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2993 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2994 u8 bt_tx_power; /* decrease Tx power (dB) */
2995 u8 bt_rx_gain; /* LNA constrain level */
2996 };
2997
2998 struct rtw89_btc_trx_info {
2999 u8 tx_lvl;
3000 u8 rx_lvl;
3001 u8 wl_rssi;
3002 u8 bt_rssi;
3003
3004 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
3005 s8 rx_gain; /* rx gain table index (TBD.) */
3006 s8 bt_tx_power; /* decrease Tx power (dB) */
3007 s8 bt_rx_gain; /* LNA constrain level */
3008
3009 u8 cn; /* condition_num */
3010 s8 nhm;
3011 u8 bt_profile;
3012 u8 rsvd2;
3013
3014 u16 tx_rate;
3015 u16 rx_rate;
3016
3017 u32 tx_tp;
3018 u32 rx_tp;
3019 u32 rx_err_ratio;
3020 };
3021
3022 enum btc_rf_path {
3023 BTC_RF_S0 = 0,
3024 BTC_RF_S1 = 1,
3025 BTC_RF_NUM,
3026 };
3027
3028 struct rtw89_btc_fbtc_outsrc_set_info {
3029 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */
3030 u8 btg_rx[BTC_RF_NUM];
3031 u8 nbtg_tx[BTC_RF_NUM];
3032
3033 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */
3034 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */
3035
3036 u8 pta_req_hw_band;
3037 u8 rf_gbt_source;
3038 } __packed;
3039
3040 union rtw89_btc_fbtc_slot_u {
3041 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
3042 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
3043 };
3044
3045 struct rtw89_btc_dm {
3046 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */
3047 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */
3048 union rtw89_btc_fbtc_slot_u slot;
3049 union rtw89_btc_fbtc_slot_u slot_now;
3050 struct rtw89_btc_fbtc_tdma tdma;
3051 struct rtw89_btc_fbtc_tdma tdma_now;
3052 struct rtw89_mac_ax_coex_gnt gnt;
3053 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
3054 struct rtw89_btc_rf_trx_para rf_trx_para;
3055 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
3056 struct rtw89_btc_dm_step dm_step;
3057 struct rtw89_btc_wl_scc_ctrl wl_scc;
3058 struct rtw89_btc_trx_info trx_info;
3059 union rtw89_btc_dm_error_map error;
3060 u32 cnt_dm[BTC_DCNT_NUM];
3061 u32 cnt_notify[BTC_NCNT_NUM];
3062
3063 u32 update_slot_map;
3064 u32 set_ant_path;
3065 u32 e2g_slot_limit;
3066 u32 e2g_slot_nulltx_time;
3067
3068 u32 wl_only: 1;
3069 u32 wl_fw_cx_offload: 1;
3070 u32 freerun: 1;
3071 u32 fddt_train: 1;
3072 u32 wl_ps_ctrl: 2;
3073 u32 wl_mimo_ps: 1;
3074 u32 leak_ap: 1;
3075 u32 noisy_level: 3;
3076 u32 coex_info_map: 8;
3077 u32 bt_only: 1;
3078 u32 wl_btg_rx: 2;
3079 u32 trx_para_level: 8;
3080 u32 wl_stb_chg: 1;
3081 u32 pta_owner: 1;
3082
3083 u32 tdma_instant_excute: 1;
3084 u32 wl_btg_rx_rb: 2;
3085
3086 u16 slot_dur[CXST_MAX];
3087 u16 bt_slot_flood;
3088
3089 u8 run_reason;
3090 u8 run_action;
3091
3092 u8 wl_pre_agc: 2;
3093 u8 wl_lna2: 1;
3094 u8 freerun_chk: 1;
3095 u8 wl_pre_agc_rb: 2;
3096 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
3097 u8 slot_req_more: 1;
3098 };
3099
3100 struct rtw89_btc_ctrl {
3101 u32 manual: 1;
3102 u32 igno_bt: 1;
3103 u32 always_freerun: 1;
3104 u32 trace_step: 16;
3105 u32 rsvd: 12;
3106 };
3107
3108 struct rtw89_btc_ctrl_v7 {
3109 u8 manual;
3110 u8 igno_bt;
3111 u8 always_freerun;
3112 u8 rsvd;
3113 } __packed;
3114
3115 union rtw89_btc_ctrl_list {
3116 struct rtw89_btc_ctrl ctrl;
3117 struct rtw89_btc_ctrl_v7 ctrl_v7;
3118 };
3119
3120 struct rtw89_btc_dbg {
3121 /* cmd "rb" */
3122 bool rb_done;
3123 u32 rb_val;
3124 };
3125
3126 enum rtw89_btc_btf_fw_event {
3127 BTF_EVNT_RPT = 0,
3128 BTF_EVNT_BT_INFO = 1,
3129 BTF_EVNT_BT_SCBD = 2,
3130 BTF_EVNT_BT_REG = 3,
3131 BTF_EVNT_CX_RUNINFO = 4,
3132 BTF_EVNT_BT_PSD = 5,
3133 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */
3134 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */
3135 BTF_EVNT_BUF_OVERFLOW,
3136 BTF_EVNT_C2H_LOOPBACK,
3137 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */
3138 BTF_EVNT_MAX,
3139 };
3140
3141 enum btf_fw_event_report {
3142 BTC_RPT_TYPE_CTRL = 0x0,
3143 BTC_RPT_TYPE_TDMA,
3144 BTC_RPT_TYPE_SLOT,
3145 BTC_RPT_TYPE_CYSTA,
3146 BTC_RPT_TYPE_STEP,
3147 BTC_RPT_TYPE_NULLSTA,
3148 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
3149 BTC_RPT_TYPE_MREG,
3150 BTC_RPT_TYPE_GPIO_DBG,
3151 BTC_RPT_TYPE_BT_VER,
3152 BTC_RPT_TYPE_BT_SCAN,
3153 BTC_RPT_TYPE_BT_AFH,
3154 BTC_RPT_TYPE_BT_DEVICE,
3155 BTC_RPT_TYPE_TEST,
3156 BTC_RPT_TYPE_MAX = 31,
3157
3158 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3159 __BTC_RPT_TYPE_V0_MAX = 12,
3160 };
3161
3162 enum rtw_btc_btf_reg_type {
3163 REG_MAC = 0x0,
3164 REG_BB = 0x1,
3165 REG_RF = 0x2,
3166 REG_BT_RF = 0x3,
3167 REG_BT_MODEM = 0x4,
3168 REG_BT_BLUEWIZE = 0x5,
3169 REG_BT_VENDOR = 0x6,
3170 REG_BT_LE = 0x7,
3171 REG_MAX_TYPE,
3172 };
3173
3174 struct rtw89_btc_rpt_cmn_info {
3175 u32 rx_cnt;
3176 u32 rx_len;
3177 u32 req_len; /* expected rsp len */
3178 u8 req_fver; /* expected rsp fver */
3179 u8 rsp_fver; /* fver from fw */
3180 u8 valid;
3181 } __packed;
3182
3183 union rtw89_btc_fbtc_btafh_info {
3184 struct rtw89_btc_fbtc_btafh v1;
3185 struct rtw89_btc_fbtc_btafh_v2 v2;
3186 struct rtw89_btc_fbtc_btafh_v7 v7;
3187 };
3188
3189 struct rtw89_btc_report_ctrl_state {
3190 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3191 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3192 };
3193
3194 struct rtw89_btc_rpt_fbtc_tdma {
3195 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3196 union rtw89_btc_fbtc_tdma_le32 finfo;
3197 };
3198
3199 struct rtw89_btc_rpt_fbtc_slots {
3200 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3201 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3202 };
3203
3204 struct rtw89_btc_rpt_fbtc_cysta {
3205 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3206 union rtw89_btc_fbtc_cysta_info finfo;
3207 };
3208
3209 struct rtw89_btc_rpt_fbtc_step {
3210 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3211 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3212 };
3213
3214 struct rtw89_btc_rpt_fbtc_nullsta {
3215 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3216 union rtw89_btc_fbtc_cynullsta_info finfo;
3217 };
3218
3219 struct rtw89_btc_rpt_fbtc_mreg {
3220 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3221 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3222 };
3223
3224 struct rtw89_btc_rpt_fbtc_gpio_dbg {
3225 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3226 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3227 };
3228
3229 struct rtw89_btc_rpt_fbtc_btver {
3230 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3231 union rtw89_btc_fbtc_btver finfo; /* info from fw */
3232 };
3233
3234 struct rtw89_btc_rpt_fbtc_btscan {
3235 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3236 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3237 };
3238
3239 struct rtw89_btc_rpt_fbtc_btafh {
3240 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3241 union rtw89_btc_fbtc_btafh_info finfo;
3242 };
3243
3244 struct rtw89_btc_rpt_fbtc_btdev {
3245 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3246 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3247 };
3248
3249 enum rtw89_btc_btfre_type {
3250 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3251 BTFRE_UNDEF_TYPE,
3252 BTFRE_EXCEPTION,
3253 BTFRE_MAX,
3254 };
3255
3256 struct rtw89_btc_ver {
3257 enum rtw89_core_chip_id chip_id;
3258 u32 fw_ver_code;
3259
3260 u8 fcxbtcrpt;
3261 u8 fcxtdma;
3262 u8 fcxslots;
3263 u8 fcxcysta;
3264 u8 fcxstep;
3265 u8 fcxnullsta;
3266 u8 fcxmreg;
3267 u8 fcxgpiodbg;
3268 u8 fcxbtver;
3269 u8 fcxbtscan;
3270 u8 fcxbtafh;
3271 u8 fcxbtdevinfo;
3272 u8 fwlrole;
3273 u8 frptmap;
3274 u8 fcxctrl;
3275 u8 fcxinit;
3276
3277 u8 fwevntrptl;
3278 u8 fwc2hfunc;
3279 u8 drvinfo_type;
3280 u16 info_buf;
3281 u8 max_role_num;
3282 u8 fcxosi;
3283 u8 fcxmlo;
3284 u8 bt_desired;
3285 };
3286
3287 struct rtw89_btc_btf_fwinfo {
3288 u32 cnt_c2h;
3289 u32 cnt_h2c;
3290 u32 cnt_h2c_fail;
3291 u32 event[BTF_EVNT_MAX];
3292
3293 u32 err[BTFRE_MAX];
3294 u32 len_mismch;
3295 u32 fver_mismch;
3296 u32 rpt_en_map;
3297
3298 struct rtw89_btc_ver fw_subver;
3299 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3300 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3301 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3302 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3303 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3304 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3305 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3306 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3307 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3308 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3309 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3310 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3311 };
3312
3313 #define RTW89_BTC_POLICY_MAXLEN 512
3314
3315 struct rtw89_btc {
3316 const struct rtw89_btc_ver *ver;
3317
3318 struct rtw89_btc_cx cx;
3319 struct rtw89_btc_dm dm;
3320 union rtw89_btc_ctrl_list ctrl;
3321 union rtw89_btc_module_info mdinfo;
3322 struct rtw89_btc_btf_fwinfo fwinfo;
3323 struct rtw89_btc_dbg dbg;
3324
3325 struct wiphy_work eapol_notify_work;
3326 struct wiphy_work arp_notify_work;
3327 struct wiphy_work dhcp_notify_work;
3328 struct wiphy_work icmp_notify_work;
3329
3330 u32 bt_req_len;
3331
3332 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3333 u8 ant_type;
3334 u8 btg_pos;
3335 u16 policy_len;
3336 u16 policy_type;
3337 u32 hubmsg_cnt;
3338 bool bt_req_en;
3339 bool update_policy_force;
3340 bool lps;
3341 bool manual_ctrl;
3342 };
3343
3344 enum rtw89_btc_hmsg {
3345 RTW89_BTC_HMSG_TMR_EN = 0x0,
3346 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3347 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3348 RTW89_BTC_HMSG_FW_EV = 0x3,
3349 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3350 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3351
3352 NUM_OF_RTW89_BTC_HMSG,
3353 };
3354
3355 enum rtw89_ra_mode {
3356 RTW89_RA_MODE_CCK = BIT(0),
3357 RTW89_RA_MODE_OFDM = BIT(1),
3358 RTW89_RA_MODE_HT = BIT(2),
3359 RTW89_RA_MODE_VHT = BIT(3),
3360 RTW89_RA_MODE_HE = BIT(4),
3361 RTW89_RA_MODE_EHT = BIT(5),
3362 };
3363
3364 enum rtw89_ra_report_mode {
3365 RTW89_RA_RPT_MODE_LEGACY,
3366 RTW89_RA_RPT_MODE_HT,
3367 RTW89_RA_RPT_MODE_VHT,
3368 RTW89_RA_RPT_MODE_HE,
3369 RTW89_RA_RPT_MODE_EHT,
3370 };
3371
3372 enum rtw89_dig_noisy_level {
3373 RTW89_DIG_NOISY_LEVEL0 = -1,
3374 RTW89_DIG_NOISY_LEVEL1 = 0,
3375 RTW89_DIG_NOISY_LEVEL2 = 1,
3376 RTW89_DIG_NOISY_LEVEL3 = 2,
3377 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3378 };
3379
3380 enum rtw89_gi_ltf {
3381 RTW89_GILTF_LGI_4XHE32 = 0,
3382 RTW89_GILTF_SGI_4XHE08 = 1,
3383 RTW89_GILTF_2XHE16 = 2,
3384 RTW89_GILTF_2XHE08 = 3,
3385 RTW89_GILTF_1XHE16 = 4,
3386 RTW89_GILTF_1XHE08 = 5,
3387 RTW89_GILTF_MAX
3388 };
3389
3390 enum rtw89_rx_frame_type {
3391 RTW89_RX_TYPE_MGNT = 0,
3392 RTW89_RX_TYPE_CTRL = 1,
3393 RTW89_RX_TYPE_DATA = 2,
3394 RTW89_RX_TYPE_RSVD = 3,
3395 };
3396
3397 enum rtw89_efuse_block {
3398 RTW89_EFUSE_BLOCK_SYS = 0,
3399 RTW89_EFUSE_BLOCK_RF = 1,
3400 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3401 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3402 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3403 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3404 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3405 RTW89_EFUSE_BLOCK_ADIE = 7,
3406
3407 RTW89_EFUSE_BLOCK_NUM,
3408 RTW89_EFUSE_BLOCK_IGNORE,
3409 };
3410
3411 struct rtw89_ra_info {
3412 u8 is_dis_ra:1;
3413 /* Bit0 : CCK
3414 * Bit1 : OFDM
3415 * Bit2 : HT
3416 * Bit3 : VHT
3417 * Bit4 : HE
3418 * Bit5 : EHT
3419 */
3420 u8 mode_ctrl:6;
3421 u8 bw_cap:3; /* enum rtw89_bandwidth */
3422 u8 macid;
3423 u8 dcm_cap:1;
3424 u8 er_cap:1;
3425 u8 init_rate_lv:2;
3426 u8 upd_all:1;
3427 u8 en_sgi:1;
3428 u8 ldpc_cap:1;
3429 u8 stbc_cap:1;
3430 u8 ss_num:3;
3431 u8 giltf:3;
3432 u8 upd_bw_nss_mask:1;
3433 u8 upd_mask:1;
3434 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3435 /* BFee CSI */
3436 u8 band_num;
3437 u8 ra_csi_rate_en:1;
3438 u8 fixed_csi_rate_en:1;
3439 u8 cr_tbl_sel:1;
3440 u8 fix_giltf_en:1;
3441 u8 fix_giltf:3;
3442 u8 partial_bw_er:1;
3443 u8 csi_mcs_ss_idx;
3444 u8 csi_mode:2;
3445 u8 csi_gi_ltf:3;
3446 u8 csi_bw:3;
3447 /* after v1 */
3448 u8 is_noisy:1;
3449 u8 psra_en:1;
3450 u8 rsvd0:1;
3451 u8 macid_msb:2;
3452 u8 band:2; /* enum rtw89_band */
3453 u8 is_new_dbgreg:1;
3454 };
3455
3456 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3457 #define RTW89_PPDU_MAC_INFO_SIZE 8
3458 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3459 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3460
3461 struct rtw89_ampdu_params {
3462 u16 agg_num;
3463 bool amsdu;
3464 };
3465
3466 struct rtw89_ra_report {
3467 struct rate_info txrate;
3468 u32 bit_rate;
3469 u16 hw_rate;
3470 bool might_fallback_legacy;
3471 };
3472
3473 DECLARE_EWMA(rssi, 10, 16);
3474 DECLARE_EWMA(evm, 10, 16);
3475 DECLARE_EWMA(snr, 10, 16);
3476
3477 struct rtw89_ba_cam_entry {
3478 struct list_head list;
3479 u8 tid;
3480 };
3481
3482 #define RTW89_MAX_ADDR_CAM_NUM 128
3483 #define RTW89_MAX_BSSID_CAM_NUM 20
3484 #define RTW89_MAX_SEC_CAM_NUM 128
3485 #define RTW89_MAX_BA_CAM_NUM 24
3486 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
3487
3488 struct rtw89_addr_cam_entry {
3489 u8 addr_cam_idx;
3490 u8 offset;
3491 u8 len;
3492 u8 valid : 1;
3493 u8 addr_mask : 6;
3494 u8 wapi : 1;
3495 u8 mask_sel : 2;
3496 u8 bssid_cam_idx: 6;
3497
3498 u8 sec_ent_mode;
3499 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3500 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3501 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3502 };
3503
3504 struct rtw89_bssid_cam_entry {
3505 u8 bssid[ETH_ALEN];
3506 u8 phy_idx;
3507 u8 bssid_cam_idx;
3508 u8 offset;
3509 u8 len;
3510 u8 valid : 1;
3511 u8 num;
3512 };
3513
3514 struct rtw89_sec_cam_entry {
3515 u8 sec_cam_idx;
3516 u8 offset;
3517 u8 len;
3518 u8 type : 4;
3519 u8 ext_key : 1;
3520 u8 spp_mode : 1;
3521 /* 256 bits */
3522 u8 key[32];
3523
3524 struct ieee80211_key_conf *key_conf;
3525 };
3526
3527 struct rtw89_sta_link {
3528 struct rtw89_sta *rtwsta;
3529 struct list_head dlink_schd;
3530 unsigned int link_id;
3531
3532 u8 mac_id;
3533 u8 tx_retry;
3534 bool er_cap;
3535 struct rtw89_vif_link *rtwvif_link;
3536 struct rtw89_ra_info ra;
3537 struct rtw89_ra_report ra_report;
3538 int max_agg_wait;
3539 u8 prev_rssi;
3540 struct ewma_rssi avg_rssi;
3541 struct ewma_rssi rssi[RF_PATH_MAX];
3542 struct ewma_snr avg_snr;
3543 struct ewma_evm evm_1ss;
3544 struct ewma_evm evm_min[RF_PATH_MAX];
3545 struct ewma_evm evm_max[RF_PATH_MAX];
3546 struct ieee80211_rx_status rx_status;
3547 u16 rx_hw_rate;
3548 __le32 htc_template;
3549 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3550 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3551 struct list_head ba_cam_list;
3552
3553 bool use_cfg_mask;
3554 struct cfg80211_bitrate_mask mask;
3555
3556 bool cctl_tx_time;
3557 u32 ampdu_max_time:4;
3558 bool cctl_tx_retry_limit;
3559 u32 data_tx_cnt_lmt:6;
3560 };
3561
3562 struct rtw89_efuse {
3563 bool valid;
3564 bool power_k_valid;
3565 u8 xtal_cap;
3566 u8 addr[ETH_ALEN];
3567 u8 rfe_type;
3568 char country_code[2];
3569 u8 adc_td;
3570 };
3571
3572 struct rtw89_phy_rate_pattern {
3573 u64 ra_mask;
3574 u16 rate;
3575 u8 ra_mode;
3576 bool enable;
3577 };
3578
3579 #define RTW89_TX_DONE 0x0
3580 #define RTW89_TX_RETRY_LIMIT 0x1
3581 #define RTW89_TX_LIFE_TIME 0x2
3582 #define RTW89_TX_MACID_DROP 0x3
3583
3584 #define RTW89_MAX_TX_RPTS 16
3585 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1)
3586 struct rtw89_tx_rpt {
3587 struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
3588 /* protect skbs array access/modification */
3589 spinlock_t skb_lock;
3590 atomic_t sn;
3591 };
3592
3593 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500)
3594 struct rtw89_tx_wait_info {
3595 struct rcu_head rcu_head;
3596 struct list_head list;
3597 struct completion completion;
3598 struct sk_buff *skb;
3599 bool tx_done;
3600 };
3601
3602 struct rtw89_tx_skb_data {
3603 struct rtw89_tx_wait_info __rcu *wait;
3604 u8 tx_rpt_sn;
3605 u8 tx_pkt_cnt_lmt;
3606 u8 hci_priv[];
3607 };
3608
3609 #define RTW89_SCAN_NULL_TIMEOUT 30
3610
3611 #define RTW89_ROC_IDLE_TIMEOUT 500
3612 #define RTW89_ROC_TX_TIMEOUT 30
3613 enum rtw89_roc_state {
3614 RTW89_ROC_IDLE,
3615 RTW89_ROC_NORMAL,
3616 RTW89_ROC_MGMT,
3617 };
3618
3619 struct rtw89_roc {
3620 struct ieee80211_channel chan;
3621 struct wiphy_delayed_work roc_work;
3622 enum ieee80211_roc_type type;
3623 enum rtw89_roc_state state;
3624 int duration;
3625 unsigned int link_id;
3626 };
3627
3628 #define RTW89_P2P_MAX_NOA_NUM 2
3629
3630 struct rtw89_p2p_ie_head {
3631 u8 eid;
3632 u8 ie_len;
3633 u8 oui[3];
3634 u8 oui_type;
3635 } __packed;
3636
3637 struct rtw89_noa_attr_head {
3638 u8 attr_type;
3639 __le16 attr_len;
3640 u8 index;
3641 u8 oppps_ctwindow;
3642 } __packed;
3643
3644 struct rtw89_p2p_noa_ie {
3645 struct rtw89_p2p_ie_head p2p_head;
3646 struct rtw89_noa_attr_head noa_head;
3647 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3648 } __packed;
3649
3650 struct rtw89_p2p_noa_setter {
3651 struct rtw89_p2p_noa_ie ie;
3652 u8 noa_count;
3653 u8 noa_index;
3654 };
3655
3656 struct rtw89_ps_noa_once_handler {
3657 bool in_duration;
3658 u64 tsf_begin;
3659 u64 tsf_end;
3660 struct wiphy_delayed_work set_work;
3661 struct wiphy_delayed_work clr_work;
3662 };
3663
3664 struct rtw89_vif_link {
3665 struct rtw89_vif *rtwvif;
3666 struct list_head dlink_schd;
3667 unsigned int link_id;
3668
3669 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3670 enum rtw89_chanctx_idx chanctx_idx;
3671 enum rtw89_reg_6ghz_power reg_6ghz_power;
3672 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3673
3674 u8 mac_id;
3675 u8 port;
3676 u8 mac_addr[ETH_ALEN];
3677 u8 bssid[ETH_ALEN];
3678 u8 phy_idx;
3679 u8 mac_idx;
3680 u8 net_type;
3681 u8 wifi_role;
3682 u8 self_role;
3683 u8 wmm;
3684 u8 bcn_hit_cond;
3685 u8 bcn_bw_idx;
3686 u8 hit_rule;
3687 u8 last_noa_nr;
3688 u64 sync_bcn_tsf;
3689 u64 last_sync_bcn_tsf;
3690 bool rand_tsf_done;
3691 bool trigger;
3692 bool lsig_txop;
3693 u8 tgt_ind;
3694 u8 frm_tgt_ind;
3695 bool wowlan_pattern;
3696 bool wowlan_uc;
3697 bool wowlan_magic;
3698 bool is_hesta;
3699 bool last_a_ctrl;
3700 bool dyn_tb_bedge_en;
3701 bool pre_pwr_diff_en;
3702 bool pwr_diff_en;
3703 u8 def_tri_idx;
3704 struct wiphy_work update_beacon_work;
3705 struct wiphy_delayed_work csa_beacon_work;
3706 struct rtw89_addr_cam_entry addr_cam;
3707 struct rtw89_bssid_cam_entry bssid_cam;
3708 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3709 struct rtw89_phy_rate_pattern rate_pattern;
3710 struct list_head general_pkt_list;
3711 struct rtw89_p2p_noa_setter p2p_noa;
3712 struct rtw89_ps_noa_once_handler noa_once;
3713 struct wiphy_delayed_work mcc_gc_detect_beacon_work;
3714 u8 detect_bcn_count;
3715 };
3716
3717 enum rtw89_lv1_rcvy_step {
3718 RTW89_LV1_RCVY_STEP_1,
3719 RTW89_LV1_RCVY_STEP_2,
3720 };
3721
3722 struct rtw89_hci_ops {
3723 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3724 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3725 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3726 void (*reset)(struct rtw89_dev *rtwdev);
3727 int (*start)(struct rtw89_dev *rtwdev);
3728 void (*stop)(struct rtw89_dev *rtwdev);
3729 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3730 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3731 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3732
3733 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3734 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3735 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3736 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3737 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3738 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3739
3740 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr);
3741
3742 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3743 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3744 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3745 int (*deinit)(struct rtw89_dev *rtwdev);
3746
3747 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3748 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3749 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3750 int (*napi_poll)(struct napi_struct *napi, int budget);
3751
3752 /* Deal with locks inside recovery_start and recovery_complete callbacks
3753 * by hci instance, and handle things which need to consider under SER.
3754 * e.g. turn on/off interrupts except for the one for halt notification.
3755 */
3756 void (*recovery_start)(struct rtw89_dev *rtwdev);
3757 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3758
3759 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3760 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3761 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3762 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3763 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3764 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3765 void (*disable_intr)(struct rtw89_dev *rtwdev);
3766 void (*enable_intr)(struct rtw89_dev *rtwdev);
3767 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3768 };
3769
3770 struct rtw89_hci_info {
3771 const struct rtw89_hci_ops *ops;
3772 enum rtw89_hci_type type;
3773 enum rtw89_hci_dle_type dle_type;
3774 u32 rpwm_addr;
3775 u32 cpwm_addr;
3776 bool paused;
3777 bool tx_rpt_enabled;
3778 };
3779
3780 struct rtw89_chip_ops {
3781 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3782 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3783 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3784 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3785 void (*bb_reset)(struct rtw89_dev *rtwdev,
3786 enum rtw89_phy_idx phy_idx);
3787 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3788 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3789 u32 addr, u32 mask);
3790 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3791 u32 addr, u32 mask, u32 data);
3792 void (*set_channel)(struct rtw89_dev *rtwdev,
3793 const struct rtw89_chan *chan,
3794 enum rtw89_mac_idx mac_idx,
3795 enum rtw89_phy_idx phy_idx);
3796 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3797 struct rtw89_channel_help_params *p,
3798 const struct rtw89_chan *chan,
3799 enum rtw89_mac_idx mac_idx,
3800 enum rtw89_phy_idx phy_idx);
3801 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3802 enum rtw89_efuse_block block);
3803 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3804 void (*fem_setup)(struct rtw89_dev *rtwdev);
3805 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3806 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3807 void (*rfk_init)(struct rtw89_dev *rtwdev);
3808 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3809 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
3810 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3811 enum rtw89_phy_idx phy_idx,
3812 const struct rtw89_chan *chan);
3813 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
3814 bool start);
3815 void (*rfk_track)(struct rtw89_dev *rtwdev);
3816 void (*power_trim)(struct rtw89_dev *rtwdev);
3817 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3818 const struct rtw89_chan *chan,
3819 enum rtw89_phy_idx phy_idx);
3820 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3821 enum rtw89_phy_idx phy_idx);
3822 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3823 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3824 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev,
3825 const struct rtw89_chan *chan);
3826 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3827 enum rtw89_phy_idx phy_idx);
3828 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3829 struct rtw89_rx_phy_ppdu *phy_ppdu,
3830 struct ieee80211_rx_status *status);
3831 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3832 struct rtw89_rx_phy_ppdu *phy_ppdu);
3833 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev,
3834 struct rtw89_rx_desc_info *desc_info,
3835 struct ieee80211_rx_status *rx_status);
3836 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3837 enum rtw89_phy_idx phy_idx);
3838 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3839 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3840 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3841 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3842 enum rtw89_phy_idx phy_idx);
3843 void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev,
3844 const struct rtw89_chan *chan,
3845 enum rtw89_rf_path path,
3846 enum rtw89_phy_idx phy_idx,
3847 struct rtw89_phy_calc_efuse_gain *calc);
3848 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3849 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3850 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3851 struct rtw89_rx_desc_info *desc_info,
3852 u8 *data, u32 data_offset);
3853 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3854 struct rtw89_tx_desc_info *desc_info,
3855 void *txdesc);
3856 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3857 struct rtw89_tx_desc_info *desc_info,
3858 void *txdesc);
3859 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel);
3860 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3861 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3862 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3863 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3864 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3865 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3866 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3867 struct rtw89_vif_link *rtwvif_link,
3868 struct rtw89_sta_link *rtwsta_link);
3869 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3870 struct rtw89_vif_link *rtwvif_link,
3871 struct rtw89_sta_link *rtwsta_link);
3872 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3873 struct rtw89_vif_link *rtwvif_link,
3874 struct rtw89_sta_link *rtwsta_link);
3875 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3876 struct rtw89_vif_link *rtwvif_link,
3877 struct rtw89_sta_link *rtwsta_link);
3878 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev,
3879 struct rtw89_sta_link *rtwsta_link);
3880 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev,
3881 struct rtw89_vif_link *rtwvif_link,
3882 u16 punctured);
3883 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3884 struct rtw89_vif_link *rtwvif_link,
3885 struct rtw89_sta_link *rtwsta_link);
3886 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3887 struct rtw89_vif_link *rtwvif_link);
3888 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev,
3889 struct rtw89_vif_link *rtwvif_link,
3890 struct rtw89_sta_link *rtwsta_link,
3891 bool valid, struct ieee80211_ampdu_params *params);
3892 int (*h2c_wow_cam_update)(struct rtw89_dev *rtwdev,
3893 struct rtw89_wow_cam_info *cam_info);
3894
3895 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3896 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3897 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3898 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3899 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3900 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3901 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3902 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3903 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3904 };
3905
3906 enum rtw89_dma_ch {
3907 RTW89_DMA_ACH0 = 0,
3908 RTW89_DMA_ACH1 = 1,
3909 RTW89_DMA_ACH2 = 2,
3910 RTW89_DMA_ACH3 = 3,
3911 RTW89_DMA_ACH4 = 4,
3912 RTW89_DMA_ACH5 = 5,
3913 RTW89_DMA_ACH6 = 6,
3914 RTW89_DMA_ACH7 = 7,
3915 RTW89_DMA_B0MG = 8,
3916 RTW89_DMA_B0HI = 9,
3917 RTW89_DMA_B1MG = 10,
3918 RTW89_DMA_B1HI = 11,
3919 RTW89_DMA_H2C = 12,
3920 RTW89_DMA_CH_NUM = 13
3921 };
3922
3923 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3924
3925 enum rtw89_mlo_dbcc_mode {
3926 MLO_DBCC_NOT_SUPPORT = 1,
3927 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3928 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3929 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3930 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3931 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3932 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3933 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3934 DBCC_LEGACY = 0xffffffff,
3935 };
3936
3937 enum rtw89_scan_be_operation {
3938 RTW89_SCAN_OP_STOP,
3939 RTW89_SCAN_OP_START,
3940 RTW89_SCAN_OP_SETPARM,
3941 RTW89_SCAN_OP_GETRPT,
3942 RTW89_SCAN_OP_NUM
3943 };
3944
3945 enum rtw89_scan_be_mode {
3946 RTW89_SCAN_MODE_SA,
3947 RTW89_SCAN_MODE_MACC,
3948 RTW89_SCAN_MODE_NUM
3949 };
3950
3951 enum rtw89_scan_be_opmode {
3952 RTW89_SCAN_OPMODE_NONE,
3953 RTW89_SCAN_OPMODE_TBTT,
3954 RTW89_SCAN_OPMODE_INTV,
3955 RTW89_SCAN_OPMODE_CNT,
3956 RTW89_SCAN_OPMODE_NUM,
3957 };
3958
3959 struct rtw89_scan_option {
3960 bool enable;
3961 bool target_ch_mode;
3962 u8 num_macc_role;
3963 u8 num_opch;
3964 u8 repeat;
3965 u16 norm_pd;
3966 u16 slow_pd;
3967 u16 norm_cy;
3968 u8 opch_end;
3969 u16 delay; /* in unit of ms */
3970 u64 prohib_chan;
3971 enum rtw89_phy_idx band;
3972 enum rtw89_scan_be_operation operation;
3973 enum rtw89_scan_be_mode scan_mode;
3974 enum rtw89_mlo_dbcc_mode mlo_mode;
3975 };
3976
3977 enum rtw89_qta_mode {
3978 RTW89_QTA_SCC,
3979 RTW89_QTA_DBCC,
3980 RTW89_QTA_DLFW,
3981 RTW89_QTA_WOW,
3982
3983 /* keep last */
3984 RTW89_QTA_INVALID,
3985 };
3986
3987 struct rtw89_hfc_ch_cfg {
3988 u16 min;
3989 u16 max;
3990 #define grp_0 0
3991 #define grp_1 1
3992 #define grp_num 2
3993 u8 grp;
3994 };
3995
3996 struct rtw89_hfc_ch_info {
3997 u16 aval;
3998 u16 used;
3999 };
4000
4001 struct rtw89_hfc_pub_cfg {
4002 u16 grp0;
4003 u16 grp1;
4004 u16 pub_max;
4005 u16 wp_thrd;
4006 };
4007
4008 struct rtw89_hfc_pub_info {
4009 u16 g0_used;
4010 u16 g1_used;
4011 u16 g0_aval;
4012 u16 g1_aval;
4013 u16 pub_aval;
4014 u16 wp_aval;
4015 };
4016
4017 struct rtw89_hfc_prec_cfg {
4018 u16 ch011_prec;
4019 u16 h2c_prec;
4020 u16 wp_ch07_prec;
4021 u16 wp_ch811_prec;
4022 u8 ch011_full_cond;
4023 u8 h2c_full_cond;
4024 u8 wp_ch07_full_cond;
4025 u8 wp_ch811_full_cond;
4026 /* for WiFi 7 chips after 8922D */
4027 u16 ch011_full_page;
4028 u16 h2c_full_page;
4029 u16 wp_ch07_full_page;
4030 u16 wp_ch811_full_page;
4031 };
4032
4033 struct rtw89_hfc_param {
4034 bool en;
4035 bool h2c_en;
4036 u8 mode;
4037 const struct rtw89_hfc_ch_cfg *ch_cfg;
4038 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
4039 struct rtw89_hfc_pub_cfg pub_cfg;
4040 struct rtw89_hfc_pub_info pub_info;
4041 struct rtw89_hfc_prec_cfg prec_cfg;
4042 };
4043
4044 struct rtw89_hfc_param_ini {
4045 const struct rtw89_hfc_ch_cfg *ch_cfg;
4046 const struct rtw89_hfc_pub_cfg *pub_cfg;
4047 const struct rtw89_hfc_prec_cfg *prec_cfg;
4048 u8 mode;
4049 };
4050
4051 struct rtw89_dle_size {
4052 u16 pge_size;
4053 u16 lnk_pge_num;
4054 u16 unlnk_pge_num;
4055 /* for WiFi 7 chips below (suffix v1) */
4056 u32 srt_ofst;
4057 };
4058
4059 struct rtw89_wde_quota {
4060 u16 hif;
4061 u16 wcpu;
4062 /* unused dcpu isn't listed */
4063 u16 pkt_in;
4064 u16 cpu_io;
4065 };
4066
4067 struct rtw89_ple_quota {
4068 u16 cma0_tx;
4069 u16 cma1_tx;
4070 u16 c2h;
4071 u16 h2c;
4072 u16 wcpu;
4073 u16 mpdu_proc;
4074 u16 cma0_dma;
4075 u16 cma1_dma;
4076 u16 bb_rpt;
4077 u16 wd_rel;
4078 u16 cpu_io;
4079 u16 tx_rpt;
4080 /* for WiFi 7 chips below (suffix v1) */
4081 u16 h2d;
4082 /* for WiFi 7 chips after 8922D (suffix v2) */
4083 u16 snrpt;
4084 };
4085
4086 struct rtw89_rsvd_quota {
4087 u16 mpdu_info_tbl;
4088 u16 b0_csi;
4089 u16 b1_csi;
4090 u16 b0_lmr;
4091 u16 b1_lmr;
4092 u16 b0_ftm;
4093 u16 b1_ftm;
4094 u16 b0_smr;
4095 u16 b1_smr;
4096 u16 others;
4097 };
4098
4099 struct rtw89_dle_rsvd_size {
4100 u32 srt_ofst;
4101 u32 size;
4102 };
4103
4104 struct rtw89_dle_input {
4105 u32 tx_ampdu_num_b0;
4106 u32 tx_ampdu_num_b1;
4107 u32 tx_amsdu_size; /* unit: KB */
4108 u32 h2c_max_size;
4109 u32 rx_amsdu_size; /* unit: KB */
4110 u32 c2h_max_size;
4111 u32 mpdu_info_tbl_b0;
4112 u32 mpdu_info_tbl_b1;
4113 };
4114
4115 struct rtw89_dle_mem {
4116 enum rtw89_qta_mode mode;
4117 const struct rtw89_dle_size *wde_size;
4118 const struct rtw89_dle_size *ple_size;
4119 const struct rtw89_wde_quota *wde_min_qt;
4120 const struct rtw89_wde_quota *wde_max_qt;
4121 const struct rtw89_ple_quota *ple_min_qt;
4122 const struct rtw89_ple_quota *ple_max_qt;
4123 /* for WiFi 7 chips below */
4124 const struct rtw89_rsvd_quota *rsvd_qt;
4125 const struct rtw89_dle_rsvd_size *rsvd0_size;
4126 const struct rtw89_dle_rsvd_size *rsvd1_size;
4127 /* for WiFi 7 chips after 8922D */
4128 const struct rtw89_dle_input *dle_input;
4129 };
4130
4131 struct rtw89_reg_def {
4132 u32 addr;
4133 u32 mask;
4134 };
4135
4136 struct rtw89_reg2_def {
4137 u32 addr;
4138 u32 data;
4139 };
4140
4141 struct rtw89_reg3_def {
4142 u32 addr;
4143 u32 mask;
4144 u32 data;
4145 };
4146
4147 struct rtw89_reg5_def {
4148 u8 flag; /* recognized by parsers */
4149 u8 path;
4150 u32 addr;
4151 u32 mask;
4152 u32 data;
4153 };
4154
4155 struct rtw89_reg_imr {
4156 u32 addr;
4157 u32 clr;
4158 u32 set;
4159 };
4160
4161 struct rtw89_phy_table {
4162 const struct rtw89_reg2_def *regs;
4163 u32 n_regs;
4164 enum rtw89_rf_path rf_path;
4165 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
4166 enum rtw89_rf_path rf_path, void *data);
4167 };
4168
4169 struct rtw89_txpwr_table {
4170 const void *data;
4171 u32 size;
4172 void (*load)(struct rtw89_dev *rtwdev,
4173 const struct rtw89_txpwr_table *tbl);
4174 };
4175
4176 struct rtw89_txpwr_rule_2ghz {
4177 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4178 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4179 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4180 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4181 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4182 };
4183
4184 struct rtw89_txpwr_rule_5ghz {
4185 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4186 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4187 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4188 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4189 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4190 };
4191
4192 struct rtw89_txpwr_rule_6ghz {
4193 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4194 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4195 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4196 [RTW89_6G_CH_NUM];
4197 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4198 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4199 [RTW89_6G_CH_NUM];
4200 };
4201
4202 struct rtw89_tx_shape {
4203 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4204 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
4205 };
4206
4207 struct rtw89_rfe_parms {
4208 const struct rtw89_txpwr_table *byr_tbl;
4209 struct rtw89_txpwr_rule_2ghz rule_2ghz;
4210 struct rtw89_txpwr_rule_5ghz rule_5ghz;
4211 struct rtw89_txpwr_rule_6ghz rule_6ghz;
4212 struct rtw89_txpwr_rule_2ghz rule_da_2ghz;
4213 struct rtw89_txpwr_rule_5ghz rule_da_5ghz;
4214 struct rtw89_txpwr_rule_6ghz rule_da_6ghz;
4215 struct rtw89_tx_shape tx_shape;
4216 bool has_da;
4217 };
4218
4219 struct rtw89_rfe_parms_conf {
4220 const struct rtw89_rfe_parms *rfe_parms;
4221 u8 rfe_type;
4222 };
4223
4224 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
4225
4226 struct rtw89_txpwr_conf {
4227 u8 rfe_type;
4228 u8 ent_sz;
4229 u32 num_ents;
4230 const void *data;
4231 };
4232
rtw89_txpwr_entcpy(void * entry,const void * cursor,u8 size,const struct rtw89_txpwr_conf * conf)4233 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
4234 const struct rtw89_txpwr_conf *conf)
4235 {
4236 u8 valid_size = min(size, conf->ent_sz);
4237
4238 memcpy(entry, cursor, valid_size);
4239 return true;
4240 }
4241
4242 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
4243
4244 #if defined(__linux__)
4245 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4246 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
4247 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4248 (cursor) += (conf)->ent_sz) \
4249 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4250 #elif defined(__FreeBSD__)
4251 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4252 for (typecheck(const u8 *, cursor), (cursor) = (conf)->data, \
4253 memcpy(&(entry), cursor, \
4254 min_t(u8, sizeof(entry), (conf)->ent_sz)); \
4255 (cursor) < (const u8 *)(conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4256 (cursor) += (conf)->ent_sz) \
4257 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4258 #endif
4259
4260 struct rtw89_txpwr_byrate_data {
4261 struct rtw89_txpwr_conf conf;
4262 struct rtw89_txpwr_table tbl;
4263 };
4264
4265 struct rtw89_txpwr_lmt_2ghz_data {
4266 struct rtw89_txpwr_conf conf;
4267 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4268 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4269 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4270 };
4271
4272 struct rtw89_txpwr_lmt_5ghz_data {
4273 struct rtw89_txpwr_conf conf;
4274 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4275 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4276 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4277 };
4278
4279 struct rtw89_txpwr_lmt_6ghz_data {
4280 struct rtw89_txpwr_conf conf;
4281 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4282 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4283 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4284 [RTW89_6G_CH_NUM];
4285 };
4286
4287 struct rtw89_txpwr_lmt_ru_2ghz_data {
4288 struct rtw89_txpwr_conf conf;
4289 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4290 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4291 };
4292
4293 struct rtw89_txpwr_lmt_ru_5ghz_data {
4294 struct rtw89_txpwr_conf conf;
4295 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4296 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4297 };
4298
4299 struct rtw89_txpwr_lmt_ru_6ghz_data {
4300 struct rtw89_txpwr_conf conf;
4301 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4302 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4303 [RTW89_6G_CH_NUM];
4304 };
4305
4306 struct rtw89_tx_shape_lmt_data {
4307 struct rtw89_txpwr_conf conf;
4308 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4309 };
4310
4311 struct rtw89_tx_shape_lmt_ru_data {
4312 struct rtw89_txpwr_conf conf;
4313 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4314 };
4315
4316 struct rtw89_rfe_data {
4317 struct rtw89_txpwr_byrate_data byrate;
4318 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4319 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4320 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4321 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz;
4322 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz;
4323 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz;
4324 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4325 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4326 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4327 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz;
4328 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz;
4329 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz;
4330 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4331 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4332 struct rtw89_rfe_parms rfe_parms;
4333 };
4334
4335 struct rtw89_page_regs {
4336 u32 hci_fc_ctrl;
4337 u32 ch_page_ctrl;
4338 u32 ach_page_ctrl;
4339 u32 ach_page_info;
4340 u32 pub_page_info3;
4341 u32 pub_page_ctrl1;
4342 u32 pub_page_ctrl2;
4343 u32 pub_page_info1;
4344 u32 pub_page_info2;
4345 u32 wp_page_ctrl1;
4346 u32 wp_page_ctrl2;
4347 u32 wp_page_info1;
4348 };
4349
4350 struct rtw89_imr_info {
4351 u32 wdrls_imr_set;
4352 u32 wsec_imr_reg;
4353 u32 wsec_imr_set;
4354 u32 mpdu_tx_imr_set;
4355 u32 mpdu_rx_imr_set;
4356 u32 sta_sch_imr_set;
4357 u32 txpktctl_imr_b0_reg;
4358 u32 txpktctl_imr_b0_clr;
4359 u32 txpktctl_imr_b0_set;
4360 u32 txpktctl_imr_b1_reg;
4361 u32 txpktctl_imr_b1_clr;
4362 u32 txpktctl_imr_b1_set;
4363 u32 wde_imr_clr;
4364 u32 wde_imr_set;
4365 u32 ple_imr_clr;
4366 u32 ple_imr_set;
4367 u32 host_disp_imr_clr;
4368 u32 host_disp_imr_set;
4369 u32 cpu_disp_imr_clr;
4370 u32 cpu_disp_imr_set;
4371 u32 other_disp_imr_clr;
4372 u32 other_disp_imr_set;
4373 u32 bbrpt_com_err_imr_reg;
4374 u32 bbrpt_chinfo_err_imr_reg;
4375 u32 bbrpt_err_imr_set;
4376 u32 bbrpt_dfs_err_imr_reg;
4377 u32 ptcl_imr_clr;
4378 u32 ptcl_imr_set;
4379 u32 cdma_imr_0_reg;
4380 u32 cdma_imr_0_clr;
4381 u32 cdma_imr_0_set;
4382 u32 cdma_imr_1_reg;
4383 u32 cdma_imr_1_clr;
4384 u32 cdma_imr_1_set;
4385 u32 phy_intf_imr_reg;
4386 u32 phy_intf_imr_clr;
4387 u32 phy_intf_imr_set;
4388 u32 rmac_imr_reg;
4389 u32 rmac_imr_clr;
4390 u32 rmac_imr_set;
4391 u32 tmac_imr_reg;
4392 u32 tmac_imr_clr;
4393 u32 tmac_imr_set;
4394 };
4395
4396 struct rtw89_imr_table {
4397 const struct rtw89_reg_imr *regs;
4398 u32 n_regs;
4399 };
4400
4401 struct rtw89_xtal_info {
4402 u32 xcap_reg;
4403 u32 sc_xo_mask;
4404 u32 sc_xi_mask;
4405 };
4406
4407 struct rtw89_rrsr_cfgs {
4408 struct rtw89_reg3_def ref_rate;
4409 struct rtw89_reg3_def rsc;
4410 };
4411
4412 struct rtw89_rfkill_regs {
4413 struct rtw89_reg3_def pinmux;
4414 struct rtw89_reg3_def mode;
4415 };
4416
4417 struct rtw89_sb_regs {
4418 struct {
4419 u32 cfg;
4420 u32 get;
4421 } n[2];
4422 };
4423
4424 struct rtw89_dig_regs {
4425 u32 seg0_pd_reg;
4426 u32 pd_lower_bound_mask;
4427 u32 pd_spatial_reuse_en;
4428 u32 bmode_pd_reg;
4429 u32 bmode_cca_rssi_limit_en;
4430 u32 bmode_pd_lower_bound_reg;
4431 u32 bmode_rssi_nocca_low_th_mask;
4432 struct rtw89_reg_def p0_lna_init;
4433 struct rtw89_reg_def p1_lna_init;
4434 struct rtw89_reg_def p0_tia_init;
4435 struct rtw89_reg_def p1_tia_init;
4436 struct rtw89_reg_def p0_rxb_init;
4437 struct rtw89_reg_def p1_rxb_init;
4438 struct rtw89_reg_def p0_p20_pagcugc_en;
4439 struct rtw89_reg_def p0_s20_pagcugc_en;
4440 struct rtw89_reg_def p1_p20_pagcugc_en;
4441 struct rtw89_reg_def p1_s20_pagcugc_en;
4442 };
4443
4444 struct rtw89_edcca_regs {
4445 u32 edcca_level;
4446 u32 edcca_mask;
4447 u32 edcca_p_mask;
4448 u32 ppdu_level;
4449 u32 ppdu_mask;
4450 struct rtw89_edcca_p_regs {
4451 u32 rpt_a;
4452 u32 rpt_b;
4453 u32 rpt_sel;
4454 u32 rpt_sel_mask;
4455 } p[RTW89_PHY_NUM];
4456 u32 rpt_sel_be;
4457 u32 rpt_sel_be_mask;
4458 u32 tx_collision_t2r_st;
4459 u32 tx_collision_t2r_st_mask;
4460 };
4461
4462 struct rtw89_phy_ul_tb_info {
4463 bool dyn_tb_tri_en;
4464 u8 def_if_bandedge;
4465 };
4466
4467 struct rtw89_antdiv_stats {
4468 struct ewma_rssi cck_rssi_avg;
4469 struct ewma_rssi ofdm_rssi_avg;
4470 struct ewma_rssi non_legacy_rssi_avg;
4471 u16 pkt_cnt_cck;
4472 u16 pkt_cnt_ofdm;
4473 u16 pkt_cnt_non_legacy;
4474 u32 evm;
4475 };
4476
4477 struct rtw89_antdiv_info {
4478 struct rtw89_antdiv_stats target_stats;
4479 struct rtw89_antdiv_stats main_stats;
4480 struct rtw89_antdiv_stats aux_stats;
4481 u8 training_count;
4482 u8 rssi_pre;
4483 bool get_stats;
4484 };
4485
4486 enum rtw89_chanctx_state {
4487 RTW89_CHANCTX_STATE_MCC_START,
4488 RTW89_CHANCTX_STATE_MCC_STOP,
4489 };
4490
4491 enum rtw89_chanctx_callbacks {
4492 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4493 RTW89_CHANCTX_CALLBACK_RFK,
4494 RTW89_CHANCTX_CALLBACK_TAS,
4495
4496 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4497 };
4498
4499 struct rtw89_chanctx_listener {
4500 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4501 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4502 };
4503
4504 #define RTW89_NHM_TH_NUM 11
4505 #define RTW89_NHM_RPT_NUM 12
4506
4507 struct rtw89_chip_info {
4508 enum rtw89_core_chip_id chip_id;
4509 enum rtw89_chip_gen chip_gen;
4510 const struct rtw89_chip_ops *ops;
4511 const struct rtw89_mac_gen_def *mac_def;
4512 const struct rtw89_phy_gen_def *phy_def;
4513 const char *fw_basename;
4514 u8 fw_format_max;
4515 bool try_ce_fw;
4516 u8 bbmcu_nr;
4517 u32 needed_fw_elms;
4518 const struct rtw89_fw_blacklist *fw_blacklist;
4519 u32 fifo_size;
4520 bool small_fifo_size;
4521 u32 dle_scc_rsvd_size;
4522 u16 max_amsdu_limit;
4523 u16 max_vht_mpdu_cap;
4524 u16 max_eht_mpdu_cap;
4525 u16 max_tx_agg_num;
4526 u16 max_rx_agg_num;
4527 bool dis_2g_40m_ul_ofdma;
4528 u32 rsvd_ple_ofst;
4529 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM];
4530 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM];
4531 u8 wde_qempty_acq_grpnum;
4532 u8 wde_qempty_mgq_grpsel;
4533 u32 rf_base_addr[2];
4534 u8 thermal_th[2];
4535 u8 support_macid_num;
4536 u8 support_link_num;
4537 u8 support_chanctx_num;
4538 u8 support_bands;
4539 u16 support_bandwidths;
4540 bool support_unii4;
4541 bool support_rnr;
4542 bool support_ant_gain;
4543 bool support_tas;
4544 bool support_sar_by_ant;
4545 bool support_noise;
4546 bool ul_tb_waveform_ctrl;
4547 bool ul_tb_pwr_diff;
4548 bool rx_freq_frome_ie;
4549 bool hw_sec_hdr;
4550 bool hw_mgmt_tx_encrypt;
4551 bool hw_tkip_crypto;
4552 bool hw_mlo_bmc_crypto;
4553 u8 rf_path_num;
4554 u8 tx_nss;
4555 u8 rx_nss;
4556 u8 acam_num;
4557 u8 bcam_num;
4558 u8 scam_num;
4559 u8 bacam_num;
4560 u8 bacam_dynamic_num;
4561 enum rtw89_bacam_ver bacam_ver;
4562 u8 addrcam_ver;
4563 u8 ppdu_max_usr;
4564
4565 u8 sec_ctrl_efuse_size;
4566 u32 physical_efuse_size;
4567 u32 logical_efuse_size;
4568 u32 limit_efuse_size;
4569 u32 dav_phy_efuse_size;
4570 u32 dav_log_efuse_size;
4571 u32 phycap_addr;
4572 u32 phycap_size;
4573 const struct rtw89_efuse_block_cfg *efuse_blocks;
4574
4575 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4576 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4577 const struct rtw89_phy_table *bb_table;
4578 const struct rtw89_phy_table *bb_gain_table;
4579 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4580 const struct rtw89_phy_table *nctl_table;
4581 const struct rtw89_rfk_tbl *nctl_post_table;
4582 const struct rtw89_phy_dig_gain_table *dig_table;
4583 const struct rtw89_dig_regs *dig_regs;
4584 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4585
4586 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4587 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4588 const struct rtw89_rfe_parms *dflt_parms;
4589 const struct rtw89_chanctx_listener *chanctx_listener;
4590
4591 u8 txpwr_factor_bb;
4592 u8 txpwr_factor_rf;
4593 u8 txpwr_factor_mac;
4594
4595 u32 para_ver;
4596 u32 wlcx_desired;
4597 u8 scbd;
4598 u8 mailbox;
4599
4600 u8 afh_guard_ch;
4601 const u8 *wl_rssi_thres;
4602 const u8 *bt_rssi_thres;
4603 u8 rssi_tol;
4604
4605 u8 mon_reg_num;
4606 const struct rtw89_btc_fbtc_mreg *mon_reg;
4607 u8 rf_para_ulink_num;
4608 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4609 u8 rf_para_dlink_num;
4610 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4611 u8 ps_mode_supported;
4612 u8 low_power_hci_modes;
4613
4614 u32 h2c_cctl_func_id;
4615 u32 hci_func_en_addr;
4616 u32 h2c_desc_size;
4617 u32 txwd_body_size;
4618 u32 txwd_info_size;
4619 u32 h2c_ctrl_reg;
4620 const u32 *h2c_regs;
4621 struct rtw89_reg_def h2c_counter_reg;
4622 u32 c2h_ctrl_reg;
4623 const u32 *c2h_regs;
4624 struct rtw89_reg_def c2h_counter_reg;
4625 const struct rtw89_page_regs *page_regs;
4626 const u32 *wow_reason_reg;
4627 bool cfo_src_fd;
4628 bool cfo_hw_comp;
4629 const struct rtw89_reg_def *dcfo_comp;
4630 u8 dcfo_comp_sft;
4631 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM];
4632 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM];
4633 const struct rtw89_imr_info *imr_info;
4634 const struct rtw89_imr_table *imr_dmac_table;
4635 const struct rtw89_imr_table *imr_cmac_table;
4636 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4637 struct rtw89_reg_def bss_clr_vld;
4638 u32 bss_clr_map_reg;
4639 const struct rtw89_rfkill_regs *rfkill_init;
4640 struct rtw89_reg_def rfkill_get;
4641 struct rtw89_sb_regs btc_sb;
4642 u32 dma_ch_mask;
4643 const struct rtw89_edcca_regs *edcca_regs;
4644 const struct wiphy_wowlan_support *wowlan_stub;
4645 const struct rtw89_xtal_info *xtal_info;
4646 unsigned long default_quirks; /* bitmap of rtw89_quirks */
4647 };
4648
4649 struct rtw89_chip_variant {
4650 bool no_mcs_12_13: 1;
4651 u32 fw_min_ver_code;
4652 };
4653
4654 union rtw89_bus_info {
4655 const struct rtw89_pci_info *pci;
4656 const struct rtw89_usb_info *usb;
4657 };
4658
4659 struct rtw89_driver_info {
4660 const struct rtw89_chip_info *chip;
4661 const struct rtw89_chip_variant *variant;
4662 const struct dmi_system_id *quirks;
4663 union rtw89_bus_info bus;
4664 };
4665
4666 enum rtw89_hcifc_mode {
4667 RTW89_HCIFC_POH = 0,
4668 RTW89_HCIFC_STF = 1,
4669 RTW89_HCIFC_SDIO = 2,
4670
4671 /* keep last */
4672 RTW89_HCIFC_MODE_INVALID,
4673 };
4674
4675 struct rtw89_dle_info {
4676 const struct rtw89_rsvd_quota *rsvd_qt;
4677 const struct rtw89_dle_input *dle_input;
4678 enum rtw89_qta_mode qta_mode;
4679 u16 ple_pg_size;
4680 u16 ple_free_pg;
4681 u16 c0_rx_qta;
4682 u16 c1_rx_qta;
4683 };
4684
4685 enum rtw89_host_rpr_mode {
4686 RTW89_RPR_MODE_POH = 0,
4687 RTW89_RPR_MODE_STF
4688 };
4689
4690 #define RTW89_COMPLETION_BUF_SIZE 40
4691 #define RTW89_WAIT_COND_IDLE UINT_MAX
4692
4693 struct rtw89_completion_data {
4694 bool err;
4695 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4696 };
4697
4698 struct rtw89_wait_response {
4699 struct rcu_head rcu_head;
4700 struct completion completion;
4701 struct rtw89_completion_data data;
4702 };
4703
4704 struct rtw89_wait_info {
4705 atomic_t cond;
4706 struct rtw89_completion_data data;
4707 struct rtw89_wait_response __rcu *resp;
4708 };
4709
4710 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4711
rtw89_init_wait(struct rtw89_wait_info * wait)4712 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4713 {
4714 rcu_assign_pointer(wait->resp, NULL);
4715 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4716 }
4717
4718 struct rtw89_mac_info {
4719 struct rtw89_dle_info dle_info;
4720 struct rtw89_hfc_param hfc_param;
4721 enum rtw89_qta_mode qta_mode;
4722 u8 rpwm_seq_num;
4723 u8 cpwm_seq_num;
4724
4725 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4726 struct rtw89_wait_info fw_ofld_wait;
4727 /* see RTW89_PS_WAIT_COND series for wait condition */
4728 struct rtw89_wait_info ps_wait;
4729 };
4730
4731 enum rtw89_fwdl_check_type {
4732 RTW89_FWDL_CHECK_FREERTOS_DONE,
4733 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4734 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4735 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4736 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4737 };
4738
4739 enum rtw89_fw_type {
4740 RTW89_FW_NORMAL = 1,
4741 RTW89_FW_WOWLAN = 3,
4742 RTW89_FW_NORMAL_CE = 5,
4743 RTW89_FW_BBMCU0 = 64,
4744 RTW89_FW_BBMCU1 = 65,
4745 RTW89_FW_LOGFMT = 255,
4746 };
4747
4748 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \
4749 RTW89_FW_FEATURE_##_grp##_MIN, \
4750 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \
4751 _features \
4752 __RTW89_FW_FEATURE_##_grp##_E, \
4753 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1
4754
4755 enum rtw89_fw_feature {
4756 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4757 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4758 RTW89_FW_FEATURE_TX_WAKE,
4759 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER,
4760 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0,
4761 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1,
4762 ),
4763 RTW89_FW_FEATURE_NO_PACKET_DROP,
4764 RTW89_FW_FEATURE_NO_DEEP_PS,
4765 RTW89_FW_FEATURE_NO_LPS_PG,
4766 RTW89_FW_FEATURE_BEACON_FILTER,
4767 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4768 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4769 RTW89_FW_FEATURE_WOW_REASON_V1,
4770 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY,
4771 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4772 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1,
4773 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V2,
4774 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V3,
4775 ),
4776 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC,
4777 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V0,
4778 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V1,
4779 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V2,
4780 ),
4781 RTW89_FW_FEATURE_RFK_RXDCK_V0,
4782 RTW89_FW_FEATURE_RFK_IQK_V0,
4783 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX,
4784 RTW89_FW_FEATURE_NOTIFY_AP_INFO,
4785 RTW89_FW_FEATURE_CH_INFO_BE_V0,
4786 RTW89_FW_FEATURE_LPS_CH_INFO,
4787 RTW89_FW_FEATURE_NO_PHYCAP_P1,
4788 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE,
4789 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1,
4790 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP,
4791 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0,
4792 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG,
4793 RTW89_FW_FEATURE_BEACON_TRACKING,
4794 RTW89_FW_FEATURE_ADDR_CAM_V0,
4795 RTW89_FW_FEATURE_SER_L1_BY_EVENT,
4796 RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C,
4797 RTW89_FW_FEATURE_LPS_ML_INFO_V1,
4798
4799 NUM_OF_RTW89_FW_FEATURES,
4800 };
4801
4802 struct rtw89_fw_suit {
4803 enum rtw89_fw_type type;
4804 const u8 *data;
4805 u32 size;
4806 u8 major_ver;
4807 u8 minor_ver;
4808 u8 sub_ver;
4809 u8 sub_idex;
4810 u16 build_year;
4811 u16 build_mon;
4812 u16 build_date;
4813 u16 build_hour;
4814 u16 build_min;
4815 u8 cmd_ver;
4816 u8 hdr_ver;
4817 u32 commitid;
4818 };
4819
4820 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4821 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4822 #define RTW89_FW_SUIT_VER_CODE(s) \
4823 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4824
4825 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4826 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4827 (mfw_hdr)->ver.minor, \
4828 (mfw_hdr)->ver.sub, \
4829 (mfw_hdr)->ver.idx)
4830
4831 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4832 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4833 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4834 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4835 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4836
4837 struct rtw89_fw_req_info {
4838 const struct firmware *firmware;
4839 struct completion completion;
4840 };
4841
4842 struct rtw89_fw_log {
4843 struct rtw89_fw_suit suit;
4844 bool enable;
4845 u32 last_fmt_id;
4846 u32 fmt_count;
4847 const __le32 *fmt_ids;
4848 const char *(*fmts)[];
4849 };
4850
4851 struct rtw89_fw_elm_info {
4852 struct rtw89_phy_table *bb_tbl;
4853 struct rtw89_phy_table *bb_gain;
4854 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4855 struct rtw89_phy_table *rf_nctl;
4856 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4857 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4858 const struct rtw89_regd_data *regd;
4859 const struct rtw89_fw_element_hdr *afe;
4860 const struct rtw89_fw_element_hdr *diag_mac;
4861 const struct rtw89_fw_element_hdr *tx_comp;
4862 };
4863
4864 enum rtw89_fw_mss_dev_type {
4865 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4866 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4867 };
4868
4869 struct rtw89_fw_secure {
4870 bool secure_boot: 1;
4871 bool can_mss_v1: 1;
4872 bool can_mss_v0: 1;
4873 u32 sb_sel_mgn;
4874 u8 mss_dev_type;
4875 u8 mss_cust_idx;
4876 u8 mss_key_num;
4877 u8 mss_idx; /* v0 */
4878 };
4879
4880 struct rtw89_fw_info {
4881 struct rtw89_fw_req_info req;
4882 int fw_format;
4883 u8 h2c_seq;
4884 u8 rec_seq;
4885 u8 h2c_counter;
4886 u8 c2h_counter;
4887 struct rtw89_fw_suit normal;
4888 struct rtw89_fw_suit wowlan;
4889 struct rtw89_fw_suit bbmcu0;
4890 struct rtw89_fw_suit bbmcu1;
4891 struct rtw89_fw_log log;
4892 struct rtw89_fw_elm_info elm_info;
4893 struct rtw89_fw_secure sec;
4894
4895 DECLARE_BITMAP(feature_map, NUM_OF_RTW89_FW_FEATURES);
4896 };
4897
4898 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4899 test_bit(RTW89_FW_FEATURE_ ## _feat, (_fw)->feature_map)
4900
4901 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \
4902 ({ \
4903 unsigned int bit = find_next_bit((_fw)->feature_map, \
4904 NUM_OF_RTW89_FW_FEATURES, \
4905 RTW89_FW_FEATURE_ ## _grp ## _MIN); \
4906 bit <= RTW89_FW_FEATURE_ ## _grp ## _MAX; \
4907 })
4908
4909 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4910 set_bit(_fw_feature, (_fw)->feature_map)
4911
4912 #define RTW89_CLR_FW_FEATURE(_fw_feature, _fw) \
4913 clear_bit(_fw_feature, (_fw)->feature_map)
4914
4915 struct rtw89_cam_info {
4916 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4917 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4918 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4919 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4920 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4921 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4922 };
4923
4924 enum rtw89_sar_sources {
4925 RTW89_SAR_SOURCE_NONE,
4926 RTW89_SAR_SOURCE_COMMON,
4927 RTW89_SAR_SOURCE_ACPI,
4928
4929 RTW89_SAR_SOURCE_NR,
4930 };
4931
4932 enum rtw89_sar_subband {
4933 RTW89_SAR_2GHZ_SUBBAND,
4934 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4935 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4936 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4937 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4938 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4939 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4940 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4941 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4942 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4943
4944 RTW89_SAR_SUBBAND_NR,
4945 };
4946
4947 struct rtw89_sar_cfg_common {
4948 bool set[RTW89_SAR_SUBBAND_NR];
4949 s32 cfg[RTW89_SAR_SUBBAND_NR];
4950 };
4951
4952 enum rtw89_acpi_sar_subband {
4953 RTW89_ACPI_SAR_2GHZ_SUBBAND,
4954 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */
4955 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */
4956 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */
4957 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4958 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4959 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4960 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4961 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4962 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4963 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4964
4965 NUM_OF_RTW89_ACPI_SAR_SUBBAND,
4966 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1,
4967 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1,
4968 };
4969
4970 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */
4971 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX
4972 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN
4973 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6
4974 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1)
4975
4976 struct rtw89_sar_entry_from_acpi {
4977 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4978 };
4979
4980 struct rtw89_sar_table_from_acpi {
4981 /* If this table is active, must fill all fields according to either
4982 * configuration in BIOS or some default values for SAR to work well.
4983 */
4984 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM];
4985 };
4986
4987 struct rtw89_sar_indicator_from_acpi {
4988 bool enable_sync;
4989 unsigned int fields;
4990 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath);
4991
4992 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path.
4993 * Not design with pointers since addresses will be invalid after
4994 * sync content with local container instance.
4995 */
4996 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4997 };
4998
4999 struct rtw89_sar_cfg_acpi {
5000 u8 downgrade_2tx;
5001 unsigned int valid_num;
5002 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL];
5003 struct rtw89_sar_indicator_from_acpi indicator;
5004 };
5005
5006 struct rtw89_sar_info {
5007 /* used to decide how to access SAR cfg union */
5008 enum rtw89_sar_sources src;
5009
5010 /* reserved for different knids of SAR cfg struct.
5011 * supposed that a single cfg struct cannot handle various SAR sources.
5012 */
5013 union {
5014 struct rtw89_sar_cfg_common cfg_common;
5015 struct rtw89_sar_cfg_acpi cfg_acpi;
5016 };
5017 };
5018
5019 enum rtw89_ant_gain_subband {
5020 RTW89_ANT_GAIN_2GHZ_SUBBAND,
5021 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */
5022 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */
5023 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */
5024 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
5025 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
5026 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
5027 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */
5028 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
5029 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
5030 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */
5031
5032 RTW89_ANT_GAIN_SUBBAND_NR,
5033 };
5034
5035 enum rtw89_ant_gain_domain_type {
5036 RTW89_ANT_GAIN_ETSI = 0,
5037
5038 RTW89_ANT_GAIN_DOMAIN_NUM,
5039 };
5040
5041 #define RTW89_ANT_GAIN_CHAIN_NUM 2
5042 struct rtw89_ant_gain_info {
5043 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR];
5044 u32 regd_enabled;
5045 bool block_country;
5046 };
5047
5048 struct rtw89_6ghz_span {
5049 enum rtw89_sar_subband sar_subband_low;
5050 enum rtw89_sar_subband sar_subband_high;
5051 enum rtw89_acpi_sar_subband acpi_sar_subband_low;
5052 enum rtw89_acpi_sar_subband acpi_sar_subband_high;
5053 enum rtw89_ant_gain_subband ant_gain_subband_low;
5054 enum rtw89_ant_gain_subband ant_gain_subband_high;
5055 };
5056
5057 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high)
5058 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high)
5059 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high)
5060
5061 enum rtw89_tas_state {
5062 RTW89_TAS_STATE_DPR_OFF,
5063 RTW89_TAS_STATE_DPR_ON,
5064 RTW89_TAS_STATE_STATIC_SAR,
5065 };
5066
5067 #define RTW89_TAS_TX_RATIO_WINDOW 6
5068 #define RTW89_TAS_TXPWR_WINDOW 180
5069 struct rtw89_tas_info {
5070 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW];
5071 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW];
5072 u8 enabled_countries;
5073 u8 txpwr_head_idx;
5074 u8 txpwr_tail_idx;
5075 u8 tx_ratio_idx;
5076 u16 total_tx_ratio;
5077 u64 total_txpwr;
5078 u64 instant_txpwr;
5079 u32 window_size;
5080 s8 dpr_on_threshold;
5081 s8 dpr_off_threshold;
5082 enum rtw89_tas_state backup_state;
5083 enum rtw89_tas_state state;
5084 bool keep_history;
5085 bool block_regd;
5086 bool enable;
5087 bool pause;
5088 };
5089
5090 struct rtw89_chanctx_cfg {
5091 enum rtw89_chanctx_idx idx;
5092 int ref_count;
5093 };
5094
5095 enum rtw89_chanctx_changes {
5096 RTW89_CHANCTX_REMOTE_STA_CHANGE,
5097 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
5098 RTW89_CHANCTX_P2P_PS_CHANGE,
5099 RTW89_CHANCTX_BT_SLOT_CHANGE,
5100 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
5101
5102 NUM_OF_RTW89_CHANCTX_CHANGES,
5103 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
5104 };
5105
5106 enum rtw89_entity_mode {
5107 RTW89_ENTITY_MODE_SCC_OR_SMLD,
5108 RTW89_ENTITY_MODE_MCC_PREPARE,
5109 RTW89_ENTITY_MODE_MCC,
5110
5111 NUM_OF_RTW89_ENTITY_MODE,
5112 RTW89_ENTITY_MODE_INVALID = -EINVAL,
5113 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
5114 };
5115
5116 #define RTW89_MAX_INTERFACE_NUM 2
5117
5118 /* only valid when running with chanctx_ops */
5119 struct rtw89_entity_mgnt {
5120 struct list_head active_list;
5121 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM];
5122 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM]
5123 [__RTW89_MLD_MAX_LINK_NUM];
5124 };
5125
5126 struct rtw89_chanctx {
5127 struct cfg80211_chan_def chandef;
5128 struct rtw89_chan chan;
5129 struct rtw89_chan_rcd rcd;
5130
5131 /* only assigned when running with chanctx_ops */
5132 struct rtw89_chanctx_cfg *cfg;
5133 };
5134
5135 struct rtw89_edcca_bak {
5136 u8 a;
5137 u8 p;
5138 u8 ppdu;
5139 u8 th_old;
5140 };
5141
5142 enum rtw89_dm_type {
5143 RTW89_DM_DYNAMIC_EDCCA,
5144 RTW89_DM_THERMAL_PROTECT,
5145 RTW89_DM_TAS,
5146 RTW89_DM_MLO,
5147 };
5148
5149 #define RTW89_THERMAL_PROT_LV_MAX 5
5150 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */
5151
5152 struct rtw89_hal {
5153 u32 rx_fltr;
5154 u8 cv;
5155 u8 cid; /* enum rtw89_core_chip_cid */
5156 u8 acv;
5157 u16 aid; /* enum rtw89_core_chip_aid */
5158 u32 antenna_tx;
5159 u32 antenna_rx;
5160 u8 tx_nss;
5161 u8 rx_nss;
5162 bool tx_path_diversity;
5163 bool ant_diversity;
5164 bool ant_diversity_fixed;
5165 bool support_cckpd;
5166 bool support_igi;
5167 bool no_mcs_12_13;
5168 bool no_eht;
5169
5170 atomic_t roc_chanctx_idx;
5171 u8 roc_link_index;
5172
5173 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
5174 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
5175 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
5176 struct cfg80211_chan_def roc_chandef;
5177
5178 bool entity_active[RTW89_PHY_NUM];
5179 bool entity_pause;
5180 enum rtw89_entity_mode entity_mode;
5181 struct rtw89_entity_mgnt entity_mgnt;
5182
5183 enum rtw89_phy_idx entity_force_hw;
5184
5185 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
5186
5187 u8 thermal_prot_th;
5188 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */
5189 };
5190
5191 #define RTW89_MAX_MAC_ID_NUM 128
5192 #define RTW89_MAX_PKT_OFLD_NUM 255
5193
5194 enum rtw89_flags {
5195 RTW89_FLAG_POWERON,
5196 RTW89_FLAG_DMAC_FUNC,
5197 RTW89_FLAG_CMAC0_FUNC,
5198 RTW89_FLAG_CMAC1_FUNC,
5199 RTW89_FLAG_CMAC0_PWR,
5200 RTW89_FLAG_CMAC1_PWR,
5201 RTW89_FLAG_FW_RDY,
5202 RTW89_FLAG_RUNNING,
5203 RTW89_FLAG_PROBE_DONE,
5204 RTW89_FLAG_BFEE_MON,
5205 RTW89_FLAG_BFEE_EN,
5206 RTW89_FLAG_BFEE_TIMER_KEEP,
5207 RTW89_FLAG_NAPI_RUNNING,
5208 RTW89_FLAG_LEISURE_PS,
5209 RTW89_FLAG_LOW_POWER_MODE,
5210 RTW89_FLAG_INACTIVE_PS,
5211 RTW89_FLAG_CRASH_SIMULATING,
5212 RTW89_FLAG_SER_HANDLING,
5213 RTW89_FLAG_WOWLAN,
5214 RTW89_FLAG_FORBIDDEN_TRACK_WORK,
5215 RTW89_FLAG_CHANGING_INTERFACE,
5216 RTW89_FLAG_HW_RFKILL_STATE,
5217 RTW89_FLAG_UNPLUGGED,
5218
5219 NUM_OF_RTW89_FLAGS,
5220 };
5221
5222 enum rtw89_quirks {
5223 RTW89_QUIRK_PCI_BER,
5224 RTW89_QUIRK_THERMAL_PROT_120C,
5225 RTW89_QUIRK_THERMAL_PROT_110C,
5226
5227 NUM_OF_RTW89_QUIRKS,
5228 };
5229
5230 enum rtw89_custid {
5231 RTW89_CUSTID_NONE = 0,
5232 RTW89_CUSTID_HP = 1,
5233 RTW89_CUSTID_ASUS = 2,
5234 RTW89_CUSTID_ACER = 3,
5235 RTW89_CUSTID_LENOVO = 4,
5236 RTW89_CUSTID_NEC = 5,
5237 RTW89_CUSTID_AMD = 6,
5238 RTW89_CUSTID_FUJITSU = 7,
5239 RTW89_CUSTID_DELL = 8,
5240 };
5241
5242 enum rtw89_pkt_drop_sel {
5243 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
5244 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
5245 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
5246 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
5247 RTW89_PKT_DROP_SEL_MACID_ALL,
5248 RTW89_PKT_DROP_SEL_MG0_ONCE,
5249 RTW89_PKT_DROP_SEL_HIQ_ONCE,
5250 RTW89_PKT_DROP_SEL_HIQ_PORT,
5251 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
5252 RTW89_PKT_DROP_SEL_BAND,
5253 RTW89_PKT_DROP_SEL_BAND_ONCE,
5254 RTW89_PKT_DROP_SEL_REL_MACID,
5255 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
5256 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
5257 };
5258
5259 struct rtw89_pkt_drop_params {
5260 enum rtw89_pkt_drop_sel sel;
5261 enum rtw89_mac_idx mac_band;
5262 u8 macid;
5263 u8 port;
5264 u8 mbssid;
5265 bool tf_trs;
5266 u32 macid_band_sel[4];
5267 };
5268
5269 struct rtw89_pkt_stat {
5270 u16 beacon_nr;
5271 u8 beacon_rate;
5272 u32 beacon_len;
5273 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
5274 };
5275
5276 #define RTW89_BCN_TRACK_STAT_NR 32
5277 #define RTW89_BCN_TRACK_SCALE_FACTOR 10
5278 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6
5279 #define RTW89_BCN_TRACK_BIN_WIDTH 5
5280 #define RTW89_BCN_TRACK_TARGET_BCN 80
5281
5282 struct rtw89_beacon_dist {
5283 u16 min;
5284 u16 max;
5285 u16 outlier_count;
5286 u16 lower_bound;
5287 u16 upper_bound;
5288 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM];
5289 };
5290
5291 struct rtw89_beacon_stat {
5292 u8 num;
5293 u8 wp;
5294 u16 tbtt_tu_min;
5295 u16 tbtt_tu_max;
5296 u16 drift[RTW89_BCN_TRACK_STAT_NR];
5297 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR];
5298 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR];
5299 struct rtw89_beacon_dist bcn_dist;
5300 };
5301
5302 DECLARE_EWMA(thermal, 4, 4);
5303
5304 struct rtw89_phy_stat {
5305 struct ewma_thermal avg_thermal[RF_PATH_MAX];
5306 u8 last_thermal_max;
5307 struct ewma_rssi bcn_rssi;
5308 struct rtw89_pkt_stat cur_pkt_stat;
5309 struct rtw89_pkt_stat last_pkt_stat;
5310 struct rtw89_beacon_stat bcn_stat;
5311 };
5312
5313 enum rtw89_rfk_report_state {
5314 RTW89_RFK_STATE_START = 0x0,
5315 RTW89_RFK_STATE_OK = 0x1,
5316 RTW89_RFK_STATE_FAIL = 0x2,
5317 RTW89_RFK_STATE_TIMEOUT = 0x3,
5318 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
5319 };
5320
5321 struct rtw89_rfk_wait_info {
5322 struct completion completion;
5323 ktime_t start_time;
5324 enum rtw89_rfk_report_state state;
5325 u8 version;
5326 };
5327
5328 #define RTW89_DACK_PATH_NR 2
5329 #define RTW89_DACK_IDX_NR 2
5330 #define RTW89_DACK_MSBK_NR 16
5331 struct rtw89_dack_info {
5332 bool dack_done;
5333 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
5334 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5335 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5336 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5337 u32 dack_cnt;
5338 bool addck_timeout[RTW89_DACK_PATH_NR];
5339 bool dadck_timeout[RTW89_DACK_PATH_NR];
5340 bool msbk_timeout[RTW89_DACK_PATH_NR];
5341 };
5342
5343 enum rtw89_rfk_chs_nrs {
5344 __RTW89_RFK_CHS_NR_V0 = 2,
5345 __RTW89_RFK_CHS_NR_V1 = 3,
5346
5347 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
5348 };
5349
5350 struct rtw89_rfk_mcc_info_data {
5351 u8 ch[RTW89_RFK_CHS_NR];
5352 u8 band[RTW89_RFK_CHS_NR];
5353 u8 bw[RTW89_RFK_CHS_NR];
5354 u32 rf18[RTW89_RFK_CHS_NR];
5355 u8 table_idx;
5356 };
5357
5358 struct rtw89_rfk_mcc_info {
5359 struct rtw89_rfk_mcc_info_data data[2];
5360 };
5361
5362 #define RTW89_IQK_CHS_NR 2
5363 #define RTW89_IQK_PATH_NR 4
5364
5365 struct rtw89_lck_info {
5366 u8 thermal[RF_PATH_MAX];
5367 };
5368
5369 struct rtw89_rx_dck_info {
5370 u8 thermal[RF_PATH_MAX];
5371 };
5372
5373 struct rtw89_iqk_info {
5374 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5375 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5376 bool lok_fail[RTW89_IQK_PATH_NR];
5377 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5378 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5379 u32 iqk_fail_cnt;
5380 bool is_iqk_init;
5381 u32 iqk_channel[RTW89_IQK_CHS_NR];
5382 u8 iqk_band[RTW89_IQK_PATH_NR];
5383 u8 iqk_ch[RTW89_IQK_PATH_NR];
5384 u8 iqk_bw[RTW89_IQK_PATH_NR];
5385 u8 iqk_times;
5386 u8 version;
5387 u32 nb_txcfir[RTW89_IQK_PATH_NR];
5388 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
5389 u32 bp_txkresult[RTW89_IQK_PATH_NR];
5390 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
5391 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
5392 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
5393 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
5394 bool is_nbiqk;
5395 bool iqk_fft_en;
5396 bool iqk_xym_en;
5397 bool iqk_sram_en;
5398 bool iqk_cfir_en;
5399 u32 syn1to2;
5400 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5401 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
5402 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5403 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5404 };
5405
5406 #define RTW89_DPK_RF_PATH 2
5407 #define RTW89_DPK_AVG_THERMAL_NUM 8
5408 #define RTW89_DPK_BKUP_NUM 2
5409 struct rtw89_dpk_bkup_para {
5410 enum rtw89_band band;
5411 enum rtw89_bandwidth bw;
5412 u8 ch;
5413 u8 path_ok;
5414 u8 mdpd_en;
5415 u8 txagc_dpk;
5416 u8 ther_dpk;
5417 u8 gs;
5418 u16 pwsf;
5419 };
5420
5421 struct rtw89_dpk_info {
5422 bool is_dpk_enable;
5423 bool is_dpk_reload_en;
5424 u8 dpk_gs[RTW89_PHY_NUM];
5425 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5426 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5427 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5428 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5429 u8 cur_idx[RTW89_DPK_RF_PATH];
5430 u8 cur_k_set;
5431 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5432 u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
5433 u32 dpk_order[RTW89_DPK_RF_PATH];
5434 };
5435
5436 struct rtw89_fem_info {
5437 bool elna_2g;
5438 bool elna_5g;
5439 bool epa_2g;
5440 bool epa_5g;
5441 bool epa_6g;
5442 };
5443
5444 struct rtw89_phy_ch_info {
5445 u8 rssi_min;
5446 u16 rssi_min_macid;
5447 u8 pre_rssi_min;
5448 u8 rssi_max;
5449 u16 rssi_max_macid;
5450 u8 rxsc_160;
5451 u8 rxsc_80;
5452 u8 rxsc_40;
5453 u8 rxsc_20;
5454 u8 rxsc_l;
5455 u8 is_noisy;
5456 };
5457
5458 struct rtw89_agc_gaincode_set {
5459 u8 lna_idx;
5460 u8 tia_idx;
5461 u8 rxb_idx;
5462 };
5463
5464 #define IGI_RSSI_TH_NUM 5
5465 #define FA_TH_NUM 4
5466 #define TIA_LNA_OP1DB_NUM 8
5467 #define LNA_GAIN_NUM 7
5468 #define TIA_GAIN_NUM 2
5469 struct rtw89_dig_info {
5470 struct rtw89_agc_gaincode_set cur_gaincode;
5471 bool force_gaincode_idx_en;
5472 struct rtw89_agc_gaincode_set force_gaincode;
5473 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
5474 u16 fa_th[FA_TH_NUM];
5475 u8 igi_rssi;
5476 u8 igi_fa_rssi;
5477 u8 fa_rssi_ofst;
5478 u8 dyn_igi_max;
5479 u8 dyn_igi_min;
5480 bool dyn_pd_th_en;
5481 u8 dyn_pd_th_max;
5482 u8 pd_low_th_ofst;
5483 u8 ib_pbk;
5484 s8 ib_pkpwr;
5485 s8 lna_gain_a[LNA_GAIN_NUM];
5486 s8 lna_gain_g[LNA_GAIN_NUM];
5487 s8 *lna_gain;
5488 s8 tia_gain_a[TIA_GAIN_NUM];
5489 s8 tia_gain_g[TIA_GAIN_NUM];
5490 s8 *tia_gain;
5491 u32 bak_dig;
5492 bool is_linked_pre;
5493 bool bypass_dig;
5494 bool pause_dig;
5495 };
5496
5497 enum rtw89_multi_cfo_mode {
5498 RTW89_PKT_BASED_AVG_MODE = 0,
5499 RTW89_ENTRY_BASED_AVG_MODE = 1,
5500 RTW89_TP_BASED_AVG_MODE = 2,
5501 };
5502
5503 enum rtw89_phy_cfo_status {
5504 RTW89_PHY_DCFO_STATE_NORMAL = 0,
5505 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
5506 RTW89_PHY_DCFO_STATE_HOLD = 2,
5507 RTW89_PHY_DCFO_STATE_MAX
5508 };
5509
5510 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
5511 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
5512 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
5513 };
5514
5515 struct rtw89_cfo_tracking_info {
5516 u16 cfo_timer_ms;
5517 bool cfo_trig_by_timer_en;
5518 enum rtw89_phy_cfo_status phy_cfo_status;
5519 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
5520 u8 phy_cfo_trk_cnt;
5521 bool is_adjust;
5522 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
5523 bool apply_compensation;
5524 u8 crystal_cap;
5525 u8 crystal_cap_default;
5526 u8 def_x_cap;
5527 s8 x_cap_ofst;
5528 u32 sta_cfo_tolerance;
5529 s32 cfo_tail[CFO_TRACK_MAX_USER];
5530 u16 cfo_cnt[CFO_TRACK_MAX_USER];
5531 s32 cfo_avg_pre;
5532 s32 cfo_avg[CFO_TRACK_MAX_USER];
5533 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
5534 s32 dcfo_avg;
5535 s32 dcfo_avg_pre;
5536 u32 packet_count;
5537 u32 packet_count_pre;
5538 s32 residual_cfo_acc;
5539 u8 phy_cfotrk_state;
5540 u8 phy_cfotrk_cnt;
5541 bool divergence_lock_en;
5542 u8 x_cap_lb;
5543 u8 x_cap_ub;
5544 u8 lock_cnt;
5545 };
5546
5547 enum rtw89_tssi_mode {
5548 RTW89_TSSI_NORMAL = 0,
5549 RTW89_TSSI_SCAN = 1,
5550 };
5551
5552 enum rtw89_tssi_alimk_band {
5553 TSSI_ALIMK_2G = 0,
5554 TSSI_ALIMK_5GL,
5555 TSSI_ALIMK_5GM,
5556 TSSI_ALIMK_5GH,
5557 TSSI_ALIMK_MAX
5558 };
5559
5560 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
5561 #define TSSI_TRIM_CH_GROUP_NUM 8
5562 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
5563
5564 #define TSSI_CCK_CH_GROUP_NUM 6
5565 #define TSSI_MCS_2G_CH_GROUP_NUM 5
5566 #define TSSI_MCS_5G_CH_GROUP_NUM 14
5567 #define TSSI_MCS_6G_CH_GROUP_NUM 32
5568 #define TSSI_MCS_CH_GROUP_NUM \
5569 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5570 #define TSSI_MAX_CH_NUM 67
5571 #define TSSI_ALIMK_VALUE_NUM 8
5572
5573 struct rtw89_tssi_info {
5574 u8 thermal[RF_PATH_MAX];
5575 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5576 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5577 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5578 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5579 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5580 s8 extra_ofst[RF_PATH_MAX];
5581 bool tssi_tracking_check[RF_PATH_MAX];
5582 u8 default_txagc_offset[RF_PATH_MAX];
5583 u32 base_thermal[RF_PATH_MAX];
5584 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5585 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5586 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5587 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5588 u64 tssi_alimk_time;
5589 };
5590
5591 struct rtw89_power_trim_info {
5592 bool pg_thermal_trim;
5593 bool pg_pa_bias_trim;
5594 u8 thermal_trim[RF_PATH_MAX];
5595 u8 pa_bias_trim[RF_PATH_MAX];
5596 u8 pad_bias_trim[RF_PATH_MAX];
5597 };
5598
5599 enum rtw89_regd_func {
5600 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */
5601 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */
5602
5603 NUM_OF_RTW89_REGD_FUNC,
5604 };
5605
5606 struct rtw89_regd {
5607 char alpha2[3];
5608 u8 txpwr_regd[RTW89_BAND_NUM];
5609 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC);
5610 };
5611
5612 struct rtw89_regd_data {
5613 unsigned int nr;
5614 struct rtw89_regd map[] __counted_by(nr);
5615 };
5616
5617 struct rtw89_regd_ctrl {
5618 unsigned int nr;
5619 const struct rtw89_regd *map;
5620 };
5621
5622 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5623 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5624 #define RTW89_5GHZ_UNII4_START_INDEX 25
5625
5626 struct rtw89_regulatory_info {
5627 struct rtw89_regd_ctrl ctrl;
5628 const struct rtw89_regd *regd;
5629 bool programmed;
5630
5631 enum rtw89_reg_6ghz_power reg_6ghz_power;
5632 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5633 bool txpwr_uk_follow_etsi;
5634
5635 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5636 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5637 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5638 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM);
5639 };
5640
5641 enum rtw89_ifs_clm_application {
5642 RTW89_IFS_CLM_INIT = 0,
5643 RTW89_IFS_CLM_BACKGROUND = 1,
5644 RTW89_IFS_CLM_ACS = 2,
5645 RTW89_IFS_CLM_DIG = 3,
5646 RTW89_IFS_CLM_TDMA_DIG = 4,
5647 RTW89_IFS_CLM_DBG = 5,
5648 RTW89_IFS_CLM_DBG_MANUAL = 6
5649 };
5650
5651 enum rtw89_env_racing_lv {
5652 RTW89_RAC_RELEASE = 0,
5653 RTW89_RAC_LV_1 = 1,
5654 RTW89_RAC_LV_2 = 2,
5655 RTW89_RAC_LV_3 = 3,
5656 RTW89_RAC_LV_4 = 4,
5657 RTW89_RAC_MAX_NUM = 5
5658 };
5659
5660 struct rtw89_ccx_para_info {
5661 enum rtw89_env_racing_lv rac_lv;
5662 u16 mntr_time;
5663 bool nhm_incld_cca;
5664 u8 nhm_manual_th_ofst;
5665 u8 nhm_manual_th0;
5666 enum rtw89_ifs_clm_application ifs_clm_app;
5667 u32 ifs_clm_manual_th_times;
5668 u32 ifs_clm_manual_th0;
5669 u8 fahm_manual_th_ofst;
5670 u8 fahm_manual_th0;
5671 u8 fahm_numer_opt;
5672 u8 fahm_denom_opt;
5673 };
5674
5675 enum rtw89_ccx_edcca_opt_sc_idx {
5676 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5677 RTW89_CCX_EDCCA_SEG0_S1 = 1,
5678 RTW89_CCX_EDCCA_SEG0_S2 = 2,
5679 RTW89_CCX_EDCCA_SEG0_S3 = 3,
5680 RTW89_CCX_EDCCA_SEG1_P0 = 4,
5681 RTW89_CCX_EDCCA_SEG1_S1 = 5,
5682 RTW89_CCX_EDCCA_SEG1_S2 = 6,
5683 RTW89_CCX_EDCCA_SEG1_S3 = 7
5684 };
5685
5686 enum rtw89_ccx_edcca_opt_bw_idx {
5687 RTW89_CCX_EDCCA_BW20_0 = 0,
5688 RTW89_CCX_EDCCA_BW20_1 = 1,
5689 RTW89_CCX_EDCCA_BW20_2 = 2,
5690 RTW89_CCX_EDCCA_BW20_3 = 3,
5691 RTW89_CCX_EDCCA_BW20_4 = 4,
5692 RTW89_CCX_EDCCA_BW20_5 = 5,
5693 RTW89_CCX_EDCCA_BW20_6 = 6,
5694 RTW89_CCX_EDCCA_BW20_7 = 7
5695 };
5696
5697 struct rtw89_nhm_report {
5698 struct list_head list;
5699 struct ieee80211_channel *channel;
5700 u8 noise;
5701 };
5702
5703 #define RTW89_FAHM_TH_NUM 11
5704 #define RTW89_FAHM_RPT_NUM 12
5705 #define RTW89_IFS_CLM_NUM 4
5706 struct rtw89_env_monitor_info {
5707 u8 ccx_watchdog_result;
5708 bool ccx_ongoing;
5709 u8 ccx_rac_lv;
5710 bool ccx_manual_ctrl;
5711 u16 ifs_clm_mntr_time;
5712 enum rtw89_ifs_clm_application ifs_clm_app;
5713 u16 ccx_period;
5714 u8 ccx_unit_idx;
5715 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5716 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5717 u16 ifs_clm_tx;
5718 u16 ifs_clm_edcca_excl_cca;
5719 u16 ifs_clm_ofdmfa;
5720 u16 ifs_clm_ofdmcca_excl_fa;
5721 u16 ifs_clm_cckfa;
5722 u16 ifs_clm_cckcca_excl_fa;
5723 u16 ifs_clm_total_ifs;
5724 u16 ifs_clm_his[RTW89_IFS_CLM_NUM];
5725 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5726 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5727 u8 ifs_clm_tx_ratio;
5728 u8 ifs_clm_edcca_excl_cca_ratio;
5729 u8 ifs_clm_cck_fa_ratio;
5730 u8 ifs_clm_ofdm_fa_ratio;
5731 u8 ifs_clm_cck_cca_excl_fa_ratio;
5732 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5733 u16 ifs_clm_cck_fa_permil;
5734 u16 ifs_clm_ofdm_fa_permil;
5735 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5736 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5737 bool nhm_include_cca;
5738 u32 nhm_sum;
5739 u32 nhm_mntr_time;
5740 u16 nhm_result[RTW89_NHM_RPT_NUM];
5741 u8 nhm_th[RTW89_NHM_RPT_NUM];
5742 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM];
5743 struct list_head nhm_rpt_list;
5744 };
5745
5746 enum rtw89_ser_rcvy_step {
5747 RTW89_SER_DRV_STOP_TX,
5748 RTW89_SER_DRV_STOP_RX,
5749 RTW89_SER_DRV_STOP_RUN,
5750 RTW89_SER_HAL_STOP_DMA,
5751 RTW89_SER_SUPPRESS_LOG,
5752 RTW89_NUM_OF_SER_FLAGS
5753 };
5754
5755 struct rtw89_ser {
5756 u8 state;
5757 u8 alarm_event;
5758 bool prehandle_l1;
5759
5760 struct work_struct ser_hdl_work;
5761 struct delayed_work ser_alarm_work;
5762 const struct state_ent *st_tbl;
5763 const struct event_ent *ev_tbl;
5764 struct list_head msg_q;
5765 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5766 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5767 };
5768
5769 enum rtw89_mac_ax_ps_mode {
5770 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5771 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5772 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5773 RTW89_MAC_AX_PS_MODE_MAX = 3,
5774 };
5775
5776 enum rtw89_last_rpwm_mode {
5777 RTW89_LAST_RPWM_PS = 0x0,
5778 RTW89_LAST_RPWM_ACTIVE = 0x6,
5779 };
5780
5781 struct rtw89_lps_parm {
5782 u8 macid;
5783 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5784 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5785 };
5786
5787 struct rtw89_ppdu_sts_info {
5788 struct sk_buff_head rx_queue[RTW89_PHY_NUM];
5789 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM];
5790 };
5791
5792 struct rtw89_early_h2c {
5793 struct list_head list;
5794 u8 *h2c;
5795 u16 h2c_len;
5796 };
5797
5798 struct rtw89_hw_scan_extra_op {
5799 bool set;
5800 u8 macid;
5801 u8 port;
5802 struct rtw89_chan chan;
5803 struct rtw89_vif_link *rtwvif_link;
5804 };
5805
5806 struct rtw89_hw_scan_info {
5807 struct rtw89_vif_link *scanning_vif;
5808 struct list_head pkt_list[NUM_NL80211_BANDS];
5809 struct list_head chan_list;
5810 struct rtw89_chan op_chan;
5811 struct rtw89_hw_scan_extra_op extra_op;
5812 bool connected;
5813 bool abort;
5814 u16 delay; /* in unit of ms */
5815 u8 seq: 2;
5816 };
5817
5818 enum rtw89_phy_bb_gain_band {
5819 RTW89_BB_GAIN_BAND_2G = 0,
5820 RTW89_BB_GAIN_BAND_5G_L = 1,
5821 RTW89_BB_GAIN_BAND_5G_M = 2,
5822 RTW89_BB_GAIN_BAND_5G_H = 3,
5823 RTW89_BB_GAIN_BAND_6G_L = 4,
5824 RTW89_BB_GAIN_BAND_6G_M = 5,
5825 RTW89_BB_GAIN_BAND_6G_H = 6,
5826 RTW89_BB_GAIN_BAND_6G_UH = 7,
5827
5828 RTW89_BB_GAIN_BAND_NR,
5829 };
5830
5831 enum rtw89_phy_gain_band_be {
5832 RTW89_BB_GAIN_BAND_2G_BE = 0,
5833 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5834 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5835 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5836 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5837 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5838 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5839 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5840 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5841 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5842 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5843 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5844
5845 RTW89_BB_GAIN_BAND_NR_BE,
5846 };
5847
5848 enum rtw89_phy_bb_bw_be {
5849 RTW89_BB_BW_20_40 = 0,
5850 RTW89_BB_BW_80_160_320 = 1,
5851
5852 RTW89_BB_BW_NR_BE,
5853 };
5854
5855 enum rtw89_bw20_sc {
5856 RTW89_BW20_SC_20M = 1,
5857 RTW89_BW20_SC_40M = 2,
5858 RTW89_BW20_SC_80M = 4,
5859 RTW89_BW20_SC_160M = 8,
5860 RTW89_BW20_SC_320M = 16,
5861 };
5862
5863 enum rtw89_cmac_table_bw {
5864 RTW89_CMAC_BW_20M = 0,
5865 RTW89_CMAC_BW_40M = 1,
5866 RTW89_CMAC_BW_80M = 2,
5867 RTW89_CMAC_BW_160M = 3,
5868 RTW89_CMAC_BW_320M = 4,
5869
5870 RTW89_CMAC_BW_NR,
5871 };
5872
5873 enum rtw89_phy_bb_rxsc_num {
5874 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5875 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5876 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5877 };
5878
5879 struct rtw89_phy_bb_gain_info {
5880 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5881 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5882 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5883 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5884 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5885 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5886 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5887 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5888 [RTW89_BB_RXSC_NUM_40];
5889 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5890 [RTW89_BB_RXSC_NUM_80];
5891 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5892 [RTW89_BB_RXSC_NUM_160];
5893 };
5894
5895 struct rtw89_phy_bb_gain_info_be {
5896 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5897 [LNA_GAIN_NUM];
5898 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5899 [TIA_GAIN_NUM];
5900 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5901 [RF_PATH_MAX][LNA_GAIN_NUM];
5902 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5903 [RF_PATH_MAX][LNA_GAIN_NUM];
5904 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5905 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5906 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5907 [RTW89_BW20_SC_20M];
5908 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5909 [RTW89_BW20_SC_40M];
5910 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5911 [RTW89_BW20_SC_80M];
5912 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5913 [RTW89_BW20_SC_160M];
5914 };
5915
5916 struct rtw89_phy_efuse_gain {
5917 bool offset_valid;
5918 bool comp_valid;
5919 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5920 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */
5921 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */
5922 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5923 };
5924
5925 struct rtw89_phy_calc_efuse_gain {
5926 s8 cck_mean_gain_bias;
5927 s8 cck_rpl_ofst;
5928 s8 rssi_ofst;
5929 };
5930
5931 #define RTW89_MAX_PATTERN_NUM 18
5932 #define RTW89_MAX_PATTERN_MASK_SIZE 4
5933 #define RTW89_MAX_PATTERN_SIZE 128
5934
5935 struct rtw89_wow_cam_info {
5936 bool r_w;
5937 u8 idx;
5938 __le32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5939 u16 crc;
5940 bool negative_pattern_match;
5941 bool skip_mac_hdr;
5942 bool uc;
5943 bool mc;
5944 bool bc;
5945 bool valid;
5946 };
5947
5948 struct rtw89_wow_key_info {
5949 u8 ptk_tx_iv[8];
5950 u8 valid_check;
5951 u8 symbol_check_en;
5952 u8 gtk_keyidx;
5953 u8 rsvd[5];
5954 u8 ptk_rx_iv[8];
5955 u8 gtk_rx_iv[4][8];
5956 } __packed;
5957
5958 struct rtw89_wow_gtk_info {
5959 u8 kck[32];
5960 u8 kek[32];
5961 u8 tk1[16];
5962 u8 rxmickey[8];
5963 u8 txmickey[8];
5964 __le32 igtk_keyid;
5965 __le64 ipn;
5966 u8 igtk[2][32];
5967 u8 psk[32];
5968 } __packed;
5969
5970 struct rtw89_wow_aoac_report {
5971 u8 rpt_ver;
5972 u8 sec_type;
5973 u8 key_idx;
5974 u8 pattern_idx;
5975 u8 rekey_ok;
5976 u8 ptk_tx_iv[8];
5977 u8 eapol_key_replay_count[8];
5978 u8 gtk[32];
5979 u8 ptk_rx_iv[8];
5980 u8 gtk_rx_iv[4][8];
5981 u64 igtk_key_id;
5982 u64 igtk_ipn;
5983 u8 igtk[32];
5984 u8 csa_pri_ch;
5985 u8 csa_bw;
5986 u8 csa_ch_offset;
5987 u8 csa_chsw_failed;
5988 u8 csa_ch_band;
5989 };
5990
5991 struct rtw89_wow_param {
5992 struct rtw89_vif_link *rtwvif_link;
5993 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5994 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5995 struct rtw89_wow_key_info key_info;
5996 struct rtw89_wow_gtk_info gtk_info;
5997 struct rtw89_wow_aoac_report aoac_rpt;
5998 u8 pattern_cnt;
5999 u8 ptk_alg;
6000 u8 gtk_alg;
6001 u8 ptk_keyidx;
6002 u8 akm;
6003
6004 /* see RTW89_WOW_WAIT_COND series for wait condition */
6005 struct rtw89_wait_info wait;
6006
6007 bool pno_inited;
6008 struct list_head pno_pkt_list;
6009 struct cfg80211_sched_scan_request *nd_config;
6010 };
6011
6012 struct rtw89_mcc_limit {
6013 bool enable;
6014 u16 max_tob; /* TU; max time offset behind */
6015 u16 max_toa; /* TU; max time offset ahead */
6016 u16 max_dur; /* TU */
6017 };
6018
6019 struct rtw89_mcc_policy {
6020 u8 c2h_rpt;
6021 u8 tx_null_early;
6022 u8 dis_tx_null;
6023 u8 in_curr_ch;
6024 u8 dis_sw_retry;
6025 u8 sw_retry_count;
6026 };
6027
6028 struct rtw89_mcc_role {
6029 struct rtw89_vif_link *rtwvif_link;
6030 struct rtw89_mcc_policy policy;
6031 struct rtw89_mcc_limit limit;
6032
6033 const struct rtw89_mcc_courtesy_cfg *crtz;
6034
6035 /* only valid when running with FW MRC mechanism */
6036 u8 slot_idx;
6037
6038 /* byte-array in LE order for FW */
6039 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
6040 u8 probe_count;
6041
6042 u16 duration; /* TU */
6043 u16 beacon_interval; /* TU */
6044 bool is_2ghz;
6045 bool is_go;
6046 bool is_gc;
6047 bool ignore_bcn;
6048 };
6049
6050 struct rtw89_mcc_bt_role {
6051 u16 duration; /* TU */
6052 };
6053
6054 struct rtw89_mcc_courtesy_cfg {
6055 u8 slot_num;
6056 u8 macid_tgt;
6057 };
6058
6059 struct rtw89_mcc_courtesy {
6060 struct rtw89_mcc_courtesy_cfg ref;
6061 struct rtw89_mcc_courtesy_cfg aux;
6062 };
6063
6064 enum rtw89_mcc_plan {
6065 RTW89_MCC_PLAN_TAIL_BT,
6066 RTW89_MCC_PLAN_MID_BT,
6067 RTW89_MCC_PLAN_NO_BT,
6068
6069 NUM_OF_RTW89_MCC_PLAN,
6070 };
6071
6072 struct rtw89_mcc_pattern {
6073 s16 tob_ref; /* TU; time offset behind of reference role */
6074 s16 toa_ref; /* TU; time offset ahead of reference role */
6075 s16 tob_aux; /* TU; time offset behind of auxiliary role */
6076 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
6077
6078 enum rtw89_mcc_plan plan;
6079 struct rtw89_mcc_courtesy courtesy;
6080 };
6081
6082 struct rtw89_mcc_sync {
6083 bool enable;
6084 u16 offset; /* TU */
6085 u8 macid_src;
6086 u8 band_src;
6087 u8 port_src;
6088 u8 macid_tgt;
6089 u8 band_tgt;
6090 u8 port_tgt;
6091 };
6092
6093 struct rtw89_mcc_config {
6094 struct rtw89_mcc_pattern pattern;
6095 struct rtw89_mcc_sync sync;
6096 u64 start_tsf;
6097 u64 start_tsf_in_aux_domain;
6098 u64 prepare_delay;
6099 u16 mcc_interval; /* TU */
6100 u16 beacon_offset; /* TU */
6101 };
6102
6103 enum rtw89_mcc_mode {
6104 RTW89_MCC_MODE_GO_STA,
6105 RTW89_MCC_MODE_GC_STA,
6106 };
6107
6108 struct rtw89_mcc_info {
6109 struct rtw89_wait_info wait;
6110
6111 u8 group;
6112 enum rtw89_mcc_mode mode;
6113 struct rtw89_mcc_role role_ref; /* reference role */
6114 struct rtw89_mcc_role role_aux; /* auxiliary role */
6115 struct rtw89_mcc_bt_role bt_role;
6116 struct rtw89_mcc_config config;
6117 };
6118
6119 enum rtw89_mlo_mode {
6120 RTW89_MLO_MODE_MLSR = 0,
6121 RTW89_MLO_MODE_EMLSR = 1,
6122
6123 NUM_OF_RTW89_MLO_MODE,
6124 };
6125
6126 struct rtw89_mlo_info {
6127 struct rtw89_wait_info wait;
6128 };
6129
6130 struct rtw89_beacon_track_info {
6131 bool is_data_ready;
6132 u32 tbtt_offset; /* in unit of microsecond */
6133 u16 bcn_timeout; /* in unit of millisecond */
6134
6135 /* The following are constant and set at association. */
6136 u8 dtim;
6137 u16 beacon_int;
6138 u16 low_bcn_th;
6139 u16 med_bcn_th;
6140 u16 high_bcn_th;
6141 u16 target_bcn_th;
6142 u16 outlier_low_bcn_th;
6143 u16 outlier_high_bcn_th;
6144 u32 close_bcn_intvl_th;
6145 u32 tbtt_diff_th;
6146 };
6147
6148 struct rtw89_dev {
6149 struct ieee80211_hw *hw;
6150 struct device *dev;
6151 const struct ieee80211_ops *ops;
6152
6153 bool dbcc_en;
6154 bool support_mlo;
6155 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
6156 struct rtw89_hw_scan_info scan_info;
6157 const struct rtw89_chip_info *chip;
6158 const struct rtw89_chip_variant *variant;
6159 const struct rtw89_pci_info *pci_info;
6160 const struct rtw89_rfe_parms *rfe_parms;
6161 struct rtw89_hal hal;
6162 struct rtw89_beacon_track_info bcn_track;
6163 struct rtw89_mcc_info mcc;
6164 struct rtw89_mlo_info mlo;
6165 struct rtw89_mac_info mac;
6166 struct rtw89_fw_info fw;
6167 struct rtw89_hci_info hci;
6168 struct rtw89_efuse efuse;
6169 struct rtw89_traffic_stats stats;
6170 struct rtw89_rfe_data *rfe_data;
6171 enum rtw89_custid custid;
6172
6173 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM];
6174 refcount_t refcount_ap_info;
6175
6176 struct list_head rtwvifs_list;
6177 /* used to protect rf read write */
6178 struct mutex rf_mutex;
6179 struct workqueue_struct *txq_wq;
6180 struct work_struct txq_work;
6181 struct delayed_work txq_reinvoke_work;
6182 /* used to protect ba_list and forbid_ba_list */
6183 spinlock_t ba_lock;
6184 /* txqs to setup ba session */
6185 struct list_head ba_list;
6186 /* txqs to forbid ba session */
6187 struct list_head forbid_ba_list;
6188 struct work_struct ba_work;
6189 /* used to protect rpwm */
6190 spinlock_t rpwm_lock;
6191
6192 struct list_head tx_waits;
6193 struct wiphy_delayed_work tx_wait_work;
6194
6195 struct rtw89_tx_rpt tx_rpt;
6196
6197 struct rtw89_cam_info cam_info;
6198
6199 struct sk_buff_head c2h_queue;
6200 struct wiphy_work c2h_work;
6201 struct wiphy_work ips_work;
6202 struct wiphy_work cancel_6ghz_probe_work;
6203 struct work_struct load_firmware_work;
6204
6205 struct list_head early_h2c_list;
6206
6207 struct rtw89_ser ser;
6208
6209 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
6210 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
6211 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
6212 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
6213 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
6214
6215 struct rtw89_phy_stat phystat;
6216 struct rtw89_rfk_wait_info rfk_wait;
6217 struct rtw89_dack_info dack;
6218 struct rtw89_iqk_info iqk;
6219 struct rtw89_dpk_info dpk;
6220 struct rtw89_rfk_mcc_info rfk_mcc;
6221 struct rtw89_lck_info lck;
6222 struct rtw89_rx_dck_info rx_dck;
6223 bool is_tssi_mode[RF_PATH_MAX];
6224 bool is_bt_iqk_timeout;
6225
6226 struct rtw89_fem_info fem;
6227 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
6228 struct rtw89_tssi_info tssi;
6229 struct rtw89_power_trim_info pwr_trim;
6230
6231 struct rtw89_cfo_tracking_info cfo_tracking;
6232 union {
6233 struct rtw89_phy_bb_gain_info ax;
6234 struct rtw89_phy_bb_gain_info_be be;
6235 } bb_gain;
6236 struct rtw89_phy_efuse_gain efuse_gain;
6237 struct rtw89_phy_ul_tb_info ul_tb_info;
6238 struct rtw89_antdiv_info antdiv;
6239
6240 struct rtw89_bb_ctx {
6241 enum rtw89_phy_idx phy_idx;
6242 struct rtw89_env_monitor_info env_monitor;
6243 struct rtw89_dig_info dig;
6244 struct rtw89_phy_ch_info ch_info;
6245 struct rtw89_edcca_bak edcca_bak;
6246 } bbs[RTW89_PHY_NUM];
6247
6248 struct wiphy_delayed_work track_work;
6249 struct wiphy_delayed_work track_ps_work;
6250 struct wiphy_delayed_work chanctx_work;
6251 struct wiphy_delayed_work coex_act1_work;
6252 struct wiphy_delayed_work coex_bt_devinfo_work;
6253 struct wiphy_delayed_work coex_rfk_chk_work;
6254 struct wiphy_delayed_work cfo_track_work;
6255 struct wiphy_delayed_work mcc_prepare_done_work;
6256 struct delayed_work forbid_ba_work;
6257 struct wiphy_delayed_work antdiv_work;
6258 struct rtw89_ppdu_sts_info ppdu_sts;
6259 u8 total_sta_assoc;
6260 bool scanning;
6261
6262 struct rtw89_regulatory_info regulatory;
6263 struct rtw89_sar_info sar;
6264 struct rtw89_tas_info tas;
6265 struct rtw89_ant_gain_info ant_gain;
6266
6267 struct rtw89_btc btc;
6268 enum rtw89_ps_mode ps_mode;
6269 bool lps_enabled;
6270 u8 ps_hang_cnt;
6271
6272 struct rtw89_wow_param wow;
6273
6274 /* napi structure */
6275 struct net_device *netdev;
6276 struct napi_struct napi;
6277 int napi_budget_countdown;
6278
6279 struct rtw89_debugfs *debugfs;
6280 struct rtw89_vif *pure_monitor_mode_vif;
6281
6282 /* HCI related data, keep last */
6283 u8 priv[] __aligned(sizeof(void *));
6284 };
6285
6286 struct rtw89_link_conf_container {
6287 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS];
6288 };
6289
6290 struct rtw89_vif_ml_trans {
6291 u16 mediate_links;
6292 u16 links_to_del;
6293 u16 links_to_add;
6294 };
6295
6296 #define RTW89_VIF_IDLE_LINK_ID 0
6297
6298 struct rtw89_vif {
6299 struct rtw89_dev *rtwdev;
6300 struct list_head list;
6301 struct list_head mgnt_entry;
6302 struct rtw89_link_conf_container __rcu *snap_link_confs;
6303
6304 u8 mac_addr[ETH_ALEN];
6305 __be32 ip_addr;
6306
6307 struct rtw89_traffic_stats stats;
6308 struct rtw89_traffic_stats stats_ps;
6309 u32 tdls_peer;
6310
6311 struct ieee80211_scan_ies *scan_ies;
6312 struct cfg80211_scan_request *scan_req;
6313
6314 struct rtw89_roc roc;
6315 bool offchan;
6316
6317 enum rtw89_mlo_mode mlo_mode;
6318 struct rtw89_vif_ml_trans ml_trans;
6319
6320 struct list_head dlink_pool;
6321 u8 links_inst_valid_num;
6322 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6323 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6324 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num);
6325 };
6326
rtw89_vif_assign_link_is_valid(struct rtw89_vif_link ** rtwvif_link,const struct rtw89_vif * rtwvif,unsigned int link_id)6327 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link,
6328 const struct rtw89_vif *rtwvif,
6329 unsigned int link_id)
6330 {
6331 *rtwvif_link = rtwvif->links[link_id];
6332 return !!*rtwvif_link;
6333 }
6334
6335 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \
6336 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6337 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id))
6338
6339 enum rtw89_sta_flags {
6340 RTW89_REMOTE_STA_IN_PS,
6341
6342 NUM_OF_RTW89_STA_FLAGS,
6343 };
6344
6345 struct rtw89_sta {
6346 struct rtw89_dev *rtwdev;
6347 struct rtw89_vif *rtwvif;
6348
6349 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS);
6350
6351 bool disassoc;
6352
6353 struct sk_buff_head roc_queue;
6354
6355 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
6356 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
6357
6358 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
6359
6360 struct list_head dlink_pool;
6361 u8 links_inst_valid_num;
6362 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6363 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6364 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num);
6365 };
6366
rtw89_sta_assign_link_is_valid(struct rtw89_sta_link ** rtwsta_link,const struct rtw89_sta * rtwsta,unsigned int link_id)6367 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link,
6368 const struct rtw89_sta *rtwsta,
6369 unsigned int link_id)
6370 {
6371 *rtwsta_link = rtwsta->links[link_id];
6372 return !!*rtwsta_link;
6373 }
6374
6375 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \
6376 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6377 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id))
6378
rtw89_vif_get_main_macid(struct rtw89_vif * rtwvif)6379 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif)
6380 {
6381 /* const after init, so no need to check if active first */
6382 return rtwvif->links_inst[0].mac_id;
6383 }
6384
rtw89_vif_get_main_port(struct rtw89_vif * rtwvif)6385 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif)
6386 {
6387 /* const after init, so no need to check if active first */
6388 return rtwvif->links_inst[0].port;
6389 }
6390
6391 static inline struct rtw89_vif_link *
rtw89_vif_get_link_inst(struct rtw89_vif * rtwvif,u8 index)6392 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index)
6393 {
6394 if (index >= rtwvif->links_inst_valid_num ||
6395 !test_bit(index, rtwvif->links_inst_map))
6396 return NULL;
6397 return &rtwvif->links_inst[index];
6398 }
6399
6400 static inline
rtw89_vif_link_inst_get_index(struct rtw89_vif_link * rtwvif_link)6401 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link)
6402 {
6403 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6404
6405 return rtwvif_link - rtwvif->links_inst;
6406 }
6407
rtw89_sta_get_main_macid(struct rtw89_sta * rtwsta)6408 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta)
6409 {
6410 /* const after init, so no need to check if active first */
6411 return rtwsta->links_inst[0].mac_id;
6412 }
6413
6414 static inline struct rtw89_sta_link *
rtw89_sta_get_link_inst(struct rtw89_sta * rtwsta,u8 index)6415 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index)
6416 {
6417 if (index >= rtwsta->links_inst_valid_num ||
6418 !test_bit(index, rtwsta->links_inst_map))
6419 return NULL;
6420 return &rtwsta->links_inst[index];
6421 }
6422
6423 static inline
rtw89_sta_link_inst_get_index(struct rtw89_sta_link * rtwsta_link)6424 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link)
6425 {
6426 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6427
6428 return rtwsta_link - rtwsta->links_inst;
6429 }
6430
rtw89_assoc_link_set(struct rtw89_sta_link * rtwsta_link)6431 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link)
6432 {
6433 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6434 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6435
6436 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6437 rtwsta_link);
6438 }
6439
rtw89_assoc_link_clr(struct rtw89_sta_link * rtwsta_link)6440 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link)
6441 {
6442 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6443 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6444
6445 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6446 NULL);
6447 synchronize_rcu();
6448 }
6449
6450 static inline struct rtw89_sta_link *
rtw89_assoc_link_rcu_dereference(struct rtw89_dev * rtwdev,u8 macid)6451 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid)
6452 {
6453 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]);
6454 }
6455
6456 #define rtw89_get_designated_link(links_holder) \
6457 ({ \
6458 typeof(links_holder) p = links_holder; \
6459 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \
6460 })
6461
rtw89_tx_wait_release(struct rtw89_tx_wait_info * wait)6462 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait)
6463 {
6464 dev_kfree_skb_any(wait->skb);
6465 kfree_rcu(wait, rcu_head);
6466 }
6467
rtw89_tx_wait_list_clear(struct rtw89_dev * rtwdev)6468 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev)
6469 {
6470 struct rtw89_tx_wait_info *wait, *tmp;
6471
6472 lockdep_assert_wiphy(rtwdev->hw->wiphy);
6473
6474 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) {
6475 if (!completion_done(&wait->completion))
6476 continue;
6477 list_del(&wait->list);
6478 rtw89_tx_wait_release(wait);
6479 }
6480 }
6481
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)6482 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
6483 struct rtw89_core_tx_request *tx_req)
6484 {
6485 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
6486 }
6487
rtw89_hci_reset(struct rtw89_dev * rtwdev)6488 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
6489 {
6490 rtwdev->hci.ops->reset(rtwdev);
6491 /* hci.ops->reset must complete all pending TX wait SKBs */
6492 rtw89_tx_wait_list_clear(rtwdev);
6493 }
6494
rtw89_hci_start(struct rtw89_dev * rtwdev)6495 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
6496 {
6497 return rtwdev->hci.ops->start(rtwdev);
6498 }
6499
rtw89_hci_stop(struct rtw89_dev * rtwdev)6500 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
6501 {
6502 rtwdev->hci.ops->stop(rtwdev);
6503 }
6504
rtw89_hci_deinit(struct rtw89_dev * rtwdev)6505 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
6506 {
6507 return rtwdev->hci.ops->deinit(rtwdev);
6508 }
6509
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)6510 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
6511 {
6512 rtwdev->hci.ops->pause(rtwdev, pause);
6513 }
6514
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)6515 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
6516 {
6517 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
6518 }
6519
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)6520 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
6521 {
6522 rtwdev->hci.ops->recalc_int_mit(rtwdev);
6523 }
6524
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)6525 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
6526 {
6527 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
6528 }
6529
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)6530 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
6531 {
6532 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
6533 }
6534
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)6535 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
6536 {
6537 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
6538 }
6539
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)6540 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
6541 bool drop)
6542 {
6543 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
6544 return;
6545
6546 if (rtwdev->hci.ops->flush_queues)
6547 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
6548 }
6549
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)6550 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
6551 {
6552 if (rtwdev->hci.ops->recovery_start)
6553 rtwdev->hci.ops->recovery_start(rtwdev);
6554 }
6555
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)6556 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
6557 {
6558 if (rtwdev->hci.ops->recovery_complete)
6559 rtwdev->hci.ops->recovery_complete(rtwdev);
6560 }
6561
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)6562 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
6563 {
6564 if (rtwdev->hci.ops->enable_intr)
6565 rtwdev->hci.ops->enable_intr(rtwdev);
6566 }
6567
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)6568 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
6569 {
6570 if (rtwdev->hci.ops->disable_intr)
6571 rtwdev->hci.ops->disable_intr(rtwdev);
6572 }
6573
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)6574 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
6575 {
6576 if (rtwdev->hci.ops->ctrl_txdma_ch)
6577 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
6578 }
6579
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)6580 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
6581 {
6582 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
6583 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
6584 }
6585
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)6586 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
6587 {
6588 if (rtwdev->hci.ops->ctrl_trxhci)
6589 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
6590 }
6591
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)6592 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
6593 {
6594 int ret = 0;
6595
6596 if (rtwdev->hci.ops->poll_txdma_ch_idle)
6597 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
6598 return ret;
6599 }
6600
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)6601 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
6602 {
6603 if (rtwdev->hci.ops->clr_idx_all)
6604 rtwdev->hci.ops->clr_idx_all(rtwdev);
6605 }
6606
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)6607 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
6608 {
6609 int ret = 0;
6610
6611 if (rtwdev->hci.ops->rst_bdram)
6612 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
6613 return ret;
6614 }
6615
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)6616 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
6617 {
6618 if (rtwdev->hci.ops->clear)
6619 rtwdev->hci.ops->clear(rtwdev, pdev);
6620 }
6621
6622 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)6623 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
6624 {
6625 /*
6626 * This should be used by/after rtw89_hci_tx_write() and before doing
6627 * ieee80211_tx_info_clear_status().
6628 */
6629 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6630
6631 return (struct rtw89_tx_skb_data *)info->driver_data;
6632 }
6633
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)6634 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
6635 {
6636 return rtwdev->hci.ops->read8(rtwdev, addr);
6637 }
6638
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)6639 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
6640 {
6641 return rtwdev->hci.ops->read16(rtwdev, addr);
6642 }
6643
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)6644 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
6645 {
6646 return rtwdev->hci.ops->read32(rtwdev, addr);
6647 }
6648
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)6649 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
6650 {
6651 rtwdev->hci.ops->write8(rtwdev, addr, data);
6652 }
6653
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)6654 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
6655 {
6656 rtwdev->hci.ops->write16(rtwdev, addr, data);
6657 }
6658
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)6659 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
6660 {
6661 rtwdev->hci.ops->write32(rtwdev, addr, data);
6662 }
6663
6664 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)6665 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6666 {
6667 u8 val;
6668
6669 val = rtw89_read8(rtwdev, addr);
6670 rtw89_write8(rtwdev, addr, val | bit);
6671 }
6672
6673 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)6674 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6675 {
6676 u16 val;
6677
6678 val = rtw89_read16(rtwdev, addr);
6679 rtw89_write16(rtwdev, addr, val | bit);
6680 }
6681
6682 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)6683 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6684 {
6685 u32 val;
6686
6687 val = rtw89_read32(rtwdev, addr);
6688 rtw89_write32(rtwdev, addr, val | bit);
6689 }
6690
6691 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)6692 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6693 {
6694 u8 val;
6695
6696 val = rtw89_read8(rtwdev, addr);
6697 rtw89_write8(rtwdev, addr, val & ~bit);
6698 }
6699
6700 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)6701 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6702 {
6703 u16 val;
6704
6705 val = rtw89_read16(rtwdev, addr);
6706 rtw89_write16(rtwdev, addr, val & ~bit);
6707 }
6708
6709 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)6710 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6711 {
6712 u32 val;
6713
6714 val = rtw89_read32(rtwdev, addr);
6715 rtw89_write32(rtwdev, addr, val & ~bit);
6716 }
6717
6718 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6719 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6720 {
6721 u32 shift = __ffs(mask);
6722 u32 orig;
6723 u32 ret;
6724
6725 orig = rtw89_read32(rtwdev, addr);
6726 ret = (orig & mask) >> shift;
6727
6728 return ret;
6729 }
6730
6731 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6732 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6733 {
6734 u32 shift = __ffs(mask);
6735 u32 orig;
6736 u32 ret;
6737
6738 orig = rtw89_read16(rtwdev, addr);
6739 ret = (orig & mask) >> shift;
6740
6741 return ret;
6742 }
6743
6744 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6745 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6746 {
6747 u32 shift = __ffs(mask);
6748 u32 orig;
6749 u32 ret;
6750
6751 orig = rtw89_read8(rtwdev, addr);
6752 ret = (orig & mask) >> shift;
6753
6754 return ret;
6755 }
6756
6757 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)6758 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
6759 {
6760 u32 shift = __ffs(mask);
6761 u32 orig;
6762 u32 set;
6763
6764 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
6765
6766 orig = rtw89_read32(rtwdev, addr);
6767 set = (orig & ~mask) | ((data << shift) & mask);
6768 rtw89_write32(rtwdev, addr, set);
6769 }
6770
6771 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)6772 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
6773 {
6774 u32 shift;
6775 u16 orig, set;
6776
6777 mask &= 0xffff;
6778 shift = __ffs(mask);
6779
6780 orig = rtw89_read16(rtwdev, addr);
6781 set = (orig & ~mask) | ((data << shift) & mask);
6782 rtw89_write16(rtwdev, addr, set);
6783 }
6784
6785 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)6786 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
6787 {
6788 u32 shift;
6789 u8 orig, set;
6790
6791 mask &= 0xff;
6792 shift = __ffs(mask);
6793
6794 orig = rtw89_read8(rtwdev, addr);
6795 set = (orig & ~mask) | ((data << shift) & mask);
6796 rtw89_write8(rtwdev, addr, set);
6797 }
6798
6799 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)6800 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6801 u32 addr, u32 mask)
6802 {
6803 u32 val;
6804
6805 mutex_lock(&rtwdev->rf_mutex);
6806 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6807 mutex_unlock(&rtwdev->rf_mutex);
6808
6809 return val;
6810 }
6811
6812 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)6813 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6814 u32 addr, u32 mask, u32 data)
6815 {
6816 mutex_lock(&rtwdev->rf_mutex);
6817 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6818 mutex_unlock(&rtwdev->rf_mutex);
6819 }
6820
rtw89_read32_pci_cfg(struct rtw89_dev * rtwdev,u32 addr)6821 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
6822 {
6823 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE ||
6824 !rtwdev->hci.ops->read32_pci_cfg)
6825 return RTW89_R32_EA;
6826
6827 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr);
6828 }
6829
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)6830 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
6831 {
6832 void *p = rtwtxq;
6833
6834 return container_of(p, struct ieee80211_txq, drv_priv);
6835 }
6836
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)6837 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
6838 struct ieee80211_txq *txq)
6839 {
6840 struct rtw89_txq *rtwtxq;
6841
6842 if (!txq)
6843 return;
6844
6845 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6846 INIT_LIST_HEAD(&rtwtxq->list);
6847 }
6848
rtwvif_to_vif(struct rtw89_vif * rtwvif)6849 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
6850 {
6851 void *p = rtwvif;
6852
6853 return container_of(p, struct ieee80211_vif, drv_priv);
6854 }
6855
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)6856 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
6857 {
6858 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
6859 }
6860
6861 static inline
rtwvif_link_to_vif(struct rtw89_vif_link * rtwvif_link)6862 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link)
6863 {
6864 return rtwvif_to_vif(rtwvif_link->rtwvif);
6865 }
6866
6867 static inline
rtwvif_link_to_vif_safe(struct rtw89_vif_link * rtwvif_link)6868 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link)
6869 {
6870 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL;
6871 }
6872
vif_to_rtwvif(struct ieee80211_vif * vif)6873 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif)
6874 {
6875 return (struct rtw89_vif *)vif->drv_priv;
6876 }
6877
vif_to_rtwvif_safe(struct ieee80211_vif * vif)6878 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
6879 {
6880 return vif ? vif_to_rtwvif(vif) : NULL;
6881 }
6882
rtwsta_to_sta(struct rtw89_sta * rtwsta)6883 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
6884 {
6885 void *p = rtwsta;
6886
6887 return container_of(p, struct ieee80211_sta, drv_priv);
6888 }
6889
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)6890 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
6891 {
6892 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
6893 }
6894
6895 static inline
rtwsta_link_to_sta(struct rtw89_sta_link * rtwsta_link)6896 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link)
6897 {
6898 return rtwsta_to_sta(rtwsta_link->rtwsta);
6899 }
6900
6901 static inline
rtwsta_link_to_sta_safe(struct rtw89_sta_link * rtwsta_link)6902 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link)
6903 {
6904 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL;
6905 }
6906
sta_to_rtwsta(struct ieee80211_sta * sta)6907 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta)
6908 {
6909 return (struct rtw89_sta *)sta->drv_priv;
6910 }
6911
sta_to_rtwsta_safe(struct ieee80211_sta * sta)6912 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
6913 {
6914 return sta ? sta_to_rtwsta(sta) : NULL;
6915 }
6916
6917 static inline struct ieee80211_bss_conf *
__rtw89_vif_rcu_dereference_link(struct rtw89_vif_link * rtwvif_link,bool * nolink)6918 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink)
6919 {
6920 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6921 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6922 struct rtw89_link_conf_container *snap;
6923 struct ieee80211_bss_conf *bss_conf;
6924
6925 snap = rcu_dereference(rtwvif->snap_link_confs);
6926 if (snap) {
6927 bss_conf = snap->link_conf[rtwvif_link->link_id];
6928 goto out;
6929 }
6930
6931 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]);
6932
6933 out:
6934 if (unlikely(!bss_conf)) {
6935 *nolink = true;
6936 return &vif->bss_conf;
6937 }
6938
6939 *nolink = false;
6940 return bss_conf;
6941 }
6942
6943 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \
6944 ({ \
6945 typeof(rtwvif_link) p = rtwvif_link; \
6946 struct ieee80211_bss_conf *bss_conf; \
6947 bool nolink; \
6948 \
6949 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \
6950 if (unlikely(nolink) && (assert)) \
6951 rtw89_err(p->rtwvif->rtwdev, \
6952 "%s: cannot find exact bss_conf for link_id %u\n",\
6953 __func__, p->link_id); \
6954 bss_conf; \
6955 })
6956
6957 static inline struct ieee80211_link_sta *
__rtw89_sta_rcu_dereference_link(struct rtw89_sta_link * rtwsta_link,bool * nolink)6958 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink)
6959 {
6960 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6961 struct ieee80211_link_sta *link_sta;
6962
6963 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]);
6964 if (unlikely(!link_sta)) {
6965 *nolink = true;
6966 return &sta->deflink;
6967 }
6968
6969 *nolink = false;
6970 return link_sta;
6971 }
6972
6973 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \
6974 ({ \
6975 typeof(rtwsta_link) p = rtwsta_link; \
6976 struct ieee80211_link_sta *link_sta; \
6977 bool nolink; \
6978 \
6979 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \
6980 if (unlikely(nolink) && (assert)) \
6981 rtw89_err(p->rtwsta->rtwdev, \
6982 "%s: cannot find exact link_sta for link_id %u\n",\
6983 __func__, p->link_id); \
6984 link_sta; \
6985 })
6986
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)6987 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
6988 {
6989 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6990 return RATE_INFO_BW_160;
6991 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6992 return RATE_INFO_BW_80;
6993 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6994 return RATE_INFO_BW_40;
6995 else
6996 return RATE_INFO_BW_20;
6997 }
6998
6999 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)7000 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
7001 {
7002 switch (hw_band) {
7003 default:
7004 case RTW89_BAND_2G:
7005 return NL80211_BAND_2GHZ;
7006 case RTW89_BAND_5G:
7007 return NL80211_BAND_5GHZ;
7008 case RTW89_BAND_6G:
7009 return NL80211_BAND_6GHZ;
7010 }
7011 }
7012
7013 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)7014 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
7015 {
7016 switch (nl_band) {
7017 default:
7018 case NL80211_BAND_2GHZ:
7019 return RTW89_BAND_2G;
7020 case NL80211_BAND_5GHZ:
7021 return RTW89_BAND_5G;
7022 case NL80211_BAND_6GHZ:
7023 return RTW89_BAND_6G;
7024 }
7025 }
7026
7027 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)7028 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
7029 {
7030 switch (width) {
7031 default:
7032 WARN(1, "Not support bandwidth %d\n", width);
7033 fallthrough;
7034 case NL80211_CHAN_WIDTH_20_NOHT:
7035 case NL80211_CHAN_WIDTH_20:
7036 return RTW89_CHANNEL_WIDTH_20;
7037 case NL80211_CHAN_WIDTH_40:
7038 return RTW89_CHANNEL_WIDTH_40;
7039 case NL80211_CHAN_WIDTH_80:
7040 return RTW89_CHANNEL_WIDTH_80;
7041 case NL80211_CHAN_WIDTH_160:
7042 return RTW89_CHANNEL_WIDTH_160;
7043 }
7044 }
7045
7046 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)7047 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
7048 {
7049 switch (rua) {
7050 default:
7051 WARN(1, "Invalid RU allocation: %d\n", rua);
7052 fallthrough;
7053 case 0 ... 36:
7054 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
7055 case 37 ... 52:
7056 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
7057 case 53 ... 60:
7058 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
7059 case 61 ... 64:
7060 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
7061 case 65 ... 66:
7062 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
7063 case 67:
7064 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
7065 case 68:
7066 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
7067 }
7068 }
7069
7070 static inline
rtw89_get_addr_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)7071 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link,
7072 struct rtw89_sta_link *rtwsta_link)
7073 {
7074 if (rtwsta_link) {
7075 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
7076
7077 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
7078 return &rtwsta_link->addr_cam;
7079 }
7080 return &rtwvif_link->addr_cam;
7081 }
7082
7083 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)7084 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link,
7085 struct rtw89_sta_link *rtwsta_link)
7086 {
7087 if (rtwsta_link) {
7088 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
7089
7090 if (sta->tdls)
7091 return &rtwsta_link->bssid_cam;
7092 }
7093 return &rtwvif_link->bssid_cam;
7094 }
7095
7096 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)7097 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
7098 struct rtw89_channel_help_params *p,
7099 const struct rtw89_chan *chan,
7100 enum rtw89_mac_idx mac_idx,
7101 enum rtw89_phy_idx phy_idx)
7102 {
7103 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
7104 mac_idx, phy_idx);
7105 }
7106
7107 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)7108 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
7109 struct rtw89_channel_help_params *p,
7110 const struct rtw89_chan *chan,
7111 enum rtw89_mac_idx mac_idx,
7112 enum rtw89_phy_idx phy_idx)
7113 {
7114 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
7115 mac_idx, phy_idx);
7116 }
7117
7118 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)7119 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
7120 enum rtw89_chanctx_idx idx)
7121 {
7122 struct rtw89_hal *hal = &rtwdev->hal;
7123 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
7124
7125 if (roc_idx == idx)
7126 return &hal->roc_chandef;
7127
7128 return &hal->chanctx[idx].chandef;
7129 }
7130
7131 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)7132 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
7133 enum rtw89_chanctx_idx idx)
7134 {
7135 struct rtw89_hal *hal = &rtwdev->hal;
7136
7137 return &hal->chanctx[idx].chan;
7138 }
7139
7140 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)7141 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
7142 enum rtw89_chanctx_idx idx)
7143 {
7144 struct rtw89_hal *hal = &rtwdev->hal;
7145
7146 return &hal->chanctx[idx].rcd;
7147 }
7148
7149 static inline
rtw89_chan_rcd_get_by_chan(const struct rtw89_chan * chan)7150 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan)
7151 {
7152 const struct rtw89_chanctx *chanctx =
7153 container_of_const(chan, struct rtw89_chanctx, chan);
7154
7155 return &chanctx->rcd;
7156 }
7157
7158 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)7159 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
7160 {
7161 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
7162
7163 if (rtwvif_link)
7164 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
7165 else
7166 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
7167 }
7168
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)7169 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
7170 {
7171 const struct rtw89_chip_info *chip = rtwdev->chip;
7172
7173 if (chip->ops->fem_setup)
7174 chip->ops->fem_setup(rtwdev);
7175 }
7176
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)7177 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
7178 {
7179 const struct rtw89_chip_info *chip = rtwdev->chip;
7180
7181 if (chip->ops->rfe_gpio)
7182 chip->ops->rfe_gpio(rtwdev);
7183 }
7184
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)7185 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
7186 {
7187 const struct rtw89_chip_info *chip = rtwdev->chip;
7188
7189 if (chip->ops->rfk_hw_init)
7190 chip->ops->rfk_hw_init(rtwdev);
7191 }
7192
7193 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev)7194 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev)
7195 {
7196 const struct rtw89_chip_info *chip = rtwdev->chip;
7197
7198 if (!chip->ops->bb_preinit)
7199 return;
7200
7201 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0);
7202
7203 if (rtwdev->dbcc_en)
7204 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1);
7205 }
7206
7207 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)7208 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
7209 {
7210 const struct rtw89_chip_info *chip = rtwdev->chip;
7211
7212 if (!chip->ops->bb_postinit)
7213 return;
7214
7215 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
7216
7217 if (rtwdev->dbcc_en)
7218 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
7219 }
7220
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)7221 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
7222 {
7223 const struct rtw89_chip_info *chip = rtwdev->chip;
7224
7225 if (chip->ops->bb_sethw)
7226 chip->ops->bb_sethw(rtwdev);
7227 }
7228
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)7229 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
7230 {
7231 const struct rtw89_chip_info *chip = rtwdev->chip;
7232
7233 if (chip->ops->rfk_init)
7234 chip->ops->rfk_init(rtwdev);
7235 }
7236
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)7237 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
7238 {
7239 const struct rtw89_chip_info *chip = rtwdev->chip;
7240
7241 if (chip->ops->rfk_init_late)
7242 chip->ops->rfk_init_late(rtwdev);
7243 }
7244
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)7245 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
7246 enum rtw89_phy_idx phy_idx,
7247 const struct rtw89_chan *chan)
7248 {
7249 const struct rtw89_chip_info *chip = rtwdev->chip;
7250
7251 if (chip->ops->rfk_band_changed)
7252 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
7253 }
7254
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)7255 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
7256 struct rtw89_vif_link *rtwvif_link, bool start)
7257 {
7258 const struct rtw89_chip_info *chip = rtwdev->chip;
7259
7260 if (chip->ops->rfk_scan)
7261 chip->ops->rfk_scan(rtwdev, rtwvif_link, start);
7262 }
7263
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)7264 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
7265 {
7266 const struct rtw89_chip_info *chip = rtwdev->chip;
7267
7268 if (chip->ops->rfk_track)
7269 chip->ops->rfk_track(rtwdev);
7270 }
7271
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)7272 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
7273 {
7274 const struct rtw89_chip_info *chip = rtwdev->chip;
7275
7276 if (!chip->ops->set_txpwr_ctrl)
7277 return;
7278
7279 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
7280 if (rtwdev->dbcc_en)
7281 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1);
7282 }
7283
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)7284 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
7285 {
7286 const struct rtw89_chip_info *chip = rtwdev->chip;
7287
7288 if (chip->ops->power_trim)
7289 chip->ops->power_trim(rtwdev);
7290 }
7291
__rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7292 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
7293 enum rtw89_phy_idx phy_idx)
7294 {
7295 const struct rtw89_chip_info *chip = rtwdev->chip;
7296
7297 if (chip->ops->init_txpwr_unit)
7298 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
7299 }
7300
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev)7301 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev)
7302 {
7303 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
7304 if (rtwdev->dbcc_en)
7305 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1);
7306 }
7307
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)7308 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
7309 enum rtw89_rf_path rf_path)
7310 {
7311 const struct rtw89_chip_info *chip = rtwdev->chip;
7312
7313 if (!chip->ops->get_thermal)
7314 return 0x10;
7315
7316 return chip->ops->get_thermal(rtwdev, rf_path);
7317 }
7318
rtw89_chip_chan_to_rf18_val(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)7319 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev,
7320 const struct rtw89_chan *chan)
7321 {
7322 const struct rtw89_chip_info *chip = rtwdev->chip;
7323
7324 if (!chip->ops->chan_to_rf18_val)
7325 return 0;
7326
7327 return chip->ops->chan_to_rf18_val(rtwdev, chan);
7328 }
7329
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)7330 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
7331 struct rtw89_rx_phy_ppdu *phy_ppdu,
7332 struct ieee80211_rx_status *status)
7333 {
7334 const struct rtw89_chip_info *chip = rtwdev->chip;
7335
7336 if (chip->ops->query_ppdu)
7337 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
7338 }
7339
rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)7340 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
7341 struct rtw89_rx_phy_ppdu *phy_ppdu)
7342 {
7343 const struct rtw89_chip_info *chip = rtwdev->chip;
7344
7345 if (chip->ops->convert_rpl_to_rssi)
7346 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
7347 }
7348
rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)7349 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
7350 struct rtw89_rx_desc_info *desc_info,
7351 struct ieee80211_rx_status *rx_status)
7352 {
7353 const struct rtw89_chip_info *chip = rtwdev->chip;
7354
7355 if (chip->ops->phy_rpt_to_rssi)
7356 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
7357 }
7358
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)7359 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
7360 enum rtw89_phy_idx phy_idx)
7361 {
7362 const struct rtw89_chip_info *chip = rtwdev->chip;
7363
7364 if (chip->ops->ctrl_nbtg_bt_tx)
7365 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
7366 }
7367
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)7368 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
7369 {
7370 const struct rtw89_chip_info *chip = rtwdev->chip;
7371
7372 if (chip->ops->cfg_txrx_path)
7373 chip->ops->cfg_txrx_path(rtwdev);
7374 }
7375
rtw89_chip_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7376 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
7377 enum rtw89_phy_idx phy_idx)
7378 {
7379 const struct rtw89_chip_info *chip = rtwdev->chip;
7380
7381 if (chip->ops->digital_pwr_comp)
7382 chip->ops->digital_pwr_comp(rtwdev, phy_idx);
7383 }
7384
7385 static inline
rtw89_chip_calc_rx_gain_normal(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx,struct rtw89_phy_calc_efuse_gain * calc)7386 void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev,
7387 const struct rtw89_chan *chan,
7388 enum rtw89_rf_path path,
7389 enum rtw89_phy_idx phy_idx,
7390 struct rtw89_phy_calc_efuse_gain *calc)
7391 {
7392 const struct rtw89_chip_info *chip = rtwdev->chip;
7393
7394 if (chip->ops->calc_rx_gain_normal)
7395 chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc);
7396 }
7397
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)7398 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
7399 const struct rtw89_txpwr_table *tbl)
7400 {
7401 tbl->load(rtwdev, tbl);
7402 }
7403
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)7404 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
7405 {
7406 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
7407 const struct rtw89_regd *regd = regulatory->regd;
7408 u8 txpwr_regd = regd->txpwr_regd[band];
7409
7410 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK)
7411 return RTW89_ETSI;
7412
7413 return txpwr_regd;
7414 }
7415
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)7416 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
7417 enum rtw89_phy_idx phy_idx)
7418 {
7419 const struct rtw89_chip_info *chip = rtwdev->chip;
7420
7421 if (chip->ops->ctrl_btg_bt_rx)
7422 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
7423 }
7424
7425 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)7426 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
7427 struct rtw89_rx_desc_info *desc_info,
7428 u8 *data, u32 data_offset)
7429 {
7430 const struct rtw89_chip_info *chip = rtwdev->chip;
7431
7432 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
7433 }
7434
7435 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)7436 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
7437 struct rtw89_tx_desc_info *desc_info,
7438 void *txdesc)
7439 {
7440 const struct rtw89_chip_info *chip = rtwdev->chip;
7441
7442 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
7443 }
7444
7445 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)7446 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
7447 struct rtw89_tx_desc_info *desc_info,
7448 void *txdesc)
7449 {
7450 const struct rtw89_chip_info *chip = rtwdev->chip;
7451
7452 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
7453 }
7454
7455 static inline
rtw89_chip_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)7456 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
7457 {
7458 const struct rtw89_chip_info *chip = rtwdev->chip;
7459
7460 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel);
7461 }
7462
7463 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)7464 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
7465 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
7466 {
7467 const struct rtw89_chip_info *chip = rtwdev->chip;
7468
7469 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
7470 }
7471
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)7472 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
7473 {
7474 const struct rtw89_chip_info *chip = rtwdev->chip;
7475
7476 chip->ops->cfg_ctrl_path(rtwdev, wl);
7477 }
7478
7479 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)7480 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
7481 u32 *tx_en, enum rtw89_sch_tx_sel sel)
7482 {
7483 const struct rtw89_chip_info *chip = rtwdev->chip;
7484
7485 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
7486 }
7487
7488 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)7489 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
7490 {
7491 const struct rtw89_chip_info *chip = rtwdev->chip;
7492
7493 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
7494 }
7495
7496 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)7497 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
7498 struct rtw89_vif_link *rtwvif_link,
7499 struct rtw89_sta_link *rtwsta_link)
7500 {
7501 const struct rtw89_chip_info *chip = rtwdev->chip;
7502
7503 if (!chip->ops->h2c_dctl_sec_cam)
7504 return 0;
7505 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link);
7506 }
7507
get_hdr_bssid(struct ieee80211_hdr * hdr)7508 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
7509 {
7510 __le16 fc = hdr->frame_control;
7511
7512 if (ieee80211_has_tods(fc))
7513 return hdr->addr1;
7514 else if (ieee80211_has_fromds(fc))
7515 return hdr->addr2;
7516 else
7517 return hdr->addr3;
7518 }
7519
7520 static inline
rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta * link_sta)7521 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta)
7522 {
7523 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
7524 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
7525 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
7526 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
7527 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] &
7528 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
7529 return true;
7530 return false;
7531 }
7532
7533 static inline
rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta * link_sta)7534 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta)
7535 {
7536 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] &
7537 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI)
7538 return true;
7539
7540 return false;
7541 }
7542
7543 static inline
rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta * link_sta)7544 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta)
7545 {
7546 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] &
7547 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI)
7548 return true;
7549
7550 return false;
7551 }
7552
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)7553 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
7554 #if defined(__linux__)
7555 enum rtw89_fw_type type)
7556 #elif defined(__FreeBSD__)
7557 const enum rtw89_fw_type type)
7558 #endif
7559 {
7560 struct rtw89_fw_info *fw_info = &rtwdev->fw;
7561
7562 switch (type) {
7563 case RTW89_FW_WOWLAN:
7564 return &fw_info->wowlan;
7565 case RTW89_FW_LOGFMT:
7566 return &fw_info->log.suit;
7567 case RTW89_FW_BBMCU0:
7568 return &fw_info->bbmcu0;
7569 case RTW89_FW_BBMCU1:
7570 return &fw_info->bbmcu1;
7571 default:
7572 break;
7573 }
7574
7575 return &fw_info->normal;
7576 }
7577
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)7578 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
7579 unsigned int length)
7580 {
7581 struct sk_buff *skb;
7582
7583 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
7584 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
7585 if (!skb)
7586 return NULL;
7587
7588 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
7589 return skb;
7590 }
7591
7592 return dev_alloc_skb(length);
7593 }
7594
rtw89_core_is_tx_wait(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data)7595 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev,
7596 struct rtw89_tx_skb_data *skb_data)
7597 {
7598 return rcu_access_pointer(skb_data->wait);
7599 }
7600
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,u8 tx_status)7601 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
7602 struct rtw89_tx_skb_data *skb_data,
7603 u8 tx_status)
7604 {
7605 struct rtw89_tx_wait_info *wait;
7606
7607 guard(rcu)();
7608
7609 wait = rcu_dereference(skb_data->wait);
7610 if (!wait)
7611 return false;
7612
7613 wait->tx_done = tx_status == RTW89_TX_DONE;
7614 /* Don't access skb anymore after completion */
7615 complete_all(&wait->completion);
7616 return true;
7617 }
7618
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)7619 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
7620 {
7621 switch (rtwdev->mlo_dbcc_mode) {
7622 case MLO_1_PLUS_1_1RF:
7623 case MLO_1_PLUS_1_2RF:
7624 case DBCC_LEGACY:
7625 return true;
7626 default:
7627 return false;
7628 }
7629 }
7630
rtw89_get_active_phy_bitmap(struct rtw89_dev * rtwdev)7631 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev)
7632 {
7633 if (!rtwdev->dbcc_en)
7634 return BIT(RTW89_PHY_0);
7635
7636 switch (rtwdev->mlo_dbcc_mode) {
7637 case MLO_0_PLUS_2_1RF:
7638 case MLO_0_PLUS_2_2RF:
7639 return BIT(RTW89_PHY_1);
7640 case MLO_1_PLUS_1_1RF:
7641 case MLO_1_PLUS_1_2RF:
7642 case MLO_2_PLUS_2_2RF:
7643 case DBCC_LEGACY:
7644 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1);
7645 case MLO_2_PLUS_0_1RF:
7646 case MLO_2_PLUS_0_2RF:
7647 default:
7648 return BIT(RTW89_PHY_0);
7649 }
7650 }
7651
7652 #define rtw89_for_each_active_bb(rtwdev, bb) \
7653 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \
7654 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \
7655 if (__active_bb_bitmap & BIT(__phy_idx) && \
7656 (bb = &rtwdev->bbs[__phy_idx]))
7657
7658 #define rtw89_for_each_capab_bb(rtwdev, bb) \
7659 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \
7660 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \
7661 if ((bb = &rtwdev->bbs[__phy_idx]))
7662
7663 static inline
rtw89_get_bb_ctx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7664 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev,
7665 enum rtw89_phy_idx phy_idx)
7666 {
7667 if (phy_idx >= RTW89_PHY_NUM)
7668 return &rtwdev->bbs[RTW89_PHY_0];
7669
7670 return &rtwdev->bbs[phy_idx];
7671 }
7672
rtw89_is_rtl885xb(struct rtw89_dev * rtwdev)7673 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
7674 {
7675 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
7676
7677 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
7678 return true;
7679
7680 return false;
7681 }
7682
rtw89_bytes_to_mbps(u64 bytes,enum rtw89_tfc_interval interval)7683 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval)
7684 {
7685 switch (interval) {
7686 default:
7687 case RTW89_TFC_INTERVAL_2SEC:
7688 return bytes >> 18; /* bytes/2s --> Mbps */;
7689 case RTW89_TFC_INTERVAL_100MS:
7690 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */
7691 }
7692 }
7693
7694 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
7695 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
7696 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
7697 struct sk_buff *skb, bool fwdl);
7698 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
7699 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
7700 struct rtw89_tx_wait_info *wait, int qsel,
7701 unsigned int timeout);
7702 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
7703 struct rtw89_tx_desc_info *desc_info,
7704 void *txdesc);
7705 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
7706 struct rtw89_tx_desc_info *desc_info,
7707 void *txdesc);
7708 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
7709 struct rtw89_tx_desc_info *desc_info,
7710 void *txdesc);
7711 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev,
7712 struct rtw89_tx_desc_info *desc_info,
7713 void *txdesc);
7714 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
7715 struct rtw89_tx_desc_info *desc_info,
7716 void *txdesc);
7717 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
7718 struct rtw89_tx_desc_info *desc_info,
7719 void *txdesc);
7720 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel);
7721 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel);
7722 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel);
7723 void rtw89_core_rx(struct rtw89_dev *rtwdev,
7724 struct rtw89_rx_desc_info *desc_info,
7725 struct sk_buff *skb);
7726 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
7727 struct rtw89_rx_desc_info *desc_info,
7728 u8 *data, u32 data_offset);
7729 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
7730 struct rtw89_rx_desc_info *desc_info,
7731 u8 *data, u32 data_offset);
7732 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
7733 struct rtw89_rx_desc_info *desc_info,
7734 u8 *data, u32 data_offset);
7735 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
7736 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
7737 int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
7738 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
7739 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
7740 struct rtw89_vif_link *rtwvif_link,
7741 struct rtw89_sta_link *rtwsta_link);
7742 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
7743 struct rtw89_vif_link *rtwvif_link,
7744 struct rtw89_sta_link *rtwsta_link);
7745 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
7746 struct rtw89_vif_link *rtwvif_link,
7747 struct rtw89_sta_link *rtwsta_link);
7748 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
7749 struct rtw89_vif_link *rtwvif_link,
7750 struct rtw89_sta_link *rtwsta_link);
7751 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
7752 struct rtw89_vif_link *rtwvif_link,
7753 struct rtw89_sta_link *rtwsta_link);
7754 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
7755 struct ieee80211_sta *sta,
7756 struct cfg80211_tid_config *tid_config);
7757 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
7758 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
7759 int rtw89_core_init(struct rtw89_dev *rtwdev);
7760 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
7761 int rtw89_core_register(struct rtw89_dev *rtwdev);
7762 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
7763 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
7764 u32 bus_data_size,
7765 const struct rtw89_chip_info *chip,
7766 const struct rtw89_chip_variant *variant);
7767 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
7768 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
7769 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
7770 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7771 u8 mac_id, u8 port);
7772 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7773 struct rtw89_sta *rtwsta, u8 mac_id);
7774 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
7775 unsigned int link_id);
7776 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id);
7777 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
7778 unsigned int link_id);
7779 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
7780 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
7781 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
7782 struct rtw89_vif_link *rtwvif_link);
7783 const struct rtw89_6ghz_span *
7784 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq);
7785 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
7786 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
7787 struct rtw89_chan *chan);
7788 int rtw89_set_channel(struct rtw89_dev *rtwdev);
7789 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
7790 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
7791 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
7792 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
7793 struct rtw89_sta_link *rtwsta_link, u8 tid,
7794 u8 *cam_idx);
7795 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
7796 struct rtw89_sta_link *rtwsta_link, u8 tid,
7797 u8 *cam_idx);
7798 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
7799 struct ieee80211_sta *sta);
7800 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
7801 struct ieee80211_sta *sta);
7802 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
7803 struct ieee80211_sta *sta);
7804 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc);
7805 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
7806 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
7807 struct rtw89_vif_link *rtwvif_link);
7808 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate);
7809 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
7810 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev);
7811 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd);
7812 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
7813 struct rtw89_traffic_stats *stats);
7814 struct rtw89_wait_response *
7815 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond)
7816 __acquires(rtw89_wait);
7817 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait,
7818 struct rtw89_wait_response *prep, int err)
7819 __releases(rtw89_wait);
7820 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
7821 const struct rtw89_completion_data *data);
7822 int rtw89_core_start(struct rtw89_dev *rtwdev);
7823 void rtw89_core_stop(struct rtw89_dev *rtwdev);
7824 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7825 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7826 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7827 bool qos, bool ps, int timeout);
7828 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work);
7829 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7830 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7831 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7832 const u8 *mac_addr, bool hw_scan);
7833 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
7834 struct rtw89_vif_link *rtwvif_link, bool hw_scan);
7835 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7836 bool active);
7837 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
7838 struct rtw89_vif_link *rtwvif_link,
7839 struct ieee80211_bss_conf *bss_conf);
7840 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
7841 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7842 unsigned int link_id);
7843
7844 #endif
7845