1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright 2006-2007 by Juniper Networks.
5 * Copyright 2008 Semihalf.
6 * Copyright 2010 The FreeBSD Foundation
7 * All rights reserved.
8 *
9 * Portions of this software were developed by Semihalf
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/ktr.h>
41 #include <sys/sockio.h>
42 #include <sys/mbuf.h>
43 #include <sys/malloc.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/queue.h>
48 #include <sys/bus.h>
49 #include <sys/lock.h>
50 #include <sys/mutex.h>
51 #include <sys/queue.h>
52 #include <sys/rman.h>
53 #include <sys/endian.h>
54 #include <sys/vmem.h>
55
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
62 #include <dev/ofw/ofwpci.h>
63 #include <dev/pci/pcivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcib_private.h>
66
67 #include "ofw_bus_if.h"
68 #include "pcib_if.h"
69 #include "pic_if.h"
70
71 #include <machine/resource.h>
72 #include <machine/bus.h>
73 #include <machine/intr_machdep.h>
74
75 #include <powerpc/mpc85xx/mpc85xx.h>
76
77 #define REG_CFG_ADDR 0x0000
78 #define CONFIG_ACCESS_ENABLE 0x80000000
79
80 #define REG_CFG_DATA 0x0004
81 #define REG_INT_ACK 0x0008
82
83 #define REG_PEX_IP_BLK_REV1 0x0bf8
84 #define IP_MJ_M 0x0000ff00
85 #define IP_MJ_S 8
86 #define IP_MN_M 0x000000ff
87 #define IP_MN_S 0
88
89 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
90 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
91 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
92 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
93
94 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
95 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
96 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
97 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
98 #define PIWAR_EN 0x80000000
99 #define PIWAR_PF 0x40000000
100 #define PIWAR_TRGT_M 0x00f00000
101 #define PIWAR_TRGT_S 20
102 #define PIWAR_TRGT_CCSR 0xe
103 #define PIWAR_TRGT_LOCAL 0xf
104
105 #define REG_PEX_MES_DR 0x0020
106 #define REG_PEX_MES_IER 0x0028
107 #define REG_PEX_ERR_DR 0x0e00
108 #define REG_PEX_ERR_EN 0x0e08
109
110 #define REG_PEX_ERR_DR 0x0e00
111 #define REG_PEX_ERR_DR_ME 0x80000000
112 #define REG_PEX_ERR_DR_PCT 0x800000
113 #define REG_PEX_ERR_DR_PAT 0x400000
114 #define REG_PEX_ERR_DR_PCAC 0x200000
115 #define REG_PEX_ERR_DR_PNM 0x100000
116 #define REG_PEX_ERR_DR_CDNSC 0x80000
117 #define REG_PEX_ERR_DR_CRSNC 0x40000
118 #define REG_PEX_ERR_DR_ICCA 0x20000
119 #define REG_PEX_ERR_DR_IACA 0x10000
120 #define REG_PEX_ERR_DR_CRST 0x8000
121 #define REG_PEX_ERR_DR_MIS 0x4000
122 #define REG_PEX_ERR_DR_IOIS 0x2000
123 #define REG_PEX_ERR_DR_CIS 0x1000
124 #define REG_PEX_ERR_DR_CIEP 0x800
125 #define REG_PEX_ERR_DR_IOIEP 0x400
126 #define REG_PEX_ERR_DR_OAC 0x200
127 #define REG_PEX_ERR_DR_IOIA 0x100
128 #define REG_PEX_ERR_DR_IMBA 0x80
129 #define REG_PEX_ERR_DR_IIOBA 0x40
130 #define REG_PEX_ERR_DR_LDDE 0x20
131 #define REG_PEX_ERR_EN 0x0e08
132
133 #define PCIR_LTSSM 0x404
134 #define LTSSM_STAT_L0 0x16
135
136 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
137
138 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */
139 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */
140
141 struct fsl_pcib_softc {
142 struct ofw_pci_softc pci_sc;
143 device_t sc_dev;
144 struct mtx sc_cfg_mtx;
145 int sc_ip_maj;
146 int sc_ip_min;
147
148 int sc_iomem_target;
149 bus_addr_t sc_iomem_start, sc_iomem_end;
150 int sc_ioport_target;
151 bus_addr_t sc_ioport_start, sc_ioport_end;
152
153 struct resource *sc_res;
154 bus_space_handle_t sc_bsh;
155 bus_space_tag_t sc_bst;
156 int sc_rid;
157
158 struct resource *sc_irq_res;
159 void *sc_ih;
160
161 int sc_busnr;
162 int sc_pcie;
163 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
164 };
165
166 struct fsl_pcib_err_dr {
167 const char *msg;
168 uint32_t err_dr_mask;
169 };
170
171 struct fsl_msi_map {
172 SLIST_ENTRY(fsl_msi_map) slist;
173 uint32_t irq_base;
174 bus_addr_t target;
175 };
176
177 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head);
178
179 static const struct fsl_pcib_err_dr pci_err[] = {
180 {"ME", REG_PEX_ERR_DR_ME},
181 {"PCT", REG_PEX_ERR_DR_PCT},
182 {"PAT", REG_PEX_ERR_DR_PAT},
183 {"PCAC", REG_PEX_ERR_DR_PCAC},
184 {"PNM", REG_PEX_ERR_DR_PNM},
185 {"CDNSC", REG_PEX_ERR_DR_CDNSC},
186 {"CRSNC", REG_PEX_ERR_DR_CRSNC},
187 {"ICCA", REG_PEX_ERR_DR_ICCA},
188 {"IACA", REG_PEX_ERR_DR_IACA},
189 {"CRST", REG_PEX_ERR_DR_CRST},
190 {"MIS", REG_PEX_ERR_DR_MIS},
191 {"IOIS", REG_PEX_ERR_DR_IOIS},
192 {"CIS", REG_PEX_ERR_DR_CIS},
193 {"CIEP", REG_PEX_ERR_DR_CIEP},
194 {"IOIEP", REG_PEX_ERR_DR_IOIEP},
195 {"OAC", REG_PEX_ERR_DR_OAC},
196 {"IOIA", REG_PEX_ERR_DR_IOIA},
197 {"IMBA", REG_PEX_ERR_DR_IMBA},
198 {"IIOBA", REG_PEX_ERR_DR_IIOBA},
199 {"LDDE", REG_PEX_ERR_DR_LDDE}
200 };
201
202 /* Local forward declerations. */
203 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
204 u_int, int);
205 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
206 u_int, uint32_t, int);
207 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
208 static void fsl_pcib_err_init(device_t);
209 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
210 uint64_t, uint64_t);
211 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
212 uint64_t, uint64_t);
213
214 /* Forward declerations. */
215 static int fsl_pcib_attach(device_t);
216 static int fsl_pcib_detach(device_t);
217 static int fsl_pcib_probe(device_t);
218
219 static int fsl_pcib_maxslots(device_t);
220 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
221 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
222 uint32_t, int);
223 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
224 int count, int maxcount, int *irqs);
225 static int fsl_pcib_release_msi(device_t dev, device_t child,
226 int count, int *irqs);
227 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq);
228 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq);
229 static int fsl_pcib_map_msi(device_t dev, device_t child,
230 int irq, uint64_t *addr, uint32_t *data);
231
232 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */
233
234 /*
235 * Bus interface definitions.
236 */
237 static device_method_t fsl_pcib_methods[] = {
238 /* Device interface */
239 DEVMETHOD(device_probe, fsl_pcib_probe),
240 DEVMETHOD(device_attach, fsl_pcib_attach),
241 DEVMETHOD(device_detach, fsl_pcib_detach),
242
243 /* pcib interface */
244 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
245 DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
246 DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
247 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi),
248 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi),
249 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix),
250 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix),
251 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi),
252
253 DEVMETHOD_END
254 };
255
256 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
257 sizeof(struct fsl_pcib_softc), ofw_pcib_driver);
258 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, 0, 0, BUS_PASS_BUS);
259
260 static void
fsl_pcib_err_intr(void * v)261 fsl_pcib_err_intr(void *v)
262 {
263 struct fsl_pcib_softc *sc;
264 device_t dev;
265 uint32_t err_reg, clear_reg;
266 uint8_t i;
267
268 dev = (device_t)v;
269 sc = device_get_softc(dev);
270
271 clear_reg = 0;
272 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);
273
274 /* Check which one error occurred */
275 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) {
276 if (err_reg & pci_err[i].err_dr_mask) {
277 device_printf(dev, "PCI %d: report %s error\n",
278 device_get_unit(dev), pci_err[i].msg);
279 clear_reg |= pci_err[i].err_dr_mask;
280 }
281 }
282
283 /* Clear pending errors */
284 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);
285 }
286
287 static int
fsl_pcib_probe(device_t dev)288 fsl_pcib_probe(device_t dev)
289 {
290
291 if (ofw_bus_get_type(dev) == NULL ||
292 strcmp(ofw_bus_get_type(dev), "pci") != 0)
293 return (ENXIO);
294
295 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
296 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
297 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||
298 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||
299 ofw_bus_is_compatible(dev, "fsl,p5040-pcie") ||
300 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||
301 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.4") ||
302 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))
303 return (ENXIO);
304
305 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
306 return (BUS_PROBE_DEFAULT);
307 }
308
309 static int
fsl_pcib_attach(device_t dev)310 fsl_pcib_attach(device_t dev)
311 {
312 struct fsl_pcib_softc *sc;
313 phandle_t node;
314 uint32_t cfgreg, brctl, ipreg;
315 int do_reset, error, rid;
316 uint8_t ltssm, capptr;
317
318 sc = device_get_softc(dev);
319 sc->sc_dev = dev;
320
321 sc->sc_rid = 0;
322 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
323 RF_ACTIVE);
324 if (sc->sc_res == NULL) {
325 device_printf(dev, "could not map I/O memory\n");
326 return (ENXIO);
327 }
328 sc->sc_bst = rman_get_bustag(sc->sc_res);
329 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
330 sc->sc_busnr = 0;
331
332 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);
333 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S;
334 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S;
335 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);
336
337 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
338 if (cfgreg != 0x1057 && cfgreg != 0x1957)
339 goto err;
340
341 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
342 while (capptr != 0) {
343 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
344 switch (cfgreg & 0xff) {
345 case PCIY_PCIX:
346 break;
347 case PCIY_EXPRESS:
348 sc->sc_pcie = 1;
349 sc->sc_pcie_capreg = capptr;
350 break;
351 }
352 capptr = (cfgreg >> 8) & 0xff;
353 }
354
355 node = ofw_bus_get_node(dev);
356
357 /*
358 * Initialize generic OF PCI interface (ranges, etc.)
359 */
360
361 error = ofw_pcib_init(dev);
362 if (error)
363 goto err;
364
365 /*
366 * Configure decode windows for PCI(E) access.
367 */
368 if (fsl_pcib_decode_win(node, sc) != 0)
369 goto err1;
370
371 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
372 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
373 PCIM_CMD_PORTEN;
374 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
375
376 do_reset = 0;
377 resource_int_value("pcib", device_get_unit(dev), "reset", &do_reset);
378 if (do_reset) {
379 /* Reset the bus. Needed for Radeon video cards. */
380 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
381 PCIR_BRIDGECTL_1, 1);
382 brctl |= PCIB_BCR_SECBUS_RESET;
383 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
384 PCIR_BRIDGECTL_1, brctl, 1);
385 DELAY(100000);
386 brctl &= ~PCIB_BCR_SECBUS_RESET;
387 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
388 PCIR_BRIDGECTL_1, brctl, 1);
389 DELAY(100000);
390 }
391
392 if (sc->sc_pcie) {
393 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
394 if (ltssm < LTSSM_STAT_L0) {
395 /* Stay attached, it may change later. */
396 if (bootverbose)
397 printf("PCI %d: no PCIE link, skipping\n",
398 device_get_unit(dev));
399 return (0);
400 }
401 }
402
403 /* Allocate irq */
404 rid = 0;
405 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
406 RF_ACTIVE | RF_SHAREABLE);
407 if (sc->sc_irq_res == NULL) {
408 error = fsl_pcib_detach(dev);
409 if (error != 0) {
410 device_printf(dev,
411 "Detach of the driver failed with error %d\n",
412 error);
413 }
414 return (ENXIO);
415 }
416
417 /* Setup interrupt handler */
418 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
419 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);
420 if (error != 0) {
421 device_printf(dev, "Could not setup irq, %d\n", error);
422 sc->sc_ih = NULL;
423 error = fsl_pcib_detach(dev);
424 if (error != 0) {
425 device_printf(dev,
426 "Detach of the driver failed with error %d\n",
427 error);
428 }
429 return (ENXIO);
430 }
431
432 fsl_pcib_err_init(dev);
433
434 return (ofw_pcib_attach(dev));
435
436 err1:
437 ofw_pcib_fini(dev);
438 err:
439 if (sc->sc_irq_res != NULL)
440 bus_release_resource(dev, sc->sc_irq_res);
441 if (sc->sc_res != NULL)
442 bus_release_resource(dev, sc->sc_res);
443 mtx_destroy(&sc->sc_cfg_mtx);
444
445 return (ENXIO);
446 }
447
448 static uint32_t
fsl_pcib_cfgread(struct fsl_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg,int bytes)449 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
450 u_int reg, int bytes)
451 {
452 uint32_t addr, data;
453
454 addr = CONFIG_ACCESS_ENABLE;
455 addr |= (bus & 0xff) << 16;
456 addr |= (slot & 0x1f) << 11;
457 addr |= (func & 0x7) << 8;
458 addr |= reg & 0xfc;
459 if (sc->sc_pcie)
460 addr |= (reg & 0xf00) << 16;
461
462 mtx_lock_spin(&sc->sc_cfg_mtx);
463 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
464
465 switch (bytes) {
466 case 1:
467 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
468 REG_CFG_DATA + (reg & 3));
469 break;
470 case 2:
471 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
472 REG_CFG_DATA + (reg & 2)));
473 break;
474 case 4:
475 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
476 REG_CFG_DATA));
477 break;
478 default:
479 data = ~0;
480 break;
481 }
482 mtx_unlock_spin(&sc->sc_cfg_mtx);
483 return (data);
484 }
485
486 static void
fsl_pcib_cfgwrite(struct fsl_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)487 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
488 u_int reg, uint32_t data, int bytes)
489 {
490 uint32_t addr;
491
492 addr = CONFIG_ACCESS_ENABLE;
493 addr |= (bus & 0xff) << 16;
494 addr |= (slot & 0x1f) << 11;
495 addr |= (func & 0x7) << 8;
496 addr |= reg & 0xfc;
497 if (sc->sc_pcie)
498 addr |= (reg & 0xf00) << 16;
499
500 mtx_lock_spin(&sc->sc_cfg_mtx);
501 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
502
503 switch (bytes) {
504 case 1:
505 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
506 REG_CFG_DATA + (reg & 3), data);
507 break;
508 case 2:
509 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
510 REG_CFG_DATA + (reg & 2), htole16(data));
511 break;
512 case 4:
513 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
514 REG_CFG_DATA, htole32(data));
515 break;
516 }
517 mtx_unlock_spin(&sc->sc_cfg_mtx);
518 }
519
520 #if 0
521 static void
522 dump(struct fsl_pcib_softc *sc)
523 {
524 unsigned int i;
525
526 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
527 for (i = 0; i < 5; i++) {
528 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
529 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
530 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
531 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
532 }
533 printf("\n");
534 for (i = 1; i < 4; i++) {
535 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
536 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
537 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
538 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
539 }
540 printf("\n");
541 #undef RD
542
543 for (i = 0; i < 0x48; i += 4) {
544 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
545 i, 4));
546 }
547 }
548 #endif
549
550 static int
fsl_pcib_maxslots(device_t dev)551 fsl_pcib_maxslots(device_t dev)
552 {
553 struct fsl_pcib_softc *sc = device_get_softc(dev);
554
555 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
556 }
557
558 static uint32_t
fsl_pcib_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)559 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
560 u_int reg, int bytes)
561 {
562 struct fsl_pcib_softc *sc = device_get_softc(dev);
563
564 if (bus == sc->sc_busnr && !sc->sc_pcie &&
565 slot < PCI_SLOT_FIRST)
566 return (~0);
567
568 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
569 }
570
571 static void
fsl_pcib_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)572 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
573 u_int reg, uint32_t val, int bytes)
574 {
575 struct fsl_pcib_softc *sc = device_get_softc(dev);
576
577 if (bus == sc->sc_busnr && !sc->sc_pcie &&
578 slot < PCI_SLOT_FIRST)
579 return;
580 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
581 }
582
583 static void
fsl_pcib_inbound(struct fsl_pcib_softc * sc,int wnd,int tgt,uint64_t start,uint64_t size,uint64_t pci_start)584 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
585 uint64_t size, uint64_t pci_start)
586 {
587 uint32_t attr, bar, tar;
588
589 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
590
591 attr = PIWAR_EN;
592
593 switch (tgt) {
594 case -1:
595 attr &= ~PIWAR_EN;
596 break;
597 case PIWAR_TRGT_LOCAL:
598 attr |= (ffsl(size) - 2);
599 default:
600 attr |= (tgt << PIWAR_TRGT_S);
601 break;
602 }
603 tar = start >> 12;
604 bar = pci_start >> 12;
605
606 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
607 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
608 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
609 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
610 }
611
612 static void
fsl_pcib_outbound(struct fsl_pcib_softc * sc,int wnd,int res,uint64_t start,uint64_t size,uint64_t pci_start)613 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
614 uint64_t size, uint64_t pci_start)
615 {
616 uint32_t attr, bar, tar;
617
618 switch (res) {
619 case SYS_RES_MEMORY:
620 attr = 0x80044000 | (ffsll(size) - 2);
621 break;
622 case SYS_RES_IOPORT:
623 attr = 0x80088000 | (ffsll(size) - 2);
624 break;
625 default:
626 attr = 0x0004401f;
627 break;
628 }
629 bar = start >> 12;
630 tar = pci_start >> 12;
631
632 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
633 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
634 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
635 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
636 }
637
638 static void
fsl_pcib_err_init(device_t dev)639 fsl_pcib_err_init(device_t dev)
640 {
641 struct fsl_pcib_softc *sc;
642 uint16_t sec_stat, dsr;
643 uint32_t dcr, err_en;
644
645 sc = device_get_softc(dev);
646
647 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
648 if (sec_stat)
649 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
650 if (sc->sc_pcie) {
651 /* Clear error bits */
652 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
653 0xffffffff);
654 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
655 0xffffffff);
656 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
657 0xffffffff);
658
659 dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
660 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
661 if (dsr)
662 fsl_pcib_cfgwrite(sc, 0, 0, 0,
663 sc->sc_pcie_capreg + PCIER_DEVICE_STA,
664 0xffff, 2);
665
666 /* Enable all errors reporting */
667 err_en = 0x00bfff00;
668 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
669 err_en);
670
671 /* Enable error reporting: URR, FER, NFER */
672 dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
673 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
674 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
675 PCIEM_CTL_NFER_ENABLE;
676 fsl_pcib_cfgwrite(sc, 0, 0, 0,
677 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
678 }
679 }
680
681 static int
fsl_pcib_detach(device_t dev)682 fsl_pcib_detach(device_t dev)
683 {
684 struct fsl_pcib_softc *sc;
685 int error;
686
687 error = bus_generic_detach(dev);
688 if (error != 0)
689 return (error);
690
691 sc = device_get_softc(dev);
692 ofw_pcib_fini(dev);
693
694 mtx_destroy(&sc->sc_cfg_mtx);
695
696 if (sc->sc_irq_res != NULL)
697 bus_release_resource(dev, sc->sc_irq_res);
698 if (sc->sc_res != NULL)
699 bus_release_resource(dev, sc->sc_res);
700
701 return (0);
702 }
703
704 static int
fsl_pcib_decode_win(phandle_t node,struct fsl_pcib_softc * sc)705 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
706 {
707 device_t dev;
708 int error, i, trgt;
709
710 dev = sc->sc_dev;
711
712 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
713
714 /*
715 * Configure LAW decode windows.
716 */
717 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
718 &sc->sc_ioport_target);
719 if (error != 0) {
720 device_printf(dev, "could not retrieve PCI LAW target info\n");
721 return (error);
722 }
723
724 for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
725 switch (sc->pci_sc.sc_range[i].pci_hi &
726 OFW_PCI_PHYS_HI_SPACEMASK) {
727 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
728 continue;
729 case OFW_PCI_PHYS_HI_SPACE_IO:
730 trgt = sc->sc_ioport_target;
731 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
732 sc->pci_sc.sc_range[i].host,
733 sc->pci_sc.sc_range[i].size,
734 sc->pci_sc.sc_range[i].pci);
735 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
736 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
737 sc->pci_sc.sc_range[i].size - 1;
738 break;
739 case OFW_PCI_PHYS_HI_SPACE_MEM32:
740 case OFW_PCI_PHYS_HI_SPACE_MEM64:
741 trgt = sc->sc_iomem_target;
742 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
743 sc->pci_sc.sc_range[i].host,
744 sc->pci_sc.sc_range[i].size,
745 sc->pci_sc.sc_range[i].pci);
746 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
747 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
748 sc->pci_sc.sc_range[i].size - 1;
749 break;
750 default:
751 panic("Unknown range type %#x\n",
752 sc->pci_sc.sc_range[i].pci_hi &
753 OFW_PCI_PHYS_HI_SPACEMASK);
754 }
755 error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
756 sc->pci_sc.sc_range[i].size);
757 if (error != 0) {
758 device_printf(dev, "could not program LAW for range "
759 "%d\n", i);
760 return (error);
761 }
762 }
763
764 /*
765 * Set outbout and inbound windows.
766 */
767 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
768 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
769
770 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
771 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
772 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0,
773 ptoa(Maxmem), 0);
774
775 /* Direct-map the CCSR for MSIs. */
776 /* Freescale PCIe 2.x has a dedicated MSI window. */
777 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */
778 if (sc->sc_ip_maj >= 2)
779 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa,
780 ccsrbar_size, ccsrbar_pa);
781 else
782 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa,
783 ccsrbar_size, ccsrbar_pa);
784
785 return (0);
786 }
787
fsl_pcib_alloc_msi(device_t dev,device_t child,int count,int maxcount,int * irqs)788 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
789 int count, int maxcount, int *irqs)
790 {
791 vmem_addr_t start;
792 int err, i;
793
794 if (msi_vmem == NULL)
795 return (ENODEV);
796
797 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0,
798 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
799
800 if (err)
801 return (err);
802
803 for (i = 0; i < count; i++)
804 irqs[i] = start + i;
805
806 return (0);
807 }
808
fsl_pcib_release_msi(device_t dev,device_t child,int count,int * irqs)809 static int fsl_pcib_release_msi(device_t dev, device_t child,
810 int count, int *irqs)
811 {
812 if (msi_vmem == NULL)
813 return (ENODEV);
814
815 vmem_xfree(msi_vmem, irqs[0], count);
816 return (0);
817 }
818
fsl_pcib_alloc_msix(device_t dev,device_t child,int * irq)819 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq)
820 {
821 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq));
822 }
823
fsl_pcib_release_msix(device_t dev,device_t child,int irq)824 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq)
825 {
826 return (fsl_pcib_release_msi(dev, child, 1, &irq));
827 }
828
fsl_pcib_map_msi(device_t dev,device_t child,int irq,uint64_t * addr,uint32_t * data)829 static int fsl_pcib_map_msi(device_t dev, device_t child,
830 int irq, uint64_t *addr, uint32_t *data)
831 {
832 struct fsl_msi_map *mp;
833
834 SLIST_FOREACH(mp, &fsl_msis, slist) {
835 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS)
836 break;
837 }
838
839 if (mp == NULL)
840 return (ENODEV);
841
842 *data = (irq & 255);
843 *addr = ccsrbar_pa + mp->target;
844
845 return (0);
846 }
847
848 /*
849 * Linux device trees put the msi@<x> as children of the SoC, with ranges based
850 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between
851 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC
852 * driver just to allocate a subregion for a sibling driver). This driver will
853 * use ccsr_write() and ccsr_read() instead.
854 */
855
856 #define FSL_NUM_IRQS 8
857 #define FSL_NUM_MSI_PER_IRQ 32
858 #define FSL_MSI_TARGET 0x140
859
860 struct fsl_msi_softc {
861 vm_offset_t sc_base;
862 vm_offset_t sc_target;
863 int sc_msi_base_irq;
864 struct fsl_msi_map sc_map;
865 struct fsl_msi_irq {
866 /* This struct gets passed as the filter private data. */
867 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */
868 struct resource *res;
869 int irq;
870 void *cookie;
871 int vectors[FSL_NUM_MSI_PER_IRQ];
872 vm_offset_t reg;
873 } sc_msi_irq[FSL_NUM_IRQS];
874 };
875
876 static int
fsl_msi_intr_filter(void * priv)877 fsl_msi_intr_filter(void *priv)
878 {
879 struct fsl_msi_irq *data = priv;
880 uint32_t reg;
881 int i;
882
883 reg = ccsr_read4(ccsrbar_va + data->reg);
884 i = 0;
885 while (reg != 0) {
886 if (reg & 1)
887 powerpc_dispatch_intr(data->vectors[i], NULL);
888 reg >>= 1;
889 i++;
890 }
891
892 return (FILTER_HANDLED);
893 }
894
895 static int
fsl_msi_probe(device_t dev)896 fsl_msi_probe(device_t dev)
897 {
898 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi"))
899 return (ENXIO);
900
901 device_set_desc(dev, "Freescale MSI");
902
903 return (BUS_PROBE_DEFAULT);
904 }
905
906 static int
fsl_msi_attach(device_t dev)907 fsl_msi_attach(device_t dev)
908 {
909 struct fsl_msi_softc *sc;
910 struct fsl_msi_irq *irq;
911 int i;
912
913 sc = device_get_softc(dev);
914
915 if (msi_vmem == NULL)
916 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK);
917
918 /* Manually play with resource entries. */
919 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
920 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1);
921
922 if (sc->sc_map.target == 0)
923 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET;
924
925 for (i = 0; i < FSL_NUM_IRQS; i++) {
926 irq = &sc->sc_msi_irq[i];
927 irq->irq = i;
928 irq->reg = sc->sc_base + 16 * i;
929 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
930 &irq->irq, RF_ACTIVE);
931 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE,
932 fsl_msi_intr_filter, NULL, irq, &irq->cookie);
933 }
934 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev),
935 FSL_NUM_MSIS, 0, 0);
936
937 /* Let vmem and the IRQ subsystem work their magic for allocations. */
938 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK);
939
940 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist);
941
942 return (0);
943 }
944
945 static void
fsl_msi_enable(device_t dev,u_int irq,u_int vector,void ** priv)946 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv)
947 {
948 struct fsl_msi_softc *sc;
949 struct fsl_msi_irq *irqd;
950
951 sc = device_get_softc(dev);
952
953 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ];
954 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector;
955 }
956
957 static device_method_t fsl_msi_methods[] = {
958 DEVMETHOD(device_probe, fsl_msi_probe),
959 DEVMETHOD(device_attach, fsl_msi_attach),
960
961 DEVMETHOD(pic_enable, fsl_msi_enable),
962 DEVMETHOD_END
963 };
964
965 static driver_t fsl_msi_driver = {
966 "fsl_msi",
967 fsl_msi_methods,
968 sizeof(struct fsl_msi_softc)
969 };
970
971 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, 0, 0,
972 BUS_PASS_INTERRUPT + 1);
973